Re: [PATCH 03/20] drm/i915/icl: Define DSI mode ctl register

[Jani Nikula <jani.nikula@intel.com>]

On Fri, 29 Jun 2018, "Chauhan, Madhav" <madhav.chauhan@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani
>> Sent: Friday, June 29, 2018 5:22 PM
>> To: Chauhan, Madhav <madhav.chauhan@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: Zanoni, Paulo R <paulo.r.zanoni@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>; Vivi, Rodrigo <rodrigo.vivi@intel.com>;
>> Chauhan, Madhav <madhav.chauhan@intel.com>
>> Subject: Re: [PATCH 03/20] drm/i915/icl: Define DSI mode ctl register
>> 
>> On Fri, 15 Jun 2018, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
>> > This patch defines DSI IO mode control register and it's bits used
>> > while enabling IO power for DSI.
>> >
>> > Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
>> >  1 file changed, 8 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> > b/drivers/gpu/drm/i915/i915_reg.h index 55ef57d..0d268d1 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -9486,6 +9486,14 @@ enum skl_power_gate {
>> >  #define _BXT_MIPIC_PORT_CTRL				0x6B8C0
>> >  #define BXT_MIPI_PORT_CTRL(tc)	_MMIO_MIPI(tc,
>> _BXT_MIPIA_PORT_CTRL, _BXT_MIPIC_PORT_CTRL)
>> >
>> > +/* ICL DSI MODE control */
>> > +#define _ICL_DSI_IO_MODECTL_0				0x6B094
>> > +#define _ICL_DSI_IO_MODECTL_1				0x6B894
>> > +#define ICL_DSI_IO_MODECTL(port)	_MMIO_PORT(port,	\
>> > +						    _ICL_DSI_IO_MODECTL_0,
>> \
>> > +						    _ICL_DSI_IO_MODECTL_1)
>> > +#define  COMBO_PHY_MODE_DSI				(1 << 0)
>> > +
>> 
>> I wonder if it would be worth it to group all ICL DSI register in one place
>> instead of mingling with the BYT/BXT registers.
>
> Just to have context of previous platforms/encoders as well, defined registers 
> Close to existing similar definitions.

With them, there's usually significant overlap. I'm not so sure
here. But it's no big deal. Can be left like this.

BR,
Jani.


>
>> 
>> Again, I'd prefer it if the register content macros were all specified in one go.
>
> Agree, will add other bit fields while publishing next version and for other patches as well
>
> Regards,
> Madhav
>> 
>> Even so,
>> 
>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>> 
>> 
>> >  #define BXT_P_DSI_REGULATOR_CFG
>> 	_MMIO(0x160020)
>> >  #define  STAP_SELECT					(1 << 0)
>> 
>> --
>> Jani Nikula, Intel Open Source Graphics Center

-- 
Jani Nikula, Intel Open Source Graphics Center
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