[Intel-gfx] [PATCH 0/2] Use i915 instead of dev_priv

[Intel-gfx] [PATCH 0/2] Use i915 instead of dev_priv

[Andi Shyti]

Hi,

just another "Friday patch". While reviewing some patches from
Tejas I found a bit confusing the use of dev_priv__ inside the
for_each_engine(), perhaps it should be moved inside the gt/?

As I was at it I made the /dev_priv/i915/ change which is still
harmless. Next in queue is to change the i915_irq.h, which is a
bit tricky (but not much) as the "dev_priv" is hardcoded inside
some defines.

Andi

Andi Shyti (2):
  drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
  drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv
    structure

 drivers/gpu/drm/i915/i915_drv.h | 462 ++++++++++++++++----------------
 1 file changed, 231 insertions(+), 231 deletions(-)

-- 
2.40.0

[Intel-gfx] [PATCH 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_gt()

[Andi Shyti]

for_each_gt() loops through engines in the GT, not in dev_priv.
Because it's misleading, call it "gt__" instead of "dev_priv__".

Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fe7eeafe9cff6..c16f8a3cd914f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -381,11 +381,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 }
 
 /* Simple iterator over all initialised engines */
-#define for_each_engine(engine__, dev_priv__, id__) \
+#define for_each_engine(engine__, gt__, id__) \
 	for ((id__) = 0; \
 	     (id__) < I915_NUM_ENGINES; \
 	     (id__)++) \
-		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
+		for_each_if ((engine__) = (gt__)->engine[(id__)])
 
 /* Iterator over subset of engines selected by mask */
 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
-- 
2.40.0

Re: [Intel-gfx] [PATCH 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_gt()

[Rodrigo Vivi]

On Fri, Apr 21, 2023 at 03:46:53PM +0200, Andi Shyti wrote:
> for_each_gt() loops through engines in the GT, not in dev_priv.

typo here? ^

with that fixed:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> Because it's misleading, call it "gt__" instead of "dev_priv__".
> 
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fe7eeafe9cff6..c16f8a3cd914f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -381,11 +381,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>  }
>  
>  /* Simple iterator over all initialised engines */
> -#define for_each_engine(engine__, dev_priv__, id__) \
> +#define for_each_engine(engine__, gt__, id__) \
>  	for ((id__) = 0; \
>  	     (id__) < I915_NUM_ENGINES; \
>  	     (id__)++) \
> -		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
> +		for_each_if ((engine__) = (gt__)->engine[(id__)])
>  
>  /* Iterator over subset of engines selected by mask */
>  #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
> -- 
> 2.40.0
> 

Re: [Intel-gfx] [PATCH 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_gt()

[Rodrigo Vivi]

On Fri, Apr 21, 2023 at 10:00:29AM -0400, Rodrigo Vivi wrote:
> On Fri, Apr 21, 2023 at 03:46:53PM +0200, Andi Shyti wrote:
> > for_each_gt() loops through engines in the GT, not in dev_priv.
> 
> typo here? ^
> 
> with that fixed:

oh, in the commit subject as well...

> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> > Because it's misleading, call it "gt__" instead of "dev_priv__".
> > 
> > Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index fe7eeafe9cff6..c16f8a3cd914f 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -381,11 +381,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> >  }
> >  
> >  /* Simple iterator over all initialised engines */
> > -#define for_each_engine(engine__, dev_priv__, id__) \
> > +#define for_each_engine(engine__, gt__, id__) \
> >  	for ((id__) = 0; \
> >  	     (id__) < I915_NUM_ENGINES; \
> >  	     (id__)++) \
> > -		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
> > +		for_each_if ((engine__) = (gt__)->engine[(id__)])
> >  
> >  /* Iterator over subset of engines selected by mask */
> >  #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
> > -- 
> > 2.40.0
> > 

Re: [Intel-gfx] [PATCH 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_gt()

[Andi Shyti]

Hi Rodrigo,

On Fri, Apr 21, 2023 at 10:05:07AM -0400, Rodrigo Vivi wrote:
> On Fri, Apr 21, 2023 at 10:00:29AM -0400, Rodrigo Vivi wrote:
> > On Fri, Apr 21, 2023 at 03:46:53PM +0200, Andi Shyti wrote:
> > > for_each_gt() loops through engines in the GT, not in dev_priv.
> > 
> > typo here? ^
> > 
> > with that fixed:
> 
> oh, in the commit subject as well...

The power of habit! Thanks!

Andi

Re: [Intel-gfx] [PATCH 1/2] drm/i915/i915_drv: Use proper parameter naming in for_each_gt()

[Andrzej Hajda]

On 21.04.2023 15:46, Andi Shyti wrote:
> for_each_gt() loops through engines in the GT, not in dev_priv.
> Because it's misleading, call it "gt__" instead of "dev_priv__".
> 
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>

With fixes mentioned by Rodrigo.

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej

> ---
>   drivers/gpu/drm/i915/i915_drv.h | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fe7eeafe9cff6..c16f8a3cd914f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -381,11 +381,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>   }
>   
>   /* Simple iterator over all initialised engines */
> -#define for_each_engine(engine__, dev_priv__, id__) \
> +#define for_each_engine(engine__, gt__, id__) \
>   	for ((id__) = 0; \
>   	     (id__) < I915_NUM_ENGINES; \
>   	     (id__)++) \
> -		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
> +		for_each_if ((engine__) = (gt__)->engine[(id__)])
>   
>   /* Iterator over subset of engines selected by mask */
>   #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \

[Intel-gfx] [PATCH 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure

[Andi Shyti]

In the process of renaming all instances of 'dev_priv' to 'i915',
start using 'i915' within the 'drm_i915_file_private' structure.

Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 458 ++++++++++++++++----------------
 1 file changed, 229 insertions(+), 229 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c16f8a3cd914f..14c5338c96a6b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -407,11 +407,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 	     (engine__) && (engine__)->uabi_class == (class__); \
 	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
 
-#define INTEL_INFO(dev_priv)	(&(dev_priv)->__info)
-#define RUNTIME_INFO(dev_priv)	(&(dev_priv)->__runtime)
-#define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)
+#define INTEL_INFO(i915)	(&(i915)->__info)
+#define RUNTIME_INFO(i915)	(&(i915)->__runtime)
+#define DRIVER_CAPS(i915)	(&(i915)->caps)
 
-#define INTEL_DEVID(dev_priv)	(RUNTIME_INFO(dev_priv)->device_id)
+#define INTEL_DEVID(i915)	(RUNTIME_INFO(i915)->device_id)
 
 #define IP_VER(ver, rel)		((ver) << 8 | (rel))
 
@@ -431,7 +431,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
 #define IS_DISPLAY_VER(i915, from, until) \
 	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
 
-#define INTEL_REVID(dev_priv)	(to_pci_dev((dev_priv)->drm.dev)->revision)
+#define INTEL_REVID(i915)	(to_pci_dev((i915)->drm.dev)->revision)
 
 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
@@ -516,135 +516,135 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
 }
 
-#define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
-#define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
-
-#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
-#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
-#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
-#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
-#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
-#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
-#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
-#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
-#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
-#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
-#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
-#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
-#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
-#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
-#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
-#define IS_IRONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
-#define IS_IRONLAKE_M(dev_priv) \
-	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
-#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
-#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
-#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 1)
-#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
-#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
-#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
-#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
-#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
-#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
-#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
-#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
-#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
-#define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
-#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_JSL_EHL(dev_priv)	(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
-				IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
-#define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
-#define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
-#define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
-#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
-#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
-#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
-#define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, INTEL_DG2)
-#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
-#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
-
-#define IS_METEORLAKE_M(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
-#define IS_METEORLAKE_P(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
-#define IS_DG2_G10(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
-#define IS_DG2_G11(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
-#define IS_DG2_G12(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
-#define IS_ADLS_RPLS(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_N(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
-#define IS_ADLP_RPLP(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
-#define IS_ADLP_RPLU(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
-#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
-				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
-#define IS_BDW_ULX(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_HSW_ULT(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
-#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 1)
+#define IS_MOBILE(i915)	(INTEL_INFO(i915)->is_mobile)
+#define IS_DGFX(i915)   (INTEL_INFO(i915)->is_dgfx)
+
+#define IS_I830(i915)	IS_PLATFORM(i915, INTEL_I830)
+#define IS_I845G(i915)	IS_PLATFORM(i915, INTEL_I845G)
+#define IS_I85X(i915)	IS_PLATFORM(i915, INTEL_I85X)
+#define IS_I865G(i915)	IS_PLATFORM(i915, INTEL_I865G)
+#define IS_I915G(i915)	IS_PLATFORM(i915, INTEL_I915G)
+#define IS_I915GM(i915)	IS_PLATFORM(i915, INTEL_I915GM)
+#define IS_I945G(i915)	IS_PLATFORM(i915, INTEL_I945G)
+#define IS_I945GM(i915)	IS_PLATFORM(i915, INTEL_I945GM)
+#define IS_I965G(i915)	IS_PLATFORM(i915, INTEL_I965G)
+#define IS_I965GM(i915)	IS_PLATFORM(i915, INTEL_I965GM)
+#define IS_G45(i915)	IS_PLATFORM(i915, INTEL_G45)
+#define IS_GM45(i915)	IS_PLATFORM(i915, INTEL_GM45)
+#define IS_G4X(i915)	(IS_G45(i915) || IS_GM45(i915))
+#define IS_PINEVIEW(i915)	IS_PLATFORM(i915, INTEL_PINEVIEW)
+#define IS_G33(i915)	IS_PLATFORM(i915, INTEL_G33)
+#define IS_IRONLAKE(i915)	IS_PLATFORM(i915, INTEL_IRONLAKE)
+#define IS_IRONLAKE_M(i915) \
+	(IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
+#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
+#define IS_IVYBRIDGE(i915)	IS_PLATFORM(i915, INTEL_IVYBRIDGE)
+#define IS_IVB_GT1(i915)	(IS_IVYBRIDGE(i915) && \
+				 INTEL_INFO(i915)->gt == 1)
+#define IS_VALLEYVIEW(i915)	IS_PLATFORM(i915, INTEL_VALLEYVIEW)
+#define IS_CHERRYVIEW(i915)	IS_PLATFORM(i915, INTEL_CHERRYVIEW)
+#define IS_HASWELL(i915)	IS_PLATFORM(i915, INTEL_HASWELL)
+#define IS_BROADWELL(i915)	IS_PLATFORM(i915, INTEL_BROADWELL)
+#define IS_SKYLAKE(i915)	IS_PLATFORM(i915, INTEL_SKYLAKE)
+#define IS_BROXTON(i915)	IS_PLATFORM(i915, INTEL_BROXTON)
+#define IS_KABYLAKE(i915)	IS_PLATFORM(i915, INTEL_KABYLAKE)
+#define IS_GEMINILAKE(i915)	IS_PLATFORM(i915, INTEL_GEMINILAKE)
+#define IS_COFFEELAKE(i915)	IS_PLATFORM(i915, INTEL_COFFEELAKE)
+#define IS_COMETLAKE(i915)	IS_PLATFORM(i915, INTEL_COMETLAKE)
+#define IS_ICELAKE(i915)	IS_PLATFORM(i915, INTEL_ICELAKE)
+#define IS_JSL_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
+				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
+#define IS_TIGERLAKE(i915)	IS_PLATFORM(i915, INTEL_TIGERLAKE)
+#define IS_ROCKETLAKE(i915)	IS_PLATFORM(i915, INTEL_ROCKETLAKE)
+#define IS_DG1(i915)        IS_PLATFORM(i915, INTEL_DG1)
+#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
+#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
+#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
+#define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
+#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
+#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
+
+#define IS_METEORLAKE_M(i915) \
+	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
+#define IS_METEORLAKE_P(i915) \
+	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
+#define IS_DG2_G10(i915) \
+	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
+#define IS_DG2_G11(i915) \
+	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
+#define IS_DG2_G12(i915) \
+	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
+#define IS_ADLS_RPLS(i915) \
+	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
+#define IS_ADLP_N(i915) \
+	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
+#define IS_ADLP_RPLP(i915) \
+	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
+#define IS_ADLP_RPLU(i915) \
+	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
+#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
+				    (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
+#define IS_BDW_ULT(i915) \
+	IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
+#define IS_BDW_ULX(i915) \
+	IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
+#define IS_BDW_GT3(i915)	(IS_BROADWELL(i915) && \
+				 INTEL_INFO(i915)->gt == 3)
+#define IS_HSW_ULT(i915) \
+	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
+#define IS_HSW_GT3(i915)	(IS_HASWELL(i915) && \
+				 INTEL_INFO(i915)->gt == 3)
+#define IS_HSW_GT1(i915)	(IS_HASWELL(i915) && \
+				 INTEL_INFO(i915)->gt == 1)
 /* ULX machines are also considered ULT. */
-#define IS_HSW_ULX(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_ULT(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_SKL_ULX(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_KBL_ULT(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_KBL_ULX(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 2)
-#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 4)
-#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 2)
-#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 3)
-#define IS_CFL_ULT(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_CFL_ULX(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 2)
-#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 3)
-
-#define IS_CML_ULT(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
-#define IS_CML_ULX(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
-#define IS_CML_GT2(dev_priv)	(IS_COMETLAKE(dev_priv) && \
-				 INTEL_INFO(dev_priv)->gt == 2)
-
-#define IS_ICL_WITH_PORT_F(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
-
-#define IS_TGL_UY(dev_priv) \
-	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
+#define IS_HSW_ULX(i915) \
+	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
+#define IS_SKL_ULT(i915) \
+	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_SKL_ULX(i915) \
+	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_KBL_ULT(i915) \
+	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_KBL_ULX(i915) \
+	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 2)
+#define IS_SKL_GT3(i915)	(IS_SKYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 3)
+#define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 4)
+#define IS_KBL_GT2(i915)	(IS_KABYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 2)
+#define IS_KBL_GT3(i915)	(IS_KABYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 3)
+#define IS_CFL_ULT(i915) \
+	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_CFL_ULX(i915) \
+	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_CFL_GT2(i915)	(IS_COFFEELAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 2)
+#define IS_CFL_GT3(i915)	(IS_COFFEELAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 3)
+
+#define IS_CML_ULT(i915) \
+	IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
+#define IS_CML_ULX(i915) \
+	IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
+#define IS_CML_GT2(i915)	(IS_COMETLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 2)
+
+#define IS_ICL_WITH_PORT_F(i915) \
+	IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
+
+#define IS_TGL_UY(i915) \
+	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
 
 #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
 
-#define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
-	(IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
-#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
-	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
+#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
+	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
+#define IS_KBL_DISPLAY_STEP(i915, since, until) \
+	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
 
 #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
 	(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
@@ -720,9 +720,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 	(IS_PONTEVECCHIO(__i915) && \
 	 IS_GRAPHICS_STEP(__i915, since, until))
 
-#define IS_LP(dev_priv)		(INTEL_INFO(dev_priv)->is_lp)
-#define IS_GEN9_LP(dev_priv)	(GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
-#define IS_GEN9_BC(dev_priv)	(GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
+#define IS_LP(i915)		(INTEL_INFO(i915)->is_lp)
+#define IS_GEN9_LP(i915)	(GRAPHICS_VER(i915) == 9 && IS_LP(i915))
+#define IS_GEN9_BC(i915)	(GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
 
 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
@@ -747,180 +747,180 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define CCS_MASK(gt) \
 	ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
 
-#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
+#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
 
 /*
  * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
  * All later gens can run the final buffer from the ppgtt
  */
-#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
+#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
 
-#define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
-#define HAS_4TILE(dev_priv)	(INTEL_INFO(dev_priv)->has_4tile)
-#define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
-#define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
-#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
-#define HAS_WT(dev_priv)	HAS_EDRAM(dev_priv)
+#define HAS_LLC(i915)	(INTEL_INFO(i915)->has_llc)
+#define HAS_4TILE(i915)	(INTEL_INFO(i915)->has_4tile)
+#define HAS_SNOOP(i915)	(INTEL_INFO(i915)->has_snoop)
+#define HAS_EDRAM(i915)	((i915)->edram_size_mb)
+#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
+#define HAS_WT(i915)	HAS_EDRAM(i915)
 
-#define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)
+#define HWS_NEEDS_PHYSICAL(i915)	(INTEL_INFO(i915)->hws_needs_physical)
 
-#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
-		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
-#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
-		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
+#define HAS_LOGICAL_RING_CONTEXTS(i915) \
+		(INTEL_INFO(i915)->has_logical_ring_contexts)
+#define HAS_LOGICAL_RING_ELSQ(i915) \
+		(INTEL_INFO(i915)->has_logical_ring_elsq)
 
-#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
+#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
 
-#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
-#define HAS_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
-#define HAS_FULL_PPGTT(dev_priv) \
-	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
+#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
+#define HAS_PPGTT(i915) \
+	(INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
+#define HAS_FULL_PPGTT(i915) \
+	(INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
 
-#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
+#define HAS_PAGE_SIZES(i915, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
-	((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
+	((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
 })
 
-#define HAS_OVERLAY(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_overlay)
-#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
-		(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
+#define HAS_OVERLAY(i915)		 (INTEL_INFO(i915)->display.has_overlay)
+#define OVERLAY_NEEDS_PHYSICAL(i915) \
+		(INTEL_INFO(i915)->display.overlay_needs_physical)
 
 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
-#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
+#define HAS_BROKEN_CS_TLB(i915)	(IS_I830(i915) || IS_I845G(i915))
 
-#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)	\
-	(IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
+#define NEEDS_RC6_CTX_CORRUPTION_WA(i915)	\
+	(IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
 
 /* WaRsDisableCoarsePowerGating:skl,cnl */
-#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)			\
-	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
+#define NEEDS_WaRsDisableCoarsePowerGating(i915)			\
+	(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
 
-#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
-#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
-					IS_GEMINILAKE(dev_priv) || \
-					IS_KABYLAKE(dev_priv))
+#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
+#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 11 || \
+					IS_GEMINILAKE(i915) || \
+					IS_KABYLAKE(i915))
 
 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
  * rows, which changed the alignment requirements and fence programming.
  */
-#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
-					 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
-#define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->display.supports_tv)
-#define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->display.has_hotplug)
+#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
+					 !(IS_I915G(i915) || IS_I915GM(i915)))
+#define SUPPORTS_TV(i915)		(INTEL_INFO(i915)->display.supports_tv)
+#define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display.has_hotplug)
 
-#define HAS_FW_BLC(dev_priv)	(DISPLAY_VER(dev_priv) > 2)
-#define HAS_FBC(dev_priv)	(RUNTIME_INFO(dev_priv)->fbc_mask != 0)
-#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
+#define HAS_FW_BLC(i915)	(DISPLAY_VER(i915) > 2)
+#define HAS_FBC(i915)	(RUNTIME_INFO(i915)->fbc_mask != 0)
+#define HAS_CUR_FBC(i915)	(!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
 
-#define HAS_DPT(dev_priv)	(DISPLAY_VER(dev_priv) >= 13)
+#define HAS_DPT(i915)	(DISPLAY_VER(i915) >= 13)
 
-#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
+#define HAS_IPS(i915)	(IS_HSW_ULT(i915) || IS_BROADWELL(i915))
 
-#define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)
-#define HAS_DP20(dev_priv)	(IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
+#define HAS_DP_MST(i915)	(INTEL_INFO(i915)->display.has_dp_mst)
+#define HAS_DP20(i915)	(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
 
-#define HAS_DOUBLE_BUFFERED_M_N(dev_priv)	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+#define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
 
-#define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
-#define HAS_CDCLK_SQUASH(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
-#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
-#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
-#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
-#define HAS_PSR_HW_TRACKING(dev_priv) \
-	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
-#define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)
-#define HAS_TRANSCODER(dev_priv, trans)	 ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
+#define HAS_CDCLK_CRAWL(i915)	 (INTEL_INFO(i915)->display.has_cdclk_crawl)
+#define HAS_CDCLK_SQUASH(i915)	 (INTEL_INFO(i915)->display.has_cdclk_squash)
+#define HAS_DDI(i915)		 (INTEL_INFO(i915)->display.has_ddi)
+#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg)
+#define HAS_PSR(i915)		 (INTEL_INFO(i915)->display.has_psr)
+#define HAS_PSR_HW_TRACKING(i915) \
+	(INTEL_INFO(i915)->display.has_psr_hw_tracking)
+#define HAS_PSR2_SEL_FETCH(i915)	 (DISPLAY_VER(i915) >= 12)
+#define HAS_TRANSCODER(i915, trans)	 ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
 
-#define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
-#define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
-#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
+#define HAS_RC6(i915)		 (INTEL_INFO(i915)->has_rc6)
+#define HAS_RC6p(i915)		 (INTEL_INFO(i915)->has_rc6p)
+#define HAS_RC6pp(i915)		 (false) /* HW was never validated */
 
-#define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)
+#define HAS_RPS(i915)	(INTEL_INFO(i915)->has_rps)
 
-#define HAS_DMC(dev_priv)	(RUNTIME_INFO(dev_priv)->has_dmc)
-#define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)
+#define HAS_DMC(i915)	(RUNTIME_INFO(i915)->has_dmc)
+#define HAS_DSB(i915)	(INTEL_INFO(i915)->display.has_dsb)
 #define HAS_DSC(__i915)		(RUNTIME_INFO(__i915)->has_dsc)
 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 
-#define HAS_HECI_PXP(dev_priv) \
-	(INTEL_INFO(dev_priv)->has_heci_pxp)
+#define HAS_HECI_PXP(i915) \
+	(INTEL_INFO(i915)->has_heci_pxp)
 
-#define HAS_HECI_GSCFI(dev_priv) \
-	(INTEL_INFO(dev_priv)->has_heci_gscfi)
+#define HAS_HECI_GSCFI(i915) \
+	(INTEL_INFO(i915)->has_heci_gscfi)
 
-#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
+#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
 
 #define HAS_MSO(i915)		(DISPLAY_VER(i915) >= 12)
 
-#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
-#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
+#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
+#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
 
-#define HAS_OA_BPC_REPORTING(dev_priv) \
-	(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
-#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
-	(INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
-#define HAS_OAM(dev_priv) \
-	(INTEL_INFO(dev_priv)->has_oam)
+#define HAS_OA_BPC_REPORTING(i915) \
+	(INTEL_INFO(i915)->has_oa_bpc_reporting)
+#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
+	(INTEL_INFO(i915)->has_oa_slice_contrib_limits)
+#define HAS_OAM(i915) \
+	(INTEL_INFO(i915)->has_oam)
 
 /*
  * Set this flag, when platform requires 64K GTT page sizes or larger for
  * device local memory access.
  */
-#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
 
-#define HAS_IPC(dev_priv)		(INTEL_INFO(dev_priv)->display.has_ipc)
-#define HAS_SAGV(dev_priv)		(DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv))
+#define HAS_IPC(i915)		(INTEL_INFO(i915)->display.has_ipc)
+#define HAS_SAGV(i915)		(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
 
 #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
 
-#define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)
+#define HAS_EXTRA_GT_LIST(i915)   (INTEL_INFO(i915)->extra_gt_list)
 
 /*
  * Platform has the dedicated compression control state for each lmem surfaces
  * stored in lmem to support the 3D and media compression formats.
  */
-#define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
+#define HAS_FLAT_CCS(i915)   (INTEL_INFO(i915)->has_flat_ccs)
 
-#define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
+#define HAS_GT_UC(i915)	(INTEL_INFO(i915)->has_gt_uc)
 
-#define HAS_POOLED_EU(dev_priv)	(RUNTIME_INFO(dev_priv)->has_pooled_eu)
+#define HAS_POOLED_EU(i915)	(RUNTIME_INFO(i915)->has_pooled_eu)
 
-#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
+#define HAS_GLOBAL_MOCS_REGISTERS(i915)	(INTEL_INFO(i915)->has_global_mocs)
 
-#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
+#define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch)
 
 #define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)
 
-#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
+#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
 
 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
 
 /* DPF == dynamic parity feature */
-#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
-#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
-				 2 : HAS_L3_DPF(dev_priv))
+#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
+#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
+				 2 : HAS_L3_DPF(i915))
 
-#define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
+#define INTEL_NUM_PIPES(i915) (hweight8(RUNTIME_INFO(i915)->pipe_mask))
 
-#define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
+#define HAS_DISPLAY(i915) (RUNTIME_INFO(i915)->pipe_mask != 0)
 
 #define HAS_VRR(i915)	(DISPLAY_VER(i915) >= 11)
 
 #define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)
 
 /* Only valid when HAS_DISPLAY() is true */
-#define INTEL_DISPLAY_ENABLED(dev_priv) \
-	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),		\
-	 !(dev_priv)->params.disable_display &&				\
-	 !intel_opregion_headless_sku(dev_priv))
+#define INTEL_DISPLAY_ENABLED(i915) \
+	(drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)),		\
+	 !(i915)->params.disable_display &&				\
+	 !intel_opregion_headless_sku(i915))
 
-#define HAS_GUC_DEPRIVILEGE(dev_priv) \
-	(INTEL_INFO(dev_priv)->has_guc_deprivilege)
+#define HAS_GUC_DEPRIVILEGE(i915) \
+	(INTEL_INFO(i915)->has_guc_deprivilege)
 
-#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
-					      IS_ALDERLAKE_S(dev_priv))
+#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || \
+					      IS_ALDERLAKE_S(i915))
 
 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 
-- 
2.40.0

Re: [Intel-gfx] [PATCH 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure

[Rodrigo Vivi]

On Fri, Apr 21, 2023 at 03:46:54PM +0200, Andi Shyti wrote:
> In the process of renaming all instances of 'dev_priv' to 'i915',
> start using 'i915' within the 'drm_i915_file_private' structure.

The patch looks good but the commit message seems off to me...

One thing we need to take care with mass conversions of dev_priv
to i915 is to ensure we are not converting the implicit declarations,
since we want to kill that. But on a quick glance it looks fine.

Did you generated this with full s/dev_priv/i915 in i915_drv.h?

> 
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 458 ++++++++++++++++----------------
>  1 file changed, 229 insertions(+), 229 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c16f8a3cd914f..14c5338c96a6b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -407,11 +407,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>  	     (engine__) && (engine__)->uabi_class == (class__); \
>  	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
>  
> -#define INTEL_INFO(dev_priv)	(&(dev_priv)->__info)
> -#define RUNTIME_INFO(dev_priv)	(&(dev_priv)->__runtime)
> -#define DRIVER_CAPS(dev_priv)	(&(dev_priv)->caps)
> +#define INTEL_INFO(i915)	(&(i915)->__info)
> +#define RUNTIME_INFO(i915)	(&(i915)->__runtime)
> +#define DRIVER_CAPS(i915)	(&(i915)->caps)
>  
> -#define INTEL_DEVID(dev_priv)	(RUNTIME_INFO(dev_priv)->device_id)
> +#define INTEL_DEVID(i915)	(RUNTIME_INFO(i915)->device_id)
>  
>  #define IP_VER(ver, rel)		((ver) << 8 | (rel))
>  
> @@ -431,7 +431,7 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
>  #define IS_DISPLAY_VER(i915, from, until) \
>  	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
>  
> -#define INTEL_REVID(dev_priv)	(to_pci_dev((dev_priv)->drm.dev)->revision)
> +#define INTEL_REVID(i915)	(to_pci_dev((i915)->drm.dev)->revision)
>  
>  #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
>  #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
> @@ -516,135 +516,135 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  	return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
>  }
>  
> -#define IS_MOBILE(dev_priv)	(INTEL_INFO(dev_priv)->is_mobile)
> -#define IS_DGFX(dev_priv)   (INTEL_INFO(dev_priv)->is_dgfx)
> -
> -#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
> -#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
> -#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
> -#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
> -#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
> -#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
> -#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
> -#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
> -#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
> -#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
> -#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
> -#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
> -#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
> -#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
> -#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
> -#define IS_IRONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IRONLAKE)
> -#define IS_IRONLAKE_M(dev_priv) \
> -	(IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv))
> -#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE)
> -#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
> -#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 1)
> -#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
> -#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
> -#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
> -#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
> -#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
> -#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
> -#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
> -#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
> -#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
> -#define IS_COMETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COMETLAKE)
> -#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> -#define IS_JSL_EHL(dev_priv)	(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \
> -				IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE))
> -#define IS_TIGERLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> -#define IS_ROCKETLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> -#define IS_DG1(dev_priv)        IS_PLATFORM(dev_priv, INTEL_DG1)
> -#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
> -#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
> -#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
> -#define IS_DG2(dev_priv)	IS_PLATFORM(dev_priv, INTEL_DG2)
> -#define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, INTEL_PONTEVECCHIO)
> -#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_METEORLAKE)
> -
> -#define IS_METEORLAKE_M(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> -#define IS_METEORLAKE_P(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
> -#define IS_DG2_G10(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
> -#define IS_DG2_G11(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
> -#define IS_DG2_G12(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
> -#define IS_ADLS_RPLS(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> -#define IS_ADLP_N(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> -#define IS_ADLP_RPLP(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> -#define IS_ADLP_RPLU(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> -#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> -				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> -#define IS_BDW_ULT(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
> -#define IS_BDW_ULX(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
> -#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_HSW_ULT(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
> -#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_HSW_GT1(dev_priv)	(IS_HASWELL(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 1)
> +#define IS_MOBILE(i915)	(INTEL_INFO(i915)->is_mobile)
> +#define IS_DGFX(i915)   (INTEL_INFO(i915)->is_dgfx)
> +
> +#define IS_I830(i915)	IS_PLATFORM(i915, INTEL_I830)
> +#define IS_I845G(i915)	IS_PLATFORM(i915, INTEL_I845G)
> +#define IS_I85X(i915)	IS_PLATFORM(i915, INTEL_I85X)
> +#define IS_I865G(i915)	IS_PLATFORM(i915, INTEL_I865G)
> +#define IS_I915G(i915)	IS_PLATFORM(i915, INTEL_I915G)
> +#define IS_I915GM(i915)	IS_PLATFORM(i915, INTEL_I915GM)
> +#define IS_I945G(i915)	IS_PLATFORM(i915, INTEL_I945G)
> +#define IS_I945GM(i915)	IS_PLATFORM(i915, INTEL_I945GM)
> +#define IS_I965G(i915)	IS_PLATFORM(i915, INTEL_I965G)
> +#define IS_I965GM(i915)	IS_PLATFORM(i915, INTEL_I965GM)
> +#define IS_G45(i915)	IS_PLATFORM(i915, INTEL_G45)
> +#define IS_GM45(i915)	IS_PLATFORM(i915, INTEL_GM45)
> +#define IS_G4X(i915)	(IS_G45(i915) || IS_GM45(i915))
> +#define IS_PINEVIEW(i915)	IS_PLATFORM(i915, INTEL_PINEVIEW)
> +#define IS_G33(i915)	IS_PLATFORM(i915, INTEL_G33)
> +#define IS_IRONLAKE(i915)	IS_PLATFORM(i915, INTEL_IRONLAKE)
> +#define IS_IRONLAKE_M(i915) \
> +	(IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
> +#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
> +#define IS_IVYBRIDGE(i915)	IS_PLATFORM(i915, INTEL_IVYBRIDGE)
> +#define IS_IVB_GT1(i915)	(IS_IVYBRIDGE(i915) && \
> +				 INTEL_INFO(i915)->gt == 1)
> +#define IS_VALLEYVIEW(i915)	IS_PLATFORM(i915, INTEL_VALLEYVIEW)
> +#define IS_CHERRYVIEW(i915)	IS_PLATFORM(i915, INTEL_CHERRYVIEW)
> +#define IS_HASWELL(i915)	IS_PLATFORM(i915, INTEL_HASWELL)
> +#define IS_BROADWELL(i915)	IS_PLATFORM(i915, INTEL_BROADWELL)
> +#define IS_SKYLAKE(i915)	IS_PLATFORM(i915, INTEL_SKYLAKE)
> +#define IS_BROXTON(i915)	IS_PLATFORM(i915, INTEL_BROXTON)
> +#define IS_KABYLAKE(i915)	IS_PLATFORM(i915, INTEL_KABYLAKE)
> +#define IS_GEMINILAKE(i915)	IS_PLATFORM(i915, INTEL_GEMINILAKE)
> +#define IS_COFFEELAKE(i915)	IS_PLATFORM(i915, INTEL_COFFEELAKE)
> +#define IS_COMETLAKE(i915)	IS_PLATFORM(i915, INTEL_COMETLAKE)
> +#define IS_ICELAKE(i915)	IS_PLATFORM(i915, INTEL_ICELAKE)
> +#define IS_JSL_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
> +				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
> +#define IS_TIGERLAKE(i915)	IS_PLATFORM(i915, INTEL_TIGERLAKE)
> +#define IS_ROCKETLAKE(i915)	IS_PLATFORM(i915, INTEL_ROCKETLAKE)
> +#define IS_DG1(i915)        IS_PLATFORM(i915, INTEL_DG1)
> +#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
> +#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
> +#define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
> +#define IS_DG2(i915)	IS_PLATFORM(i915, INTEL_DG2)
> +#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
> +#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
> +
> +#define IS_METEORLAKE_M(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
> +#define IS_METEORLAKE_P(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
> +#define IS_DG2_G10(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
> +#define IS_DG2_G11(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
> +#define IS_DG2_G12(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
> +#define IS_ADLS_RPLS(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
> +#define IS_ADLP_N(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
> +#define IS_ADLP_RPLP(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
> +#define IS_ADLP_RPLU(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
> +#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
> +				    (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
> +#define IS_BDW_ULT(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
> +#define IS_BDW_ULX(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
> +#define IS_BDW_GT3(i915)	(IS_BROADWELL(i915) && \
> +				 INTEL_INFO(i915)->gt == 3)
> +#define IS_HSW_ULT(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
> +#define IS_HSW_GT3(i915)	(IS_HASWELL(i915) && \
> +				 INTEL_INFO(i915)->gt == 3)
> +#define IS_HSW_GT1(i915)	(IS_HASWELL(i915) && \
> +				 INTEL_INFO(i915)->gt == 1)
>  /* ULX machines are also considered ULT. */
> -#define IS_HSW_ULX(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
> -#define IS_SKL_ULT(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
> -#define IS_SKL_ULX(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
> -#define IS_KBL_ULT(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
> -#define IS_KBL_ULX(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
> -#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 2)
> -#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 4)
> -#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 2)
> -#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 3)
> -#define IS_CFL_ULT(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
> -#define IS_CFL_ULX(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
> -#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 2)
> -#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 3)
> -
> -#define IS_CML_ULT(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
> -#define IS_CML_ULX(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
> -#define IS_CML_GT2(dev_priv)	(IS_COMETLAKE(dev_priv) && \
> -				 INTEL_INFO(dev_priv)->gt == 2)
> -
> -#define IS_ICL_WITH_PORT_F(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
> -
> -#define IS_TGL_UY(dev_priv) \
> -	IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
> +#define IS_HSW_ULX(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
> +#define IS_SKL_ULT(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
> +#define IS_SKL_ULX(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
> +#define IS_KBL_ULT(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
> +#define IS_KBL_ULX(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
> +#define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
> +				 INTEL_INFO(i915)->gt == 2)
> +#define IS_SKL_GT3(i915)	(IS_SKYLAKE(i915) && \
> +				 INTEL_INFO(i915)->gt == 3)
> +#define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
> +				 INTEL_INFO(i915)->gt == 4)
> +#define IS_KBL_GT2(i915)	(IS_KABYLAKE(i915) && \
> +				 INTEL_INFO(i915)->gt == 2)
> +#define IS_KBL_GT3(i915)	(IS_KABYLAKE(i915) && \
> +				 INTEL_INFO(i915)->gt == 3)
> +#define IS_CFL_ULT(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
> +#define IS_CFL_ULX(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
> +#define IS_CFL_GT2(i915)	(IS_COFFEELAKE(i915) && \
> +				 INTEL_INFO(i915)->gt == 2)
> +#define IS_CFL_GT3(i915)	(IS_COFFEELAKE(i915) && \
> +				 INTEL_INFO(i915)->gt == 3)
> +
> +#define IS_CML_ULT(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
> +#define IS_CML_ULX(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
> +#define IS_CML_GT2(i915)	(IS_COMETLAKE(i915) && \
> +				 INTEL_INFO(i915)->gt == 2)
> +
> +#define IS_ICL_WITH_PORT_F(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
> +
> +#define IS_TGL_UY(i915) \
> +	IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
>  
>  #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until))
>  
> -#define IS_KBL_GRAPHICS_STEP(dev_priv, since, until) \
> -	(IS_KABYLAKE(dev_priv) && IS_GRAPHICS_STEP(dev_priv, since, until))
> -#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \
> -	(IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until))
> +#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
> +	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))
> +#define IS_KBL_DISPLAY_STEP(i915, since, until) \
> +	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))
>  
>  #define IS_JSL_EHL_GRAPHICS_STEP(p, since, until) \
>  	(IS_JSL_EHL(p) && IS_GRAPHICS_STEP(p, since, until))
> @@ -720,9 +720,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  	(IS_PONTEVECCHIO(__i915) && \
>  	 IS_GRAPHICS_STEP(__i915, since, until))
>  
> -#define IS_LP(dev_priv)		(INTEL_INFO(dev_priv)->is_lp)
> -#define IS_GEN9_LP(dev_priv)	(GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
> -#define IS_GEN9_BC(dev_priv)	(GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
> +#define IS_LP(i915)		(INTEL_INFO(i915)->is_lp)
> +#define IS_GEN9_LP(i915)	(GRAPHICS_VER(i915) == 9 && IS_LP(i915))
> +#define IS_GEN9_BC(i915)	(GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
>  
>  #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
>  #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
> @@ -747,180 +747,180 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define CCS_MASK(gt) \
>  	ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
>  
> -#define HAS_MEDIA_RATIO_MODE(dev_priv) (INTEL_INFO(dev_priv)->has_media_ratio_mode)
> +#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
>  
>  /*
>   * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
>   * All later gens can run the final buffer from the ppgtt
>   */
> -#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
> +#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
>  
> -#define HAS_LLC(dev_priv)	(INTEL_INFO(dev_priv)->has_llc)
> -#define HAS_4TILE(dev_priv)	(INTEL_INFO(dev_priv)->has_4tile)
> -#define HAS_SNOOP(dev_priv)	(INTEL_INFO(dev_priv)->has_snoop)
> -#define HAS_EDRAM(dev_priv)	((dev_priv)->edram_size_mb)
> -#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
> -#define HAS_WT(dev_priv)	HAS_EDRAM(dev_priv)
> +#define HAS_LLC(i915)	(INTEL_INFO(i915)->has_llc)
> +#define HAS_4TILE(i915)	(INTEL_INFO(i915)->has_4tile)
> +#define HAS_SNOOP(i915)	(INTEL_INFO(i915)->has_snoop)
> +#define HAS_EDRAM(i915)	((i915)->edram_size_mb)
> +#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
> +#define HAS_WT(i915)	HAS_EDRAM(i915)
>  
> -#define HWS_NEEDS_PHYSICAL(dev_priv)	(INTEL_INFO(dev_priv)->hws_needs_physical)
> +#define HWS_NEEDS_PHYSICAL(i915)	(INTEL_INFO(i915)->hws_needs_physical)
>  
> -#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
> -		(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
> -#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
> -		(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
> +#define HAS_LOGICAL_RING_CONTEXTS(i915) \
> +		(INTEL_INFO(i915)->has_logical_ring_contexts)
> +#define HAS_LOGICAL_RING_ELSQ(i915) \
> +		(INTEL_INFO(i915)->has_logical_ring_elsq)
>  
> -#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
> +#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
>  
> -#define INTEL_PPGTT(dev_priv) (RUNTIME_INFO(dev_priv)->ppgtt_type)
> -#define HAS_PPGTT(dev_priv) \
> -	(INTEL_PPGTT(dev_priv) != INTEL_PPGTT_NONE)
> -#define HAS_FULL_PPGTT(dev_priv) \
> -	(INTEL_PPGTT(dev_priv) >= INTEL_PPGTT_FULL)
> +#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
> +#define HAS_PPGTT(i915) \
> +	(INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
> +#define HAS_FULL_PPGTT(i915) \
> +	(INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
>  
> -#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
> +#define HAS_PAGE_SIZES(i915, sizes) ({ \
>  	GEM_BUG_ON((sizes) == 0); \
> -	((sizes) & ~RUNTIME_INFO(dev_priv)->page_sizes) == 0; \
> +	((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
>  })
>  
> -#define HAS_OVERLAY(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_overlay)
> -#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
> -		(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
> +#define HAS_OVERLAY(i915)		 (INTEL_INFO(i915)->display.has_overlay)
> +#define OVERLAY_NEEDS_PHYSICAL(i915) \
> +		(INTEL_INFO(i915)->display.overlay_needs_physical)
>  
>  /* Early gen2 have a totally busted CS tlb and require pinned batches. */
> -#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
> +#define HAS_BROKEN_CS_TLB(i915)	(IS_I830(i915) || IS_I845G(i915))
>  
> -#define NEEDS_RC6_CTX_CORRUPTION_WA(dev_priv)	\
> -	(IS_BROADWELL(dev_priv) || GRAPHICS_VER(dev_priv) == 9)
> +#define NEEDS_RC6_CTX_CORRUPTION_WA(i915)	\
> +	(IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
>  
>  /* WaRsDisableCoarsePowerGating:skl,cnl */
> -#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv)			\
> -	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
> +#define NEEDS_WaRsDisableCoarsePowerGating(i915)			\
> +	(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))
>  
> -#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
> -#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
> -					IS_GEMINILAKE(dev_priv) || \
> -					IS_KABYLAKE(dev_priv))
> +#define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4)
> +#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 11 || \
> +					IS_GEMINILAKE(i915) || \
> +					IS_KABYLAKE(i915))
>  
>  /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
>   * rows, which changed the alignment requirements and fence programming.
>   */
> -#define HAS_128_BYTE_Y_TILING(dev_priv) (GRAPHICS_VER(dev_priv) != 2 && \
> -					 !(IS_I915G(dev_priv) || IS_I915GM(dev_priv)))
> -#define SUPPORTS_TV(dev_priv)		(INTEL_INFO(dev_priv)->display.supports_tv)
> -#define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->display.has_hotplug)
> +#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
> +					 !(IS_I915G(i915) || IS_I915GM(i915)))
> +#define SUPPORTS_TV(i915)		(INTEL_INFO(i915)->display.supports_tv)
> +#define I915_HAS_HOTPLUG(i915)	(INTEL_INFO(i915)->display.has_hotplug)
>  
> -#define HAS_FW_BLC(dev_priv)	(DISPLAY_VER(dev_priv) > 2)
> -#define HAS_FBC(dev_priv)	(RUNTIME_INFO(dev_priv)->fbc_mask != 0)
> -#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
> +#define HAS_FW_BLC(i915)	(DISPLAY_VER(i915) > 2)
> +#define HAS_FBC(i915)	(RUNTIME_INFO(i915)->fbc_mask != 0)
> +#define HAS_CUR_FBC(i915)	(!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)
>  
> -#define HAS_DPT(dev_priv)	(DISPLAY_VER(dev_priv) >= 13)
> +#define HAS_DPT(i915)	(DISPLAY_VER(i915) >= 13)
>  
> -#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
> +#define HAS_IPS(i915)	(IS_HSW_ULT(i915) || IS_BROADWELL(i915))
>  
> -#define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)
> -#define HAS_DP20(dev_priv)	(IS_DG2(dev_priv) || DISPLAY_VER(dev_priv) >= 14)
> +#define HAS_DP_MST(i915)	(INTEL_INFO(i915)->display.has_dp_mst)
> +#define HAS_DP20(i915)	(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
>  
> -#define HAS_DOUBLE_BUFFERED_M_N(dev_priv)	(DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
> +#define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
>  
> -#define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
> -#define HAS_CDCLK_SQUASH(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
> -#define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
> -#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
> -#define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
> -#define HAS_PSR_HW_TRACKING(dev_priv) \
> -	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
> -#define HAS_PSR2_SEL_FETCH(dev_priv)	 (DISPLAY_VER(dev_priv) >= 12)
> -#define HAS_TRANSCODER(dev_priv, trans)	 ((RUNTIME_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
> +#define HAS_CDCLK_CRAWL(i915)	 (INTEL_INFO(i915)->display.has_cdclk_crawl)
> +#define HAS_CDCLK_SQUASH(i915)	 (INTEL_INFO(i915)->display.has_cdclk_squash)
> +#define HAS_DDI(i915)		 (INTEL_INFO(i915)->display.has_ddi)
> +#define HAS_FPGA_DBG_UNCLAIMED(i915) (INTEL_INFO(i915)->display.has_fpga_dbg)
> +#define HAS_PSR(i915)		 (INTEL_INFO(i915)->display.has_psr)
> +#define HAS_PSR_HW_TRACKING(i915) \
> +	(INTEL_INFO(i915)->display.has_psr_hw_tracking)
> +#define HAS_PSR2_SEL_FETCH(i915)	 (DISPLAY_VER(i915) >= 12)
> +#define HAS_TRANSCODER(i915, trans)	 ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)
>  
> -#define HAS_RC6(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6)
> -#define HAS_RC6p(dev_priv)		 (INTEL_INFO(dev_priv)->has_rc6p)
> -#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
> +#define HAS_RC6(i915)		 (INTEL_INFO(i915)->has_rc6)
> +#define HAS_RC6p(i915)		 (INTEL_INFO(i915)->has_rc6p)
> +#define HAS_RC6pp(i915)		 (false) /* HW was never validated */
>  
> -#define HAS_RPS(dev_priv)	(INTEL_INFO(dev_priv)->has_rps)
> +#define HAS_RPS(i915)	(INTEL_INFO(i915)->has_rps)
>  
> -#define HAS_DMC(dev_priv)	(RUNTIME_INFO(dev_priv)->has_dmc)
> -#define HAS_DSB(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dsb)
> +#define HAS_DMC(i915)	(RUNTIME_INFO(i915)->has_dmc)
> +#define HAS_DSB(i915)	(INTEL_INFO(i915)->display.has_dsb)
>  #define HAS_DSC(__i915)		(RUNTIME_INFO(__i915)->has_dsc)
>  #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
>  
> -#define HAS_HECI_PXP(dev_priv) \
> -	(INTEL_INFO(dev_priv)->has_heci_pxp)
> +#define HAS_HECI_PXP(i915) \
> +	(INTEL_INFO(i915)->has_heci_pxp)
>  
> -#define HAS_HECI_GSCFI(dev_priv) \
> -	(INTEL_INFO(dev_priv)->has_heci_gscfi)
> +#define HAS_HECI_GSCFI(i915) \
> +	(INTEL_INFO(i915)->has_heci_gscfi)
>  
> -#define HAS_HECI_GSC(dev_priv) (HAS_HECI_PXP(dev_priv) || HAS_HECI_GSCFI(dev_priv))
> +#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
>  
>  #define HAS_MSO(i915)		(DISPLAY_VER(i915) >= 12)
>  
> -#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
> -#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
> +#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
> +#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
>  
> -#define HAS_OA_BPC_REPORTING(dev_priv) \
> -	(INTEL_INFO(dev_priv)->has_oa_bpc_reporting)
> -#define HAS_OA_SLICE_CONTRIB_LIMITS(dev_priv) \
> -	(INTEL_INFO(dev_priv)->has_oa_slice_contrib_limits)
> -#define HAS_OAM(dev_priv) \
> -	(INTEL_INFO(dev_priv)->has_oam)
> +#define HAS_OA_BPC_REPORTING(i915) \
> +	(INTEL_INFO(i915)->has_oa_bpc_reporting)
> +#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
> +	(INTEL_INFO(i915)->has_oa_slice_contrib_limits)
> +#define HAS_OAM(i915) \
> +	(INTEL_INFO(i915)->has_oam)
>  
>  /*
>   * Set this flag, when platform requires 64K GTT page sizes or larger for
>   * device local memory access.
>   */
> -#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
> +#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
>  
> -#define HAS_IPC(dev_priv)		(INTEL_INFO(dev_priv)->display.has_ipc)
> -#define HAS_SAGV(dev_priv)		(DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv))
> +#define HAS_IPC(i915)		(INTEL_INFO(i915)->display.has_ipc)
> +#define HAS_SAGV(i915)		(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
>  
>  #define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
>  #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
>  
> -#define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)
> +#define HAS_EXTRA_GT_LIST(i915)   (INTEL_INFO(i915)->extra_gt_list)
>  
>  /*
>   * Platform has the dedicated compression control state for each lmem surfaces
>   * stored in lmem to support the 3D and media compression formats.
>   */
> -#define HAS_FLAT_CCS(dev_priv)   (INTEL_INFO(dev_priv)->has_flat_ccs)
> +#define HAS_FLAT_CCS(i915)   (INTEL_INFO(i915)->has_flat_ccs)
>  
> -#define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
> +#define HAS_GT_UC(i915)	(INTEL_INFO(i915)->has_gt_uc)
>  
> -#define HAS_POOLED_EU(dev_priv)	(RUNTIME_INFO(dev_priv)->has_pooled_eu)
> +#define HAS_POOLED_EU(i915)	(RUNTIME_INFO(i915)->has_pooled_eu)
>  
> -#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
> +#define HAS_GLOBAL_MOCS_REGISTERS(i915)	(INTEL_INFO(i915)->has_global_mocs)
>  
> -#define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
> +#define HAS_GMCH(i915) (INTEL_INFO(i915)->display.has_gmch)
>  
>  #define HAS_GMD_ID(i915)	(INTEL_INFO(i915)->has_gmd_id)
>  
> -#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
> +#define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10))
>  
>  #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
>  
>  /* DPF == dynamic parity feature */
> -#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
> -#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
> -				 2 : HAS_L3_DPF(dev_priv))
> +#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
> +#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
> +				 2 : HAS_L3_DPF(i915))
>  
> -#define INTEL_NUM_PIPES(dev_priv) (hweight8(RUNTIME_INFO(dev_priv)->pipe_mask))
> +#define INTEL_NUM_PIPES(i915) (hweight8(RUNTIME_INFO(i915)->pipe_mask))
>  
> -#define HAS_DISPLAY(dev_priv) (RUNTIME_INFO(dev_priv)->pipe_mask != 0)
> +#define HAS_DISPLAY(i915) (RUNTIME_INFO(i915)->pipe_mask != 0)
>  
>  #define HAS_VRR(i915)	(DISPLAY_VER(i915) >= 11)
>  
>  #define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)
>  
>  /* Only valid when HAS_DISPLAY() is true */
> -#define INTEL_DISPLAY_ENABLED(dev_priv) \
> -	(drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),		\
> -	 !(dev_priv)->params.disable_display &&				\
> -	 !intel_opregion_headless_sku(dev_priv))
> +#define INTEL_DISPLAY_ENABLED(i915) \
> +	(drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)),		\
> +	 !(i915)->params.disable_display &&				\
> +	 !intel_opregion_headless_sku(i915))
>  
> -#define HAS_GUC_DEPRIVILEGE(dev_priv) \
> -	(INTEL_INFO(dev_priv)->has_guc_deprivilege)
> +#define HAS_GUC_DEPRIVILEGE(i915) \
> +	(INTEL_INFO(i915)->has_guc_deprivilege)
>  
> -#define HAS_D12_PLANE_MINIMIZATION(dev_priv) (IS_ROCKETLAKE(dev_priv) || \
> -					      IS_ALDERLAKE_S(dev_priv))
> +#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || \
> +					      IS_ALDERLAKE_S(i915))
>  
>  #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
>  
> -- 
> 2.40.0
> 

Re: [Intel-gfx] [PATCH 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure

[Andi Shyti]

On Fri, Apr 21, 2023 at 10:07:28AM -0400, Rodrigo Vivi wrote:
> On Fri, Apr 21, 2023 at 03:46:54PM +0200, Andi Shyti wrote:
> > In the process of renaming all instances of 'dev_priv' to 'i915',
> > start using 'i915' within the 'drm_i915_file_private' structure.
> 
> The patch looks good but the commit message seems off to me...

Will rephrase.

> One thing we need to take care with mass conversions of dev_priv
> to i915 is to ensure we are not converting the implicit declarations,
> since we want to kill that. But on a quick glance it looks fine.
> 
> Did you generated this with full s/dev_priv/i915 in i915_drv.h?

Yes, I did such swap in i915_drv.h but I checked each line not to
break anything.  In this file it's OK to do a /dev_priv/i915/
change.

It will be different with i915_irq.h where dev_priv is embedded
in the define.

I there is anything off it wouldn't have compiled and anyway,
CI will warn.

Thanks, Rodrigo!
Andi

Re: [Intel-gfx] [PATCH 2/2] drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure

[Andrzej Hajda]

On 21.04.2023 15:46, Andi Shyti wrote:
> In the process of renaming all instances of 'dev_priv' to 'i915',
> start using 'i915' within the 'drm_i915_file_private' structure.
> 
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Use i915 instead of dev_priv

[Patchwork]

== Series Details ==

Series: Use i915 instead of dev_priv
URL   : https://patchwork.freedesktop.org/series/116816/
State : warning

== Summary ==

Error: dim checkpatch failed
4f2ff1f3fb31 drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
-:22: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#22: FILE: drivers/gpu/drm/i915/i915_drv.h:384:
+#define for_each_engine(engine__, gt__, id__) \
 	for ((id__) = 0; \
 	     (id__) < I915_NUM_ENGINES; \
 	     (id__)++) \
+		for_each_if ((engine__) = (gt__)->engine[(id__)])

-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id__' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_drv.h:384:
+#define for_each_engine(engine__, gt__, id__) \
 	for ((id__) = 0; \
 	     (id__) < I915_NUM_ENGINES; \
 	     (id__)++) \
+		for_each_if ((engine__) = (gt__)->engine[(id__)])

-:27: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#27: FILE: drivers/gpu/drm/i915/i915_drv.h:388:
+		for_each_if ((engine__) = (gt__)->engine[(id__)])

total: 1 errors, 1 warnings, 1 checks, 13 lines checked
51c8ab2e0ecd drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure
-:140: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#140: FILE: drivers/gpu/drm/i915/i915_drv.h:534:
+#define IS_G4X(i915)	(IS_G45(i915) || IS_GM45(i915))

-:144: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#144: FILE: drivers/gpu/drm/i915/i915_drv.h:538:
+#define IS_IRONLAKE_M(i915) \
+	(IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))

-:148: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#148: FILE: drivers/gpu/drm/i915/i915_drv.h:542:
+#define IS_IVB_GT1(i915)	(IS_IVYBRIDGE(i915) && \
+				 INTEL_INFO(i915)->gt == 1)

-:161: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#161: FILE: drivers/gpu/drm/i915/i915_drv.h:555:
+#define IS_JSL_EHL(i915)	(IS_PLATFORM(i915, INTEL_JASPERLAKE) || \
+				IS_PLATFORM(i915, INTEL_ELKHARTLAKE))

-:191: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#191: FILE: drivers/gpu/drm/i915/i915_drv.h:585:
+#define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \
+				    (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)

-:197: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#197: FILE: drivers/gpu/drm/i915/i915_drv.h:591:
+#define IS_BDW_GT3(i915)	(IS_BROADWELL(i915) && \
+				 INTEL_INFO(i915)->gt == 3)

-:201: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#201: FILE: drivers/gpu/drm/i915/i915_drv.h:595:
+#define IS_HSW_GT3(i915)	(IS_HASWELL(i915) && \
+				 INTEL_INFO(i915)->gt == 3)

-:203: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#203: FILE: drivers/gpu/drm/i915/i915_drv.h:597:
+#define IS_HSW_GT1(i915)	(IS_HASWELL(i915) && \
+				 INTEL_INFO(i915)->gt == 1)

-:257: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#257: FILE: drivers/gpu/drm/i915/i915_drv.h:610:
+#define IS_SKL_GT2(i915)	(IS_SKYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 2)

-:259: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#259: FILE: drivers/gpu/drm/i915/i915_drv.h:612:
+#define IS_SKL_GT3(i915)	(IS_SKYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 3)

-:261: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#261: FILE: drivers/gpu/drm/i915/i915_drv.h:614:
+#define IS_SKL_GT4(i915)	(IS_SKYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 4)

-:263: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#263: FILE: drivers/gpu/drm/i915/i915_drv.h:616:
+#define IS_KBL_GT2(i915)	(IS_KABYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 2)

-:265: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#265: FILE: drivers/gpu/drm/i915/i915_drv.h:618:
+#define IS_KBL_GT3(i915)	(IS_KABYLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 3)

-:271: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#271: FILE: drivers/gpu/drm/i915/i915_drv.h:624:
+#define IS_CFL_GT2(i915)	(IS_COFFEELAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 2)

-:273: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#273: FILE: drivers/gpu/drm/i915/i915_drv.h:626:
+#define IS_CFL_GT3(i915)	(IS_COFFEELAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 3)

-:280: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#280: FILE: drivers/gpu/drm/i915/i915_drv.h:633:
+#define IS_CML_GT2(i915)	(IS_COMETLAKE(i915) && \
+				 INTEL_INFO(i915)->gt == 2)

-:295: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#295: FILE: drivers/gpu/drm/i915/i915_drv.h:644:
+#define IS_KBL_GRAPHICS_STEP(i915, since, until) \
+	(IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, since, until))

-:297: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#297: FILE: drivers/gpu/drm/i915/i915_drv.h:646:
+#define IS_KBL_DISPLAY_STEP(i915, since, until) \
+	(IS_KABYLAKE(i915) && IS_DISPLAY_STEP(i915, since, until))

-:310: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#310: FILE: drivers/gpu/drm/i915/i915_drv.h:724:
+#define IS_GEN9_LP(i915)	(GRAPHICS_VER(i915) == 9 && IS_LP(i915))

-:311: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#311: FILE: drivers/gpu/drm/i915/i915_drv.h:725:
+#define IS_GEN9_BC(i915)	(GRAPHICS_VER(i915) == 9 && !IS_LP(i915))

-:369: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'sizes' - possible side-effects?
#369: FILE: drivers/gpu/drm/i915/i915_drv.h:780:
+#define HAS_PAGE_SIZES(i915, sizes) ({ \
 	GEM_BUG_ON((sizes) == 0); \
+	((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
 })

-:384: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#384: FILE: drivers/gpu/drm/i915/i915_drv.h:790:
+#define HAS_BROKEN_CS_TLB(i915)	(IS_I830(i915) || IS_I845G(i915))

-:388: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#388: FILE: drivers/gpu/drm/i915/i915_drv.h:792:
+#define NEEDS_RC6_CTX_CORRUPTION_WA(i915)	\
+	(IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)

-:394: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#394: FILE: drivers/gpu/drm/i915/i915_drv.h:796:
+#define NEEDS_WaRsDisableCoarsePowerGating(i915)			\
+	(IS_SKL_GT3(i915) || IS_SKL_GT4(i915))

-:402: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#402: FILE: drivers/gpu/drm/i915/i915_drv.h:800:
+#define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 11 || \
+					IS_GEMINILAKE(i915) || \
+					IS_KABYLAKE(i915))

-:413: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#413: FILE: drivers/gpu/drm/i915/i915_drv.h:807:
+#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
+					 !(IS_I915G(i915) || IS_I915GM(i915)))

-:423: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#423: FILE: drivers/gpu/drm/i915/i915_drv.h:814:
+#define HAS_CUR_FBC(i915)	(!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7)

-:429: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#429: FILE: drivers/gpu/drm/i915/i915_drv.h:818:
+#define HAS_IPS(i915)	(IS_HSW_ULT(i915) || IS_BROADWELL(i915))

-:434: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#434: FILE: drivers/gpu/drm/i915/i915_drv.h:821:
+#define HAS_DP20(i915)	(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)

-:437: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#437: FILE: drivers/gpu/drm/i915/i915_drv.h:823:
+#define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))

-:456: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#456: FILE: drivers/gpu/drm/i915/i915_drv.h:833:
+#define HAS_TRANSCODER(i915, trans)	 ((RUNTIME_INFO(i915)->cpu_transcoder_mask & BIT(trans)) != 0)

-:486: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#486: FILE: drivers/gpu/drm/i915/i915_drv.h:852:
+#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))

-:518: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#518: FILE: drivers/gpu/drm/i915/i915_drv.h:873:
+#define HAS_SAGV(i915)		(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))

-:557: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#557: FILE: drivers/gpu/drm/i915/i915_drv.h:902:
+#define NUM_L3_SLICES(i915) (IS_HSW_GT3(i915) ? \
+				 2 : HAS_L3_DPF(i915))

-:575: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#575: FILE: drivers/gpu/drm/i915/i915_drv.h:914:
+#define INTEL_DISPLAY_ENABLED(i915) \
+	(drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)),		\
+	 !(i915)->params.disable_display &&				\
+	 !intel_opregion_headless_sku(i915))

-:587: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#587: FILE: drivers/gpu/drm/i915/i915_drv.h:922:
+#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || \
+					      IS_ALDERLAKE_S(i915))

total: 0 errors, 1 warnings, 35 checks, 571 lines checked

[Intel-gfx] ✓ Fi.CI.BAT: success for Use i915 instead of dev_priv

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4373 bytes --]

== Series Details ==

Series: Use i915 instead of dev_priv
URL   : https://patchwork.freedesktop.org/series/116816/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_13041 -> Patchwork_116816v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/index.html

Participating hosts (37 -> 36)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_116816v1:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@requests:
    - {bat-mtlp-8}:       [ABORT][1] ([i915#4983]) -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@i915_selftest@live@requests.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-mtlp-8/igt@i915_selftest@live@requests.html

  
Known issues
------------

  Here are the changes found in Patchwork_116816v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - bat-rpls-1:         [PASS][3] -> [ABORT][4] ([i915#6687] / [i915#7978])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@kms_pipe_crc_basic@read-crc:
    - bat-adlp-9:         NOTRUN -> [SKIP][5] ([i915#3546]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-adlp-9/igt@kms_pipe_crc_basic@read-crc.html

  
#### Possible fixes ####

  * igt@gem_exec_parallel@engines@basic:
    - {bat-mtlp-8}:       [FAIL][6] -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@gem_exec_parallel@engines@basic.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-mtlp-8/igt@gem_exec_parallel@engines@basic.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - fi-bsw-n3050:       [DMESG-WARN][8] ([i915#1982]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/fi-bsw-n3050/igt@i915_suspend@basic-s2idle-without-i915.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/fi-bsw-n3050/igt@i915_suspend@basic-s2idle-without-i915.html

  
#### Warnings ####

  * igt@i915_selftest@live@slpc:
    - bat-rpls-1:         [DMESG-FAIL][10] ([i915#6997]) -> [DMESG-FAIL][11] ([i915#6367] / [i915#7996])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-rpls-1/igt@i915_selftest@live@slpc.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/bat-rpls-1/igt@i915_selftest@live@slpc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996


Build changes
-------------

  * Linux: CI_DRM_13041 -> Patchwork_116816v1

  CI-20190529: 20190529
  CI_DRM_13041: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_116816v1: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

b2b666af4dd2 drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv structure
b11418a94280 drm/i915/i915_drv: Use proper parameter naming in for_each_gt()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116816v1/index.html

[-- Attachment #2: Type: text/html, Size: 5129 bytes --]

Re: [Intel-gfx] [PATCH 0/2] Use i915 instead of dev_priv

[Andi Shyti]

Hi,

On Fri, Apr 21, 2023 at 03:46:52PM +0200, Andi Shyti wrote:
> Hi,
> 
> just another "Friday patch". While reviewing some patches from
> Tejas I found a bit confusing the use of dev_priv__ inside the
> for_each_engine(), perhaps it should be moved inside the gt/?
> 
> As I was at it I made the /dev_priv/i915/ change which is still
> harmless. Next in queue is to change the i915_irq.h, which is a
> bit tricky (but not much) as the "dev_priv" is hardcoded inside
> some defines.
> 
> Andi
> 
> Andi Shyti (2):
>   drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
>   drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv
>     structure
> 
>  drivers/gpu/drm/i915/i915_drv.h | 462 ++++++++++++++++----------------
>  1 file changed, 231 insertions(+), 231 deletions(-)

Pushed to dmr-intel-gt-next.

Thanks Rodrigo and Andrzej for your review.

Andi

Re: [Intel-gfx] [PATCH 0/2] Use i915 instead of dev_priv

[Jani Nikula]

On Sun, 23 Apr 2023, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> Hi,
>
> On Fri, Apr 21, 2023 at 03:46:52PM +0200, Andi Shyti wrote:
>> Hi,
>> 
>> just another "Friday patch". While reviewing some patches from
>> Tejas I found a bit confusing the use of dev_priv__ inside the
>> for_each_engine(), perhaps it should be moved inside the gt/?
>> 
>> As I was at it I made the /dev_priv/i915/ change which is still
>> harmless. Next in queue is to change the i915_irq.h, which is a
>> bit tricky (but not much) as the "dev_priv" is hardcoded inside
>> some defines.
>> 
>> Andi
>> 
>> Andi Shyti (2):
>>   drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
>>   drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv
>>     structure
>> 
>>  drivers/gpu/drm/i915/i915_drv.h | 462 ++++++++++++++++----------------
>>  1 file changed, 231 insertions(+), 231 deletions(-)
>
> Pushed to dmr-intel-gt-next.

That's going to create problems for us for weeks to come. I'm actually
tempted to ask Joonas or Tvrtko to just force push that out of there.

Only use drm-intel-gt-next for stuff that's specifically about gt or
gem, and touches files used by gt or gem only. For everything else, use
drm-intel-next. When in doubt, err on the side of drm-intel-next.

It's not enough that one of the patches changes parameters of
for_each_gt() macro.

We can cross-merge drm-intel-next to drm-intel-gt-next, but we can't
cross-merge drm-intel-gt-next to drm-intel-next. This means the only way
to sync those i915_drv.h changes to drm-intel-next is to have a
drm-intel-gt-next pull request merged to drm-next, and then backmerged
to drm-intel-next. That's not going to happen for several weeks.

Any change aimed at drm-intel-next that conflicts with the i915_drv.h
changes will now be pending on those merges.

BR,
Jani.



>
> Thanks Rodrigo and Andrzej for your review.
>
> Andi

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/2] Use i915 instead of dev_priv

[Andi Shyti]

Hi Jani,

> >> just another "Friday patch". While reviewing some patches from
> >> Tejas I found a bit confusing the use of dev_priv__ inside the
> >> for_each_engine(), perhaps it should be moved inside the gt/?
> >> 
> >> As I was at it I made the /dev_priv/i915/ change which is still
> >> harmless. Next in queue is to change the i915_irq.h, which is a
> >> bit tricky (but not much) as the "dev_priv" is hardcoded inside
> >> some defines.
> >> 
> >> Andi
> >> 
> >> Andi Shyti (2):
> >>   drm/i915/i915_drv: Use proper parameter naming in for_each_gt()
> >>   drm/i915/i915_drv: Use i915 instead of dev_priv insied the file_priv
> >>     structure
> >> 
> >>  drivers/gpu/drm/i915/i915_drv.h | 462 ++++++++++++++++----------------
> >>  1 file changed, 231 insertions(+), 231 deletions(-)
> >
> > Pushed to dmr-intel-gt-next.
> 
> That's going to create problems for us for weeks to come. I'm actually
> tempted to ask Joonas or Tvrtko to just force push that out of there.
> 
> Only use drm-intel-gt-next for stuff that's specifically about gt or
> gem, and touches files used by gt or gem only. For everything else, use
> drm-intel-next. When in doubt, err on the side of drm-intel-next.

sorry, I did think of it. But...

> It's not enough that one of the patches changes parameters of
> for_each_gt() macro.

... I was fooled by the gt/i915 parameter.

Thanks and sorry,
Andi

> We can cross-merge drm-intel-next to drm-intel-gt-next, but we can't
> cross-merge drm-intel-gt-next to drm-intel-next. This means the only way
> to sync those i915_drv.h changes to drm-intel-next is to have a
> drm-intel-gt-next pull request merged to drm-next, and then backmerged
> to drm-intel-next. That's not going to happen for several weeks.
> 
> Any change aimed at drm-intel-next that conflicts with the i915_drv.h
> changes will now be pending on those merges.