From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/mtl: Update OA mux whitelist for MTL
Date: Wed, 30 Nov 2022 19:17:22 -0800 [thread overview]
Message-ID: <87sfhz3j99.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <20221201010535.1097741-4-umesh.nerlige.ramappa@intel.com>
On Wed, 30 Nov 2022 17:05:34 -0800, Umesh Nerlige Ramappa wrote:
>
> 0x20cc (WAIT_FOR_RC6_EXIT on other platforms) is repurposed on MTL. Use
> a separate mux table to verify oa configs passed by user.
> I looked for WAIT_FOR_RC6_EXIT in the bspec and did not find it defined for
> MTL, so it's dropped completely. If you could confirm, that would be great.
Yup looks like it.
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_perf.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 8ed9af571de9..8369ae4b850d 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -4318,6 +4318,17 @@ static const struct i915_range gen12_oa_mux_regs[] = {
> {}
> };
>
> +/*
> + * Ref: 14010536224:
> + * 0x20cc is repurposed on MTL, so use a separate array for MTL.
> + */
> +static const struct i915_range mtl_oa_mux_regs[] = {
> + { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
> + { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
> + { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
> + { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
> +};
> +
> static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
> {
> return reg_in_range_table(addr, gen7_oa_b_counters);
> @@ -4361,7 +4372,10 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
>
> static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
> {
> - return reg_in_range_table(addr, gen12_oa_mux_regs);
> + if (IS_METEORLAKE(perf->i915))
> + return reg_in_range_table(addr, mtl_oa_mux_regs);
> + else
> + return reg_in_range_table(addr, gen12_oa_mux_regs);
> }
>
> static u32 mask_reg_value(u32 reg, u32 val)
> --
> 2.36.1
>
next prev parent reply other threads:[~2022-12-01 3:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-01 1:05 [Intel-gfx] [PATCH v2 0/4] drm/i915/mtl: Add OAG 32 bit format support for MTL Umesh Nerlige Ramappa
2022-12-01 1:05 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs Umesh Nerlige Ramappa
2022-12-01 2:18 ` Dixit, Ashutosh
2022-12-01 1:05 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/mtl: Add Wa_14015846243 to fix OA vs CS timestamp mismatch Umesh Nerlige Ramappa
2022-12-01 2:16 ` Dixit, Ashutosh
2022-12-01 1:05 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/mtl: Update OA mux whitelist for MTL Umesh Nerlige Ramappa
2022-12-01 3:17 ` Dixit, Ashutosh [this message]
2022-12-01 1:05 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/mtl: Add OA support by enabling 32 bit OAG formats " Umesh Nerlige Ramappa
2022-12-01 2:14 ` Dixit, Ashutosh
2022-12-08 17:08 ` Umesh Nerlige Ramappa
2022-12-12 10:48 ` Joonas Lahtinen
2022-12-01 1:07 ` [Intel-gfx] [PATCH v2 0/4] drm/i915/mtl: Add OAG 32 bit format support " Umesh Nerlige Ramappa
2022-12-01 1:31 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: Add OAG 32 bit format support for MTL (rev2) Patchwork
2022-12-01 1:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-12-01 14:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-12-01 18:43 ` Umesh Nerlige Ramappa
-- strict thread matches above, loose matches on Subject: below --
2022-12-01 0:59 [Intel-gfx] [PATCH v2 0/4] drm/i915/mtl: Add OAG 32 bit format support for MTL Umesh Nerlige Ramappa
2022-12-01 0:59 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/mtl: Update OA mux whitelist " Umesh Nerlige Ramappa
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