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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 6/8] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()
Date: Wed, 16 Feb 2022 11:57:12 +0200	[thread overview]
Message-ID: <87v8xf3zif.fsf@intel.com> (raw)
In-Reply-To: <20220211182045.23555-1-ville.syrjala@linux.intel.com>

On Fri, 11 Feb 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We treat SSKPD as a 64 bit register. Add the support macros
> to define/extract bits in such registers.
>
> v2: Fix 32bit builds
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg_defs.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
> index 34d37bbf08cd..d78d78fce431 100644
> --- a/drivers/gpu/drm/i915/i915_reg_defs.h
> +++ b/drivers/gpu/drm/i915/i915_reg_defs.h
> @@ -37,6 +37,21 @@
>  				 __is_constexpr(__low) &&		\
>  				 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
>  
> +/**
> + * REG_GENMASK64() - Prepare a continuous u64 bitmask
> + * @__high: 0-based high bit
> + * @__low: 0-based low bit
> + *
> + * Local wrapper for GENMASK_ULL() to force u64, with compile time checks.
> + *
> + * @return: Continuous bitmask from @__high to @__low, inclusive.
> + */
> +#define REG_GENMASK64(__high, __low)					\
> +	((u64)(GENMASK_ULL(__high, __low) +				\
> +	       BUILD_BUG_ON_ZERO(__is_constexpr(__high) &&		\
> +				 __is_constexpr(__low) &&		\
> +				 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
> +
>  /*
>   * Local integer constant expression version of is_power_of_2().
>   */
> @@ -71,6 +86,18 @@
>   */
>  #define REG_FIELD_GET(__mask, __val)	((u32)FIELD_GET(__mask, __val))
>  
> +/**
> + * REG_FIELD_GET64() - Extract a u64 bitfield value
> + * @__mask: shifted mask defining the field's length and position
> + * @__val: value to extract the bitfield value from
> + *
> + * Local wrapper for FIELD_GET() to force u64 and for consistency with
> + * REG_GENMASK64().
> + *
> + * @return: Masked and shifted value of the field defined by @__mask in @__val.
> + */
> +#define REG_FIELD_GET64(__mask, __val)	((u64)FIELD_GET(__mask, __val))
> +
>  typedef struct {
>  	u32 reg;
>  } i915_reg_t;

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-02-16  9:58 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-11  9:06 [Intel-gfx] [PATCH 0/8] drm/i915: Plane/wm cleanups Ville Syrjala
2022-02-11  9:06 ` [Intel-gfx] [PATCH 1/8] drm/i915: Move intel_plane_atomic_calc_changes() & co. out Ville Syrjala
2022-02-16  9:30   ` Jani Nikula
2022-02-11  9:06 ` [Intel-gfx] [PATCH 2/8] drm/i915: Introduce intel_arm_planes_on_crtc() Ville Syrjala
2022-02-16  9:38   ` Jani Nikula
2022-02-16 12:44     ` Ville Syrjälä
2022-02-16 12:57       ` Jani Nikula
2022-02-11  9:06 ` [Intel-gfx] [PATCH 3/8] drm/i915: Introduce scaled_planes bitmask Ville Syrjala
2022-02-16  9:39   ` Jani Nikula
2022-02-11  9:06 ` [Intel-gfx] [PATCH 4/8] drm/i915: Use {active, scaled}_planes to compute ilk watermarks Ville Syrjala
2022-02-16  9:39   ` Jani Nikula
2022-02-11  9:06 ` [Intel-gfx] [PATCH 5/8] drm/i915: Remove gen6_check_mch_setup() Ville Syrjala
2022-02-16  9:54   ` Jani Nikula
2022-02-16 10:09     ` Ville Syrjälä
2022-02-11  9:06 ` [Intel-gfx] [PATCH 6/8] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64() Ville Syrjala
2022-02-11 18:20   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-02-16  9:57     ` Jani Nikula [this message]
2022-02-11  9:06 ` [Intel-gfx] [PATCH 7/8] drm/i915: Clean up SSKPD/MLTR defines Ville Syrjala
2022-02-11 17:58   ` kernel test robot
2022-02-11 17:58   ` kernel test robot
2022-02-11 17:59   ` kernel test robot
2022-02-16 10:12   ` Jani Nikula
2022-02-11  9:06 ` [Intel-gfx] [PATCH 8/8] drm/i915: Polish ilk+ wm register bits Ville Syrjala
2022-02-16 10:29   ` Jani Nikula
2022-02-16 10:40     ` Ville Syrjälä
2022-02-11 16:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane/wm cleanups Patchwork
2022-02-11 16:49 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-11 17:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-11 17:19 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2022-02-11 18:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane/wm cleanups (rev2) Patchwork
2022-02-11 18:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-02-11 19:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-11 23:21 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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