[v5 1/4] drm/i915: Fix the pipe state timing mismatch warnings

[v5 1/4] drm/i915: Fix the pipe state timing mismatch warnings

[Vandita Kulkarni]

Adjust the get transcoder timings for mipi dsi as per the
set timing calculations.

v2: Use the existing intel_get_pipe_timings and do the dsi
    specific adjustments in the encoder get_config hook.(Ville, Jani)

v3: Exclude VBLANK and HBLANK registers for dsi transcoder.

v4: Fix the incomplete conditional logic.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c       | 29 +++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++++------
 2 files changed, 45 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index c6ecc00..45fe69c 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1194,6 +1194,34 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
 	gen11_dsi_disable_io_power(encoder);
 }
 
+static void gen11_dsi_get_timings(struct intel_encoder *encoder,
+				  struct intel_crtc_state *pipe_config)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct drm_display_mode *adjusted_mode =
+					&pipe_config->base.adjusted_mode;
+
+	if (intel_dsi->dual_link) {
+		adjusted_mode->crtc_hdisplay *= 2;
+		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
+			adjusted_mode->crtc_hdisplay -=
+						intel_dsi->pixel_overlap;
+		adjusted_mode->crtc_htotal *= 2;
+	}
+	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
+	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
+
+	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
+		if (intel_dsi->dual_link) {
+			adjusted_mode->crtc_hsync_start *= 2;
+			adjusted_mode->crtc_hsync_end *= 2;
+		}
+	}
+	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
+	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
+
+}
+
 static void gen11_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
@@ -1204,6 +1232,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->port_clock =
 		cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
 	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dd65d7c..c8cfddc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7736,9 +7736,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
 	tmp = I915_READ(HTOTAL(cpu_transcoder));
 	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
 	pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
-	tmp = I915_READ(HBLANK(cpu_transcoder));
-	pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
-	pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
+
+	if (!transcoder_is_dsi(cpu_transcoder)) {
+		tmp = I915_READ(HBLANK(cpu_transcoder));
+		pipe_config->base.adjusted_mode.crtc_hblank_start =
+							(tmp & 0xffff) + 1;
+		pipe_config->base.adjusted_mode.crtc_hblank_end =
+						((tmp >> 16) & 0xffff) + 1;
+	}
 	tmp = I915_READ(HSYNC(cpu_transcoder));
 	pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
 	pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
@@ -7746,9 +7751,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
 	tmp = I915_READ(VTOTAL(cpu_transcoder));
 	pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
 	pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
-	tmp = I915_READ(VBLANK(cpu_transcoder));
-	pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
-	pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
+
+	if (!transcoder_is_dsi(cpu_transcoder)) {
+		tmp = I915_READ(VBLANK(cpu_transcoder));
+		pipe_config->base.adjusted_mode.crtc_vblank_start =
+							(tmp & 0xffff) + 1;
+		pipe_config->base.adjusted_mode.crtc_vblank_end =
+						((tmp >> 16) & 0xffff) + 1;
+	}
 	tmp = I915_READ(VSYNC(cpu_transcoder));
 	pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
 	pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
-- 
1.9.1

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[v5 2/4] drm/i915: Refactor bdw_get_pipemisc_bpp

[Vandita Kulkarni]

Move bdw_get_pipemisc_bpp alongside bdw_set_pipemisc

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/vlv_dsi.c       | 22 ----------------------
 3 files changed, 23 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c8cfddc..bbdb1ff 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8946,6 +8946,28 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
 	I915_WRITE(PIPEMISC(crtc->pipe), val);
 }
 
+int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	u32 tmp;
+
+	tmp = I915_READ(PIPEMISC(crtc->pipe));
+
+	switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
+	case PIPEMISC_DITHER_6_BPC:
+		return 18;
+	case PIPEMISC_DITHER_8_BPC:
+		return 24;
+	case PIPEMISC_DITHER_10_BPC:
+		return 30;
+	case PIPEMISC_DITHER_12_BPC:
+		return 36;
+	default:
+		MISSING_CASE(tmp);
+		return 0;
+	}
+}
+
 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
 {
 	/*
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 57ae396..ba75842 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1759,6 +1759,7 @@ u32 skl_plane_stride(const struct intel_plane_state *plane_state,
 unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
 				   u32 pixel_format, u64 modifier,
 				   unsigned int rotation);
+int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
 
 /* intel_runtime_pm.c */
 static inline void
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index bc5b782..895ea1a 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -262,28 +262,6 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
 	vlv_flisdsi_put(dev_priv);
 }
 
-static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 tmp;
-
-	tmp = I915_READ(PIPEMISC(crtc->pipe));
-
-	switch (tmp & PIPEMISC_DITHER_BPC_MASK) {
-	case PIPEMISC_DITHER_6_BPC:
-		return 18;
-	case PIPEMISC_DITHER_8_BPC:
-		return 24;
-	case PIPEMISC_DITHER_10_BPC:
-		return 30;
-	case PIPEMISC_DITHER_12_BPC:
-		return 36;
-	default:
-		MISSING_CASE(tmp);
-		return 0;
-	}
-}
-
 static int intel_dsi_compute_config(struct intel_encoder *encoder,
 				    struct intel_crtc_state *pipe_config,
 				    struct drm_connector_state *conn_state)
-- 
1.9.1

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[v5 3/4] drm/i915: Fix pipe config mismatch for bpp, output format

[Vandita Kulkarni]

Read back the pixel fomrat register and get the bpp.

v2: Read the PIPE_MISC register (Jani).

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index 45fe69c..cd6a4f3 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1226,6 +1226,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 
 	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
@@ -1234,6 +1235,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
 	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
+	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
 }
 
 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
@@ -1249,6 +1251,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	struct drm_display_mode *adjusted_mode =
 					&pipe_config->base.adjusted_mode;
 
+	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	intel_fixed_panel_mode(fixed_mode, adjusted_mode);
 	intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode);
 
-- 
1.9.1

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[v5 4/4] drm/i915: Fix pixel clock and crtc clock config mismatch

[Vandita Kulkarni]

In case of dual link mode, the mode clock that we get
from the VBT is halved.

v2: Simplify the calculation (Jani).

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/icl_dsi.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index cd6a4f3..46b3d30 100644
--- a/drivers/gpu/drm/i915/icl_dsi.c
+++ b/drivers/gpu/drm/i915/icl_dsi.c
@@ -1232,7 +1232,11 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */
 	pipe_config->port_clock =
 		cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
+
 	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
+	if (intel_dsi->dual_link)
+		pipe_config->base.adjusted_mode.crtc_clock *= 2;
+
 	gen11_dsi_get_timings(encoder, pipe_config);
 	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
 	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
-- 
1.9.1

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✗ Fi.CI.CHECKPATCH: warning for series starting with [v5,1/4] drm/i915: Fix the pipe state timing mismatch warnings

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/4] drm/i915: Fix the pipe state timing mismatch warnings
URL   : https://patchwork.freedesktop.org/series/60218/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
91207cbf0ccb drm/i915: Fix the pipe state timing mismatch warnings
-:52: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#52: FILE: drivers/gpu/drm/i915/icl_dsi.c:1204:
+
+}

total: 0 errors, 0 warnings, 1 checks, 75 lines checked
a28cace108e0 drm/i915: Refactor bdw_get_pipemisc_bpp
38eb90b2c673 drm/i915: Fix pipe config mismatch for bpp, output format
ad63c51d1394 drm/i915: Fix pixel clock and crtc clock config mismatch

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✓ Fi.CI.BAT: success for series starting with [v5,1/4] drm/i915: Fix the pipe state timing mismatch warnings

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/4] drm/i915: Fix the pipe state timing mismatch warnings
URL   : https://patchwork.freedesktop.org/series/60218/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6029 -> Patchwork_12949
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/60218/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_12949:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_chamelium@dp-crc-fast:
    - {fi-icl-dsi}:       NOTRUN -> [SKIP][1] +12 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/fi-icl-dsi/igt@kms_chamelium@dp-crc-fast.html

  
Known issues
------------

  Here are the changes found in Patchwork_12949 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [PASS][2] -> [INCOMPLETE][3] ([fdo#107718] / [fdo#110581])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_ringfill@basic-default-fd:
    - fi-icl-y:           [PASS][4] -> [INCOMPLETE][5] ([fdo#107713] / [fdo#110581])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/fi-icl-y/igt@gem_ringfill@basic-default-fd.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/fi-icl-y/igt@gem_ringfill@basic-default-fd.html

  
#### Warnings ####

  * igt@runner@aborted:
    - fi-skl-iommu:       [FAIL][6] ([fdo#104108]) -> [FAIL][7] ([fdo#104108] / [fdo#108602])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/fi-skl-iommu/igt@runner@aborted.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/fi-skl-iommu/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
  [fdo#110581]: https://bugs.freedesktop.org/show_bug.cgi?id=110581


Participating hosts (54 -> 43)
------------------------------

  Missing    (11): fi-kbl-soraka fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-skl-guc fi-byt-squawks fi-bsw-cyan fi-kbl-guc fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6029 -> Patchwork_12949

  CI_DRM_6029: 0548213ff6d52d4638778a95a4b3a7900e683ac3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12949: ad63c51d1394b6cd4bc5d134a10dbfffc307448f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ad63c51d1394 drm/i915: Fix pixel clock and crtc clock config mismatch
38eb90b2c673 drm/i915: Fix pipe config mismatch for bpp, output format
a28cace108e0 drm/i915: Refactor bdw_get_pipemisc_bpp
91207cbf0ccb drm/i915: Fix the pipe state timing mismatch warnings

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/
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✓ Fi.CI.IGT: success for series starting with [v5,1/4] drm/i915: Fix the pipe state timing mismatch warnings

[Patchwork]

== Series Details ==

Series: series starting with [v5,1/4] drm/i915: Fix the pipe state timing mismatch warnings
URL   : https://patchwork.freedesktop.org/series/60218/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6029_full -> Patchwork_12949_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12949_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@dpms-lpsp:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107807] / [fdo#110581]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-skl2/igt@i915_pm_rpm@dpms-lpsp.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-skl7/igt@i915_pm_rpm@dpms-lpsp.html

  * igt@kms_cursor_crc@cursor-128x128-onscreen:
    - shard-snb:          [PASS][3] -> [SKIP][4] ([fdo#109271])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-snb4/igt@kms_cursor_crc@cursor-128x128-onscreen.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-snb4/igt@kms_cursor_crc@cursor-128x128-onscreen.html

  * igt@kms_cursor_crc@cursor-128x128-suspend:
    - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#110581])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-skl2/igt@kms_cursor_crc@cursor-128x128-suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-skl8/igt@kms_cursor_crc@cursor-128x128-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [PASS][7] -> [FAIL][8] ([fdo#105363])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-iclb:         [PASS][9] -> [FAIL][10] ([fdo#103167]) +6 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-glk:          [PASS][11] -> [SKIP][12] ([fdo#109271]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-glk9/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-glk3/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-apl:          [PASS][13] -> [DMESG-WARN][14] ([fdo#108566]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-apl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][15] -> [FAIL][16] ([fdo#108145]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109441]) +3 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-iclb5/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [PASS][19] -> [FAIL][20] ([fdo#99912])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-kbl3/igt@kms_setmode@basic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-kbl2/igt@kms_setmode@basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-iclb:         [PASS][21] -> [FAIL][22] ([fdo#100047])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-iclb4/igt@kms_sysfs_edid_timing.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-iclb2/igt@kms_sysfs_edid_timing.html

  
#### Possible fixes ####

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [DMESG-WARN][23] ([fdo#108566]) -> [PASS][24] +7 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-apl8/igt@gem_workarounds@suspend-resume-context.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-apl3/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
    - shard-hsw:          [FAIL][25] ([fdo#103355]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-hsw7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][27] ([fdo#105363]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
    - shard-iclb:         [FAIL][29] ([fdo#103167]) -> [PASS][30] +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_plane@pixel-format-pipe-b-planes:
    - shard-glk:          [SKIP][31] ([fdo#109271]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-glk1/igt@kms_plane@pixel-format-pipe-b-planes.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-glk9/igt@kms_plane@pixel-format-pipe-b-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [FAIL][33] ([fdo#103166]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_plane_scaling@pipe-c-scaler-with-rotation:
    - shard-glk:          [SKIP][35] ([fdo#109271] / [fdo#109278]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-glk7/igt@kms_plane_scaling@pipe-c-scaler-with-rotation.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-glk9/igt@kms_plane_scaling@pipe-c-scaler-with-rotation.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][37] ([fdo#109441]) -> [PASS][38] +3 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6029/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110581]: https://bugs.freedesktop.org/show_bug.cgi?id=110581
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6029 -> Patchwork_12949

  CI_DRM_6029: 0548213ff6d52d4638778a95a4b3a7900e683ac3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4972: f052e49a43cc9704ea5f240df15dd9d3dfed68ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12949: ad63c51d1394b6cd4bc5d134a10dbfffc307448f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12949/
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Re: [v5 1/4] drm/i915: Fix the pipe state timing mismatch warnings

[Jani Nikula]

On Thu, 02 May 2019, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> Adjust the get transcoder timings for mipi dsi as per the
> set timing calculations.
>
> v2: Use the existing intel_get_pipe_timings and do the dsi
>     specific adjustments in the encoder get_config hook.(Ville, Jani)
>
> v3: Exclude VBLANK and HBLANK registers for dsi transcoder.
>
> v4: Fix the incomplete conditional logic.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

Pushed the series, thanks for the patches.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/icl_dsi.c       | 29 +++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c | 22 ++++++++++++++++------
>  2 files changed, 45 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
> index c6ecc00..45fe69c 100644
> --- a/drivers/gpu/drm/i915/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/icl_dsi.c
> @@ -1194,6 +1194,34 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
>  	gen11_dsi_disable_io_power(encoder);
>  }
>  
> +static void gen11_dsi_get_timings(struct intel_encoder *encoder,
> +				  struct intel_crtc_state *pipe_config)
> +{
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	struct drm_display_mode *adjusted_mode =
> +					&pipe_config->base.adjusted_mode;
> +
> +	if (intel_dsi->dual_link) {
> +		adjusted_mode->crtc_hdisplay *= 2;
> +		if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
> +			adjusted_mode->crtc_hdisplay -=
> +						intel_dsi->pixel_overlap;
> +		adjusted_mode->crtc_htotal *= 2;
> +	}
> +	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
> +	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
> +
> +	if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
> +		if (intel_dsi->dual_link) {
> +			adjusted_mode->crtc_hsync_start *= 2;
> +			adjusted_mode->crtc_hsync_end *= 2;
> +		}
> +	}
> +	adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
> +	adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
> +
> +}
> +
>  static void gen11_dsi_get_config(struct intel_encoder *encoder,
>  				 struct intel_crtc_state *pipe_config)
>  {
> @@ -1204,6 +1232,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
>  	pipe_config->port_clock =
>  		cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state);
>  	pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk;
> +	gen11_dsi_get_timings(encoder, pipe_config);
>  	pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dd65d7c..c8cfddc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -7736,9 +7736,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
>  	tmp = I915_READ(HTOTAL(cpu_transcoder));
>  	pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
>  	pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
> -	tmp = I915_READ(HBLANK(cpu_transcoder));
> -	pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
> -	pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
> +
> +	if (!transcoder_is_dsi(cpu_transcoder)) {
> +		tmp = I915_READ(HBLANK(cpu_transcoder));
> +		pipe_config->base.adjusted_mode.crtc_hblank_start =
> +							(tmp & 0xffff) + 1;
> +		pipe_config->base.adjusted_mode.crtc_hblank_end =
> +						((tmp >> 16) & 0xffff) + 1;
> +	}
>  	tmp = I915_READ(HSYNC(cpu_transcoder));
>  	pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
>  	pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
> @@ -7746,9 +7751,14 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
>  	tmp = I915_READ(VTOTAL(cpu_transcoder));
>  	pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
>  	pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
> -	tmp = I915_READ(VBLANK(cpu_transcoder));
> -	pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
> -	pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
> +
> +	if (!transcoder_is_dsi(cpu_transcoder)) {
> +		tmp = I915_READ(VBLANK(cpu_transcoder));
> +		pipe_config->base.adjusted_mode.crtc_vblank_start =
> +							(tmp & 0xffff) + 1;
> +		pipe_config->base.adjusted_mode.crtc_vblank_end =
> +						((tmp >> 16) & 0xffff) + 1;
> +	}
>  	tmp = I915_READ(VSYNC(cpu_transcoder));
>  	pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
>  	pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;

-- 
Jani Nikula, Intel Open Source Graphics Center
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