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From: Jani Nikula <jani.nikula@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH 01/18] drm/i915: Comments for semaphore clarification
Date: Wed, 07 Nov 2012 15:30:41 +0200	[thread overview]
Message-ID: <87y5idlev2.fsf@intel.com> (raw)
In-Reply-To: <1352219142-1395-2-git-send-email-ben@bwidawsk.net>

On Tue, 06 Nov 2012, Ben Widawsky <ben@bwidawsk.net> wrote:
> Semaphores are tied very closely to the rings in the GPU. Trivial patch
> adds comments to the existing code so that when we add new rings we can
> include comments there as well. It also helps distinguish the ring to
> semaphore mailbox interactions by using the ringname in the semaphore
> data structures.
>
> This patch should have no functional impact.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> A subset of this patch was:
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 12 ++++++------
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++---------
>  drivers/gpu/drm/i915/intel_ringbuffer.h |  2 +-
>  3 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9118bd1..f82755e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -252,12 +252,12 @@
>  #define  MI_SEMAPHORE_UPDATE	    (1<<21)
>  #define  MI_SEMAPHORE_COMPARE	    (1<<20)
>  #define  MI_SEMAPHORE_REGISTER	    (1<<18)
> -#define  MI_SEMAPHORE_SYNC_RV	    (2<<16)
> -#define  MI_SEMAPHORE_SYNC_RB	    (0<<16)
> -#define  MI_SEMAPHORE_SYNC_VR	    (0<<16)
> -#define  MI_SEMAPHORE_SYNC_VB	    (2<<16)
> -#define  MI_SEMAPHORE_SYNC_BR	    (2<<16)
> -#define  MI_SEMAPHORE_SYNC_BV	    (0<<16)
> +#define  MI_SEMAPHORE_SYNC_RB	    (0<<16) /* RCS wait for BCS  (BRSYNC) */
> +#define  MI_SEMAPHORE_SYNC_RV	    (2<<16) /* RCS wait for VCS  (VRSYNC) */
> +#define  MI_SEMAPHORE_SYNC_VR	    (0<<16) /* VCS wait for RCS  (RVSYNC) */
> +#define  MI_SEMAPHORE_SYNC_VB	    (2<<16) /* VCS wait for BCS  (BVSYNC) */
> +#define  MI_SEMAPHORE_SYNC_BV	    (0<<16) /* BCS wait for VCS  (VBSYNC) */
> +#define  MI_SEMAPHORE_SYNC_BR	    (2<<16) /* BCS wait for RCS  (RBSYNC) */
>  #define  MI_SEMAPHORE_SYNC_INVALID  (1<<0)
>  /*
>   * 3D instructions used by the kernel
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index a035ac2..423948f 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1503,9 +1503,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>  		ring->irq_enable_mask = GT_USER_INTERRUPT;
>  		ring->get_seqno = gen6_ring_get_seqno;
>  		ring->sync_to = gen6_ring_sync;
> -		ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
> -		ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
> -		ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
> +		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> +		ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> +		ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
>  		ring->signal_mbox[0] = GEN6_VRSYNC;
>  		ring->signal_mbox[1] = GEN6_BRSYNC;
>  	} else if (IS_GEN5(dev)) {
> @@ -1639,9 +1639,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
>  		ring->irq_put = gen6_ring_put_irq;
>  		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>  		ring->sync_to = gen6_ring_sync;
> -		ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
> -		ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
> -		ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
> +		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> +		ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> +		ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
>  		ring->signal_mbox[0] = GEN6_RVSYNC;
>  		ring->signal_mbox[1] = GEN6_BVSYNC;
>  	} else {
> @@ -1684,9 +1684,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
>  	ring->irq_put = gen6_ring_put_irq;
>  	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>  	ring->sync_to = gen6_ring_sync;
> -	ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
> -	ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
> -	ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
> +	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> +	ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> +	ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
>  	ring->signal_mbox[0] = GEN6_RBSYNC;
>  	ring->signal_mbox[1] = GEN6_VBSYNC;
>  	ring->init = init_ring_common;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 5af65b8..df1a0a2 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -89,7 +89,7 @@ struct  intel_ring_buffer {
>  				   struct intel_ring_buffer *to,
>  				   u32 seqno);
>  
> -	u32		semaphore_register[3]; /*our mbox written by others */
> +	u32		semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
>  	u32		signal_mbox[2]; /* mboxes this ring signals to */
>  	/**
>  	 * List of objects currently involved in rendering from the
> -- 
> 1.8.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2012-11-07 13:25 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-11-06 16:25 [PATCH 00/18] [RFC] Introduce the Haswell VECS Ben Widawsky
2012-11-06 16:25 ` [PATCH 01/18] drm/i915: Comments for semaphore clarification Ben Widawsky
2012-11-07 13:30   ` Jani Nikula [this message]
2012-11-06 16:25 ` [PATCH 02/18] drm/i915: Semaphore MBOX update generalization Ben Widawsky
2012-11-07 14:00   ` Jani Nikula
2012-11-06 16:25 ` [PATCH 03/18] drm/i915: Introduce VECS: the 4th ring Ben Widawsky
2012-11-06 16:25 ` [PATCH 04/18] drm/i915: Add VECS semaphore bits Ben Widawsky
2012-11-06 16:25 ` [PATCH 05/18] drm/i915: Rename ring flush functions Ben Widawsky
2012-11-07 14:47   ` Jani Nikula
2012-11-06 16:25 ` [PATCH 06/18] drm/i915: add HAS_VEBOX Ben Widawsky
2012-11-07 14:59   ` Jani Nikula
2012-11-06 16:25 ` [PATCH 07/18] drm/i915: Vebox ringbuffer init Ben Widawsky
2012-11-06 16:25 ` [PATCH 08/18] drm/i915: Create a more generic pm handler for hsw+ Ben Widawsky
2012-11-06 16:25 ` [PATCH 09/18] drm/i915: make PM interrupt writes non-destructive Ben Widawsky
2012-11-07 10:17   ` Chris Wilson
2012-11-07 11:53     ` Ben Widawsky
2012-11-12 19:11   ` [PATCH 09/18 v3] " Ben Widawsky
2012-11-12 19:39     ` [PATCH 09/18 v4] " Ben Widawsky
2012-11-06 16:25 ` [PATCH 10/18] drm/i915: Create an ivybridge_irq_preinstall Ben Widawsky
2012-11-06 16:25 ` [PATCH 11/18] drm/i915: Add PM regs to pre install Ben Widawsky
2012-11-06 16:25 ` [PATCH 12/18] drm/i915: Convert irq_refounct to struct Ben Widawsky
2012-11-06 16:25 ` [PATCH 13/18] drm/i915: consolidate interrupt naming scheme Ben Widawsky
2012-11-06 16:25 ` [PATCH 14/18] drm/i915: vebox interrupt get/put Ben Widawsky
2013-02-13 19:28   ` Daniel Vetter
2012-11-06 16:25 ` [PATCH 15/18] drm/i915: Enable vebox interrupts Ben Widawsky
2012-11-06 16:25 ` [PATCH 16/18] drm/i915: add VEBOX into debugfs Ben Widawsky
2012-11-06 16:25 ` [PATCH 17/18] drm/i915: add I915_EXEC_VEBOX to i915_gem_do_execbuffer() Ben Widawsky
2012-11-06 16:25 ` [PATCH 18/18] drm/i915: add I915_PARAM_HAS_VEBOX to i915_getparam Ben Widawsky
2012-11-07 12:03 ` [PATCH 00/18] [RFC] Introduce the Haswell VECS Ben Widawsky
  -- strict thread matches above, loose matches on Subject: below --
2013-04-28  0:59 [PATCH 00/18] " Ben Widawsky
2013-04-28  0:59 ` [PATCH 01/18] drm/i915: Comments for semaphore clarification Ben Widawsky
2013-05-07 13:54   ` Damien Lespiau
2013-05-07 16:51     ` Ben Widawsky
2013-05-07 17:00       ` Ben Widawsky

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