* [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice
@ 2019-05-28 20:06 Chris Wilson
2019-05-28 20:45 ` Summers, Stuart
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Chris Wilson @ 2019-05-28 20:06 UTC (permalink / raw)
To: intel-gfx
We want the index corresponding to the set bit but fls() returns the
1-index value.
Otherwise, we trigger the sanitycheck
intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu->max_slices)
when we look up the invalid slice.
The only remaining question then is just how reliable the rest of
intel_calculate_mcr_s_ss_select() is -- how many more of those fls() are
also off-by-one.
Fixes: 1ac159e23c2c ("drm/i915: Expand subslice mask")
Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index fbc853085809..485cd1c8ecc4 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -781,7 +781,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
* read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
* enabled subslice, no need to redirect MCR packet
*/
- u32 slice = fls(sseu->slice_mask);
+ u32 slice = __fls(sseu->slice_mask);
u32 fuse3 =
intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
u32 ss_mask = intel_sseu_get_subslices(sseu, slice);
--
2.20.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice
2019-05-28 20:06 [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice Chris Wilson
@ 2019-05-28 20:45 ` Summers, Stuart
2019-05-28 22:03 ` Chris Wilson
2019-05-28 21:53 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Summers, Stuart @ 2019-05-28 20:45 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, chris@chris-wilson.co.uk
[-- Attachment #1.1: Type: text/plain, Size: 2153 bytes --]
On Tue, 2019-05-28 at 21:06 +0100, Chris Wilson wrote:
> We want the index corresponding to the set bit but fls() returns the
> 1-index value.
>
> Otherwise, we trigger the sanitycheck
> intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu-
> >max_slices)
> when we look up the invalid slice.
>
> The only remaining question then is just how reliable the rest of
> intel_calculate_mcr_s_ss_select() is -- how many more of those fls()
> are
> also off-by-one.
>
> Fixes: 1ac159e23c2c ("drm/i915: Expand subslice mask")
> Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement
> WaProgramMgsrForCorrectSliceSpecificMmioReads")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index fbc853085809..485cd1c8ecc4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -781,7 +781,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> * read FUSE3 for enabled L3 Bank IDs, if L3 Bank
> matches
> * enabled subslice, no need to redirect MCR packet
> */
> - u32 slice = fls(sseu->slice_mask);
> + u32 slice = __fls(sseu->slice_mask);
The condition around this (is_power_of_2) makes sure we meet the case
where the slice_mask is uninitialized. This is going to work here, but
might not work in all other places. If we propagate this change to the
other places we call fls(slice_mask), which I'd recommend, we'll want
to make sure we check for that.
Once we show results in CI:
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> u32 fuse3 =
> intel_uncore_read(&i915->uncore,
> GEN10_MIRROR_FUSE3);
> u32 ss_mask = intel_sseu_get_subslices(sseu, slice);
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice
2019-05-28 20:45 ` Summers, Stuart
@ 2019-05-28 22:03 ` Chris Wilson
2019-05-28 22:05 ` Chris Wilson
0 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2019-05-28 22:03 UTC (permalink / raw)
To: Summers, Stuart, intel-gfx@lists.freedesktop.org
Quoting Summers, Stuart (2019-05-28 21:45:05)
> On Tue, 2019-05-28 at 21:06 +0100, Chris Wilson wrote:
> > We want the index corresponding to the set bit but fls() returns the
> > 1-index value.
> >
> > Otherwise, we trigger the sanitycheck
> > intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu-
> > >max_slices)
> > when we look up the invalid slice.
> >
> > The only remaining question then is just how reliable the rest of
> > intel_calculate_mcr_s_ss_select() is -- how many more of those fls()
> > are
> > also off-by-one.
> >
> > Fixes: 1ac159e23c2c ("drm/i915: Expand subslice mask")
> > Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement
> > WaProgramMgsrForCorrectSliceSpecificMmioReads")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > Cc: Stuart Summers <stuart.summers@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index fbc853085809..485cd1c8ecc4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -781,7 +781,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct
> > i915_wa_list *wal)
> > * read FUSE3 for enabled L3 Bank IDs, if L3 Bank
> > matches
> > * enabled subslice, no need to redirect MCR packet
> > */
> > - u32 slice = fls(sseu->slice_mask);
> > + u32 slice = __fls(sseu->slice_mask);
>
> The condition around this (is_power_of_2) makes sure we meet the case
> where the slice_mask is uninitialized. This is going to work here, but
> might not work in all other places. If we propagate this change to the
> other places we call fls(slice_mask), which I'd recommend, we'll want
> to make sure we check for that.
>
> Once we show results in CI:
> Reviewed-by: Stuart Summers <stuart.summers@intel.com>
This brought icl back from the dead. The other fls can be fixed up at
leisure! Ta,
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice
2019-05-28 22:03 ` Chris Wilson
@ 2019-05-28 22:05 ` Chris Wilson
2019-05-28 22:17 ` Summers, Stuart
0 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2019-05-28 22:05 UTC (permalink / raw)
To: Summers, Stuart, intel-gfx@lists.freedesktop.org; +Cc: Manasi, Landwerlin
Quoting Chris Wilson (2019-05-28 23:03:16)
> Quoting Summers, Stuart (2019-05-28 21:45:05)
> > On Tue, 2019-05-28 at 21:06 +0100, Chris Wilson wrote:
> > > We want the index corresponding to the set bit but fls() returns the
> > > 1-index value.
> > >
> > > Otherwise, we trigger the sanitycheck
> > > intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu-
> > > >max_slices)
> > > when we look up the invalid slice.
> > >
> > > The only remaining question then is just how reliable the rest of
> > > intel_calculate_mcr_s_ss_select() is -- how many more of those fls()
> > > are
> > > also off-by-one.
> > >
> > > Fixes: 1ac159e23c2c ("drm/i915: Expand subslice mask")
> > > Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement
> > > WaProgramMgsrForCorrectSliceSpecificMmioReads")
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > > Cc: Stuart Summers <stuart.summers@intel.com>
> > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index fbc853085809..485cd1c8ecc4 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -781,7 +781,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct
> > > i915_wa_list *wal)
> > > * read FUSE3 for enabled L3 Bank IDs, if L3 Bank
> > > matches
> > > * enabled subslice, no need to redirect MCR packet
> > > */
> > > - u32 slice = fls(sseu->slice_mask);
> > > + u32 slice = __fls(sseu->slice_mask);
> >
> > The condition around this (is_power_of_2) makes sure we meet the case
> > where the slice_mask is uninitialized. This is going to work here, but
> > might not work in all other places. If we propagate this change to the
> > other places we call fls(slice_mask), which I'd recommend, we'll want
> > to make sure we check for that.
> >
> > Once we show results in CI:
> > Reviewed-by: Stuart Summers <stuart.summers@intel.com>
>
> This brought icl back from the dead. The other fls can be fixed up at
> leisure! Ta,
Only for it to die at
<4>[ 12.083315] WARN_ON((enabled_mask & disabled_mask) != enabled_mask)
<4>[ 12.083370] WARNING: CPU: 7 PID: 387 at drivers/gpu/drm/i915/gt/intel_workarounds.c:797 wa_init_mcr+0xfa/0x110 [i915]
Onwards,
-Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice
2019-05-28 22:05 ` Chris Wilson
@ 2019-05-28 22:17 ` Summers, Stuart
0 siblings, 0 replies; 10+ messages in thread
From: Summers, Stuart @ 2019-05-28 22:17 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, chris@chris-wilson.co.uk
[-- Attachment #1.1: Type: text/plain, Size: 3170 bytes --]
On Tue, 2019-05-28 at 23:05 +0100, Chris Wilson wrote:
> Quoting Chris Wilson (2019-05-28 23:03:16)
> > Quoting Summers, Stuart (2019-05-28 21:45:05)
> > > On Tue, 2019-05-28 at 21:06 +0100, Chris Wilson wrote:
> > > > We want the index corresponding to the set bit but fls()
> > > > returns the
> > > > 1-index value.
> > > >
> > > > Otherwise, we trigger the sanitycheck
> > > > intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu-
> > > > > max_slices)
> > > >
> > > > when we look up the invalid slice.
> > > >
> > > > The only remaining question then is just how reliable the rest
> > > > of
> > > > intel_calculate_mcr_s_ss_select() is -- how many more of those
> > > > fls()
> > > > are
> > > > also off-by-one.
> > > >
> > > > Fixes: 1ac159e23c2c ("drm/i915: Expand subslice mask")
> > > > Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement
> > > > WaProgramMgsrForCorrectSliceSpecificMmioReads")
> > > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > > > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> > > > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> > > > Cc: Stuart Summers <stuart.summers@intel.com>
> > > > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> > > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > index fbc853085809..485cd1c8ecc4 100644
> > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c(enabled_mask
> > > > & disabled_mask) != enabled_mask
> > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > @@ -781,7 +781,7 @@ wa_init_mcr(struct drm_i915_private *i915,
> > > > struct
> > > > i915_wa_list *wal)
> > > > * read FUSE3 for enabled L3 Bank IDs, if L3 Bank
> > > > matches
> > > > * enabled subslice, no need to redirect MCR
> > > > packet
> > > > */
> > > > - u32 slice = fls(sseu->slice_mask);
> > > > + u32 slice = __fls(sseu->slice_mask);
> > >
> > > The condition around this (is_power_of_2) makes sure we meet the
> > > case
> > > where the slice_mask is uninitialized. This is going to work
> > > here, but
> > > might not work in all other places. If we propagate this change
> > > to the
> > > other places we call fls(slice_mask), which I'd recommend, we'll
> > > want
> > > to make sure we check for that.
> > >
> > > Once we show results in CI:
> > > Reviewed-by: Stuart Summers <stuart.summers@intel.com>
> >
> > This brought icl back from the dead. The other fls can be fixed up
> > at
> > leisure! Ta,
>
> Only for it to die at
> <4>[ 12.083315] WARN_ON((enabled_mask & disabled_mask) !=
> enabled_mask)
> <4>[ 12.083370] WARNING: CPU: 7 PID: 387 at
> drivers/gpu/drm/i915/gt/intel_workarounds.c:797
> wa_init_mcr+0xfa/0x110 [i915]
I'll also take a closer look here. I see the warning in the CI logs
too. I'm not sure why this didn't come up in my local testing.
-Stuart
>
> Onwards,
> -Chris
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^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Fix off-by-one in looking up icl sseu slice
2019-05-28 20:06 [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice Chris Wilson
2019-05-28 20:45 ` Summers, Stuart
@ 2019-05-28 21:53 ` Patchwork
2019-05-29 8:08 ` ✓ Fi.CI.IGT: " Patchwork
2019-05-29 8:26 ` [PATCH] " Jani Nikula
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-05-28 21:53 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix off-by-one in looking up icl sseu slice
URL : https://patchwork.freedesktop.org/series/61276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6159 -> Patchwork_13119
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/
Known issues
------------
Here are the changes found in Patchwork_13119 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_contexts:
- fi-skl-gvtdvm: [PASS][1] -> [DMESG-FAIL][2] ([fdo#110235])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
Participating hosts (48 -> 46)
------------------------------
Additional (5): fi-icl-u2 fi-icl-u3 fi-icl-y fi-icl-guc fi-icl-dsi
Missing (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_6159 -> Patchwork_13119
CI_DRM_6159: f280d33ae895624a247d4431ece09b5088e6f021 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5021: 2d64cb6808075b0d0696a89d2ce290220e6eff8e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13119: d05b03cf1b2925840bc3a15531b7bd60896e3749 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d05b03cf1b29 drm/i915: Fix off-by-one in looking up icl sseu slice
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/
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^ permalink raw reply [flat|nested] 10+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: Fix off-by-one in looking up icl sseu slice
2019-05-28 20:06 [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice Chris Wilson
2019-05-28 20:45 ` Summers, Stuart
2019-05-28 21:53 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2019-05-29 8:08 ` Patchwork
2019-05-29 8:26 ` [PATCH] " Jani Nikula
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-05-29 8:08 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Fix off-by-one in looking up icl sseu slice
URL : https://patchwork.freedesktop.org/series/61276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6159_full -> Patchwork_13119_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_13119_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2] ([fdo#103665])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][3] -> [DMESG-WARN][4] ([fdo#108566]) +5 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-apl1/igt@gem_workarounds@suspend-resume.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-apl8/igt@gem_workarounds@suspend-resume.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [PASS][5] -> [FAIL][6] ([fdo#105363])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@plain-flip-ts-check:
- shard-glk: [PASS][7] -> [FAIL][8] ([fdo#100368])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-glk3/igt@kms_flip@plain-flip-ts-check.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-glk8/igt@kms_flip@plain-flip-ts-check.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-hsw: [PASS][9] -> [SKIP][10] ([fdo#109271]) +26 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-hsw6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][11] -> [FAIL][12] ([fdo#108145] / [fdo#110403]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][13] -> [FAIL][14] ([fdo#99912])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-apl4/igt@kms_setmode@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-apl8/igt@kms_setmode@basic.html
- shard-kbl: [PASS][15] -> [FAIL][16] ([fdo#99912])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-kbl4/igt@kms_setmode@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-kbl7/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-kbl3/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
* igt@tools_test@tools_test:
- shard-kbl: [PASS][19] -> [SKIP][20] ([fdo#109271])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-kbl3/igt@tools_test@tools_test.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-kbl7/igt@tools_test@tools_test.html
#### Possible fixes ####
* igt@gem_eio@in-flight-suspend:
- shard-skl: [INCOMPLETE][21] ([fdo#104108]) -> [PASS][22] +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-skl3/igt@gem_eio@in-flight-suspend.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-skl5/igt@gem_eio@in-flight-suspend.html
* igt@i915_pm_rpm@debugfs-read:
- shard-skl: [INCOMPLETE][23] ([fdo#107807]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-skl5/igt@i915_pm_rpm@debugfs-read.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-skl2/igt@i915_pm_rpm@debugfs-read.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [DMESG-WARN][25] ([fdo#108566]) -> [PASS][26] +5 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-apl3/igt@i915_suspend@debugfs-reader.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-apl1/igt@i915_suspend@debugfs-reader.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-hsw: [SKIP][27] ([fdo#109271]) -> [PASS][28] +15 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-hsw1/igt@kms_flip@2x-plain-flip-interruptible.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-hsw6/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-kbl: [DMESG-WARN][29] ([fdo#108566]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6159/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible.html
[fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_6159 -> Patchwork_13119
CI_DRM_6159: f280d33ae895624a247d4431ece09b5088e6f021 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5021: 2d64cb6808075b0d0696a89d2ce290220e6eff8e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_13119: d05b03cf1b2925840bc3a15531b7bd60896e3749 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13119/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice
2019-05-28 20:06 [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice Chris Wilson
` (2 preceding siblings ...)
2019-05-29 8:08 ` ✓ Fi.CI.IGT: " Patchwork
@ 2019-05-29 8:26 ` Jani Nikula
2019-05-29 14:23 ` Jani Nikula
3 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2019-05-29 8:26 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On Tue, 28 May 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> We want the index corresponding to the set bit but fls() returns the
> 1-index value.
>
> Otherwise, we trigger the sanitycheck
> intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu->max_slices)
> when we look up the invalid slice.
>
> The only remaining question then is just how reliable the rest of
> intel_calculate_mcr_s_ss_select() is -- how many more of those fls() are
> also off-by-one.
>
> Fixes: 1ac159e23c2c ("drm/i915: Expand subslice mask")
I sent a revert of this commit [1] for reasons explained in the commit
message.
BR,
Jani.
[1] http://patchwork.freedesktop.org/patch/msgid/20190529082150.31526-1-jani.nikula@intel.com
> Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index fbc853085809..485cd1c8ecc4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -781,7 +781,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
> * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> * enabled subslice, no need to redirect MCR packet
> */
> - u32 slice = fls(sseu->slice_mask);
> + u32 slice = __fls(sseu->slice_mask);
> u32 fuse3 =
> intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
> u32 ss_mask = intel_sseu_get_subslices(sseu, slice);
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice
2019-05-29 8:26 ` [PATCH] " Jani Nikula
@ 2019-05-29 14:23 ` Jani Nikula
2019-05-29 14:32 ` Saarinen, Jani
0 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2019-05-29 14:23 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On Wed, 29 May 2019, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Tue, 28 May 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> We want the index corresponding to the set bit but fls() returns the
>> 1-index value.
>>
>> Otherwise, we trigger the sanitycheck
>> intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu->max_slices)
>> when we look up the invalid slice.
>>
>> The only remaining question then is just how reliable the rest of
>> intel_calculate_mcr_s_ss_select() is -- how many more of those fls() are
>> also off-by-one.
>>
>> Fixes: 1ac159e23c2c ("drm/i915: Expand subslice mask")
>
> I sent a revert of this commit [1] for reasons explained in the commit
> message.
I've gone ahead and pushed the revert.
We can now calmly get back to the drawing board, and get this sorted
out.
BR,
Jani.
>
> BR,
> Jani.
>
>
> [1] http://patchwork.freedesktop.org/patch/msgid/20190529082150.31526-1-jani.nikula@intel.com
>
>
>> Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement WaProgramMgsrForCorrectSliceSpecificMmioReads")
>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Cc: Stuart Summers <stuart.summers@intel.com>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index fbc853085809..485cd1c8ecc4 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -781,7 +781,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
>> * enabled subslice, no need to redirect MCR packet
>> */
>> - u32 slice = fls(sseu->slice_mask);
>> + u32 slice = __fls(sseu->slice_mask);
>> u32 fuse3 =
>> intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3);
>> u32 ss_mask = intel_sseu_get_subslices(sseu, slice);
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice
2019-05-29 14:23 ` Jani Nikula
@ 2019-05-29 14:32 ` Saarinen, Jani
0 siblings, 0 replies; 10+ messages in thread
From: Saarinen, Jani @ 2019-05-29 14:32 UTC (permalink / raw)
To: Jani Nikula, Chris Wilson, intel-gfx@lists.freedesktop.org
HI,
> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Jani
> Nikula
> Sent: keskiviikko 29. toukokuuta 2019 17.23
> To: Chris Wilson <chris@chris-wilson.co.uk>; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice
>
> On Wed, 29 May 2019, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Tue, 28 May 2019, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >> We want the index corresponding to the set bit but fls() returns the
> >> 1-index value.
> >>
> >> Otherwise, we trigger the sanitycheck
> >> intel_sseu_get_subslices:46 GEM_BUG_ON(slice >= sseu->max_slices)
> >> when we look up the invalid slice.
> >>
> >> The only remaining question then is just how reliable the rest of
> >> intel_calculate_mcr_s_ss_select() is -- how many more of those fls()
> >> are also off-by-one.
> >>
> >> Fixes: 1ac159e23c2c ("drm/i915: Expand subslice mask")
> >
> > I sent a revert of this commit [1] for reasons explained in the commit
> > message.
>
> I've gone ahead and pushed the revert.
>
> We can now calmly get back to the drawing board, and get this sorted out.
Ack ;)
>
> BR,
> Jani.
>
>
> >
> > BR,
> > Jani.
> >
> >
> > [1]
> > http://patchwork.freedesktop.org/patch/msgid/20190529082150.31526-1-ja
> > ni.nikula@intel.com
> >
> >
> >> Fixes: 1e40d4aea57b ("drm/i915/cnl: Implement
> >> WaProgramMgsrForCorrectSliceSpecificMmioReads")
> >> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> >> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> >> Cc: Stuart Summers <stuart.summers@intel.com>
> >> Cc: Manasi Navare <manasi.d.navare@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> index fbc853085809..485cd1c8ecc4 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> @@ -781,7 +781,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> >> * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches
> >> * enabled subslice, no need to redirect MCR packet
> >> */
> >> - u32 slice = fls(sseu->slice_mask);
> >> + u32 slice = __fls(sseu->slice_mask);
> >> u32 fuse3 =
> >> intel_uncore_read(&i915->uncore,
> GEN10_MIRROR_FUSE3);
> >> u32 ss_mask = intel_sseu_get_subslices(sseu, slice);
>
> --
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-05-29 14:32 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-05-28 20:06 [PATCH] drm/i915: Fix off-by-one in looking up icl sseu slice Chris Wilson
2019-05-28 20:45 ` Summers, Stuart
2019-05-28 22:03 ` Chris Wilson
2019-05-28 22:05 ` Chris Wilson
2019-05-28 22:17 ` Summers, Stuart
2019-05-28 21:53 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-05-29 8:08 ` ✓ Fi.CI.IGT: " Patchwork
2019-05-29 8:26 ` [PATCH] " Jani Nikula
2019-05-29 14:23 ` Jani Nikula
2019-05-29 14:32 ` Saarinen, Jani
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