Re: [PATCH v2 14/22] drm/i915/guc: New GuC scratch registers for Gen11

[Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>]

On 4/11/19 1:44 AM, Michal Wajdeczko wrote:
> Gen11 adds new set of scratch registers that can be used for MMIO
> based Host-to-Guc communication. Due to limited number of these
> registers it is expected that host will use them only for command
> transport buffers (CTB) communication setup if one is available.
> 
> Bspec: 21044
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> ---
>   drivers/gpu/drm/i915/intel_guc.c     | 12 +++++++++---
>   drivers/gpu/drm/i915/intel_guc_reg.h |  3 +++
>   2 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
> index 5bc9bc7c956a..e54de551b567 100644
> --- a/drivers/gpu/drm/i915/intel_guc.c
> +++ b/drivers/gpu/drm/i915/intel_guc.c
> @@ -56,9 +56,15 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
>   	enum forcewake_domains fw_domains = 0;
>   	unsigned int i;
>   
> -	guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
> -	guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
> -	BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
> +	if (HAS_GUC_CT(dev_priv) && INTEL_GEN(dev_priv) >= 11) {
> +		guc->send_regs.base =
> +				i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
> +		guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
> +	} else {
> +		guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
> +		guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
> +		BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
> +	}
>   
>   	for (i = 0; i < guc->send_regs.count; i++) {
>   		fw_domains |= intel_uncore_forcewake_for_reg(&dev_priv->uncore,
> diff --git a/drivers/gpu/drm/i915/intel_guc_reg.h b/drivers/gpu/drm/i915/intel_guc_reg.h
> index aec02eddbaed..d26de5193568 100644
> --- a/drivers/gpu/drm/i915/intel_guc_reg.h
> +++ b/drivers/gpu/drm/i915/intel_guc_reg.h
> @@ -51,6 +51,9 @@
>   #define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)
>   #define SOFT_SCRATCH_COUNT		16
>   
> +#define GEN11_SOFT_SCRATCH(n)		_MMIO(0x190240 + (n) * 4)
> +#define GEN11_SOFT_SCRATCH_COUNT	4
> +
>   #define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)
>   #define UOS_RSA_SCRATCH_COUNT		64
>   
> 
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