Re: [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function

From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: "Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function
Date: Mon, 11 Mar 2019 17:15:41 -0700	[thread overview]
Message-ID: <8df961409d5f808234a9ba8980fae40dccc3b927.camel@intel.com> (raw)
In-Reply-To: <20190311232802.GD24277@intel.com>

On Mon, 2019-03-11 at 16:28 -0700, Rodrigo Vivi wrote:
> On Tue, Mar 05, 2019 at 03:47:33PM -0800, José Roberto de Souza
> wrote:
> > This will make hsw_activate_psr1() more easy to read and will make
> > future modification to TPS registers more easy to review and read.
> > 
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 56 +++++++++++++++++++---------
> > ----
> >  1 file changed, 33 insertions(+), 23 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 831f345b4ad8..2fa2f4c9c935 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -437,32 +437,13 @@ static void intel_psr_enable_sink(struct
> > intel_dp *intel_dp)
> >  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
> >  }
> >  
> > -static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > +static u32 psr1_tps_regs_val_get(struct intel_dp *intel_dp)
> >  {
> >  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > -	u32 max_sleep_time = 0x1f;
> > -	u32 val = EDP_PSR_ENABLE;
> > -
> > -	/* Let's use 6 as the minimum to cover all known cases
> > including the
> > -	 * off-by-one issue that HW has in some cases.
> > -	 */
> > -	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > -
> > -	/* sink_sync_latency of 8 means source has to wait for more
> > than 8
> > -	 * frames, we'll go with 9 frames for now
> > -	 */
> > -	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > + 1);
> > -	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> > -
> > -	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> > -	if (IS_HASWELL(dev_priv))
> > -		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> > -
> > -	if (dev_priv->psr.link_standby)
> > -		val |= EDP_PSR_LINK_STANDBY;
> > +	u32 val = 0;
> >  
> >  	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
> > -		val |=  EDP_PSR_TP1_TIME_0us;
> > +		val |= EDP_PSR_TP1_TIME_0us;
> >  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
> >  		val |= EDP_PSR_TP1_TIME_100us;
> >  	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)
> > @@ -471,7 +452,7 @@ static void hsw_activate_psr1(struct intel_dp
> > *intel_dp)
> >  		val |= EDP_PSR_TP1_TIME_2500us;
> >  
> >  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)
> > -		val |=  EDP_PSR_TP2_TP3_TIME_0us;
> > +		val |= EDP_PSR_TP2_TP3_TIME_0us;
> >  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)
> >  		val |= EDP_PSR_TP2_TP3_TIME_100us;
> >  	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)
> > @@ -485,6 +466,35 @@ static void hsw_activate_psr1(struct intel_dp
> > *intel_dp)
> >  	else
> >  		val |= EDP_PSR_TP1_TP2_SEL;
> >  
> > +	return val;
> > +}
> > +
> > +static void hsw_activate_psr1(struct intel_dp *intel_dp)
> > +{
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +	u32 max_sleep_time = 0x1f;
> > +	u32 val = EDP_PSR_ENABLE;
> > +
> > +	/* Let's use 6 as the minimum to cover all known cases
> > including the
> > +	 * off-by-one issue that HW has in some cases.
> > +	 */
> > +	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
> > +
> > +	/* sink_sync_latency of 8 means source has to wait for more
> > than 8
> > +	 * frames, we'll go with 9 frames for now
> > +	 */
> > +	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency
> > + 1);
> > +	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> > +
> > +	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> > +	if (IS_HASWELL(dev_priv))
> > +		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> > +
> > +	if (dev_priv->psr.link_standby)
> > +		val |= EDP_PSR_LINK_STANDBY;
> > +
> > +	val |= psr1_tps_regs_val_get(intel_dp);
> 
> I'd prefer intel_psr1_tps...
> 

intel_psr1_get_tp_time(intel_dp)?

> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> > +
> >  	if (INTEL_GEN(dev_priv) >= 8)
> >  		val |= EDP_PSR_CRC_ENABLE;
> >  
> > -- 
> > 2.21.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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