From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 07/14] drm/i915: Sort HSW PCI IDs
Date: Thu, 24 Sep 2020 00:44:53 +0000 [thread overview]
Message-ID: <941e267eafc647fdb91fb80565a2c2c2@intel.com> (raw)
In-Reply-To: <20200716172106.2656-8-ville.syrjala@linux.intel.com>
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Thursday, July 16, 2020 10:21 AM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 07/14] drm/i915: Sort HSW PCI IDs
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Sort the HSW PCI IDs numerically. Some order seems better than
> randomness.
I think the sorting, OCD-ness with hex and reclassifying can be combined in one patch.
Anusha
> Cc: Alexei Podtelezhnikov <apodtele@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> include/drm/i915_pciids.h | 34 +++++++++++++++++-----------------
> 1 file changed, 17 insertions(+), 17 deletions(-)
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> 026db4d496e9..4870c3c9f9b2 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -170,9 +170,9 @@
>
> #define INTEL_HSW_ULT_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
> - INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0A06, info) /* ULT GT1 mobile */
> + INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */
>
> #define INTEL_HSW_ULX_GT1_IDS(info) \
> INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */ @@ -181,26
> +181,26 @@
> INTEL_HSW_ULT_GT1_IDS(info), \
> INTEL_HSW_ULX_GT1_IDS(info), \
> INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \
> INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
> INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
> INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
> INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
> INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
> INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
> + INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
> INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
> INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
> - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
> - INTEL_VGA_DEVICE(0x0D06, info) /* CRW GT1 mobile */
> + INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */
>
> #define INTEL_HSW_ULT_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
> - INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0A16, info) /* ULT GT2 mobile */
> + INTEL_VGA_DEVICE(0x0A1B, info) /* ULT GT2 reserved */ \
>
> #define INTEL_HSW_ULX_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \ @@ -
> 209,45 +209,45 @@
> INTEL_HSW_ULT_GT2_IDS(info), \
> INTEL_HSW_ULX_GT2_IDS(info), \
> INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \
> INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
> INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
> INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
> INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
> INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
> INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
> + INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
> INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
> INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
> - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
> - INTEL_VGA_DEVICE(0x0D16, info) /* CRW GT2 mobile */
> + INTEL_VGA_DEVICE(0x0D1E, info) /* CRW GT2 reserved */
>
> #define INTEL_HSW_ULT_GT3_IDS(info) \
> INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
> INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
> INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */
>
> #define INTEL_HSW_GT3_IDS(info) \
> INTEL_HSW_ULT_GT3_IDS(info), \
> INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
> INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \
> INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
> INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
> INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
> INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
> + INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \
> INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
> INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0D2E, info), /* CRW GT3 reserved */ \
> - INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
> - INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
> + INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */
>
> #define INTEL_HSW_IDS(info) \
> INTEL_HSW_GT1_IDS(info), \
> --
> 2.26.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2020-09-24 0:44 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200716172106.2656-1-ville.syrjala@linux.intel.com>
[not found] ` <20200716172106.2656-2-ville.syrjala@linux.intel.com>
2020-09-23 23:46 ` [Intel-gfx] [PATCH 01/14] drm/i915: Update Haswell PCI IDs Srivatsa, Anusha
[not found] ` <20200716172106.2656-4-ville.syrjala@linux.intel.com>
2020-09-24 0:32 ` [Intel-gfx] [PATCH 03/14] drm/i915: Reclassify SKL 0x1923 and 0x1927 as ULT Srivatsa, Anusha
[not found] ` <20200716172106.2656-5-ville.syrjala@linux.intel.com>
2020-09-24 0:37 ` [Intel-gfx] [PATCH 04/14] drm/i915: Add SKL GT1.5 PCI IDs Srivatsa, Anusha
2020-09-24 10:46 ` Ville Syrjälä
2020-09-24 17:54 ` Srivatsa, Anusha
[not found] ` <20200716172106.2656-6-ville.syrjala@linux.intel.com>
2020-09-24 0:40 ` [Intel-gfx] [PATCH 05/14] drm/i915: Try to fix the SKL GT3/4 vs. GT3e/4e comments Srivatsa, Anusha
[not found] ` <20200716172106.2656-7-ville.syrjala@linux.intel.com>
2020-09-24 0:42 ` [Intel-gfx] [PATCH 06/14] drm/i915: Ocd the HSW PCI ID hex numbers Srivatsa, Anusha
[not found] ` <20200716172106.2656-8-ville.syrjala@linux.intel.com>
2020-09-24 0:44 ` Srivatsa, Anusha [this message]
[not found] ` <20200716172106.2656-9-ville.syrjala@linux.intel.com>
2020-09-24 0:49 ` [Intel-gfx] [PATCH 08/14] drm/i915: Sort SKL PCI IDs Srivatsa, Anusha
2020-09-24 10:50 ` Ville Syrjälä
[not found] ` <20200716172106.2656-10-ville.syrjala@linux.intel.com>
2020-09-24 0:50 ` [Intel-gfx] [PATCH 09/14] drm/i915: Sort KBL " Srivatsa, Anusha
[not found] ` <20200716172106.2656-11-ville.syrjala@linux.intel.com>
2020-09-24 0:53 ` [Intel-gfx] [PATCH 10/14] drm/i915: Sort CML " Srivatsa, Anusha
[not found] ` <20200716172106.2656-12-ville.syrjala@linux.intel.com>
2020-09-24 0:55 ` [Intel-gfx] [PATCH 11/14] drm/i915: Sort CFL " Srivatsa, Anusha
[not found] ` <20200716172106.2656-13-ville.syrjala@linux.intel.com>
2020-09-24 0:59 ` [Intel-gfx] [PATCH 12/14] drm/i915: Sort CNL " Srivatsa, Anusha
[not found] ` <20200716172106.2656-14-ville.syrjala@linux.intel.com>
2020-09-24 1:01 ` [Intel-gfx] [PATCH 13/14] drm/i915: Sort ICL " Srivatsa, Anusha
2020-10-23 23:55 ` Lucas De Marchi
[not found] ` <20200716172106.2656-15-ville.syrjala@linux.intel.com>
2020-09-24 1:04 ` [Intel-gfx] [PATCH 14/14] drm/i915: Sort EHL/JSL " Srivatsa, Anusha
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