* [PATCH] drm/i915/gt: Convert the leftover for_each_engine(gt)
@ 2019-10-18 11:49 Chris Wilson
2019-10-18 11:53 ` Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Chris Wilson @ 2019-10-18 11:49 UTC (permalink / raw)
To: intel-gfx
Use the local gt for iterating over the available set of engines.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 12 ++++++------
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 6 +++---
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 71184aa72896..70f0e01a38b9 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -65,7 +65,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
- for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+ for_each_engine(engine, rc6_to_gt(rc6), id)
set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
@@ -133,7 +133,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
- for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+ for_each_engine(engine, rc6_to_gt(rc6), id)
set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
@@ -192,7 +192,7 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6)
set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
- for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+ for_each_engine(engine, rc6_to_gt(rc6), id)
set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
set(uncore, GEN6_RC_SLEEP, 0);
set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
@@ -219,7 +219,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
- for_each_engine(engine, i915, id)
+ for_each_engine(engine, rc6_to_gt(rc6), id)
set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
set(uncore, GEN6_RC_SLEEP, 0);
@@ -344,7 +344,7 @@ static void chv_rc6_enable(struct intel_rc6 *rc6)
set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
- for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+ for_each_engine(engine, rc6_to_gt(rc6), id)
set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
set(uncore, GEN6_RC_SLEEP, 0);
@@ -371,7 +371,7 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
- for_each_engine(engine, rc6_to_gt(rc6)->i915, id)
+ for_each_engine(engine, rc6_to_gt(rc6), id)
set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
set(uncore, GEN6_RC6_THRESHOLD, 0x557);
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 311fdc0a21bc..bf631f15aa78 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -1609,7 +1609,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
struct intel_engine_cs *signaller;
*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
- for_each_engine(signaller, i915, id) {
+ for_each_engine(signaller, engine->gt, id) {
if (signaller == engine)
continue;
@@ -1663,7 +1663,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
i915_reg_t last_reg = {}; /* keep gcc quiet */
*cs++ = MI_LOAD_REGISTER_IMM(num_engines);
- for_each_engine(signaller, i915, id) {
+ for_each_engine(signaller, engine->gt, id) {
if (signaller == engine)
continue;
@@ -1676,7 +1676,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
/* Insert a delay before the next switch! */
*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
*cs++ = i915_mmio_reg_offset(last_reg);
- *cs++ = intel_gt_scratch_offset(rq->engine->gt,
+ *cs++ = intel_gt_scratch_offset(engine->gt,
INTEL_GT_SCRATCH_FIELD_DEFAULT);
*cs++ = MI_NOOP;
}
--
2.23.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH] drm/i915/gt: Convert the leftover for_each_engine(gt) 2019-10-18 11:49 [PATCH] drm/i915/gt: Convert the leftover for_each_engine(gt) Chris Wilson @ 2019-10-18 11:53 ` Chris Wilson 2019-10-18 12:13 ` Tvrtko Ursulin 2019-10-18 12:11 ` Tvrtko Ursulin 2019-10-18 14:04 ` ✗ Fi.CI.BAT: failure for drm/i915/gt: Convert the leftover for_each_engine(gt) (rev2) Patchwork 2 siblings, 1 reply; 5+ messages in thread From: Chris Wilson @ 2019-10-18 11:53 UTC (permalink / raw) To: intel-gfx Use the local gt for iterating over the available set of engines. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/gt/intel_rc6.c | 12 ++++++------ drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 6 +++--- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- drivers/gpu/drm/i915/i915_pmu.c | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 71184aa72896..70f0e01a38b9 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -65,7 +65,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) + for_each_engine(engine, rc6_to_gt(rc6), id) set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); set(uncore, GUC_MAX_IDLE_COUNT, 0xA); @@ -133,7 +133,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) + for_each_engine(engine, rc6_to_gt(rc6), id) set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); set(uncore, GUC_MAX_IDLE_COUNT, 0xA); @@ -192,7 +192,7 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6) set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) + for_each_engine(engine, rc6_to_gt(rc6), id) set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); set(uncore, GEN6_RC_SLEEP, 0); set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ @@ -219,7 +219,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6) set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); - for_each_engine(engine, i915, id) + for_each_engine(engine, rc6_to_gt(rc6), id) set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); set(uncore, GEN6_RC_SLEEP, 0); @@ -344,7 +344,7 @@ static void chv_rc6_enable(struct intel_rc6 *rc6) set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) + for_each_engine(engine, rc6_to_gt(rc6), id) set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); set(uncore, GEN6_RC_SLEEP, 0); @@ -371,7 +371,7 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6) set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) + for_each_engine(engine, rc6_to_gt(rc6), id) set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); set(uncore, GEN6_RC6_THRESHOLD, 0x557); diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c index 311fdc0a21bc..bf631f15aa78 100644 --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c @@ -1609,7 +1609,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) struct intel_engine_cs *signaller; *cs++ = MI_LOAD_REGISTER_IMM(num_engines); - for_each_engine(signaller, i915, id) { + for_each_engine(signaller, engine->gt, id) { if (signaller == engine) continue; @@ -1663,7 +1663,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) i915_reg_t last_reg = {}; /* keep gcc quiet */ *cs++ = MI_LOAD_REGISTER_IMM(num_engines); - for_each_engine(signaller, i915, id) { + for_each_engine(signaller, engine->gt, id) { if (signaller == engine) continue; @@ -1676,7 +1676,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) /* Insert a delay before the next switch! */ *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; *cs++ = i915_mmio_reg_offset(last_reg); - *cs++ = intel_gt_scratch_offset(rq->engine->gt, + *cs++ = intel_gt_scratch_offset(engine->gt, INTEL_GT_SCRATCH_FIELD_DEFAULT); *cs++ = MI_NOOP; } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 0df057838a24..3148d5946b63 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1569,7 +1569,7 @@ static void gen7_ppgtt_enable(struct intel_gt *gt) } intel_uncore_write(uncore, GAM_ECOCHK, ecochk); - for_each_engine(engine, i915, id) { + for_each_engine(engine, gt, id) { /* GFX_MODE is per-ring on gen7+ */ ENGINE_WRITE(engine, RING_MODE_GEN7, diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index 144c32eed045..85912917c062 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -301,7 +301,7 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0) return; - for_each_engine(engine, i915, id) { + for_each_engine(engine, gt, id) { struct intel_engine_pmu *pmu = &engine->pmu; unsigned long flags; bool busy; -- 2.23.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/gt: Convert the leftover for_each_engine(gt) 2019-10-18 11:53 ` Chris Wilson @ 2019-10-18 12:13 ` Tvrtko Ursulin 0 siblings, 0 replies; 5+ messages in thread From: Tvrtko Ursulin @ 2019-10-18 12:13 UTC (permalink / raw) To: Chris Wilson, intel-gfx On 18/10/2019 12:53, Chris Wilson wrote: > Use the local gt for iterating over the available set of engines. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_rc6.c | 12 ++++++------ > drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 6 +++--- > drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +- > drivers/gpu/drm/i915/i915_pmu.c | 2 +- > 4 files changed, 11 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c > index 71184aa72896..70f0e01a38b9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > @@ -65,7 +65,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) > > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > > set(uncore, GUC_MAX_IDLE_COUNT, 0xA); > @@ -133,7 +133,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) > > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > > set(uncore, GUC_MAX_IDLE_COUNT, 0xA); > @@ -192,7 +192,7 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6) > set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > set(uncore, GEN6_RC_SLEEP, 0); > set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ > @@ -219,7 +219,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6) > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); > > - for_each_engine(engine, i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > > set(uncore, GEN6_RC_SLEEP, 0); > @@ -344,7 +344,7 @@ static void chv_rc6_enable(struct intel_rc6 *rc6) > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > set(uncore, GEN6_RC_SLEEP, 0); > > @@ -371,7 +371,7 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6) > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); > > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > > set(uncore, GEN6_RC6_THRESHOLD, 0x557); > diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > index 311fdc0a21bc..bf631f15aa78 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > @@ -1609,7 +1609,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > struct intel_engine_cs *signaller; > > *cs++ = MI_LOAD_REGISTER_IMM(num_engines); > - for_each_engine(signaller, i915, id) { > + for_each_engine(signaller, engine->gt, id) { > if (signaller == engine) > continue; > > @@ -1663,7 +1663,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > i915_reg_t last_reg = {}; /* keep gcc quiet */ > > *cs++ = MI_LOAD_REGISTER_IMM(num_engines); > - for_each_engine(signaller, i915, id) { > + for_each_engine(signaller, engine->gt, id) { > if (signaller == engine) > continue; > > @@ -1676,7 +1676,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > /* Insert a delay before the next switch! */ > *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; > *cs++ = i915_mmio_reg_offset(last_reg); > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, > + *cs++ = intel_gt_scratch_offset(engine->gt, > INTEL_GT_SCRATCH_FIELD_DEFAULT); > *cs++ = MI_NOOP; > } > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 0df057838a24..3148d5946b63 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1569,7 +1569,7 @@ static void gen7_ppgtt_enable(struct intel_gt *gt) > } > intel_uncore_write(uncore, GAM_ECOCHK, ecochk); > > - for_each_engine(engine, i915, id) { > + for_each_engine(engine, gt, id) { > /* GFX_MODE is per-ring on gen7+ */ > ENGINE_WRITE(engine, > RING_MODE_GEN7, > diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c > index 144c32eed045..85912917c062 100644 > --- a/drivers/gpu/drm/i915/i915_pmu.c > +++ b/drivers/gpu/drm/i915/i915_pmu.c > @@ -301,7 +301,7 @@ engines_sample(struct intel_gt *gt, unsigned int period_ns) > if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0) > return; > > - for_each_engine(engine, i915, id) { > + for_each_engine(engine, gt, id) { > struct intel_engine_pmu *pmu = &engine->pmu; > unsigned long flags; > bool busy; > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/gt: Convert the leftover for_each_engine(gt) 2019-10-18 11:49 [PATCH] drm/i915/gt: Convert the leftover for_each_engine(gt) Chris Wilson 2019-10-18 11:53 ` Chris Wilson @ 2019-10-18 12:11 ` Tvrtko Ursulin 2019-10-18 14:04 ` ✗ Fi.CI.BAT: failure for drm/i915/gt: Convert the leftover for_each_engine(gt) (rev2) Patchwork 2 siblings, 0 replies; 5+ messages in thread From: Tvrtko Ursulin @ 2019-10-18 12:11 UTC (permalink / raw) To: Chris Wilson, intel-gfx On 18/10/2019 12:49, Chris Wilson wrote: > Use the local gt for iterating over the available set of engines. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_rc6.c | 12 ++++++------ > drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 6 +++--- > 2 files changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c > index 71184aa72896..70f0e01a38b9 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rc6.c > +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c > @@ -65,7 +65,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) > > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > > set(uncore, GUC_MAX_IDLE_COUNT, 0xA); > @@ -133,7 +133,7 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6) > > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > > set(uncore, GUC_MAX_IDLE_COUNT, 0xA); > @@ -192,7 +192,7 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6) > set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > set(uncore, GEN6_RC_SLEEP, 0); > set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ > @@ -219,7 +219,7 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6) > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); > > - for_each_engine(engine, i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > > set(uncore, GEN6_RC_SLEEP, 0); > @@ -344,7 +344,7 @@ static void chv_rc6_enable(struct intel_rc6 *rc6) > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ > > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > set(uncore, GEN6_RC_SLEEP, 0); > > @@ -371,7 +371,7 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6) > set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); > set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); > > - for_each_engine(engine, rc6_to_gt(rc6)->i915, id) > + for_each_engine(engine, rc6_to_gt(rc6), id) > set(uncore, RING_MAX_IDLE(engine->mmio_base), 10); > > set(uncore, GEN6_RC6_THRESHOLD, 0x557); > diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > index 311fdc0a21bc..bf631f15aa78 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c > @@ -1609,7 +1609,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > struct intel_engine_cs *signaller; > > *cs++ = MI_LOAD_REGISTER_IMM(num_engines); > - for_each_engine(signaller, i915, id) { > + for_each_engine(signaller, engine->gt, id) { > if (signaller == engine) > continue; > > @@ -1663,7 +1663,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > i915_reg_t last_reg = {}; /* keep gcc quiet */ > > *cs++ = MI_LOAD_REGISTER_IMM(num_engines); > - for_each_engine(signaller, i915, id) { > + for_each_engine(signaller, engine->gt, id) { > if (signaller == engine) > continue; > > @@ -1676,7 +1676,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > /* Insert a delay before the next switch! */ > *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; > *cs++ = i915_mmio_reg_offset(last_reg); > - *cs++ = intel_gt_scratch_offset(rq->engine->gt, > + *cs++ = intel_gt_scratch_offset(engine->gt, > INTEL_GT_SCRATCH_FIELD_DEFAULT); > *cs++ = MI_NOOP; > } > Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/gt: Convert the leftover for_each_engine(gt) (rev2) 2019-10-18 11:49 [PATCH] drm/i915/gt: Convert the leftover for_each_engine(gt) Chris Wilson 2019-10-18 11:53 ` Chris Wilson 2019-10-18 12:11 ` Tvrtko Ursulin @ 2019-10-18 14:04 ` Patchwork 2 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2019-10-18 14:04 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx == Series Details == Series: drm/i915/gt: Convert the leftover for_each_engine(gt) (rev2) URL : https://patchwork.freedesktop.org/series/68194/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7128 -> Patchwork_14881 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_14881 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_14881, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_14881: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live_execlists: - fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/fi-cfl-8109u/igt@i915_selftest@live_execlists.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/fi-cfl-8109u/igt@i915_selftest@live_execlists.html Known issues ------------ Here are the changes found in Patchwork_14881 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_flink_basic@bad-open: - fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/fi-icl-u3/igt@gem_flink_basic@bad-open.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/fi-icl-u3/igt@gem_flink_basic@bad-open.html #### Possible fixes #### * igt@gem_exec_suspend@basic: - {fi-icl-u4}: [FAIL][5] ([fdo#111699]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/fi-icl-u4/igt@gem_exec_suspend@basic.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/fi-icl-u4/igt@gem_exec_suspend@basic.html * igt@i915_selftest@live_execlists: - fi-whl-u: [INCOMPLETE][7] ([fdo#112065]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/fi-whl-u/igt@i915_selftest@live_execlists.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/fi-whl-u/igt@i915_selftest@live_execlists.html - fi-cml-u2: [INCOMPLETE][9] ([fdo#110566]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/fi-cml-u2/igt@i915_selftest@live_execlists.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/fi-cml-u2/igt@i915_selftest@live_execlists.html * igt@i915_selftest@live_gem_contexts: - fi-cfl-8109u: [DMESG-FAIL][11] ([fdo#112050 ]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html * igt@i915_selftest@live_hangcheck: - {fi-icl-guc}: [DMESG-FAIL][13] ([fdo#111144] / [fdo#111678]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/fi-icl-guc/igt@i915_selftest@live_hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/fi-icl-guc/igt@i915_selftest@live_hangcheck.html * igt@i915_selftest@live_sanitycheck: - fi-icl-u3: [DMESG-WARN][15] ([fdo#107724]) -> [PASS][16] +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html #### Warnings #### * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][17] ([fdo#111407]) -> [FAIL][18] ([fdo#111045] / [fdo#111096]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7128/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724 [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#110566]: https://bugs.freedesktop.org/show_bug.cgi?id=110566 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111144]: https://bugs.freedesktop.org/show_bug.cgi?id=111144 [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678 [fdo#111699]: https://bugs.freedesktop.org/show_bug.cgi?id=111699 [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735 [fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050 [fdo#112065]: https://bugs.freedesktop.org/show_bug.cgi?id=112065 Participating hosts (52 -> 45) ------------------------------ Additional (1): fi-pnv-d510 Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7128 -> Patchwork_14881 CI-20190529: 20190529 CI_DRM_7128: 8b9127d9e8ad36b96096fb3358a1edb34eda96ba @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5232: bb5735423eaf6fdbf6b2f94ef0b8520e74eab993 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14881: 87fc1c72e05cacb1f2dd60ec50c8163fd0710e84 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 87fc1c72e05c drm/i915/gt: Convert the leftover for_each_engine(gt) == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14881/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-10-18 14:04 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-10-18 11:49 [PATCH] drm/i915/gt: Convert the leftover for_each_engine(gt) Chris Wilson 2019-10-18 11:53 ` Chris Wilson 2019-10-18 12:13 ` Tvrtko Ursulin 2019-10-18 12:11 ` Tvrtko Ursulin 2019-10-18 14:04 ` ✗ Fi.CI.BAT: failure for drm/i915/gt: Convert the leftover for_each_engine(gt) (rev2) Patchwork
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