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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v6 2/6] drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006
Date: Wed, 29 Mar 2023 12:58:24 +0000	[thread overview]
Message-ID: <99be0f4fc47fdd9e55b65e00a09a23ee5437c85c.camel@intel.com> (raw)
In-Reply-To: <ZCQjqUJjyEAqVX1X@intel.com>

On Wed, 2023-03-29 at 14:40 +0300, Ville Syrjälä wrote:
> On Wed, Mar 29, 2023 at 12:45:28PM +0300, Jouni Högander wrote:
> > Wa_16013835468 is a separate from Wa_14015648006 and needs to be
> > applied for TGL onwards. Fix this by removing all the references to
> > Wa_14015648006 and apply Wa_16013835468 according to Bspec.
> > 
> > Also move workaround into separate function as a preparation for
> > Wa_14015648006 implementation.
> > 
> > Bspec: 55378
> > 
> > v2:
> >  - keep applying the wa in intel_psr_enable_source
> > 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_psr.c | 35 ++++++++++++++++----
> > ----
> >  1 file changed, 24 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 8dbf452d63c2..26ad4365960f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1134,6 +1134,28 @@ static u32 wa_16013835468_bit_get(struct
> > intel_dp *intel_dp)
> >         }
> >  }
> >  
> > +/*
> > + * Wa_16013835468
> > + */
> > +static void wm_optimization_wa(struct intel_dp *intel_dp,
> > +                              const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +       struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +       bool set_wa_bit = false;
> > +
> > +       /* Wa_16013835468 */
> > +       if (DISPLAY_VER(dev_priv) >= 12)
> 
> Looks like this should actually be == 12

Ok,I will fix this. It seems I misread the Bspec on this.

> > +               set_wa_bit |= crtc_state-
> > >hw.adjusted_mode.crtc_vblank_start !=
> > +                       crtc_state->hw.adjusted_mode.crtc_vdisplay;
> > +
> > +       if (set_wa_bit)
> > +               intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> 
> Can you drop that 0 to the next line so the two branches
> at least looks a bit more alike?

I will change it.

> 
> Alternatively
> intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
>              wa_16013835468_bit_get(intel_dp),
>              set_wa_bit ? wa_16013835468_bit_get(intel_dp) : 0);
> or something along those lines.
> 
> > +                            wa_16013835468_bit_get(intel_dp));
> > +       else
> > +               intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > +                            wa_16013835468_bit_get(intel_dp), 0);
> > +}
> > +
> >  static void intel_psr_enable_source(struct intel_dp *intel_dp,
> >                                     const struct intel_crtc_state
> > *crtc_state)
> >  {
> > @@ -1175,15 +1197,8 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> >  
> >         /*
> >          * Wa_16013835468
> > -        * Wa_14015648006
> >          */
> > -       if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > -           IS_DISPLAY_VER(dev_priv, 12, 13)) {
> > -               if (crtc_state->hw.adjusted_mode.crtc_vblank_start
> > !=
> > -                   crtc_state->hw.adjusted_mode.crtc_vdisplay)
> > -                       intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> > 0,
> > -                                   
> > wa_16013835468_bit_get(intel_dp));
> > -       }
> > +       wm_optimization_wa(intel_dp, crtc_state);
> >  
> >         if (intel_dp->psr.psr2_enabled) {
> >                 if (DISPLAY_VER(dev_priv) == 9)
> > @@ -1359,10 +1374,8 @@ static void intel_psr_disable_locked(struct
> > intel_dp *intel_dp)
> >  
> >         /*
> >          * Wa_16013835468
> > -        * Wa_14015648006
> >          */
> > -       if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
> > -           IS_DISPLAY_VER(dev_priv, 12, 13))
> > +       if (DISPLAY_VER(dev_priv) >= 12)
> >                 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1,
> >                              wa_16013835468_bit_get(intel_dp), 0);
> >  
> > -- 
> > 2.34.1
> 


  reply	other threads:[~2023-03-29 12:58 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-29  9:45 [Intel-gfx] [PATCH v6 0/6] High refresh rate PSR fixes Jouni Högander
2023-03-29  9:45 ` [Intel-gfx] [PATCH v6 1/6] drm/i915/psr: Unify pre/post hooks Jouni Högander
2023-03-29  9:45 ` [Intel-gfx] [PATCH v6 2/6] drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006 Jouni Högander
2023-03-29 11:40   ` Ville Syrjälä
2023-03-29 12:58     ` Hogander, Jouni [this message]
2023-03-29  9:45 ` [Intel-gfx] [PATCH v6 3/6] drm/i915/psr: Implement Wa_14015648006 Jouni Högander
2023-03-29 11:44   ` Ville Syrjälä
2023-03-29 12:44     ` Hogander, Jouni
2023-03-29  9:45 ` [Intel-gfx] [PATCH v6 4/6] drm/i915/psr: Add helpers for block count number handling Jouni Högander
2023-03-29  9:45 ` [Intel-gfx] [PATCH v6 5/6] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
2023-03-29  9:45 ` [Intel-gfx] [PATCH v6 6/6] drm/i915/psr: Implement Display WA #1136 Jouni Högander
2023-03-29 12:52   ` Ville Syrjälä
2023-03-29 12:59     ` Hogander, Jouni

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