From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Jouni Högander" <jouni.hogander@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v6 6/6] drm/i915/psr: Implement Display WA #1136
Date: Wed, 29 Mar 2023 15:52:14 +0300 [thread overview]
Message-ID: <ZCQ0fuLJRnsGSRs0@intel.com> (raw)
In-Reply-To: <20230329094532.221450-7-jouni.hogander@intel.com>
On Wed, Mar 29, 2023 at 12:45:32PM +0300, Jouni Högander wrote:
> Implement Display WA #1136 for SKL/BXT.
Pre-ICL is more accurate now.
Maybe also mention here that the chicken bit approach
might work for KBL+ but implementing that is left
out for the time being.
>
> Bspec: 21664
>
> v2: Handle disable psr in pre/post plane hooks
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++
> drivers/gpu/drm/i915/display/skl_watermark.c | 5 -----
> 2 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index f86d9f83429f..52f73c65d365 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1968,11 +1968,14 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> * - PSR disabled in new state
> * - All planes will go inactive
> * - Changing between PSR versions
> + * - Display WA #1136: skl, bxt
> */
> needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state);
> needs_to_disable |= !new_crtc_state->has_psr;
> needs_to_disable |= !new_crtc_state->active_planes;
> needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;
> + needs_to_disable |= DISPLAY_VER(i915) < 11 &&
> + new_crtc_state->wm_level_disabled;
>
> if (psr->enabled && needs_to_disable)
> intel_psr_disable_locked(intel_dp);
> @@ -2007,6 +2010,10 @@ static void _intel_psr_post_plane_update(const struct intel_atomic_state *state,
> keep_disabled |= psr->sink_not_reliable;
> keep_disabled |= !crtc_state->active_planes;
>
> + /* Display WA #1136: skl, bxt */
> + keep_disabled |= DISPLAY_VER(dev_priv) < 11 &&
> + crtc_state->wm_level_disabled;
> +
> if (!psr->enabled && !keep_disabled)
> intel_psr_enable_locked(intel_dp, crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 7e2e76afbf2a..5296a20d62d3 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2281,11 +2281,6 @@ static int skl_wm_check_vblank(struct intel_crtc_state *crtc_state)
> */
> crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1;
>
> - /*
> - * FIXME also related to skl+ w/a 1136 (also unimplemented as of
> - * now) perhaps?
> - */
> -
> for (level++; level < i915->display.wm.num_levels; level++) {
> enum plane_id plane_id;
>
> --
> 2.34.1
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-03-29 12:52 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-29 9:45 [Intel-gfx] [PATCH v6 0/6] High refresh rate PSR fixes Jouni Högander
2023-03-29 9:45 ` [Intel-gfx] [PATCH v6 1/6] drm/i915/psr: Unify pre/post hooks Jouni Högander
2023-03-29 9:45 ` [Intel-gfx] [PATCH v6 2/6] drm/i915/psr: Modify/Fix Wa_16013835468 and prepare for Wa_14015648006 Jouni Högander
2023-03-29 11:40 ` Ville Syrjälä
2023-03-29 12:58 ` Hogander, Jouni
2023-03-29 9:45 ` [Intel-gfx] [PATCH v6 3/6] drm/i915/psr: Implement Wa_14015648006 Jouni Högander
2023-03-29 11:44 ` Ville Syrjälä
2023-03-29 12:44 ` Hogander, Jouni
2023-03-29 9:45 ` [Intel-gfx] [PATCH v6 4/6] drm/i915/psr: Add helpers for block count number handling Jouni Högander
2023-03-29 9:45 ` [Intel-gfx] [PATCH v6 5/6] drm/i915/psr: Check that vblank is long enough for psr2 Jouni Högander
2023-03-29 9:45 ` [Intel-gfx] [PATCH v6 6/6] drm/i915/psr: Implement Display WA #1136 Jouni Högander
2023-03-29 12:52 ` Ville Syrjälä [this message]
2023-03-29 12:59 ` Hogander, Jouni
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