[Intel-gfx] [PATCH] i915/pmu: Use a faster read for 2x32 mmio reads

[Intel-gfx] [PATCH] i915/pmu: Use a faster read for 2x32 mmio reads

[Umesh Nerlige Ramappa]

PMU reads the GT timestamp as a 2x32 mmio read and since upper and lower
32 bit registers are read in a loop, there is a latency involved in
getting the GT timestamp. To reduce the latency, define another version
of the helper that requires caller to acquire uncore->spinlock and
necessary forcewakes.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 ++++++++++++++++---
 drivers/gpu/drm/i915/intel_uncore.h           | 24 +++++++++++++++++
 2 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 693b07a97789..64b0193c9ee4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1252,6 +1252,28 @@ static u32 gpm_timestamp_shift(struct intel_gt *gt)
 	return 3 - shift;
 }
 
+static u64 gpm_timestamp(struct intel_uncore *uncore, ktime_t *now)
+{
+	enum forcewake_domains fw_domains;
+	u64 reg;
+
+	/* Assume MISC_STATUS0 and MISC_STATUS1 are in the same fw_domain */
+	fw_domains = intel_uncore_forcewake_for_reg(uncore,
+						    MISC_STATUS0,
+						    FW_REG_READ);
+
+	spin_lock_irq(&uncore->lock);
+	intel_uncore_forcewake_get__locked(uncore, fw_domains);
+
+	reg = intel_uncore_read64_2x32_fw(uncore, MISC_STATUS0, MISC_STATUS1);
+	*now = ktime_get();
+
+	intel_uncore_forcewake_put__locked(uncore, fw_domains);
+	spin_unlock_irq(&uncore->lock);
+
+	return reg;
+}
+
 static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
 {
 	struct intel_gt *gt = guc_to_gt(guc);
@@ -1261,10 +1283,8 @@ static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
 	lockdep_assert_held(&guc->timestamp.lock);
 
 	gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
-	gpm_ts = intel_uncore_read64_2x32(gt->uncore, MISC_STATUS0,
-					  MISC_STATUS1) >> guc->timestamp.shift;
+	gpm_ts = gpm_timestamp(gt->uncore, now) >> guc->timestamp.shift;
 	gt_stamp_lo = lower_32_bits(gpm_ts);
-	*now = ktime_get();
 
 	if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
 		gt_stamp_hi++;
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 5449146a0624..dd0cf7d4ce6c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -455,6 +455,30 @@ static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
 		intel_uncore_write_fw(uncore, reg, val);
 }
 
+/*
+ * Introduce a _fw version of intel_uncore_read64_2x32 so that the 64 bit
+ * register read is as quick as possible.
+ *
+ * NOTE:
+ * Prior to calling this function, the caller must
+ * 1. obtain the uncore->lock
+ * 2. acquire forcewakes for the upper and lower register
+ */
+static inline u64
+intel_uncore_read64_2x32_fw(struct intel_uncore *uncore,
+			    i915_reg_t lower_reg, i915_reg_t upper_reg)
+{
+	u32 upper, lower, old_upper, loop = 0;
+
+	upper = intel_uncore_read_fw(uncore, upper_reg);
+	do {
+		old_upper = upper;
+		lower = intel_uncore_read_fw(uncore, lower_reg);
+		upper = intel_uncore_read_fw(uncore, upper_reg);
+	} while (upper != old_upper && loop++ < 2);
+	return (u64)upper << 32 | lower;
+}
+
 static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
 						i915_reg_t reg, u32 val,
 						u32 mask, u32 expected_val)
-- 
2.36.1

Re: [Intel-gfx] [PATCH] i915/pmu: Use a faster read for 2x32 mmio reads

[Umesh Nerlige Ramappa]

On Thu, Nov 03, 2022 at 11:07:05AM -0700, Umesh Nerlige Ramappa wrote:
>PMU reads the GT timestamp as a 2x32 mmio read and since upper and lower
>32 bit registers are read in a loop, there is a latency involved in
>getting the GT timestamp. To reduce the latency, define another version
>of the helper that requires caller to acquire uncore->spinlock and
>necessary forcewakes.
>
>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Not for review, just to demonstrate one of the solutions to a DG1 BAT 
issue

Thanks,
Umesh
>---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 ++++++++++++++++---
> drivers/gpu/drm/i915/intel_uncore.h           | 24 +++++++++++++++++
> 2 files changed, 47 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>index 693b07a97789..64b0193c9ee4 100644
>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>@@ -1252,6 +1252,28 @@ static u32 gpm_timestamp_shift(struct intel_gt *gt)
> 	return 3 - shift;
> }
>
>+static u64 gpm_timestamp(struct intel_uncore *uncore, ktime_t *now)
>+{
>+	enum forcewake_domains fw_domains;
>+	u64 reg;
>+
>+	/* Assume MISC_STATUS0 and MISC_STATUS1 are in the same fw_domain */
>+	fw_domains = intel_uncore_forcewake_for_reg(uncore,
>+						    MISC_STATUS0,
>+						    FW_REG_READ);
>+
>+	spin_lock_irq(&uncore->lock);
>+	intel_uncore_forcewake_get__locked(uncore, fw_domains);
>+
>+	reg = intel_uncore_read64_2x32_fw(uncore, MISC_STATUS0, MISC_STATUS1);
>+	*now = ktime_get();
>+
>+	intel_uncore_forcewake_put__locked(uncore, fw_domains);
>+	spin_unlock_irq(&uncore->lock);
>+
>+	return reg;
>+}
>+
> static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
> {
> 	struct intel_gt *gt = guc_to_gt(guc);
>@@ -1261,10 +1283,8 @@ static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
> 	lockdep_assert_held(&guc->timestamp.lock);
>
> 	gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
>-	gpm_ts = intel_uncore_read64_2x32(gt->uncore, MISC_STATUS0,
>-					  MISC_STATUS1) >> guc->timestamp.shift;
>+	gpm_ts = gpm_timestamp(gt->uncore, now) >> guc->timestamp.shift;
> 	gt_stamp_lo = lower_32_bits(gpm_ts);
>-	*now = ktime_get();
>
> 	if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
> 		gt_stamp_hi++;
>diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
>index 5449146a0624..dd0cf7d4ce6c 100644
>--- a/drivers/gpu/drm/i915/intel_uncore.h
>+++ b/drivers/gpu/drm/i915/intel_uncore.h
>@@ -455,6 +455,30 @@ static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
> 		intel_uncore_write_fw(uncore, reg, val);
> }
>
>+/*
>+ * Introduce a _fw version of intel_uncore_read64_2x32 so that the 64 bit
>+ * register read is as quick as possible.
>+ *
>+ * NOTE:
>+ * Prior to calling this function, the caller must
>+ * 1. obtain the uncore->lock
>+ * 2. acquire forcewakes for the upper and lower register
>+ */
>+static inline u64
>+intel_uncore_read64_2x32_fw(struct intel_uncore *uncore,
>+			    i915_reg_t lower_reg, i915_reg_t upper_reg)
>+{
>+	u32 upper, lower, old_upper, loop = 0;
>+
>+	upper = intel_uncore_read_fw(uncore, upper_reg);
>+	do {
>+		old_upper = upper;
>+		lower = intel_uncore_read_fw(uncore, lower_reg);
>+		upper = intel_uncore_read_fw(uncore, upper_reg);
>+	} while (upper != old_upper && loop++ < 2);
>+	return (u64)upper << 32 | lower;
>+}
>+
> static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
> 						i915_reg_t reg, u32 val,
> 						u32 mask, u32 expected_val)
>-- 
>2.36.1
>

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915/pmu: Use a faster read for 2x32 mmio reads

[Patchwork]

== Series Details ==

Series: i915/pmu: Use a faster read for 2x32 mmio reads
URL   : https://patchwork.freedesktop.org/series/110497/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.BAT: failure for i915/pmu: Use a faster read for 2x32 mmio reads

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4204 bytes --]

== Series Details ==

Series: i915/pmu: Use a faster read for 2x32 mmio reads
URL   : https://patchwork.freedesktop.org/series/110497/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12339 -> Patchwork_110497v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_110497v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_110497v1, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110497v1/index.html

Participating hosts (40 -> 28)
------------------------------

  Missing    (12): fi-hsw-4200u bat-dg2-8 bat-dg2-9 bat-adlp-6 bat-adlp-4 fi-ctg-p8600 bat-adln-1 bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-dg2-11 fi-bdw-samus 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_110497v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - fi-rkl-guc:         [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12339/fi-rkl-guc/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110497v1/fi-rkl-guc/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_110497v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-g3258:       [PASS][3] -> [INCOMPLETE][4] ([i915#3303] / [i915#4785])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12339/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110497v1/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html

  * igt@runner@aborted:
    - fi-rkl-guc:         NOTRUN -> [FAIL][5] ([i915#4312])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110497v1/fi-rkl-guc/igt@runner@aborted.html
    - fi-hsw-g3258:       NOTRUN -> [FAIL][6] ([fdo#109271] / [i915#4312] / [i915#4991])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110497v1/fi-hsw-g3258/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [FAIL][7] ([i915#7229]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12339/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110497v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
    - fi-bsw-kefka:       [FAIL][9] ([i915#6298]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12339/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110497v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229


Build changes
-------------

  * Linux: CI_DRM_12339 -> Patchwork_110497v1

  CI-20190529: 20190529
  CI_DRM_12339: fafe2d945b3d76b8a7e32102311d8d0495724a3e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7041: 40ea6325f69eb56653171c21b5d4977982a92d0a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_110497v1: fafe2d945b3d76b8a7e32102311d8d0495724a3e @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

06c490fee89b i915/pmu: Use a faster read for 2x32 mmio reads

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_110497v1/index.html

[-- Attachment #2: Type: text/html, Size: 5019 bytes --]

Re: [Intel-gfx] [PATCH] i915/pmu: Use a faster read for 2x32 mmio reads

[Dixit, Ashutosh]

On Thu, 03 Nov 2022 11:07:05 -0700, Umesh Nerlige Ramappa wrote:
>

Hi Umesh,

> PMU reads the GT timestamp as a 2x32 mmio read and since upper and lower
> 32 bit registers are read in a loop, there is a latency involved in
> getting the GT timestamp. To reduce the latency, define another version
> of the helper that requires caller to acquire uncore->spinlock and
> necessary forcewakes.

Why does this reduces the latency compared to intel_uncore_read64_2x32?

Thanks.
--
Ashutosh

> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 ++++++++++++++++---
>  drivers/gpu/drm/i915/intel_uncore.h           | 24 +++++++++++++++++
>  2 files changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 693b07a97789..64b0193c9ee4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -1252,6 +1252,28 @@ static u32 gpm_timestamp_shift(struct intel_gt *gt)
>	return 3 - shift;
>  }
>
> +static u64 gpm_timestamp(struct intel_uncore *uncore, ktime_t *now)
> +{
> +	enum forcewake_domains fw_domains;
> +	u64 reg;
> +
> +	/* Assume MISC_STATUS0 and MISC_STATUS1 are in the same fw_domain */
> +	fw_domains = intel_uncore_forcewake_for_reg(uncore,
> +						    MISC_STATUS0,
> +						    FW_REG_READ);
> +
> +	spin_lock_irq(&uncore->lock);
> +	intel_uncore_forcewake_get__locked(uncore, fw_domains);
> +
> +	reg = intel_uncore_read64_2x32_fw(uncore, MISC_STATUS0, MISC_STATUS1);
> +	*now = ktime_get();
> +
> +	intel_uncore_forcewake_put__locked(uncore, fw_domains);
> +	spin_unlock_irq(&uncore->lock);
> +
> +	return reg;
> +}
> +
>  static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
>  {
>	struct intel_gt *gt = guc_to_gt(guc);
> @@ -1261,10 +1283,8 @@ static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
>	lockdep_assert_held(&guc->timestamp.lock);
>
>	gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
> -	gpm_ts = intel_uncore_read64_2x32(gt->uncore, MISC_STATUS0,
> -					  MISC_STATUS1) >> guc->timestamp.shift;
> +	gpm_ts = gpm_timestamp(gt->uncore, now) >> guc->timestamp.shift;
>	gt_stamp_lo = lower_32_bits(gpm_ts);
> -	*now = ktime_get();
>
>	if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
>		gt_stamp_hi++;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 5449146a0624..dd0cf7d4ce6c 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -455,6 +455,30 @@ static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
>		intel_uncore_write_fw(uncore, reg, val);
>  }
>
> +/*
> + * Introduce a _fw version of intel_uncore_read64_2x32 so that the 64 bit
> + * register read is as quick as possible.
> + *
> + * NOTE:
> + * Prior to calling this function, the caller must
> + * 1. obtain the uncore->lock
> + * 2. acquire forcewakes for the upper and lower register
> + */
> +static inline u64
> +intel_uncore_read64_2x32_fw(struct intel_uncore *uncore,
> +			    i915_reg_t lower_reg, i915_reg_t upper_reg)
> +{
> +	u32 upper, lower, old_upper, loop = 0;
> +
> +	upper = intel_uncore_read_fw(uncore, upper_reg);
> +	do {
> +		old_upper = upper;
> +		lower = intel_uncore_read_fw(uncore, lower_reg);
> +		upper = intel_uncore_read_fw(uncore, upper_reg);
> +	} while (upper != old_upper && loop++ < 2);
> +	return (u64)upper << 32 | lower;
> +}
> +
>  static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
>						i915_reg_t reg, u32 val,
>						u32 mask, u32 expected_val)
> --
> 2.36.1
>

Re: [Intel-gfx] [PATCH] i915/pmu: Use a faster read for 2x32 mmio reads

[Umesh Nerlige Ramappa]

On Thu, Nov 03, 2022 at 10:10:14PM -0700, Dixit, Ashutosh wrote:
>On Thu, 03 Nov 2022 11:07:05 -0700, Umesh Nerlige Ramappa wrote:
>>
>
>Hi Umesh,
>
>> PMU reads the GT timestamp as a 2x32 mmio read and since upper and lower
>> 32 bit registers are read in a loop, there is a latency involved in
>> getting the GT timestamp. To reduce the latency, define another version
>> of the helper that requires caller to acquire uncore->spinlock and
>> necessary forcewakes.
>
>Why does this reduces the latency compared to intel_uncore_read64_2x32?

Most of the error introduced is between the time we capture GPU and CPU 
timestamps. I believe, with intel_uncore_read64_2x32, the time taken for 
forcewake is also included in that time, so that adds up.

Regards,
Umesh
>
>Thanks.
>--
>Ashutosh
>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> ---
>>  .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 26 ++++++++++++++++---
>>  drivers/gpu/drm/i915/intel_uncore.h           | 24 +++++++++++++++++
>>  2 files changed, 47 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> index 693b07a97789..64b0193c9ee4 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>> @@ -1252,6 +1252,28 @@ static u32 gpm_timestamp_shift(struct intel_gt *gt)
>>	return 3 - shift;
>>  }
>>
>> +static u64 gpm_timestamp(struct intel_uncore *uncore, ktime_t *now)
>> +{
>> +	enum forcewake_domains fw_domains;
>> +	u64 reg;
>> +
>> +	/* Assume MISC_STATUS0 and MISC_STATUS1 are in the same fw_domain */
>> +	fw_domains = intel_uncore_forcewake_for_reg(uncore,
>> +						    MISC_STATUS0,
>> +						    FW_REG_READ);
>> +
>> +	spin_lock_irq(&uncore->lock);
>> +	intel_uncore_forcewake_get__locked(uncore, fw_domains);
>> +
>> +	reg = intel_uncore_read64_2x32_fw(uncore, MISC_STATUS0, MISC_STATUS1);
>> +	*now = ktime_get();
>> +
>> +	intel_uncore_forcewake_put__locked(uncore, fw_domains);
>> +	spin_unlock_irq(&uncore->lock);
>> +
>> +	return reg;
>> +}
>> +
>>  static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
>>  {
>>	struct intel_gt *gt = guc_to_gt(guc);
>> @@ -1261,10 +1283,8 @@ static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
>>	lockdep_assert_held(&guc->timestamp.lock);
>>
>>	gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
>> -	gpm_ts = intel_uncore_read64_2x32(gt->uncore, MISC_STATUS0,
>> -					  MISC_STATUS1) >> guc->timestamp.shift;
>> +	gpm_ts = gpm_timestamp(gt->uncore, now) >> guc->timestamp.shift;
>>	gt_stamp_lo = lower_32_bits(gpm_ts);
>> -	*now = ktime_get();
>>
>>	if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
>>		gt_stamp_hi++;
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
>> index 5449146a0624..dd0cf7d4ce6c 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>> @@ -455,6 +455,30 @@ static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
>>		intel_uncore_write_fw(uncore, reg, val);
>>  }
>>
>> +/*
>> + * Introduce a _fw version of intel_uncore_read64_2x32 so that the 64 bit
>> + * register read is as quick as possible.
>> + *
>> + * NOTE:
>> + * Prior to calling this function, the caller must
>> + * 1. obtain the uncore->lock
>> + * 2. acquire forcewakes for the upper and lower register
>> + */
>> +static inline u64
>> +intel_uncore_read64_2x32_fw(struct intel_uncore *uncore,
>> +			    i915_reg_t lower_reg, i915_reg_t upper_reg)
>> +{
>> +	u32 upper, lower, old_upper, loop = 0;
>> +
>> +	upper = intel_uncore_read_fw(uncore, upper_reg);
>> +	do {
>> +		old_upper = upper;
>> +		lower = intel_uncore_read_fw(uncore, lower_reg);
>> +		upper = intel_uncore_read_fw(uncore, upper_reg);
>> +	} while (upper != old_upper && loop++ < 2);
>> +	return (u64)upper << 32 | lower;
>> +}
>> +
>>  static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
>>						i915_reg_t reg, u32 val,
>>						u32 mask, u32 expected_val)
>> --
>> 2.36.1
>>