From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Varide, Nischal" <nischal.varide@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout for platforms that support it
Date: Tue, 2 Mar 2021 16:57:12 +0200 [thread overview]
Message-ID: <YD5SSEELPvX8hiv2@intel.com> (raw)
In-Reply-To: <87czwhq2df.fsf@intel.com>
On Tue, Mar 02, 2021 at 12:25:00PM +0200, Jani Nikula wrote:
> On Mon, 22 Feb 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> > On Mon, 22 Feb 2021, "Shankar, Uma" <uma.shankar@intel.com> wrote:
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> index 71611b596c88..5564db512d22 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >>> @@ -1161,6 +1161,13 @@ struct intel_crtc_state {
> >>> u8 pipeline_full;
> >>> u16 flipline, vmin, vmax;
> >>> } vrr;
> >>> +
> >>> + /* Stream Splitter for eDP MSO */
> >>> + struct {
> >>> + bool enable;
> >>> + u8 link_count;
> >>> + u8 pixel_overlap;
> >>> + } splitter;
> >>
> >> For DSI which also has this in common along with MSO, may be we can
> >> take these link_count and pixel_overlap out of splitter which is more
> >> of a MSO feature. Thoughts ?
> >
> > Ville suggested the same I think.
>
> Coming back to this. DSI does not actually use crtc state for this
> currently. But it does use the display stream splitter. The register is
> different, but the functionality is roughly the same.
>
> I suggest we keep the "splitter" substruct as above, and convert DSI
> code to use it in follow-up.
>
> In early versions of the patch the substruct was called "mso"; I think
> "splitter" is better, and captures both MSO and DSI cases.
The "splitter" name is rather icl+ specific. Earlier DSI or LVDS do not
have such a hw block (at least in name).
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2021-03-02 14:57 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-11 14:52 [Intel-gfx] [PATCH v3 0/9] drm/i915/edp: enable eDP Multi-SST Operation (MSO) Jani Nikula
2021-02-11 14:52 ` [Intel-gfx] [PATCH v3 1/9] drm/dp: add MSO related DPCD registers Jani Nikula
2021-02-22 5:25 ` Shankar, Uma
2021-02-11 14:52 ` [Intel-gfx] [PATCH v3 2/9] drm/i915/edp: reject modes with dimensions other than fixed mode Jani Nikula
2021-02-22 5:36 ` Shankar, Uma
2021-02-11 14:52 ` [Intel-gfx] [PATCH v3 3/9] drm/i915/edp: always add fixed mode to probed modes in ->get_modes() Jani Nikula
2021-02-22 5:50 ` Shankar, Uma
2021-02-11 14:52 ` [Intel-gfx] [PATCH v3 4/9] drm/i915/edp: read sink MSO configuration for eDP 1.4+ Jani Nikula
2021-02-22 5:57 ` Shankar, Uma
2021-02-11 14:52 ` [Intel-gfx] [PATCH v3 5/9] drm/i915/reg: add stream splitter configuration definitions Jani Nikula
2021-02-22 5:58 ` Shankar, Uma
2021-02-22 16:31 ` Jani Nikula
2021-02-11 14:52 ` [Intel-gfx] [PATCH v3 6/9] drm/i915/mso: add splitter state readout for platforms that support it Jani Nikula
2021-02-22 9:09 ` Shankar, Uma
2021-02-22 16:55 ` Jani Nikula
2021-02-22 18:11 ` Shankar, Uma
2021-03-02 10:25 ` Jani Nikula
2021-03-02 10:29 ` Shankar, Uma
2021-03-02 14:57 ` Ville Syrjälä [this message]
2021-03-02 17:20 ` Jani Nikula
2021-02-11 14:52 ` [Intel-gfx] [PATCH v3 7/9] drm/i915/mso: add splitter state check Jani Nikula
2021-02-22 9:13 ` Shankar, Uma
2021-02-11 14:52 ` [Intel-gfx] [PATCH v3 8/9] drm/i915/edp: modify fixed and downclock modes for MSO Jani Nikula
2021-02-22 9:21 ` Shankar, Uma
2021-02-11 14:52 ` [Intel-gfx] [PATCH v3 9/9] drm/i915/edp: enable eDP MSO during link training Jani Nikula
2021-02-22 10:06 ` Shankar, Uma
2021-02-11 15:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/edp: enable eDP Multi-SST Operation (MSO) Patchwork
2021-02-11 16:03 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-11 17:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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