Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Daniel Vetter <daniel@ffwll.ch>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	Vinay Belgaumkar <vinay.belgaumkar@intel.com>,
	Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Subject: Re: [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain
Date: Wed, 8 Sep 2021 18:46:29 +0200	[thread overview]
Message-ID: <YTjo5Yfcjoyf/Evz@phenom.ffwll.local> (raw)
In-Reply-To: <20210907171916.2548047-3-matthew.d.roper@intel.com>

On Tue, Sep 07, 2021 at 10:19:10AM -0700, Matt Roper wrote:
> The reset domain is shared between render and all compute engines,
> so resetting one will affect the others.
> 
> Note:  Before performing a reset on an RCS or CCS engine, the GuC will
> attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
> impacting other clients (since some shared modules will be reset).  If
> other engines are executing non-preemptable workloads, the impact is
> unavoidable and some work may be lost.
> 
> Bspec: 52549
> Original-patch-by: Michel Thierry
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Do we have igts validating this all properly?

Specifically that the reset stats are incremented correctly for guilty
respectively victimized contexts.

This is necessary if it doesn't exist yet.

Also you need a patch set here that fixes up the igts which have wrong
assumptions about context isolation.
-Daniel

> ---
>  drivers/gpu/drm/i915/gt/intel_reset.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 91200c43951f..30598c1d070c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -507,6 +507,10 @@ static int gen11_reset_engines(struct intel_gt *gt,
>  		[VECS1] = GEN11_GRDOM_VECS2,
>  		[VECS2] = GEN11_GRDOM_VECS3,
>  		[VECS3] = GEN11_GRDOM_VECS4,
> +		[CCS0] = GEN11_GRDOM_RENDER,
> +		[CCS1] = GEN11_GRDOM_RENDER,
> +		[CCS2] = GEN11_GRDOM_RENDER,
> +		[CCS3] = GEN11_GRDOM_RENDER,
>  	};
>  	struct intel_engine_cs *engine;
>  	intel_engine_mask_t tmp;
> -- 
> 2.25.4
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

  parent reply	other threads:[~2021-09-08 16:46 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-07 17:19 [Intel-gfx] [PATCH 0/8] i915: Introduce Xe_HP compute engines Matt Roper
2021-09-07 17:19 ` [Intel-gfx] [PATCH 1/8] drm/i915/xehp: Define compute class and engine Matt Roper
2021-09-08  9:46   ` Tvrtko Ursulin
2021-09-08 16:42   ` Daniel Vetter
2021-09-07 17:19 ` [Intel-gfx] [PATCH 2/8] drm/i915/xehp: CCS shares the render reset domain Matt Roper
2021-09-08 10:07   ` Tvrtko Ursulin
2021-09-08 20:23     ` Matt Roper
2021-09-09  8:11       ` Tvrtko Ursulin
2021-09-08 16:46   ` Daniel Vetter [this message]
2021-09-07 17:19 ` [Intel-gfx] [PATCH 3/8] drm/i915/xehp: Add Compute CS IRQ handlers Matt Roper
2021-09-08 10:09   ` Tvrtko Ursulin
2021-09-07 17:19 ` [Intel-gfx] [PATCH 4/8] drm/i915/xehp: CCS should use RCS setup functions Matt Roper
2021-09-08 10:13   ` Tvrtko Ursulin
2021-09-08 13:57     ` Tvrtko Ursulin
2021-09-07 17:19 ` [Intel-gfx] [PATCH 5/8] drm/i915/xehp: compute engine pipe_control Matt Roper
2021-09-07 17:19 ` [Intel-gfx] [PATCH 6/8] drm/i915/xehp: Define context scheduling attributes in lrc descriptor Matt Roper
2021-09-08 14:01   ` Tvrtko Ursulin
2021-09-07 17:19 ` [Intel-gfx] [PATCH 7/8] drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE Matt Roper
2021-09-08 14:10   ` Tvrtko Ursulin
2021-09-07 17:19 ` [Intel-gfx] [PATCH 8/8] drm/i915/xehp: Extend uninterruptible OpenCL workloads to CCS Matt Roper
2021-09-08 14:15   ` Tvrtko Ursulin
2021-09-07 20:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Introduce Xe_HP compute engines Patchwork
2021-09-07 20:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-07 20:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-08  0:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YTjo5Yfcjoyf/Evz@phenom.ffwll.local \
    --to=daniel@ffwll.ch \
    --cc=aravind.iddamsetty@intel.com \
    --cc=daniele.ceraolospurio@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=matthew.d.roper@intel.com \
    --cc=tvrtko.ursulin@linux.intel.com \
    --cc=vinay.belgaumkar@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox