[Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2

[Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2

[Stanislav Lisovskiy]

Bug in the register unit which results in WM1 register
used when only WM0 is enabled on cursor.
Software workaround is when only WM0 enabled on cursor,
copy contents of CUR_WM_0[30:0] (exclude the enable bit)
into CUR_WM_1[30:0].

HSDES: 14012656716

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89dc7f69baf3..4bc90196d0fb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5095,6 +5095,18 @@ skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
 	}
 }
 
+static bool icl_need_wm1_wa(struct drm_i915_private *dev_priv,
+			    enum plane_id plane_id)
+{
+	/*
+	 * Wa_1408961008:icl, ehl
+	 * Wa_14012656716:tgl, adl
+	 * Underruns with WM1+ disabled
+	 */
+	return (DISPLAY_VER(dev_priv) == 11) ||
+	       (IS_DISPLAY_VER(dev_priv, 12, 13) && (plane_id == PLANE_CURSOR));
+}
+
 static int
 skl_allocate_plane_ddb(struct intel_atomic_state *state,
 		       struct intel_crtc *crtc)
@@ -5265,11 +5277,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 			skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
 						total[plane_id], uv_total[plane_id]);
 
-			/*
-			 * Wa_1408961008:icl, ehl
-			 * Underruns with WM1+ disabled
-			 */
-			if (DISPLAY_VER(dev_priv) == 11 &&
+			if (icl_need_wm1_wa(dev_priv, plane_id) &&
 			    level == 1 && wm->wm[0].enable) {
 				wm->wm[level].blocks = wm->wm[0].blocks;
 				wm->wm[level].lines = wm->wm[0].lines;
-- 
2.24.1.485.gad05a3d8e5

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2

[Ville Syrjälä]

On Wed, Nov 17, 2021 at 03:43:41PM +0200, Stanislav Lisovskiy wrote:
> Bug in the register unit which results in WM1 register
> used when only WM0 is enabled on cursor.
> Software workaround is when only WM0 enabled on cursor,
> copy contents of CUR_WM_0[30:0] (exclude the enable bit)
> into CUR_WM_1[30:0].
> 
> HSDES: 14012656716
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 89dc7f69baf3..4bc90196d0fb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5095,6 +5095,18 @@ skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
>  	}
>  }
>  
> +static bool icl_need_wm1_wa(struct drm_i915_private *dev_priv,

s/dev_priv/i915/

> +			    enum plane_id plane_id)
> +{
> +	/*
> +	 * Wa_1408961008:icl, ehl
> +	 * Wa_14012656716:tgl, adl
> +	 * Underruns with WM1+ disabled
> +	 */
> +	return (DISPLAY_VER(dev_priv) == 11) ||
> +	       (IS_DISPLAY_VER(dev_priv, 12, 13) && (plane_id == PLANE_CURSOR));

Unnecessary parens in a few places there. With those removed this is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +}
> +
>  static int
>  skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  		       struct intel_crtc *crtc)
> @@ -5265,11 +5277,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  			skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
>  						total[plane_id], uv_total[plane_id]);
>  
> -			/*
> -			 * Wa_1408961008:icl, ehl
> -			 * Underruns with WM1+ disabled
> -			 */
> -			if (DISPLAY_VER(dev_priv) == 11 &&
> +			if (icl_need_wm1_wa(dev_priv, plane_id) &&
>  			    level == 1 && wm->wm[0].enable) {
>  				wm->wm[level].blocks = wm->wm[0].blocks;
>  				wm->wm[level].lines = wm->wm[0].lines;
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dg2: Implement WM0 cursor WA for DG2

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6570 bytes --]

== Series Details ==

Series: drm/i915/dg2: Implement WM0 cursor WA for DG2
URL   : https://patchwork.freedesktop.org/series/97022/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10896 -> Patchwork_21616
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_21616 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21616, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/index.html

Participating hosts (40 -> 33)
------------------------------

  Additional (1): fi-tgl-1115g4 
  Missing    (8): bat-dg1-6 fi-tgl-u2 fi-hsw-4200u fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 bat-jsl-2 bat-jsl-1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_21616:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_lmem_swapping@verify-random:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][1] +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@gem_lmem_swapping@verify-random.html

  * igt@kms_psr@primary_page_flip:
    - fi-skl-6600u:       [PASS][2] -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10896/fi-skl-6600u/igt@kms_psr@primary_page_flip.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-skl-6600u/igt@kms_psr@primary_page_flip.html

  
Known issues
------------

  Here are the changes found in Patchwork_21616 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-gfx:
    - fi-rkl-guc:         NOTRUN -> [SKIP][4] ([fdo#109315]) +17 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-rkl-guc/igt@amdgpu/amd_basic@cs-gfx.html

  * igt@amdgpu/amd_basic@query-info:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][5] ([fdo#109315])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html

  * igt@amdgpu/amd_cs_nop@nop-gfx0:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][6] ([fdo#109315] / [i915#2575]) +16 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][8] ([i915#1155])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][9] ([fdo#111827]) +8 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][10] ([i915#4103]) +1 similar issue
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][11] ([fdo#109285])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@primary_mmap_gtt:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][12] ([i915#1072]) +3 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html

  * igt@prime_vgem@basic-userptr:
    - fi-tgl-1115g4:      NOTRUN -> [SKIP][13] ([i915#3301])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-skl-6600u:       NOTRUN -> [FAIL][14] ([i915#3363] / [i915#4312])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-skl-6600u/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@evict:
    - fi-kbl-soraka:      [DMESG-WARN][15] -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10896/fi-kbl-soraka/igt@i915_selftest@live@evict.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-kbl-soraka/igt@i915_selftest@live@evict.html

  * igt@i915_selftest@live@gt_engines:
    - fi-rkl-guc:         [DMESG-FAIL][17] -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10896/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312


Build changes
-------------

  * Linux: CI_DRM_10896 -> Patchwork_21616

  CI-20190529: 20190529
  CI_DRM_10896: bf11e5f354ac51635d032893d80a1d0015d277dc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6283: a2cd90a7c24bb7a4c19ca74c75ed8c950820dee2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21616: 6b95a81bcd383659aaec4bf61c0f6bfbf935c4c5 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6b95a81bcd38 drm/i915/dg2: Implement WM0 cursor WA for DG2

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21616/index.html

[-- Attachment #2: Type: text/html, Size: 7657 bytes --]

[Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2

[Stanislav Lisovskiy]

Bug in the register unit which results in WM1 register
used when only WM0 is enabled on cursor.
Software workaround is when only WM0 enabled on cursor,
copy contents of CUR_WM_0[30:0] (exclude the enable bit)
into CUR_WM_1[30:0].

v2:  - s/dev_priv/i915/ (Ville Syrjälä)
     - Removed unneeded brackets (Ville Syrjälä)

HSDES: 14012656716

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89dc7f69baf3..01fa3fac1b57 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5095,6 +5095,18 @@ skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
 	}
 }
 
+static bool icl_need_wm1_wa(struct drm_i915_private *i915,
+			    enum plane_id plane_id)
+{
+	/*
+	 * Wa_1408961008:icl, ehl
+	 * Wa_14012656716:tgl, adl
+	 * Underruns with WM1+ disabled
+	 */
+	return DISPLAY_VER(i915) == 11 ||
+	       (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
+}
+
 static int
 skl_allocate_plane_ddb(struct intel_atomic_state *state,
 		       struct intel_crtc *crtc)
@@ -5265,11 +5277,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
 			skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
 						total[plane_id], uv_total[plane_id]);
 
-			/*
-			 * Wa_1408961008:icl, ehl
-			 * Underruns with WM1+ disabled
-			 */
-			if (DISPLAY_VER(dev_priv) == 11 &&
+			if (icl_need_wm1_wa(dev_priv, plane_id) &&
 			    level == 1 && wm->wm[0].enable) {
 				wm->wm[level].blocks = wm->wm[0].blocks;
 				wm->wm[level].lines = wm->wm[0].lines;
-- 
2.24.1.485.gad05a3d8e5

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2

[Jani Nikula]

On Thu, 18 Nov 2021, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> Bug in the register unit which results in WM1 register
> used when only WM0 is enabled on cursor.
> Software workaround is when only WM0 enabled on cursor,
> copy contents of CUR_WM_0[30:0] (exclude the enable bit)
> into CUR_WM_1[30:0].
>
> v2:  - s/dev_priv/i915/ (Ville Syrjälä)
>      - Removed unneeded brackets (Ville Syrjälä)
>
> HSDES: 14012656716
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++-----
>  1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 89dc7f69baf3..01fa3fac1b57 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5095,6 +5095,18 @@ skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
>  	}
>  }
>  
> +static bool icl_need_wm1_wa(struct drm_i915_private *i915,
> +			    enum plane_id plane_id)

Commit subject having "WM0 cursor WA" and the function saying "wm1_wa"
looks like a discrepancy to the casual reader.

BR,
Jani.

> +{
> +	/*
> +	 * Wa_1408961008:icl, ehl
> +	 * Wa_14012656716:tgl, adl
> +	 * Underruns with WM1+ disabled
> +	 */
> +	return DISPLAY_VER(i915) == 11 ||
> +	       (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
> +}
> +
>  static int
>  skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  		       struct intel_crtc *crtc)
> @@ -5265,11 +5277,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
>  			skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
>  						total[plane_id], uv_total[plane_id]);
>  
> -			/*
> -			 * Wa_1408961008:icl, ehl
> -			 * Underruns with WM1+ disabled
> -			 */
> -			if (DISPLAY_VER(dev_priv) == 11 &&
> +			if (icl_need_wm1_wa(dev_priv, plane_id) &&
>  			    level == 1 && wm->wm[0].enable) {
>  				wm->wm[level].blocks = wm->wm[0].blocks;
>  				wm->wm[level].lines = wm->wm[0].lines;

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2

[Lisovskiy, Stanislav]

On Wed, Nov 24, 2021 at 12:23:08PM +0200, Jani Nikula wrote:
> On Thu, 18 Nov 2021, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
> > Bug in the register unit which results in WM1 register
> > used when only WM0 is enabled on cursor.
> > Software workaround is when only WM0 enabled on cursor,
> > copy contents of CUR_WM_0[30:0] (exclude the enable bit)
> > into CUR_WM_1[30:0].
> >
> > v2:  - s/dev_priv/i915/ (Ville Syrjälä)
> >      - Removed unneeded brackets (Ville Syrjälä)
> >
> > HSDES: 14012656716
> >
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++++++-----
> >  1 file changed, 13 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 89dc7f69baf3..01fa3fac1b57 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5095,6 +5095,18 @@ skl_check_nv12_wm_level(struct skl_wm_level *wm, struct skl_wm_level *uv_wm,
> >  	}
> >  }
> >  
> > +static bool icl_need_wm1_wa(struct drm_i915_private *i915,
> > +			    enum plane_id plane_id)
> 
> Commit subject having "WM0 cursor WA" and the function saying "wm1_wa"
> looks like a discrepancy to the casual reader.

Agree, not the best naming. Should be either WM0 or WM1.
Thing is that due to nature of that W/A both can be correct.
Patch has been pushed week ago, after r-b from Ville.

I will send a fix anyway.

Stan

> 
> BR,
> Jani.
> 
> > +{
> > +	/*
> > +	 * Wa_1408961008:icl, ehl
> > +	 * Wa_14012656716:tgl, adl
> > +	 * Underruns with WM1+ disabled
> > +	 */
> > +	return DISPLAY_VER(i915) == 11 ||
> > +	       (IS_DISPLAY_VER(i915, 12, 13) && plane_id == PLANE_CURSOR);
> > +}
> > +
> >  static int
> >  skl_allocate_plane_ddb(struct intel_atomic_state *state,
> >  		       struct intel_crtc *crtc)
> > @@ -5265,11 +5277,7 @@ skl_allocate_plane_ddb(struct intel_atomic_state *state,
> >  			skl_check_nv12_wm_level(&wm->wm[level], &wm->uv_wm[level],
> >  						total[plane_id], uv_total[plane_id]);
> >  
> > -			/*
> > -			 * Wa_1408961008:icl, ehl
> > -			 * Underruns with WM1+ disabled
> > -			 */
> > -			if (DISPLAY_VER(dev_priv) == 11 &&
> > +			if (icl_need_wm1_wa(dev_priv, plane_id) &&
> >  			    level == 1 && wm->wm[0].enable) {
> >  				wm->wm[level].blocks = wm->wm[0].blocks;
> >  				wm->wm[level].lines = wm->wm[0].lines;
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH] drm/i915/dg2: Implement WM0 cursor WA for DG2

[Jani Nikula]

On Wed, 24 Nov 2021, "Lisovskiy, Stanislav" <stanislav.lisovskiy@intel.com> wrote:
> On Wed, Nov 24, 2021 at 12:23:08PM +0200, Jani Nikula wrote:
>> On Thu, 18 Nov 2021, Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> wrote:
>> > +static bool icl_need_wm1_wa(struct drm_i915_private *i915,
>> > +			    enum plane_id plane_id)
>> 
>> Commit subject having "WM0 cursor WA" and the function saying "wm1_wa"
>> looks like a discrepancy to the casual reader.
>
> Agree, not the best naming. Should be either WM0 or WM1.
> Thing is that due to nature of that W/A both can be correct.
> Patch has been pushed week ago, after r-b from Ville.
>
> I will send a fix anyway.

*shrug* Not sure it matters, just an observation going through mails.

BR,
Jani.


-- 
Jani Nikula, Intel Open Source Graphics Center