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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 6/8] drm/i915/debugfs: Add perf_limit_reasons in debugfs
Date: Fri, 9 Sep 2022 06:13:05 -0400	[thread overview]
Message-ID: <YxsRscHgVHEv9+VS@intel.com> (raw)
In-Reply-To: <aba9305853caa054dc598a0f559495d3e4e2b1be.1662613377.git.ashutosh.dixit@intel.com>

On Wed, Sep 07, 2022 at 10:22:49PM -0700, Ashutosh Dixit wrote:
> From: Tilak Tangudu <tilak.tangudu@intel.com>
> 
> Add perf_limit_reasons in debugfs. The upper 16 perf_limit_reasons RW "log"
> bits are identical to the lower 16 RO "status" bits except that the "log"
> bits remain set until cleared, thereby ensuring the throttling occurrence
> is not missed. The clear fop clears the upper 16 "log" bits, the get fop
> gets all 32 "log" and "status" bits.
> 
> v2: Expand commit message and clarify "log" and "status" bits in
>     comment (Rodrigo)
> 
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Signed-off-by: Tilak Tangudu <tilak.tangudu@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 31 +++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               |  1 +
>  2 files changed, 32 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index 108b9e76c32e..a009cf69103a 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -655,6 +655,36 @@ static bool rps_eval(void *data)
>  
>  DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(rps_boost);
>  
> +static int perf_limit_reasons_get(void *data, u64 *val)
> +{
> +	struct intel_gt *gt = data;
> +	intel_wakeref_t wakeref;
> +
> +	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> +		*val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
> +
> +	return 0;
> +}
> +
> +static int perf_limit_reasons_clear(void *data, u64 val)
> +{
> +	struct intel_gt *gt = data;
> +	intel_wakeref_t wakeref;
> +
> +	/*
> +	 * Clear the upper 16 "log" bits, the lower 16 "status" bits are
> +	 * read-only. The upper 16 "log" bits are identical to the lower 16
> +	 * "status" bits except that the "log" bits remain set until cleared.
> +	 */
> +	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> +		intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
> +				 GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
> +
> +	return 0;
> +}
> +DEFINE_SIMPLE_ATTRIBUTE(perf_limit_reasons_fops, perf_limit_reasons_get,
> +			perf_limit_reasons_clear, "%llu\n");
> +
>  void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
>  {
>  	static const struct intel_gt_debugfs_file files[] = {
> @@ -664,6 +694,7 @@ void intel_gt_pm_debugfs_register(struct intel_gt *gt, struct dentry *root)
>  		{ "forcewake_user", &forcewake_user_fops, NULL},
>  		{ "llc", &llc_fops, llc_eval },
>  		{ "rps_boost", &rps_boost_fops, rps_eval },
> +		{ "perf_limit_reasons", &perf_limit_reasons_fops, NULL },
>  	};
>  
>  	intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 24009786f88b..9492f8f43b25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1802,6 +1802,7 @@
>  #define   POWER_LIMIT_4_MASK		REG_BIT(8)
>  #define   POWER_LIMIT_1_MASK		REG_BIT(10)
>  #define   POWER_LIMIT_2_MASK		REG_BIT(11)
> +#define   GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
>

I'm kind of confused here because I saw the other bits in the patch 5.

but, anyway, thanks for improving the commit msg.


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  #define CHV_CLK_CTL1			_MMIO(0x101100)
>  #define VLV_CLK_CTL2			_MMIO(0x101104)
> -- 
> 2.34.1
> 

  reply	other threads:[~2022-09-09 10:13 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-08  5:18 [Intel-gfx] [PATCH 0/8] i915: freq caps and perf_limit_reasons changes for MTL Ashutosh Dixit
2022-09-08  5:18 ` [Intel-gfx] [PATCH 1/8] drm/i915: Prepare more multi-GT initialization Ashutosh Dixit
2022-09-08  5:18 ` [Intel-gfx] [PATCH 2/8] drm/i915: Rename and expose common GT early init routine Ashutosh Dixit
2022-09-08  5:18 ` [Intel-gfx] [PATCH 3/8] drm/i915/uncore: Add GSI offset to uncore Ashutosh Dixit
2022-09-08  5:18 ` [Intel-gfx] [PATCH 4/8] drm/i915/xelpmp: Expose media as another GT Ashutosh Dixit
2022-09-08  5:21 ` [Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions Ashutosh Dixit
2022-09-08 10:42   ` Andi Shyti
2022-09-08 12:37     ` Sundaresan, Sujaritha
2022-09-08 12:50       ` Andi Shyti
2022-09-08 15:49       ` Dixit, Ashutosh
2022-09-08  5:22 ` [Intel-gfx] [PATCH 6/8] drm/i915/debugfs: Add perf_limit_reasons in debugfs Ashutosh Dixit
2022-09-09 10:13   ` Rodrigo Vivi [this message]
2022-09-09 15:38     ` Dixit, Ashutosh
2022-09-09 16:39       ` Vivi, Rodrigo
2022-09-08  5:23 ` [Intel-gfx] [PATCH 7/8] drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL Ashutosh Dixit
2022-09-09 10:15   ` Rodrigo Vivi
2022-09-08  5:23 ` [Intel-gfx] [PATCH 8/8] drm/i915/rps: Freq caps " Ashutosh Dixit
2022-09-09 10:16   ` Rodrigo Vivi
2022-09-08  5:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: freq caps and perf_limit_reasons changes for MTL (rev2) Patchwork
2022-09-08  5:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-08  6:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-08 11:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-09-09 18:13 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for i915: freq caps and perf_limit_reasons changes for MTL (rev3) Patchwork

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