Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL
Date: Fri, 9 Sep 2022 06:15:35 -0400	[thread overview]
Message-ID: <YxsSR0FNNlpaxmPs@intel.com> (raw)
In-Reply-To: <33dce2f6fd36cbaa570265997a5b2f4034fb6688.1662613377.git.ashutosh.dixit@intel.com>

On Wed, Sep 07, 2022 at 10:23:38PM -0700, Ashutosh Dixit wrote:
> PERF_LIMIT_REASONS register for MTL media gt is different now.
> 
> v2: Avoid static inline for intel_gt_perf_limit_reasons_reg() (Jani)
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Badal Nilawar <badal.nilawar@intel.com>
> Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c            | 6 ++++++
>  drivers/gpu/drm/i915/gt/intel_gt.h            | 1 +
>  drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 ++--
>  drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c   | 6 +++---
>  drivers/gpu/drm/i915/i915_reg.h               | 1 +
>  5 files changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 070068524a19..602d711d3c9e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -224,6 +224,12 @@ static void gen6_clear_engine_error_register(struct intel_engine_cs *engine)
>  	GEN6_RING_FAULT_REG_POSTING_READ(engine);
>  }
>  
> +i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt)
> +{
> +	return gt->type == GT_MEDIA ?
> +		MTL_MEDIA_PERF_LIMIT_REASONS : GT0_PERF_LIMIT_REASONS;
> +}
> +
>  void
>  intel_gt_clear_error_registers(struct intel_gt *gt,
>  			       intel_engine_mask_t engine_mask)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index c9a359f35d0f..b6509d3e8804 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -60,6 +60,7 @@ void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>  int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
>  
>  void intel_gt_check_and_clear_faults(struct intel_gt *gt);
> +i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt);
>  void intel_gt_clear_error_registers(struct intel_gt *gt,
>  				    intel_engine_mask_t engine_mask);
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> index a009cf69103a..68310881a793 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
> @@ -661,7 +661,7 @@ static int perf_limit_reasons_get(void *data, u64 *val)
>  	intel_wakeref_t wakeref;
>  
>  	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> -		*val = intel_uncore_read(gt->uncore, GT0_PERF_LIMIT_REASONS);
> +		*val = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt));
>  
>  	return 0;
>  }
> @@ -677,7 +677,7 @@ static int perf_limit_reasons_clear(void *data, u64 val)
>  	 * "status" bits except that the "log" bits remain set until cleared.
>  	 */
>  	with_intel_runtime_pm(gt->uncore->rpm, wakeref)
> -		intel_uncore_rmw(gt->uncore, GT0_PERF_LIMIT_REASONS,
> +		intel_uncore_rmw(gt->uncore, intel_gt_perf_limit_reasons_reg(gt),
>  				 GT0_PERF_LIMIT_REASONS_LOG_MASK, 0);
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index e066cc33d9f2..54deae45d81f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -510,7 +510,7 @@ struct intel_gt_bool_throttle_attr {
>  	struct attribute attr;
>  	ssize_t (*show)(struct device *dev, struct device_attribute *attr,
>  			char *buf);
> -	i915_reg_t reg32;
> +	i915_reg_t (*reg32)(struct intel_gt *gt);
>  	u32 mask;
>  };
>  
> @@ -521,7 +521,7 @@ static ssize_t throttle_reason_bool_show(struct device *dev,
>  	struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
>  	struct intel_gt_bool_throttle_attr *t_attr =
>  				(struct intel_gt_bool_throttle_attr *) attr;
> -	bool val = rps_read_mask_mmio(&gt->rps, t_attr->reg32, t_attr->mask);
> +	bool val = rps_read_mask_mmio(&gt->rps, t_attr->reg32(gt), t_attr->mask);
>  
>  	return sysfs_emit(buff, "%u\n", val);
>  }
> @@ -530,7 +530,7 @@ static ssize_t throttle_reason_bool_show(struct device *dev,
>  struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
>  	.attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
>  	.show = throttle_reason_bool_show, \
> -	.reg32 = GT0_PERF_LIMIT_REASONS, \
> +	.reg32 = intel_gt_perf_limit_reasons_reg, \
>  	.mask = mask__, \
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9492f8f43b25..10a89d869b00 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1803,6 +1803,7 @@
>  #define   POWER_LIMIT_1_MASK		REG_BIT(10)
>  #define   POWER_LIMIT_2_MASK		REG_BIT(11)
>  #define   GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
> +#define MTL_MEDIA_PERF_LIMIT_REASONS	_MMIO(0x138030)
>  
>  #define CHV_CLK_CTL1			_MMIO(0x101100)
>  #define VLV_CLK_CTL2			_MMIO(0x101104)
> -- 
> 2.34.1
> 

  reply	other threads:[~2022-09-09 10:15 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-08  5:18 [Intel-gfx] [PATCH 0/8] i915: freq caps and perf_limit_reasons changes for MTL Ashutosh Dixit
2022-09-08  5:18 ` [Intel-gfx] [PATCH 1/8] drm/i915: Prepare more multi-GT initialization Ashutosh Dixit
2022-09-08  5:18 ` [Intel-gfx] [PATCH 2/8] drm/i915: Rename and expose common GT early init routine Ashutosh Dixit
2022-09-08  5:18 ` [Intel-gfx] [PATCH 3/8] drm/i915/uncore: Add GSI offset to uncore Ashutosh Dixit
2022-09-08  5:18 ` [Intel-gfx] [PATCH 4/8] drm/i915/xelpmp: Expose media as another GT Ashutosh Dixit
2022-09-08  5:21 ` [Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions Ashutosh Dixit
2022-09-08 10:42   ` Andi Shyti
2022-09-08 12:37     ` Sundaresan, Sujaritha
2022-09-08 12:50       ` Andi Shyti
2022-09-08 15:49       ` Dixit, Ashutosh
2022-09-08  5:22 ` [Intel-gfx] [PATCH 6/8] drm/i915/debugfs: Add perf_limit_reasons in debugfs Ashutosh Dixit
2022-09-09 10:13   ` Rodrigo Vivi
2022-09-09 15:38     ` Dixit, Ashutosh
2022-09-09 16:39       ` Vivi, Rodrigo
2022-09-08  5:23 ` [Intel-gfx] [PATCH 7/8] drm/i915/mtl: PERF_LIMIT_REASONS changes for MTL Ashutosh Dixit
2022-09-09 10:15   ` Rodrigo Vivi [this message]
2022-09-08  5:23 ` [Intel-gfx] [PATCH 8/8] drm/i915/rps: Freq caps " Ashutosh Dixit
2022-09-09 10:16   ` Rodrigo Vivi
2022-09-08  5:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: freq caps and perf_limit_reasons changes for MTL (rev2) Patchwork
2022-09-08  5:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-09-08  6:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-09-08 11:48 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-09-09 18:13 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for i915: freq caps and perf_limit_reasons changes for MTL (rev3) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YxsSR0FNNlpaxmPs@intel.com \
    --to=rodrigo.vivi@intel.com \
    --cc=ashutosh.dixit@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox