Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, Paz Zcharya <pazz@chromium.org>
Subject: Re: [PATCH 6/8] drm/i915: Allow fastboot to fix up the vblank delay
Date: Mon, 20 Jan 2025 21:21:47 +0200	[thread overview]
Message-ID: <Z46iSx1Wz-5BpDTZ@intel.com> (raw)
In-Reply-To: <87r04xpgu3.fsf@intel.com>

On Mon, Jan 20, 2025 at 06:53:24PM +0200, Jani Nikula wrote:
> On Thu, 16 Jan 2025, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > GOP might not agree with our idea of what the vblank delay should be.
> > Reuse the LRR codepaths to fix that up via a fastset.
> >
> > The relevant registers aren't actually double buffered so this is a
> > little bit dodgy. While I've not seen any real issues from frobbing
> > these live, let's limit this to just the fastboot case (by only
> > allowing it when old_crtc_state->inherited==true).
> >
> > Cc: Paz Zcharya <pazz@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 26 +++++++++++++++++---
> >  1 file changed, 22 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index 9b42d980ed7e..471fe7d80f30 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5358,6 +5358,19 @@ pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
> >  	intel_cx0pll_dump_hw_state(display, b);
> >  }
> >  
> > +static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
> > +{
> > +	struct intel_display *display = to_intel_display(old_crtc_state);
> > +
> > +	/*
> > +	 * Allow fastboot to fix up vblank delay (handled via LRR
> > +	 * codepaths), a bit dodgy as the registers aren't
> > +	 * double buffered but seems to be working more or less...
> > +	 */
> > +	return HAS_LRR(display) && old_crtc_state->inherited &&
> > +		!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
> > +}
> > +
> >  bool
> >  intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> >  			  const struct intel_crtc_state *pipe_config,
> > @@ -5490,7 +5503,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
> >  	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> >  	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> >  	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> > -	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> > +	if (!fastset || !allow_vblank_delay_fastset(current_config)) \
> > +		PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> 
> Side note, part of me wants to change fastset to some variation of "full
> modeset" because *all* the compare checks are for !fastset.

fastset==true here indicates that we're checking whether fastset
is possible, fastset==false indicates we're running the actual
state checker. Not quite sure what the best naming for the
opposite situation would be.

> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Ta.

> 
> >  	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> >  	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> >  	if (!fastset || !pipe_config->update_lrr) { \
> > @@ -6084,7 +6098,8 @@ static int intel_modeset_checks(struct intel_atomic_state *state)
> >  static bool lrr_params_changed(const struct drm_display_mode *old_adjusted_mode,
> >  			       const struct drm_display_mode *new_adjusted_mode)
> >  {
> > -	return old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||
> > +	return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start ||
> > +		old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||
> >  		old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal;
> >  }
> >  
> > @@ -6098,11 +6113,14 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
> >  	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
> >  		new_crtc_state->update_lrr = false;
> >  
> > -	if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
> > +	if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
> >  		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",
> >  			    crtc->base.base.id, crtc->base.name);
> > -	else
> > +	} else {
> > +		if (allow_vblank_delay_fastset(old_crtc_state))
> > +			new_crtc_state->update_lrr = true;
> >  		new_crtc_state->uapi.mode_changed = false;
> > +	}
> >  
> >  	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,
> >  				   &new_crtc_state->dp_m_n))
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2025-01-20 19:21 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-16 20:16 [PATCH 0/8] drm/i915: Handle vblank delay vs. fastboot and finish DSB plane update enabling Ville Syrjala
2025-01-16 20:16 ` [PATCH 1/8] drm/i915: Keep TRANS_VBLANK.vblank_start==0 on ADL+ even when doing LRR updates Ville Syrjala
2025-01-20 16:48   ` Jani Nikula
2025-01-21 14:38     ` Ville Syrjälä
2025-01-16 20:16 ` [PATCH 2/8] drm/i915: Handle interlaced modes in intel_set_transcoder_timings_lrr() Ville Syrjala
2025-01-20 16:49   ` Jani Nikula
2025-01-16 20:16 ` [PATCH 3/8] drm/i915: Update TRANS_SET_CONTEXT_LATENCY during LRR updates Ville Syrjala
2025-01-20 16:49   ` Jani Nikula
2025-01-16 20:16 ` [PATCH 4/8] drm/i915: Warn if someone tries to use intel_set_transcoder_timings*() on DSI outputs Ville Syrjala
2025-01-20 16:50   ` Jani Nikula
2025-01-16 20:16 ` [PATCH 5/8] drm/i915: Extract lrr_params_changed() Ville Syrjala
2025-01-20 16:50   ` Jani Nikula
2025-01-16 20:16 ` [PATCH 6/8] drm/i915: Allow fastboot to fix up the vblank delay Ville Syrjala
2025-01-20 16:53   ` Jani Nikula
2025-01-20 19:21     ` Ville Syrjälä [this message]
2025-01-16 20:16 ` [PATCH 7/8] drm/i915/dsb: Add support for triggering VRR push with DSB Ville Syrjala
2025-01-16 20:16 ` [PATCH 8/8] drm/i915/dsb: Allow DSB to perform commits when VRR is enabled Ville Syrjala
2025-01-17  1:54 ` ✗ i915.CI.BAT: failure for drm/i915: Handle vblank delay vs. fastboot and finish DSB plane update enabling Patchwork
2025-01-17 12:01 ` ✓ i915.CI.BAT: success for drm/i915: Handle vblank delay vs. fastboot and finish DSB plane update enabling (rev2) Patchwork
2025-01-19 13:06 ` ✗ i915.CI.Full: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=Z46iSx1Wz-5BpDTZ@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jani.nikula@linux.intel.com \
    --cc=pazz@chromium.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox