From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Jouni Högander" <jouni.hogander@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Animesh Manna <animesh.manna@intel.com>
Subject: Re: [PATCH v7 13/13] drm/i915/psr: Allow DSB usage when PSR is enabled
Date: Wed, 12 Feb 2025 16:52:35 +0200 [thread overview]
Message-ID: <Z6y1s4Unvrx0Vn8z@intel.com> (raw)
In-Reply-To: <20250212075742.995022-15-jouni.hogander@intel.com>
On Wed, Feb 12, 2025 at 09:57:42AM +0200, Jouni Högander wrote:
> Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
> usage also when PSR is enabled for LunarLake onwards.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> Reviewed-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0ba85623835c..a6966a664d87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7698,6 +7698,7 @@ static void intel_atomic_dsb_prepare(struct intel_atomic_state *state,
> static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> + struct intel_display *display = to_intel_display(state);
> const struct intel_crtc_state *old_crtc_state =
> intel_atomic_get_old_crtc_state(state, crtc);
> struct intel_crtc_state *new_crtc_state =
> @@ -7713,7 +7714,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
> new_crtc_state->use_dsb =
> new_crtc_state->update_planes &&
> !new_crtc_state->do_async_flip &&
> - !new_crtc_state->has_psr &&
> + (DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
Couldn't we also do it for !selective_fetch on earlier platforms?
> !new_crtc_state->scaler_state.scaler_users &&
> !old_crtc_state->scaler_state.scaler_users &&
> !intel_crtc_needs_modeset(new_crtc_state) &&
> --
> 2.43.0
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2025-02-12 14:52 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-12 7:57 [PATCH v7 00/13] PSR DSB support Jouni Högander
2025-02-12 7:57 ` [PATCH v7 01/13] drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update Jouni Högander
2025-02-12 10:25 ` Manna, Animesh
2025-02-12 7:57 ` [PATCH v7 02/13] drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update Jouni Högander
2025-02-12 7:57 ` [PATCH v7 03/13] drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update Jouni Högander
2025-02-12 7:57 ` [PATCH v7 04/13] drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers Jouni Högander
2025-02-12 7:57 ` [PATCH v7 05/13] drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards Jouni Högander
2025-02-12 7:57 ` [PATCH v7 06/13] drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB Jouni Högander
2025-02-12 7:57 ` [PATCH v7 07/13] drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use Jouni Högander
2025-02-12 7:57 ` [PATCH v7 07/13] drm/i915/psr: Write PSR2_MAN_TRK_CTL on DSB commit as well Jouni Högander
2025-02-12 7:57 ` [PATCH v7 08/13] drm/i915/display: Warn on use_dsb in non-dsb pipe update functions Jouni Högander
2025-02-12 14:51 ` Ville Syrjälä
2025-02-12 7:57 ` [PATCH v7 09/13] drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit Jouni Högander
2025-02-12 7:57 ` [PATCH v7 10/13] drm/i915/display: Evade scanline 0 as well if PSR1 or PSR2 is enabled Jouni Högander
2025-02-12 7:57 ` [PATCH v7 11/13] drm/i915/psr: Add function for triggering "Frame Change" event Jouni Högander
2025-02-12 7:57 ` [PATCH v7 12/13] drm/i915/display: Ensure we have "Frame Change" event in DSB commit Jouni Högander
2025-02-12 7:57 ` [PATCH v7 13/13] drm/i915/psr: Allow DSB usage when PSR is enabled Jouni Högander
2025-02-12 14:52 ` Ville Syrjälä [this message]
2025-02-12 18:22 ` Hogander, Jouni
2025-02-12 18:52 ` Ville Syrjälä
2025-02-12 9:06 ` ✗ Fi.CI.SPARSE: warning for PSR DSB support (rev9) Patchwork
2025-02-12 9:34 ` ✓ i915.CI.BAT: success " Patchwork
2025-02-12 14:33 ` ✗ i915.CI.Full: failure " Patchwork
2025-02-13 6:08 ` Hogander, Jouni
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Z6y1s4Unvrx0Vn8z@intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=animesh.manna@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
--cc=jouni.hogander@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox