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* [Intel-gfx] [PATCH 1/3] drm/i915: Don't switch to TPS1 when disabling DP_TP_CTL
@ 2023-02-14 13:43 Ville Syrjala
  2023-02-14 13:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Don't send idle pattern after DP2.0 link training Ville Syrjala
                   ` (7 more replies)
  0 siblings, 8 replies; 14+ messages in thread
From: Ville Syrjala @ 2023-02-14 13:43 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

AFAICS Bspec has never asked us to switch to TPS1 when *disabling*
DP_TP_CTL. Let's stop doing that in case it confuses something.
We do have to switch before we *enable* DP_TP_CTL, but that
is already being handled correctly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index bfd1e30a27b4..4af2ba2dfcad 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2624,8 +2624,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
 
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
 		val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
-		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
-		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
+		val &= ~DP_TP_CTL_ENABLE;
 		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
 	}
 
@@ -3153,8 +3152,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 			wait = true;
 		}
 
-		dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
-		dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
+		dp_tp_ctl &= ~DP_TP_CTL_ENABLE;
 		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
 		intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
 
-- 
2.39.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2023-03-08 22:25 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-02-14 13:43 [Intel-gfx] [PATCH 1/3] drm/i915: Don't switch to TPS1 when disabling DP_TP_CTL Ville Syrjala
2023-02-14 13:43 ` [Intel-gfx] [PATCH 2/3] drm/i915: Don't send idle pattern after DP2.0 link training Ville Syrjala
2023-03-02 18:54   ` Imre Deak
2023-02-14 13:43 ` [Intel-gfx] [PATCH 3/3] drm/i915: Fix idle pattern enabling Ville Syrjala
2023-03-02 19:03   ` Imre Deak
2023-03-08 21:28     ` Ville Syrjälä
2023-03-08 22:19       ` Imre Deak
2023-03-08 22:25         ` Ville Syrjälä
2023-02-14 15:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915: Don't switch to TPS1 when disabling DP_TP_CTL Patchwork
2023-02-14 15:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-15  3:22 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-03-02 18:53 ` [Intel-gfx] [PATCH 1/3] " Imre Deak
2023-03-07 16:26 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2023-03-07 22:07 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [v2,1/3] drm/i915: Don't switch to TPS1 when disabling DP_TP_CTL (rev2) Patchwork

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