From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: fei.yang@intel.com
Cc: Chris Wilson <chris.p.wilson@linux.intel.com>,
intel-gfx@lists.freedesktop.org,
Matt Roper <matthew.d.roper@intel.com>,
dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 7/7] drm/i915: Allow user to set cache at BO creation
Date: Mon, 3 Apr 2023 19:02:08 +0300 [thread overview]
Message-ID: <ZCr4gB8Q75+QWr19@intel.com> (raw)
In-Reply-To: <20230401063830.438127-8-fei.yang@intel.com>
On Fri, Mar 31, 2023 at 11:38:30PM -0700, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
>
> To comply with the design that buffer objects shall have immutable
> cache setting through out its life cycle, {set, get}_caching ioctl's
> are no longer supported from MTL onward. With that change caching
> policy can only be set at object creation time. The current code
> applies a default (platform dependent) cache setting for all objects.
> However this is not optimal for performance tuning. The patch extends
> the existing gem_create uAPI to let user set PAT index for the object
> at creation time.
This is missing the whole justification for the new uapi.
Why is MOCS not sufficient?
> The new extension is platform independent, so UMD's can switch to using
> this extension for older platforms as well, while {set, get}_caching are
> still supported on these legacy paltforms for compatibility reason.
>
> Cc: Chris Wilson <chris.p.wilson@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Fei Yang <fei.yang@intel.com>
> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 33 ++++++++++++++++++++
> include/uapi/drm/i915_drm.h | 36 ++++++++++++++++++++++
> tools/include/uapi/drm/i915_drm.h | 36 ++++++++++++++++++++++
> 3 files changed, 105 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index e76c9703680e..1c6e2034d28e 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -244,6 +244,7 @@ struct create_ext {
> unsigned int n_placements;
> unsigned int placement_mask;
> unsigned long flags;
> + unsigned int pat_index;
> };
>
> static void repr_placements(char *buf, size_t size,
> @@ -393,11 +394,39 @@ static int ext_set_protected(struct i915_user_extension __user *base, void *data
> return 0;
> }
>
> +static int ext_set_pat(struct i915_user_extension __user *base, void *data)
> +{
> + struct create_ext *ext_data = data;
> + struct drm_i915_private *i915 = ext_data->i915;
> + struct drm_i915_gem_create_ext_set_pat ext;
> + unsigned int max_pat_index;
> +
> + BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
> + offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
> +
> + if (copy_from_user(&ext, base, sizeof(ext)))
> + return -EFAULT;
> +
> + max_pat_index = INTEL_INFO(i915)->max_pat_index;
> +
> + if (ext.pat_index > max_pat_index) {
> + drm_dbg(&i915->drm, "PAT index is invalid: %u\n",
> + ext.pat_index);
> + return -EINVAL;
> + }
> +
> + ext_data->pat_index = ext.pat_index;
> +
> + return 0;
> +}
> +
> static const i915_user_extension_fn create_extensions[] = {
> [I915_GEM_CREATE_EXT_MEMORY_REGIONS] = ext_set_placements,
> [I915_GEM_CREATE_EXT_PROTECTED_CONTENT] = ext_set_protected,
> + [I915_GEM_CREATE_EXT_SET_PAT] = ext_set_pat,
> };
>
> +#define PAT_INDEX_NOT_SET 0xffff
> /**
> * Creates a new mm object and returns a handle to it.
> * @dev: drm device pointer
> @@ -417,6 +446,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data,
> if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS)
> return -EINVAL;
>
> + ext_data.pat_index = PAT_INDEX_NOT_SET;
> ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
> create_extensions,
> ARRAY_SIZE(create_extensions),
> @@ -453,5 +483,8 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data,
> if (IS_ERR(obj))
> return PTR_ERR(obj);
>
> + if (ext_data.pat_index != PAT_INDEX_NOT_SET)
> + i915_gem_object_set_pat_index(obj, ext_data.pat_index);
> +
> return i915_gem_publish(obj, file, &args->size, &args->handle);
> }
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index dba7c5a5b25e..03c5c314846e 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -3630,9 +3630,13 @@ struct drm_i915_gem_create_ext {
> *
> * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
> * struct drm_i915_gem_create_ext_protected_content.
> + *
> + * For I915_GEM_CREATE_EXT_SET_PAT usage see
> + * struct drm_i915_gem_create_ext_set_pat.
> */
> #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
> #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
> +#define I915_GEM_CREATE_EXT_SET_PAT 2
> __u64 extensions;
> };
>
> @@ -3747,6 +3751,38 @@ struct drm_i915_gem_create_ext_protected_content {
> __u32 flags;
> };
>
> +/**
> + * struct drm_i915_gem_create_ext_set_pat - The
> + * I915_GEM_CREATE_EXT_SET_PAT extension.
> + *
> + * If this extension is provided, the specified caching policy (PAT index) is
> + * applied to the buffer object.
> + *
> + * Below is an example on how to create an object with specific caching policy:
> + *
> + * .. code-block:: C
> + *
> + * struct drm_i915_gem_create_ext_set_pat set_pat_ext = {
> + * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT },
> + * .pat_index = 0,
> + * };
> + * struct drm_i915_gem_create_ext create_ext = {
> + * .size = PAGE_SIZE,
> + * .extensions = (uintptr_t)&set_pat_ext,
> + * };
> + *
> + * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
> + * if (err) ...
> + */
> +struct drm_i915_gem_create_ext_set_pat {
> + /** @base: Extension link. See struct i915_user_extension. */
> + struct i915_user_extension base;
> + /** @pat_index: PAT index to be set */
> + __u32 pat_index;
> + /** @rsvd: reserved for future use */
> + __u32 rsvd;
> +};
> +
> /* ID of the protected content session managed by i915 when PXP is active */
> #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
>
> diff --git a/tools/include/uapi/drm/i915_drm.h b/tools/include/uapi/drm/i915_drm.h
> index 8df261c5ab9b..8cdcdb5fac26 100644
> --- a/tools/include/uapi/drm/i915_drm.h
> +++ b/tools/include/uapi/drm/i915_drm.h
> @@ -3607,9 +3607,13 @@ struct drm_i915_gem_create_ext {
> *
> * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
> * struct drm_i915_gem_create_ext_protected_content.
> + *
> + * For I915_GEM_CREATE_EXT_SET_PAT usage see
> + * struct drm_i915_gem_create_ext_set_pat.
> */
> #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
> #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
> +#define I915_GEM_CREATE_EXT_SET_PAT 2
> __u64 extensions;
> };
>
> @@ -3724,6 +3728,38 @@ struct drm_i915_gem_create_ext_protected_content {
> __u32 flags;
> };
>
> +/**
> + * struct drm_i915_gem_create_ext_set_pat - The
> + * I915_GEM_CREATE_EXT_SET_PAT extension.
> + *
> + * If this extension is provided, the specified caching policy (PAT index) is
> + * applied to the buffer object.
> + *
> + * Below is an example on how to create an object with specific caching policy:
> + *
> + * .. code-block:: C
> + *
> + * struct drm_i915_gem_create_ext_set_pat set_pat_ext = {
> + * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT },
> + * .pat_index = 0,
> + * };
> + * struct drm_i915_gem_create_ext create_ext = {
> + * .size = PAGE_SIZE,
> + * .extensions = (uintptr_t)&set_pat_ext,
> + * };
> + *
> + * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
> + * if (err) ...
> + */
> +struct drm_i915_gem_create_ext_set_pat {
> + /** @base: Extension link. See struct i915_user_extension. */
> + struct i915_user_extension base;
> + /** @pat_index: PAT index to be set */
> + __u32 pat_index;
> + /** @rsvd: reserved for future use */
> + __u32 rsvd;
> +};
> +
> /* ID of the protected content session managed by i915 when PXP is active */
> #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
>
> --
> 2.25.1
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-04-03 16:02 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-01 6:38 [Intel-gfx] [PATCH 0/7] drm/i915/mtl: Define MOCS and PAT tables for MTL fei.yang
2023-04-01 6:38 ` [Intel-gfx] [PATCH 1/7] " fei.yang
2023-04-03 12:50 ` Jani Nikula
2023-04-06 8:16 ` Andi Shyti
2023-04-06 18:22 ` Yang, Fei
2023-04-06 8:28 ` Das, Nirmoy
2023-04-06 14:55 ` Yang, Fei
2023-04-06 18:13 ` Das, Nirmoy
2023-04-01 6:38 ` [Intel-gfx] [PATCH 2/7] drm/i915/mtl: workaround coherency issue for Media fei.yang
2023-04-01 6:38 ` [Intel-gfx] [PATCH 3/7] drm/i915/mtl: end support for set caching ioctl fei.yang
2023-04-01 6:38 ` [Intel-gfx] [PATCH 4/7] drm/i915: preparation for using PAT index fei.yang
2023-04-01 6:38 ` [Intel-gfx] [PATCH 5/7] drm/i915: use pat_index instead of cache_level fei.yang
2023-04-03 14:50 ` Ville Syrjälä
2023-04-03 16:57 ` Yang, Fei
2023-04-03 17:14 ` Ville Syrjälä
2023-04-03 19:39 ` Yang, Fei
2023-04-03 19:52 ` Ville Syrjälä
2023-04-06 6:28 ` Yang, Fei
2023-04-01 6:38 ` [Intel-gfx] [PATCH 6/7] drm/i915: make sure correct pte encode is used fei.yang
2023-04-01 6:38 ` [Intel-gfx] [PATCH 7/7] drm/i915: Allow user to set cache at BO creation fei.yang
2023-04-03 16:02 ` Ville Syrjälä [this message]
2023-04-03 16:35 ` Matt Roper
2023-04-03 16:48 ` Ville Syrjälä
2023-04-04 22:15 ` Kenneth Graunke
2023-04-04 7:29 ` Lionel Landwerlin
2023-04-04 16:04 ` Yang, Fei
2023-04-05 7:45 ` Lionel Landwerlin
2023-04-05 20:26 ` Jordan Justen
2023-04-10 8:23 ` Jordan Justen
2023-04-13 20:49 ` Yang, Fei
2023-04-05 23:06 ` Yang, Fei
2023-04-06 9:11 ` Matthew Auld
2023-04-01 7:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/mtl: Define MOCS and PAT tables for MTL Patchwork
2023-04-01 7:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-01 7:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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