* [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff
@ 2023-08-28 5:41 Ville Syrjala
2023-08-28 5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
` (8 more replies)
0 siblings, 9 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-08-28 5:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Some prep work towards reconciling VRR and M/N. I think after these
we coukd try VRR fastsets that alter the state of the VRR registers,
assuming we toggle VRR off and on around the update.
Cc: Manasi Navare <navaremanasi@chromium.org>
Ville Syrjälä (6):
drm/i915: Move psr unlock out from the pipe update critical section
drm/i915: Change intel_pipe_update_{start,end}() calling convention
drm/i915: Extract intel_crtc_vblank_evade_scanlines()
drm/i915: Enable VRR later during fastsets
drm/i915: Adjust seamless_m_n flag behaviour
drm/i915: Optimize out redundant M/N updates
drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 105 +++++++++++-------
drivers/gpu/drm/i915/display/intel_crtc.h | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 45 +++++---
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
6 files changed, 101 insertions(+), 60 deletions(-)
--
2.41.0
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
@ 2023-08-28 5:41 ` Ville Syrjala
2023-08-28 18:16 ` Manasi Navare
2023-08-28 5:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
` (7 subsequent siblings)
8 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2023-08-28 5:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Do the PSR unlock after the vblank evade critcal section is
fully over, not before.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 182c6dd64f47..5caa928e5ce9 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -646,10 +646,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
ktime_t end_vbl_time = ktime_get();
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- intel_psr_unlock(new_crtc_state);
-
if (new_crtc_state->do_async_flip)
- return;
+ goto out;
trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
@@ -709,7 +707,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
local_irq_enable();
if (intel_vgpu_active(dev_priv))
- return;
+ goto out;
if (crtc->debug.start_vbl_count &&
crtc->debug.start_vbl_count != end_vbl_count) {
@@ -724,4 +722,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
}
dbg_vblank_evade(crtc, end_vbl_time);
+
+out:
+ intel_psr_unlock(new_crtc_state);
}
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 2/6] drm/i915: Change intel_pipe_update_{start, end}() calling convention
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
2023-08-28 5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
@ 2023-08-28 5:41 ` Ville Syrjala
2023-08-28 18:30 ` Manasi Navare
2023-08-28 5:41 ` [Intel-gfx] [PATCH 3/6] drm/i915: Extract intel_crtc_vblank_evade_scanlines() Ville Syrjala
` (6 subsequent siblings)
8 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2023-08-28 5:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We'll need to also look at the old crtc state in
intel_pipe_update_start() so change the calling convention to
just plumb in the full atomic state instead.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 18 ++++++++++++------
drivers/gpu/drm/i915/display/intel_crtc.h | 6 ++++--
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
3 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 5caa928e5ce9..461949b48411 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -470,7 +470,8 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
/**
* intel_pipe_update_start() - start update of a set of display registers
- * @new_crtc_state: the new crtc state
+ * @state: the atomic state
+ * @crtc: the crtc
*
* Mark the start of an update to pipe registers that should be updated
* atomically regarding vblank. If the next vblank will happens within
@@ -480,10 +481,12 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
* until a subsequent call to intel_pipe_update_end(). That is done to
* avoid random delays.
*/
-void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
+void intel_pipe_update_start(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
long timeout = msecs_to_jiffies_timeout(1);
int scanline, min, max, vblank_start;
@@ -631,15 +634,18 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
/**
* intel_pipe_update_end() - end update of a set of display registers
- * @new_crtc_state: the new crtc state
+ * @state: the atomic state
+ * @crtc: the crtc
*
* Mark the end of an update started with intel_pipe_update_start(). This
* re-enables interrupts and verifies the update was actually completed
* before a vblank.
*/
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
+void intel_pipe_update_end(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
int scanline_end = intel_get_crtc_scanline(crtc);
u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
index 51a4c8df9e65..22d7993d1f0b 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc.h
@@ -36,8 +36,10 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
-void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
-void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
+void intel_pipe_update_start(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+void intel_pipe_update_end(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915);
struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f6397462e4c2..cfad967b5684 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6559,7 +6559,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_crtc_planes_update_noarm(state, crtc);
/* Perform vblank evasion around commit operation */
- intel_pipe_update_start(new_crtc_state);
+ intel_pipe_update_start(state, crtc);
commit_pipe_pre_planes(state, crtc);
@@ -6567,7 +6567,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
commit_pipe_post_planes(state, crtc);
- intel_pipe_update_end(new_crtc_state);
+ intel_pipe_update_end(state, crtc);
/*
* We usually enable FIFO underrun interrupts as part of the
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 3/6] drm/i915: Extract intel_crtc_vblank_evade_scanlines()
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
2023-08-28 5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
2023-08-28 5:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
@ 2023-08-28 5:41 ` Ville Syrjala
2023-08-28 18:31 ` Manasi Navare
2023-08-28 5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets Ville Syrjala
` (5 subsequent siblings)
8 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2023-08-28 5:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pull the vblank evasion scanline calculations into their own helper
to declutter intel_pipe_update_start() a bit.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 53 +++++++++++++----------
1 file changed, 31 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 461949b48411..e46a15d59d79 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -468,6 +468,36 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
return vblank_start;
}
+static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ int *min, int *max, int *vblank_start)
+{
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
+
+ if (new_crtc_state->vrr.enable) {
+ if (intel_vrr_is_push_sent(new_crtc_state))
+ *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
+ else
+ *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
+ } else {
+ *vblank_start = intel_mode_vblank_start(adjusted_mode);
+ }
+
+ /* FIXME needs to be calibrated sensibly */
+ *min = *vblank_start - intel_usecs_to_scanlines(adjusted_mode,
+ VBLANK_EVASION_TIME_US);
+ *max = *vblank_start - 1;
+
+ /*
+ * M/N is double buffered on the transcoder's undelayed vblank,
+ * so with seamless M/N we must evade both vblanks.
+ */
+ if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
+ *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
+}
+
/**
* intel_pipe_update_start() - start update of a set of display registers
* @state: the atomic state
@@ -487,7 +517,6 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
long timeout = msecs_to_jiffies_timeout(1);
int scanline, min, max, vblank_start;
wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
@@ -503,27 +532,7 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
if (intel_crtc_needs_vblank_work(new_crtc_state))
intel_crtc_vblank_work_init(new_crtc_state);
- if (new_crtc_state->vrr.enable) {
- if (intel_vrr_is_push_sent(new_crtc_state))
- vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
- else
- vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
- } else {
- vblank_start = intel_mode_vblank_start(adjusted_mode);
- }
-
- /* FIXME needs to be calibrated sensibly */
- min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
- VBLANK_EVASION_TIME_US);
- max = vblank_start - 1;
-
- /*
- * M/N is double buffered on the transcoder's undelayed vblank,
- * so with seamless M/N we must evade both vblanks.
- */
- if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
- min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
-
+ intel_crtc_vblank_evade_scanlines(state, crtc, &min, &max, &vblank_start);
if (min <= 0 || max <= 0)
goto irq_disable;
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
` (2 preceding siblings ...)
2023-08-28 5:41 ` [Intel-gfx] [PATCH 3/6] drm/i915: Extract intel_crtc_vblank_evade_scanlines() Ville Syrjala
@ 2023-08-28 5:41 ` Ville Syrjala
2023-08-28 18:47 ` Manasi Navare
2023-09-11 18:21 ` Golani, Mitulkumar Ajitkumar
2023-08-28 5:41 ` [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour Ville Syrjala
` (4 subsequent siblings)
8 siblings, 2 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-08-28 5:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
In order to reconcile seamless M/N updates with VRR we'll
need to defer the fastset VRR enable to happen after the
seamless M/N update (which happens during the vblank evade
critical section). So just push the VRR enable to be the last
thing during the update.
This will also affect the vblank evasion as the transcoder
will now still be running with the old VRR state during
the vblank evasion. So just grab the timings always from the
old crtc state during any non-modeset commit, and also grab
the current state of VRR from the active timings (as we disable
VRR before vblank evasion during fastsets).
This also fixes vblank evasion for seamless M/N updates as
we now properly account for the fact that the M/N update
happens after vblank evasion.
Cc: Manasi Navare <navaremanasi@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 35 ++++++++++++--------
drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++----
2 files changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index e46a15d59d79..1992e7060263 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -472,15 +472,31 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
struct intel_crtc *crtc,
int *min, int *max, int *vblank_start)
{
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
+ const struct intel_crtc_state *crtc_state;
+ const struct drm_display_mode *adjusted_mode;
- if (new_crtc_state->vrr.enable) {
- if (intel_vrr_is_push_sent(new_crtc_state))
- *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
+ /*
+ * During fastsets/etc. the transcoder is still
+ * running with the old timings at this point.
+ *
+ * TODO: maybe just use the active timings here?
+ */
+ if (intel_crtc_needs_modeset(new_crtc_state))
+ crtc_state = new_crtc_state;
+ else
+ crtc_state = old_crtc_state;
+
+ adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
+ if (intel_vrr_is_push_sent(crtc_state))
+ *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
else
- *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
+ *vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
} else {
*vblank_start = intel_mode_vblank_start(adjusted_mode);
}
@@ -710,15 +726,6 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
*/
intel_vrr_send_push(new_crtc_state);
- /*
- * Seamless M/N update may need to update frame timings.
- *
- * FIXME Should be synchronized with the start of vblank somehow...
- */
- if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
- intel_crtc_update_active_timings(new_crtc_state,
- new_crtc_state->vrr.enable);
-
local_irq_enable();
if (intel_vgpu_active(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cfad967b5684..632f1f58df9e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6476,6 +6476,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
@@ -6487,6 +6489,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) >= 9 &&
!intel_crtc_needs_modeset(new_crtc_state))
skl_detach_scalers(new_crtc_state);
+
+ if (vrr_enabling(old_crtc_state, new_crtc_state))
+ intel_vrr_enable(new_crtc_state);
}
static void intel_enable_crtc(struct intel_atomic_state *state,
@@ -6527,12 +6532,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_dpt_configure(crtc);
}
- if (vrr_enabling(old_crtc_state, new_crtc_state)) {
- intel_vrr_enable(new_crtc_state);
- intel_crtc_update_active_timings(new_crtc_state,
- new_crtc_state->vrr.enable);
- }
-
if (!modeset) {
if (new_crtc_state->preload_luts &&
intel_crtc_needs_color_update(new_crtc_state))
@@ -6569,6 +6568,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
intel_pipe_update_end(state, crtc);
+ /*
+ * VRR/Seamless M/N update may need to update frame timings.
+ *
+ * FIXME Should be synchronized with the start of vblank somehow...
+ */
+ if (vrr_enabling(old_crtc_state, new_crtc_state) ||
+ (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
+ intel_crtc_update_active_timings(new_crtc_state,
+ new_crtc_state->vrr.enable);
+
/*
* We usually enable FIFO underrun interrupts as part of the
* CRTC enable sequence during modesets. But when we inherit a
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
` (3 preceding siblings ...)
2023-08-28 5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets Ville Syrjala
@ 2023-08-28 5:41 ` Ville Syrjala
2023-08-28 16:58 ` Golani, Mitulkumar Ajitkumar
2023-08-28 5:41 ` [Intel-gfx] [PATCH 6/6] drm/i915: Optimize out redundant M/N updates Ville Syrjala
` (3 subsequent siblings)
8 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2023-08-28 5:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the seamless_m_n flag more like the update_pipe fastset
flag, ie. the flag will only be set if we need to do the seamless
M/N update, and in all other cases the flag is cleared. Also
rename the flag to update_m_n to make it more clear it's similar
to update_pipe.
I believe special casing seamless_m_n like this makes sense
as it also affects eg. vblank evasion. We can potentially avoid
some vblank evasion tricks, simplify some checks, and hopefully
will help with the VRR vs. M/N mess.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++--------
.../drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
5 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 7cf51dd8c056..aaddd8c0cfa0 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
drm_property_blob_get(crtc_state->post_csc_lut);
crtc_state->update_pipe = false;
+ crtc_state->update_m_n = false;
crtc_state->disable_lp_wm = false;
crtc_state->disable_cxsr = false;
crtc_state->update_wm_pre = false;
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 1992e7060263..a04076064f02 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -510,7 +510,7 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
* M/N is double buffered on the transcoder's undelayed vblank,
* so with seamless M/N we must evade both vblanks.
*/
- if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
+ if (new_crtc_state->update_m_n)
*min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 632f1f58df9e..6196ef76390b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_X(lane_lat_optim_mask);
if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
- if (!fastset || !pipe_config->seamless_m_n)
+ if (!fastset || !pipe_config->update_m_n)
PIPE_CONF_CHECK_M_N(dp_m_n);
} else {
PIPE_CONF_CHECK_M_N(dp_m_n);
@@ -5307,7 +5307,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
PIPE_CONF_CHECK_I(pipe_bpp);
- if (!fastset || !pipe_config->seamless_m_n) {
+ if (!fastset || !pipe_config->update_m_n) {
PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
}
@@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
crtc_state->uapi.mode_changed = true;
crtc_state->update_pipe = false;
+ crtc_state->update_m_n = false;
ret = drm_atomic_add_affected_connectors(&state->base,
&crtc->base);
@@ -5519,13 +5520,14 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
{
struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
- if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
+ if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true))
drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
+ else
+ new_crtc_state->uapi.mode_changed = false;
- return;
- }
+ if (intel_crtc_needs_modeset(new_crtc_state))
+ new_crtc_state->update_m_n = false;
- new_crtc_state->uapi.mode_changed = false;
if (!intel_crtc_needs_modeset(new_crtc_state))
new_crtc_state->update_pipe = true;
}
@@ -6240,6 +6242,7 @@ int intel_atomic_check(struct drm_device *dev,
if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
+ new_crtc_state->update_m_n = false;
}
}
@@ -6252,6 +6255,7 @@ int intel_atomic_check(struct drm_device *dev,
if (intel_cpu_transcoders_need_modeset(state, trans)) {
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
+ new_crtc_state->update_m_n = false;
}
}
@@ -6259,6 +6263,7 @@ int intel_atomic_check(struct drm_device *dev,
if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
new_crtc_state->uapi.mode_changed = true;
new_crtc_state->update_pipe = false;
+ new_crtc_state->update_m_n = false;
}
}
}
@@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
hsw_set_linetime_wm(new_crtc_state);
- if (new_crtc_state->seamless_m_n)
+ if (new_crtc_state->update_m_n)
intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
&new_crtc_state->dp_m_n);
}
@@ -6573,8 +6578,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
*
* FIXME Should be synchronized with the start of vblank somehow...
*/
- if (vrr_enabling(old_crtc_state, new_crtc_state) ||
- (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
+ if (vrr_enabling(old_crtc_state, new_crtc_state) || new_crtc_state->update_m_n)
intel_crtc_update_active_timings(new_crtc_state,
new_crtc_state->vrr.enable);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 731f2ec04d5c..2367b030b469 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1083,6 +1083,7 @@ struct intel_crtc_state {
unsigned fb_bits; /* framebuffers to flip */
bool update_pipe; /* can a fast modeset be performed? */
+ bool update_m_n; /* update M/N seamlessly during fastset? */
bool disable_cxsr;
bool update_wm_pre, update_wm_post; /* watermarks are updated */
bool fifo_changed; /* FIFO split is changed */
@@ -1195,7 +1196,6 @@ struct intel_crtc_state {
/* m2_n2 for eDP downclock */
struct intel_link_m_n dp_m2_n2;
bool has_drrs;
- bool seamless_m_n;
/* PSR is supported but might not be enabled due the lack of enabled planes */
bool has_psr;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 05694e0b6143..ceab5b26b5e8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2535,7 +2535,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
int pixel_clock;
if (has_seamless_m_n(connector))
- pipe_config->seamless_m_n = true;
+ pipe_config->update_m_n = true;
if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 6/6] drm/i915: Optimize out redundant M/N updates
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
` (4 preceding siblings ...)
2023-08-28 5:41 ` [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour Ville Syrjala
@ 2023-08-28 5:41 ` Ville Syrjala
2023-08-28 6:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR and M/N stuff Patchwork
` (2 subsequent siblings)
8 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-08-28 5:41 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Don't perform a seamless M/N update if the values aren't actually
changing. This avoids doing extra shenanigans during vblank evasion
needlessly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6196ef76390b..c20eaf0e7a91 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5525,7 +5525,9 @@ static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta
else
new_crtc_state->uapi.mode_changed = false;
- if (intel_crtc_needs_modeset(new_crtc_state))
+ if (intel_crtc_needs_modeset(new_crtc_state) ||
+ intel_compare_link_m_n(&old_crtc_state->dp_m_n,
+ &new_crtc_state->dp_m_n))
new_crtc_state->update_m_n = false;
if (!intel_crtc_needs_modeset(new_crtc_state))
--
2.41.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR and M/N stuff
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
` (5 preceding siblings ...)
2023-08-28 5:41 ` [Intel-gfx] [PATCH 6/6] drm/i915: Optimize out redundant M/N updates Ville Syrjala
@ 2023-08-28 6:11 ` Patchwork
2023-08-28 6:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-28 8:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-08-28 6:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: VRR and M/N stuff
URL : https://patchwork.freedesktop.org/series/122955/
State : warning
== Summary ==
Error: dim sparse failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: VRR and M/N stuff
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
` (6 preceding siblings ...)
2023-08-28 6:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR and M/N stuff Patchwork
@ 2023-08-28 6:29 ` Patchwork
2023-08-28 8:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-08-28 6:29 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5978 bytes --]
== Series Details ==
Series: drm/i915: VRR and M/N stuff
URL : https://patchwork.freedesktop.org/series/122955/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13569 -> Patchwork_122955v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/index.html
Participating hosts (40 -> 37)
------------------------------
Missing (3): bat-atsm-1 fi-snb-2520m fi-bsw-n3050
Known issues
------------
Here are the changes found in Patchwork_122955v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@verify-random:
- bat-mtlp-8: NOTRUN -> [SKIP][1] ([i915#4613]) +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][2] ([i915#6621])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@mman:
- bat-rpls-1: [PASS][3] -> [TIMEOUT][4] ([i915#6794] / [i915#7392])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/bat-rpls-1/igt@i915_selftest@live@mman.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-rpls-1/igt@i915_selftest@live@mman.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-1: [PASS][5] -> [WARN][6] ([i915#8747])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#6645])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: NOTRUN -> [SKIP][8] ([i915#1072]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: NOTRUN -> [ABORT][9] ([i915#8260] / [i915#8668])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-mmap:
- bat-mtlp-8: NOTRUN -> [SKIP][10] ([i915#3708] / [i915#4077]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][11] ([i915#3708]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- bat-dg2-9: [INCOMPLETE][12] ([i915#6311]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- bat-mtlp-8: [ABORT][14] ([i915#7077] / [i915#7977] / [i915#8668]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/bat-mtlp-8/igt@i915_pm_rpm@basic-pci-d3-state.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-mtlp-8/igt@i915_pm_rpm@basic-pci-d3-state.html
#### Warnings ####
* igt@kms_psr@primary_page_flip:
- bat-rplp-1: [ABORT][16] ([i915#8860]) -> [SKIP][17] ([i915#1072])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/bat-rplp-1/igt@kms_psr@primary_page_flip.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/bat-rplp-1/igt@kms_psr@primary_page_flip.html
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7977]: https://gitlab.freedesktop.org/drm/intel/issues/7977
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8747]: https://gitlab.freedesktop.org/drm/intel/issues/8747
[i915#8860]: https://gitlab.freedesktop.org/drm/intel/issues/8860
Build changes
-------------
* Linux: CI_DRM_13569 -> Patchwork_122955v1
CI-20190529: 20190529
CI_DRM_13569: eb0ba85982a1832f4a61954c3fb99ac3e3f2e076 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7454: 7454
Patchwork_122955v1: eb0ba85982a1832f4a61954c3fb99ac3e3f2e076 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a60179b26f91 drm/i915: Optimize out redundant M/N updates
7e9f49faf2b1 drm/i915: Adjust seamless_m_n flag behaviour
d685640c176a drm/i915: Enable VRR later during fastsets
7be2f37b8992 drm/i915: Extract intel_crtc_vblank_evade_scanlines()
6d943c4d89ed drm/i915: Change intel_pipe_update_{start, end}() calling convention
1a1a4852bf2a drm/i915: Move psr unlock out from the pipe update critical section
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/index.html
[-- Attachment #2: Type: text/html, Size: 7097 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: VRR and M/N stuff
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
` (7 preceding siblings ...)
2023-08-28 6:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-08-28 8:03 ` Patchwork
8 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-08-28 8:03 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 54808 bytes --]
== Series Details ==
Series: drm/i915: VRR and M/N stuff
URL : https://patchwork.freedesktop.org/series/122955/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13569_full -> Patchwork_122955v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_122955v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2: NOTRUN -> [SKIP][1] ([i915#8414]) +9 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][2] -> [FAIL][3] ([i915#7742])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_busy@close-race:
- shard-mtlp: [PASS][4] -> [ABORT][5] ([i915#9151])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-5/igt@gem_busy@close-race.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-2/igt@gem_busy@close-race.html
* igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0:
- shard-dg2: [PASS][6] -> [INCOMPLETE][7] ([i915#6311] / [i915#7297])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-11/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-10/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0.html
* igt@gem_close_race@multigpu-basic-process:
- shard-mtlp: NOTRUN -> [SKIP][8] ([i915#7697])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-set-pat:
- shard-rkl: NOTRUN -> [SKIP][9] ([i915#8562])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [PASS][10] -> [FAIL][11] ([i915#6268])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-7/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-dg2: NOTRUN -> [SKIP][12] ([fdo#109314])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_ctx_persistence@legacy-engines-mixed:
- shard-snb: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-snb7/igt@gem_ctx_persistence@legacy-engines-mixed.html
* igt@gem_ctx_sseu@invalid-args:
- shard-mtlp: NOTRUN -> [SKIP][14] ([i915#280])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@hibernate:
- shard-tglu: [PASS][15] -> [ABORT][16] ([i915#7975] / [i915#8213] / [i915#8398])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-tglu-2/igt@gem_eio@hibernate.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-tglu-10/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-dg1: [PASS][17] -> [FAIL][18] ([i915#5784])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg1-14/igt@gem_eio@kms.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-18/igt@gem_eio@kms.html
* igt@gem_exec_capture@pi@bcs0:
- shard-mtlp: [PASS][19] -> [FAIL][20] ([i915#4475] / [i915#7765])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-2/igt@gem_exec_capture@pi@bcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-4/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-none:
- shard-dg2: NOTRUN -> [SKIP][21] ([i915#3539] / [i915#4852])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@gem_exec_fair@basic-none.html
* igt@gem_exec_fair@basic-pace:
- shard-dg2: NOTRUN -> [SKIP][22] ([i915#3539])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][23] -> [FAIL][24] ([i915#2842])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fence@concurrent:
- shard-mtlp: NOTRUN -> [SKIP][25] ([i915#4812])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@gem_exec_fence@concurrent.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-dg2: NOTRUN -> [SKIP][26] ([fdo#109283] / [i915#5107])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-cpu-read-active:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#3281]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_exec_reloc@basic-cpu-read-active.html
* igt@gem_exec_reloc@basic-wc:
- shard-rkl: NOTRUN -> [SKIP][28] ([i915#3281])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@gem_exec_reloc@basic-wc.html
* igt@gem_exec_schedule@preempt-engines@ccs0:
- shard-mtlp: [PASS][29] -> [FAIL][30] ([i915#9119]) +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-2/igt@gem_exec_schedule@preempt-engines@ccs0.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-4/igt@gem_exec_schedule@preempt-engines@ccs0.html
* igt@gem_exec_schedule@preempt-engines@rcs0:
- shard-mtlp: [PASS][31] -> [DMESG-FAIL][32] ([i915#8962] / [i915#9121]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-2/igt@gem_exec_schedule@preempt-engines@rcs0.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-4/igt@gem_exec_schedule@preempt-engines@rcs0.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#4537] / [i915#4812])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_exec_suspend@basic-s0@lmem0:
- shard-dg2: [PASS][34] -> [INCOMPLETE][35] ([i915#6311])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-2/igt@gem_exec_suspend@basic-s0@lmem0.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-2/igt@gem_exec_suspend@basic-s0@lmem0.html
* igt@gem_fenced_exec_thrash@no-spare-fences:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#4860]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@gem_fenced_exec_thrash@no-spare-fences.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-mtlp: NOTRUN -> [SKIP][37] ([i915#4613])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: NOTRUN -> [DMESG-WARN][38] ([i915#4936] / [i915#5493])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_mmap_gtt@basic-write-read-distinct:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#4077]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@gem_mmap_gtt@basic-write-read-distinct.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#4077]) +6 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@bad-object:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#4083]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_mmap_wc@bad-object.html
* igt@gem_partial_pwrite_pread@write-uncached:
- shard-mtlp: NOTRUN -> [SKIP][42] ([i915#3282])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-3/igt@gem_partial_pwrite_pread@write-uncached.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][43] ([i915#2658]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-snb2/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#3282])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@display-protected-crc:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#4270])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#4270])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
- shard-mtlp: NOTRUN -> [SKIP][47] ([i915#8428])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][48] ([i915#5190]) +5 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-dg2: NOTRUN -> [SKIP][49] ([i915#4079])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_tiled_partial_pwrite_pread@writes:
- shard-rkl: NOTRUN -> [SKIP][50] ([i915#3282])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@gem_tiled_partial_pwrite_pread@writes.html
* igt@gem_userptr_blits@coherency-sync:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#3297])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@gem_userptr_blits@coherency-sync.html
* igt@gen3_render_tiledx_blits:
- shard-dg2: NOTRUN -> [SKIP][52] ([fdo#109289])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@gen3_render_tiledx_blits.html
* igt@gen7_exec_parse@basic-allowed:
- shard-rkl: NOTRUN -> [SKIP][53] ([fdo#109289])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@gen7_exec_parse@basic-allowed.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][54] -> [ABORT][55] ([i915#5566])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-apl7/igt@gen9_exec_parse@allowed-all.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-apl4/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@valid-registers:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#2856])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@gen9_exec_parse@valid-registers.html
* igt@i915_module_load@load:
- shard-snb: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#6227])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-snb7/igt@i915_module_load@load.html
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#6227])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@i915_module_load@load.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [PASS][59] -> [DMESG-WARN][60] ([i915#7061] / [i915#8617])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-3/igt@i915_module_load@reload-with-fault-injection.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-5/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: [PASS][61] -> [ABORT][62] ([i915#8489] / [i915#8668])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-4/igt@i915_module_load@reload-with-fault-injection.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglu: [PASS][63] -> [FAIL][64] ([i915#3989] / [i915#454])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-tglu-2/igt@i915_pm_dc@dc6-dpms.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-tglu-8/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc6-psr:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#658]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-dg1: [PASS][66] -> [SKIP][67] ([i915#1937])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg1-19/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-15/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_lpsp@screens-disabled:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#1902])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@i915_pm_lpsp@screens-disabled.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-dg1: [PASS][69] -> [FAIL][70] ([i915#3591]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-14/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-rkl: NOTRUN -> [SKIP][71] ([i915#1397])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][72] -> [SKIP][73] ([i915#1397])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-2/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-rkl: [PASS][74] -> [SKIP][75] ([i915#1397])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@system-suspend-devices:
- shard-mtlp: [PASS][76] -> [FAIL][77] ([i915#6121] / [i915#7052]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-6/igt@i915_pm_rpm@system-suspend-devices.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-1/igt@i915_pm_rpm@system-suspend-devices.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][78] -> [INCOMPLETE][79] ([i915#7790])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-snb4/igt@i915_pm_rps@reset.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-snb4/igt@i915_pm_rps@reset.html
* igt@i915_pm_rps@thresholds-idle@gt1:
- shard-mtlp: NOTRUN -> [SKIP][80] ([i915#8925]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@i915_pm_rps@thresholds-idle@gt1.html
* igt@i915_selftest@live@requests:
- shard-mtlp: [PASS][81] -> [ABORT][82] ([i915#7982] / [i915#8865])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-7/igt@i915_selftest@live@requests.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-7/igt@i915_selftest@live@requests.html
* igt@i915_suspend@forcewake:
- shard-dg2: [PASS][83] -> [FAIL][84] ([fdo#103375]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-3/igt@i915_suspend@forcewake.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-5/igt@i915_suspend@forcewake.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#4215] / [i915#5190])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg2: NOTRUN -> [SKIP][86] ([i915#4212])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
- shard-rkl: NOTRUN -> [SKIP][87] ([i915#3826])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-2-y-rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][88] ([i915#8502]) +3 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-2-y-rc_ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][89] ([i915#8502]) +7 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-18/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-4-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [FAIL][90] ([i915#8247]) +3 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-6/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html
* igt@kms_async_flips@crc@pipe-c-hdmi-a-1:
- shard-dg1: NOTRUN -> [FAIL][91] ([i915#8247]) +3 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-19/igt@kms_async_flips@crc@pipe-c-hdmi-a-1.html
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][92] ([fdo#111614]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][93] ([i915#5286])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
- shard-mtlp: [PASS][94] -> [FAIL][95] ([i915#5138])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: [PASS][96] -> [FAIL][97] ([i915#3743]) +3 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-mtlp: NOTRUN -> [SKIP][98] ([fdo#111615])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#4538] / [i915#5190]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-5/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-addfb:
- shard-rkl: NOTRUN -> [SKIP][100] ([fdo#111615])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_big_fb@yf-tiled-addfb.html
* igt@kms_big_joiner@basic:
- shard-rkl: NOTRUN -> [SKIP][101] ([i915#2705])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][102] ([i915#6095]) +3 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@kms_ccs@pipe-b-bad-rotation-90-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-4_tiled_mtl_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][103] ([i915#5354] / [i915#6095]) +3 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_ccs@pipe-b-ccs-on-another-bo-4_tiled_mtl_rc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][104] ([i915#3734] / [i915#5354] / [i915#6095])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-dg2: NOTRUN -> [SKIP][105] ([i915#3689] / [i915#3886] / [i915#5354]) +3 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#5354]) +3 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#3689] / [i915#5354]) +13 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#7213]) +3 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-2/igt@kms_cdclk@mode-transition@pipe-b-hdmi-a-2.html
* igt@kms_chamelium_color@ctm-0-50:
- shard-dg2: NOTRUN -> [SKIP][109] ([fdo#111827])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@kms_chamelium_color@ctm-0-50.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#7828]) +4 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium_frames@hdmi-frame-dump:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#7828]) +2 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_chamelium_frames@hdmi-frame-dump.html
* igt@kms_content_protection@legacy:
- shard-rkl: NOTRUN -> [SKIP][112] ([i915#7118])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_content_protection@legacy.html
* igt@kms_content_protection@lic:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#7118])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_content_protection@lic.html
* igt@kms_content_protection@uevent@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][114] ([i915#1339])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-11/igt@kms_content_protection@uevent@pipe-a-dp-4.html
* igt@kms_cursor_crc@cursor-random-32x32:
- shard-dg2: NOTRUN -> [SKIP][115] ([i915#3555])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@kms_cursor_crc@cursor-random-32x32.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg2: NOTRUN -> [SKIP][116] ([i915#3359])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-mtlp: NOTRUN -> [SKIP][117] ([i915#3546])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions:
- shard-dg2: NOTRUN -> [SKIP][118] ([fdo#109274] / [i915#5354]) +1 similar issue
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-rkl: NOTRUN -> [SKIP][119] ([fdo#111825])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
- shard-snb: NOTRUN -> [SKIP][120] ([fdo#109271] / [fdo#111767]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-snb2/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#3804])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-dg2: NOTRUN -> [SKIP][122] ([i915#3555] / [i915#3840])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#3637]) +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
- shard-dg2: NOTRUN -> [SKIP][124] ([fdo#109274]) +3 similar issues
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][125] ([i915#8810])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#2672])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][127] ([i915#2672]) +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: NOTRUN -> [SKIP][128] ([fdo#109285])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][129] ([i915#5354]) +17 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][130] ([i915#1825]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#8708]) +9 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#3458]) +8 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][133] ([i915#3023]) +4 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][134] ([fdo#111825] / [i915#1825]) +5 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_hdr@static-swap:
- shard-dg2: NOTRUN -> [SKIP][135] ([i915#3555] / [i915#8228]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-6/igt@kms_hdr@static-swap.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-snb: NOTRUN -> [DMESG-FAIL][136] ([fdo#103375])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-snb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#5176]) +11 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#5176]) +7 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][139] ([i915#5176]) +27 similar issues
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][140] ([i915#5235]) +19 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-19/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][141] ([i915#5235]) +5 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-1/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#5235]) +3 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-d-edp-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4:
- shard-dg2: NOTRUN -> [SKIP][143] ([i915#5235]) +11 similar issues
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-11/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-dp-4.html
* igt@kms_prime@basic-crc-hybrid:
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#6524])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr@sprite_blt:
- shard-dg2: NOTRUN -> [SKIP][145] ([i915#1072]) +3 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@kms_psr@sprite_blt.html
* igt@kms_rotation_crc@bad-pixel-format:
- shard-snb: NOTRUN -> [SKIP][146] ([fdo#109271]) +272 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-snb7/igt@kms_rotation_crc@bad-pixel-format.html
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#4235])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@kms_rotation_crc@bad-pixel-format.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][148] ([i915#5465]) +1 similar issue
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-snb1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@universal-plane-pipe-d-functional:
- shard-rkl: NOTRUN -> [SKIP][149] ([i915#4070] / [i915#533] / [i915#6768]) +1 similar issue
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-d-functional.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [PASS][150] -> [FAIL][151] ([i915#7484])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-3/igt@perf@non-zero-reason@0-rcs0.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][152] ([i915#5793] / [i915#6121])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@perf_pmu@module-unload.html
* igt@perf_pmu@rc6-suspend:
- shard-snb: NOTRUN -> [DMESG-WARN][153] ([i915#8841]) +6 similar issues
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-snb6/igt@perf_pmu@rc6-suspend.html
* igt@prime_vgem@basic-fence-mmap:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#3708] / [i915#4077])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@prime_vgem@basic-fence-mmap.html
* igt@v3d/v3d_perfmon@create-single-perfmon:
- shard-rkl: NOTRUN -> [SKIP][155] ([fdo#109315]) +1 similar issue
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@v3d/v3d_perfmon@create-single-perfmon.html
* igt@v3d/v3d_wait_bo@bad-bo:
- shard-mtlp: NOTRUN -> [SKIP][156] ([i915#2575])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@v3d/v3d_wait_bo@bad-bo.html
* igt@v3d/v3d_wait_bo@used-bo-1ns:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#2575]) +5 similar issues
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-5/igt@v3d/v3d_wait_bo@used-bo-1ns.html
* igt@vc4/vc4_label_bo@set-kernel-name:
- shard-dg2: NOTRUN -> [SKIP][158] ([i915#7711]) +4 similar issues
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@vc4/vc4_label_bo@set-kernel-name.html
* igt@vc4/vc4_mmap@mmap-bad-handle:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#7711])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@vc4/vc4_mmap@mmap-bad-handle.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [FAIL][160] ([i915#7742]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-7/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [FAIL][162] ([i915#6268]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-tglu-2/igt@gem_ctx_exec@basic-nohangcheck.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-tglu-8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-mtlp: [ABORT][164] ([i915#7941]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-5/igt@gem_eio@in-flight-contexts-10ms.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-6/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_eio@reset-stress:
- shard-dg1: [FAIL][166] ([i915#5784]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg1-14/igt@gem_eio@reset-stress.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-18/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][168] ([i915#2846]) -> [PASS][169]
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-glk4/igt@gem_exec_fair@basic-deadline.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-glk4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][170] ([i915#2842]) -> [PASS][171]
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [FAIL][172] ([i915#2842]) -> [PASS][173]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-tglu-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-tglu-10/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [TIMEOUT][174] ([i915#5493]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg1-19/igt@gem_lmem_swapping@smem-oom@lmem0.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglu: [SKIP][176] ([i915#4281]) -> [PASS][177]
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-tglu-5/igt@i915_pm_dc@dc9-dpms.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-tglu-4/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-dg2: [SKIP][178] ([i915#1937]) -> [PASS][179]
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-10/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-dg2: [SKIP][180] ([i915#1397]) -> [PASS][181]
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-2/igt@i915_pm_rpm@dpms-lpsp.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-10/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp:
- shard-rkl: [SKIP][182] ([i915#1397]) -> [PASS][183] +1 similar issue
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-dg1: [SKIP][184] ([i915#1397]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg1-14/igt@i915_pm_rpm@modeset-lpsp-stress.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-19/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-mtlp: [FAIL][186] ([i915#3743]) -> [PASS][187]
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-rkl: [ABORT][188] -> [PASS][189]
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-rkl-4/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-6/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html
* igt@perf_pmu@rc6-suspend:
- shard-dg2: [INCOMPLETE][190] ([i915#8772]) -> [PASS][191]
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-5/igt@perf_pmu@rc6-suspend.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-1/igt@perf_pmu@rc6-suspend.html
#### Warnings ####
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][192] ([i915#7118] / [i915#7162]) -> [SKIP][193] ([i915#7118])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-12/igt@kms_content_protection@type1.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-6/igt@kms_content_protection@type1.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: [DMESG-FAIL][194] ([i915#2017] / [i915#5954]) -> [FAIL][195] ([i915#2346])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-mtlp-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-mtlp-4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr:
- shard-rkl: [SKIP][196] ([fdo#110189] / [i915#3955]) -> [SKIP][197] ([i915#3955])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-rkl-2/igt@kms_fbcon_fbt@psr.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-rkl-7/igt@kms_fbcon_fbt@psr.html
* igt@kms_psr@primary_page_flip:
- shard-dg1: [SKIP][198] ([i915#1072] / [i915#4078]) -> [SKIP][199] ([i915#1072])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg1-13/igt@kms_psr@primary_page_flip.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg1-14/igt@kms_psr@primary_page_flip.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][200] ([i915#5493]) -> [CRASH][201] ([i915#7331])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13569/shard-dg2-2/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/shard-dg2-12/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1339]: https://gitlab.freedesktop.org/drm/intel/issues/1339
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
[i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#7052]: https://gitlab.freedesktop.org/drm/intel/issues/7052
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7765]: https://gitlab.freedesktop.org/drm/intel/issues/7765
[i915#7790]: https://gitlab.freedesktop.org/drm/intel/issues/7790
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7941]: https://gitlab.freedesktop.org/drm/intel/issues/7941
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8398]: https://gitlab.freedesktop.org/drm/intel/issues/8398
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8489]: https://gitlab.freedesktop.org/drm/intel/issues/8489
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
[i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8772]: https://gitlab.freedesktop.org/drm/intel/issues/8772
[i915#8810]: https://gitlab.freedesktop.org/drm/intel/issues/8810
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
[i915#9053]: https://gitlab.freedesktop.org/drm/intel/issues/9053
[i915#9119]: https://gitlab.freedesktop.org/drm/intel/issues/9119
[i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121
[i915#9151]: https://gitlab.freedesktop.org/drm/intel/issues/9151
Build changes
-------------
* Linux: CI_DRM_13569 -> Patchwork_122955v1
CI-20190529: 20190529
CI_DRM_13569: eb0ba85982a1832f4a61954c3fb99ac3e3f2e076 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7454: 7454
Patchwork_122955v1: eb0ba85982a1832f4a61954c3fb99ac3e3f2e076 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122955v1/index.html
[-- Attachment #2: Type: text/html, Size: 63284 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour
2023-08-28 5:41 ` [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour Ville Syrjala
@ 2023-08-28 16:58 ` Golani, Mitulkumar Ajitkumar
2023-08-29 8:20 ` Ville Syrjälä
0 siblings, 1 reply; 27+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-08-28 16:58 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
Hi Ville,
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 28 August 2023 11:12
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> behaviour
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the seamless_m_n flag more like the update_pipe fastset flag, ie. the
> flag will only be set if we need to do the seamless M/N update, and in all
> other cases the flag is cleared. Also rename the flag to update_m_n to
> make it more clear it's similar to update_pipe.
>
> I believe special casing seamless_m_n like this makes sense as it also affects
> eg. vblank evasion. We can potentially avoid some vblank evasion tricks,
> simplify some checks, and hopefully will help with the VRR vs. M/N mess.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++--------
> .../drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> 5 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 7cf51dd8c056..aaddd8c0cfa0 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> drm_property_blob_get(crtc_state->post_csc_lut);
>
> crtc_state->update_pipe = false;
> + crtc_state->update_m_n = false;
> crtc_state->disable_lp_wm = false;
> crtc_state->disable_cxsr = false;
> crtc_state->update_wm_pre = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 1992e7060263..a04076064f02 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -510,7 +510,7 @@ static void intel_crtc_vblank_evade_scanlines(struct
> intel_atomic_state *state,
> * M/N is double buffered on the transcoder's undelayed vblank,
> * so with seamless M/N we must evade both vblanks.
> */
> - if (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state))
> + if (new_crtc_state->update_m_n)
> *min -= adjusted_mode->crtc_vblank_start -
> adjusted_mode->crtc_vdisplay; }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 632f1f58df9e..6196ef76390b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> PIPE_CONF_CHECK_X(lane_lat_optim_mask);
>
> if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
> - if (!fastset || !pipe_config->seamless_m_n)
> + if (!fastset || !pipe_config->update_m_n)
> PIPE_CONF_CHECK_M_N(dp_m_n);
> } else {
> PIPE_CONF_CHECK_M_N(dp_m_n);
> @@ -5307,7 +5307,7 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> PIPE_CONF_CHECK_I(pipe_bpp);
>
> - if (!fastset || !pipe_config->seamless_m_n) {
> + if (!fastset || !pipe_config->update_m_n) {
> PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> }
> @@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct
> intel_atomic_state *state,
>
> crtc_state->uapi.mode_changed = true;
> crtc_state->update_pipe = false;
> + crtc_state->update_m_n = false;
>
> ret = drm_atomic_add_affected_connectors(&state->base,
> &crtc->base);
> @@ -5519,13 +5520,14 @@ static void intel_crtc_check_fastset(const struct
> intel_crtc_state *old_crtc_sta {
> struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc-
> >dev);
>
> - if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state,
> true)) {
> + if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state,
> true))
> drm_dbg_kms(&i915->drm, "fastset requirement not met,
> forcing full modeset\n");
> + else
> + new_crtc_state->uapi.mode_changed = false;
>
> - return;
> - }
> + if (intel_crtc_needs_modeset(new_crtc_state))
> + new_crtc_state->update_m_n = false;
>
> - new_crtc_state->uapi.mode_changed = false;
> if (!intel_crtc_needs_modeset(new_crtc_state))
> new_crtc_state->update_pipe = true;
> }
> @@ -6240,6 +6242,7 @@ int intel_atomic_check(struct drm_device *dev,
> if (intel_cpu_transcoders_need_modeset(state,
> BIT(master))) {
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> + new_crtc_state->update_m_n = false;
> }
> }
>
> @@ -6252,6 +6255,7 @@ int intel_atomic_check(struct drm_device *dev,
> if (intel_cpu_transcoders_need_modeset(state,
> trans)) {
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> + new_crtc_state->update_m_n = false;
> }
> }
>
> @@ -6259,6 +6263,7 @@ int intel_atomic_check(struct drm_device *dev,
> if (intel_pipes_need_modeset(state, new_crtc_state-
> >bigjoiner_pipes)) {
> new_crtc_state->uapi.mode_changed = true;
> new_crtc_state->update_pipe = false;
> + new_crtc_state->update_m_n = false;
> }
> }
> }
> @@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const struct
> intel_crtc_state *old_crtc_state,
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> hsw_set_linetime_wm(new_crtc_state);
>
> - if (new_crtc_state->seamless_m_n)
> + if (new_crtc_state->update_m_n)
> intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state-
> >cpu_transcoder,
> &new_crtc_state->dp_m_n);
> }
> @@ -6573,8 +6578,7 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
> *
> * FIXME Should be synchronized with the start of vblank
> somehow...
> */
> - if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> - (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state)))
> + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> +new_crtc_state->update_m_n)
> intel_crtc_update_active_timings(new_crtc_state,
> new_crtc_state->vrr.enable);
In the context where a Push has already been sent, should the update occur when we enable VRR itself? I'm curious about the rationale for not updating it immediately upon enabling VRR.
Regards,
Mitul
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 731f2ec04d5c..2367b030b469 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1083,6 +1083,7 @@ struct intel_crtc_state {
>
> unsigned fb_bits; /* framebuffers to flip */
> bool update_pipe; /* can a fast modeset be performed? */
> + bool update_m_n; /* update M/N seamlessly during fastset? */
> bool disable_cxsr;
> bool update_wm_pre, update_wm_post; /* watermarks are
> updated */
> bool fifo_changed; /* FIFO split is changed */ @@ -1195,7 +1196,6
> @@ struct intel_crtc_state {
> /* m2_n2 for eDP downclock */
> struct intel_link_m_n dp_m2_n2;
> bool has_drrs;
> - bool seamless_m_n;
>
> /* PSR is supported but might not be enabled due the lack of
> enabled planes */
> bool has_psr;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 05694e0b6143..ceab5b26b5e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2535,7 +2535,7 @@ intel_dp_drrs_compute_config(struct
> intel_connector *connector,
> int pixel_clock;
>
> if (has_seamless_m_n(connector))
> - pipe_config->seamless_m_n = true;
> + pipe_config->update_m_n = true;
>
> if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
> if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config-
> >cpu_transcoder))
> --
> 2.41.0
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section
2023-08-28 5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
@ 2023-08-28 18:16 ` Manasi Navare
2023-08-29 8:23 ` Ville Syrjälä
0 siblings, 1 reply; 27+ messages in thread
From: Manasi Navare @ 2023-08-28 18:16 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
By doing psr_unlock after the vblank evade, are we ensuring that even
when VRR params change during the pipe update, psr unlock will
happen after the actual vblank based on newly programmed VRR params?
Manasi
On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Do the PSR unlock after the vblank evade critcal section is
> fully over, not before.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 182c6dd64f47..5caa928e5ce9 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -646,10 +646,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> ktime_t end_vbl_time = ktime_get();
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - intel_psr_unlock(new_crtc_state);
> -
> if (new_crtc_state->do_async_flip)
> - return;
> + goto out;
>
> trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
>
> @@ -709,7 +707,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> local_irq_enable();
>
> if (intel_vgpu_active(dev_priv))
> - return;
> + goto out;
>
> if (crtc->debug.start_vbl_count &&
> crtc->debug.start_vbl_count != end_vbl_count) {
> @@ -724,4 +722,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> }
>
> dbg_vblank_evade(crtc, end_vbl_time);
> +
> +out:
> + intel_psr_unlock(new_crtc_state);
> }
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 2/6] drm/i915: Change intel_pipe_update_{start, end}() calling convention
2023-08-28 5:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
@ 2023-08-28 18:30 ` Manasi Navare
2023-08-29 8:27 ` Ville Syrjälä
0 siblings, 1 reply; 27+ messages in thread
From: Manasi Navare @ 2023-08-28 18:30 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We'll need to also look at the old crtc state in
> intel_pipe_update_start() so change the calling convention to
> just plumb in the full atomic state instead.
I am guessing we would need the old crtc state to look at if VRR parameters
were changed?
Could we elaborate why we would need old crtc state so we better understand this
change in the patch?
Manasi
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 18 ++++++++++++------
> drivers/gpu/drm/i915/display/intel_crtc.h | 6 ++++--
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 3 files changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 5caa928e5ce9..461949b48411 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -470,7 +470,8 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
>
> /**
> * intel_pipe_update_start() - start update of a set of display registers
> - * @new_crtc_state: the new crtc state
> + * @state: the atomic state
> + * @crtc: the crtc
> *
> * Mark the start of an update to pipe registers that should be updated
> * atomically regarding vblank. If the next vblank will happens within
> @@ -480,10 +481,12 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
> * until a subsequent call to intel_pipe_update_end(). That is done to
> * avoid random delays.
> */
> -void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
> +void intel_pipe_update_start(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> @@ -631,15 +634,18 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
>
> /**
> * intel_pipe_update_end() - end update of a set of display registers
> - * @new_crtc_state: the new crtc state
> + * @state: the atomic state
> + * @crtc: the crtc
> *
> * Mark the end of an update started with intel_pipe_update_start(). This
> * re-enables interrupts and verifies the update was actually completed
> * before a vblank.
> */
> -void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> +void intel_pipe_update_end(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> enum pipe pipe = crtc->pipe;
> int scanline_end = intel_get_crtc_scanline(crtc);
> u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
> index 51a4c8df9e65..22d7993d1f0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.h
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.h
> @@ -36,8 +36,10 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
> u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
> void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
> void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
> -void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
> -void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
> +void intel_pipe_update_start(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> +void intel_pipe_update_end(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
> struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915);
> struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f6397462e4c2..cfad967b5684 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6559,7 +6559,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> intel_crtc_planes_update_noarm(state, crtc);
>
> /* Perform vblank evasion around commit operation */
> - intel_pipe_update_start(new_crtc_state);
> + intel_pipe_update_start(state, crtc);
>
> commit_pipe_pre_planes(state, crtc);
>
> @@ -6567,7 +6567,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>
> commit_pipe_post_planes(state, crtc);
>
> - intel_pipe_update_end(new_crtc_state);
> + intel_pipe_update_end(state, crtc);
>
> /*
> * We usually enable FIFO underrun interrupts as part of the
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 3/6] drm/i915: Extract intel_crtc_vblank_evade_scanlines()
2023-08-28 5:41 ` [Intel-gfx] [PATCH 3/6] drm/i915: Extract intel_crtc_vblank_evade_scanlines() Ville Syrjala
@ 2023-08-28 18:31 ` Manasi Navare
0 siblings, 0 replies; 27+ messages in thread
From: Manasi Navare @ 2023-08-28 18:31 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
This looks good to me,
Reviewed-by: Manasi Navare <navaremanasi@chromium.org>
Manasi
On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the vblank evasion scanline calculations into their own helper
> to declutter intel_pipe_update_start() a bit.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 53 +++++++++++++----------
> 1 file changed, 31 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 461949b48411..e46a15d59d79 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -468,6 +468,36 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
> return vblank_start;
> }
>
> +static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + int *min, int *max, int *vblank_start)
> +{
> + const struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> + const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> +
> + if (new_crtc_state->vrr.enable) {
> + if (intel_vrr_is_push_sent(new_crtc_state))
> + *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
> + else
> + *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
> + } else {
> + *vblank_start = intel_mode_vblank_start(adjusted_mode);
> + }
> +
> + /* FIXME needs to be calibrated sensibly */
> + *min = *vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> + VBLANK_EVASION_TIME_US);
> + *max = *vblank_start - 1;
> +
> + /*
> + * M/N is double buffered on the transcoder's undelayed vblank,
> + * so with seamless M/N we must evade both vblanks.
> + */
> + if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
> + *min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> +}
> +
> /**
> * intel_pipe_update_start() - start update of a set of display registers
> * @state: the atomic state
> @@ -487,7 +517,6 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> long timeout = msecs_to_jiffies_timeout(1);
> int scanline, min, max, vblank_start;
> wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
> @@ -503,27 +532,7 @@ void intel_pipe_update_start(struct intel_atomic_state *state,
> if (intel_crtc_needs_vblank_work(new_crtc_state))
> intel_crtc_vblank_work_init(new_crtc_state);
>
> - if (new_crtc_state->vrr.enable) {
> - if (intel_vrr_is_push_sent(new_crtc_state))
> - vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
> - else
> - vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
> - } else {
> - vblank_start = intel_mode_vblank_start(adjusted_mode);
> - }
> -
> - /* FIXME needs to be calibrated sensibly */
> - min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> - VBLANK_EVASION_TIME_US);
> - max = vblank_start - 1;
> -
> - /*
> - * M/N is double buffered on the transcoder's undelayed vblank,
> - * so with seamless M/N we must evade both vblanks.
> - */
> - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
> - min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
> -
> + intel_crtc_vblank_evade_scanlines(state, crtc, &min, &max, &vblank_start);
> if (min <= 0 || max <= 0)
> goto irq_disable;
>
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets
2023-08-28 5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets Ville Syrjala
@ 2023-08-28 18:47 ` Manasi Navare
2023-08-29 8:26 ` Ville Syrjälä
2023-09-11 18:21 ` Golani, Mitulkumar Ajitkumar
1 sibling, 1 reply; 27+ messages in thread
From: Manasi Navare @ 2023-08-28 18:47 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
<ville.syrjala@linux.intel.com> wrote:
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In order to reconcile seamless M/N updates with VRR we'll
> need to defer the fastset VRR enable to happen after the
> seamless M/N update (which happens during the vblank evade
> critical section). So just push the VRR enable to be the last
> thing during the update.
>
> This will also affect the vblank evasion as the transcoder
> will now still be running with the old VRR state during
> the vblank evasion. So just grab the timings always from the
> old crtc state during any non-modeset commit, and also grab
> the current state of VRR from the active timings (as we disable
> VRR before vblank evasion during fastsets).
>
> This also fixes vblank evasion for seamless M/N updates as
> we now properly account for the fact that the M/N update
> happens after vblank evasion.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 35 ++++++++++++--------
> drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++----
> 2 files changed, 36 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index e46a15d59d79..1992e7060263 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -472,15 +472,31 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> int *min, int *max, int *vblank_start)
> {
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> + const struct intel_crtc_state *crtc_state;
> + const struct drm_display_mode *adjusted_mode;
>
> - if (new_crtc_state->vrr.enable) {
> - if (intel_vrr_is_push_sent(new_crtc_state))
> - *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
> + /*
> + * During fastsets/etc. the transcoder is still
> + * running with the old timings at this point.
> + *
> + * TODO: maybe just use the active timings here?
> + */
> + if (intel_crtc_needs_modeset(new_crtc_state))
> + crtc_state = new_crtc_state;
> + else
> + crtc_state = old_crtc_state;
> +
> + adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> + if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> + if (intel_vrr_is_push_sent(crtc_state))
> + *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> else
> - *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
> + *vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
> } else {
> *vblank_start = intel_mode_vblank_start(adjusted_mode);
> }
> @@ -710,15 +726,6 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
> */
> intel_vrr_send_push(new_crtc_state);
>
> - /*
> - * Seamless M/N update may need to update frame timings.
> - *
> - * FIXME Should be synchronized with the start of vblank somehow...
> - */
> - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
> - intel_crtc_update_active_timings(new_crtc_state,
> - new_crtc_state->vrr.enable);
> -
> local_irq_enable();
>
> if (intel_vgpu_active(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index cfad967b5684..632f1f58df9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6476,6 +6476,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> @@ -6487,6 +6489,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> if (DISPLAY_VER(dev_priv) >= 9 &&
> !intel_crtc_needs_modeset(new_crtc_state))
> skl_detach_scalers(new_crtc_state);
> +
> + if (vrr_enabling(old_crtc_state, new_crtc_state))
> + intel_vrr_enable(new_crtc_state);
Wouldnt we also need the condition here:
new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
So that we update VRR enable bit in the seamless_m_n fastset case as well.
This will be needed later once we start updating the VRR params regs
in fastset, since
that otherwise ends up resetting VRR enable bit.
> }
>
> static void intel_enable_crtc(struct intel_atomic_state *state,
> @@ -6527,12 +6532,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> intel_dpt_configure(crtc);
> }
>
> - if (vrr_enabling(old_crtc_state, new_crtc_state)) {
> - intel_vrr_enable(new_crtc_state);
> - intel_crtc_update_active_timings(new_crtc_state,
> - new_crtc_state->vrr.enable);
> - }
> -
> if (!modeset) {
> if (new_crtc_state->preload_luts &&
> intel_crtc_needs_color_update(new_crtc_state))
> @@ -6569,6 +6568,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
>
> intel_pipe_update_end(state, crtc);
>
> + /*
> + * VRR/Seamless M/N update may need to update frame timings.
> + *
> + * FIXME Should be synchronized with the start of vblank somehow...
> + */
> + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> + (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
> + intel_crtc_update_active_timings(new_crtc_state,
> + new_crtc_state->vrr.enable);
> +
So would the VRR min/max, flipline values also be updated here
eventually for the fastset in seamless_m_n case?
Manasi
> /*
> * We usually enable FIFO underrun interrupts as part of the
> * CRTC enable sequence during modesets. But when we inherit a
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour
2023-08-28 16:58 ` Golani, Mitulkumar Ajitkumar
@ 2023-08-29 8:20 ` Ville Syrjälä
2023-08-29 13:48 ` Golani, Mitulkumar Ajitkumar
0 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjälä @ 2023-08-29 8:20 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar; +Cc: intel-gfx@lists.freedesktop.org
On Mon, Aug 28, 2023 at 04:58:49PM +0000, Golani, Mitulkumar Ajitkumar wrote:
> Hi Ville,
>
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: 28 August 2023 11:12
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> > behaviour
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Make the seamless_m_n flag more like the update_pipe fastset flag, ie. the
> > flag will only be set if we need to do the seamless M/N update, and in all
> > other cases the flag is cleared. Also rename the flag to update_m_n to
> > make it more clear it's similar to update_pipe.
> >
> > I believe special casing seamless_m_n like this makes sense as it also affects
> > eg. vblank evasion. We can potentially avoid some vblank evasion tricks,
> > simplify some checks, and hopefully will help with the VRR vs. M/N mess.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++--------
> > .../drm/i915/display/intel_display_types.h | 2 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > 5 files changed, 17 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index 7cf51dd8c056..aaddd8c0cfa0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> > drm_property_blob_get(crtc_state->post_csc_lut);
> >
> > crtc_state->update_pipe = false;
> > + crtc_state->update_m_n = false;
> > crtc_state->disable_lp_wm = false;
> > crtc_state->disable_cxsr = false;
> > crtc_state->update_wm_pre = false;
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 1992e7060263..a04076064f02 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -510,7 +510,7 @@ static void intel_crtc_vblank_evade_scanlines(struct
> > intel_atomic_state *state,
> > * M/N is double buffered on the transcoder's undelayed vblank,
> > * so with seamless M/N we must evade both vblanks.
> > */
> > - if (new_crtc_state->seamless_m_n &&
> > intel_crtc_needs_fastset(new_crtc_state))
> > + if (new_crtc_state->update_m_n)
> > *min -= adjusted_mode->crtc_vblank_start -
> > adjusted_mode->crtc_vdisplay; }
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 632f1f58df9e..6196ef76390b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> > PIPE_CONF_CHECK_X(lane_lat_optim_mask);
> >
> > if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
> > - if (!fastset || !pipe_config->seamless_m_n)
> > + if (!fastset || !pipe_config->update_m_n)
> > PIPE_CONF_CHECK_M_N(dp_m_n);
> > } else {
> > PIPE_CONF_CHECK_M_N(dp_m_n);
> > @@ -5307,7 +5307,7 @@ intel_pipe_config_compare(const struct
> > intel_crtc_state *current_config,
> > if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> > PIPE_CONF_CHECK_I(pipe_bpp);
> >
> > - if (!fastset || !pipe_config->seamless_m_n) {
> > + if (!fastset || !pipe_config->update_m_n) {
> > PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> > PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> > }
> > @@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct
> > intel_atomic_state *state,
> >
> > crtc_state->uapi.mode_changed = true;
> > crtc_state->update_pipe = false;
> > + crtc_state->update_m_n = false;
> >
> > ret = drm_atomic_add_affected_connectors(&state->base,
> > &crtc->base);
> > @@ -5519,13 +5520,14 @@ static void intel_crtc_check_fastset(const struct
> > intel_crtc_state *old_crtc_sta {
> > struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc-
> > >dev);
> >
> > - if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state,
> > true)) {
> > + if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state,
> > true))
> > drm_dbg_kms(&i915->drm, "fastset requirement not met,
> > forcing full modeset\n");
> > + else
> > + new_crtc_state->uapi.mode_changed = false;
> >
> > - return;
> > - }
> > + if (intel_crtc_needs_modeset(new_crtc_state))
> > + new_crtc_state->update_m_n = false;
> >
> > - new_crtc_state->uapi.mode_changed = false;
> > if (!intel_crtc_needs_modeset(new_crtc_state))
> > new_crtc_state->update_pipe = true;
> > }
> > @@ -6240,6 +6242,7 @@ int intel_atomic_check(struct drm_device *dev,
> > if (intel_cpu_transcoders_need_modeset(state,
> > BIT(master))) {
> > new_crtc_state->uapi.mode_changed = true;
> > new_crtc_state->update_pipe = false;
> > + new_crtc_state->update_m_n = false;
> > }
> > }
> >
> > @@ -6252,6 +6255,7 @@ int intel_atomic_check(struct drm_device *dev,
> > if (intel_cpu_transcoders_need_modeset(state,
> > trans)) {
> > new_crtc_state->uapi.mode_changed = true;
> > new_crtc_state->update_pipe = false;
> > + new_crtc_state->update_m_n = false;
> > }
> > }
> >
> > @@ -6259,6 +6263,7 @@ int intel_atomic_check(struct drm_device *dev,
> > if (intel_pipes_need_modeset(state, new_crtc_state-
> > >bigjoiner_pipes)) {
> > new_crtc_state->uapi.mode_changed = true;
> > new_crtc_state->update_pipe = false;
> > + new_crtc_state->update_m_n = false;
> > }
> > }
> > }
> > @@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const struct
> > intel_crtc_state *old_crtc_state,
> > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > hsw_set_linetime_wm(new_crtc_state);
> >
> > - if (new_crtc_state->seamless_m_n)
> > + if (new_crtc_state->update_m_n)
> > intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state-
> > >cpu_transcoder,
> > &new_crtc_state->dp_m_n);
> > }
> > @@ -6573,8 +6578,7 @@ static void intel_update_crtc(struct
> > intel_atomic_state *state,
> > *
> > * FIXME Should be synchronized with the start of vblank
> > somehow...
> > */
> > - if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > - (new_crtc_state->seamless_m_n &&
> > intel_crtc_needs_fastset(new_crtc_state)))
> > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > +new_crtc_state->update_m_n)
> > intel_crtc_update_active_timings(new_crtc_state,
> > new_crtc_state->vrr.enable);
>
> In the context where a Push has already been sent, should the update occur when we enable VRR itself? I'm curious about the rationale for not updating it immediately upon enabling VRR.
The active timings should really be updated synchronously
with the hardware latching the new values. But that is actually
impossible so some race conditions will always remain.
I haven't actually verified how the hardware behaves when we
enable VRR. I assume the VRR_CTL will get latched at the next
start of vblank as well. But we should really try to confirm
that on actual hardware.
The case where we have VRR already enabled while updating
M/N might go badly with the current order of doing things
as the vblank irq may trigger immediately upon push. So for
that case it would be better to update the active timings
before the push. Or perhaps we should just make sure VRR is
always disabled around M/N updates...
>
> Regards,
> Mitul
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 731f2ec04d5c..2367b030b469 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1083,6 +1083,7 @@ struct intel_crtc_state {
> >
> > unsigned fb_bits; /* framebuffers to flip */
> > bool update_pipe; /* can a fast modeset be performed? */
> > + bool update_m_n; /* update M/N seamlessly during fastset? */
> > bool disable_cxsr;
> > bool update_wm_pre, update_wm_post; /* watermarks are
> > updated */
> > bool fifo_changed; /* FIFO split is changed */ @@ -1195,7 +1196,6
> > @@ struct intel_crtc_state {
> > /* m2_n2 for eDP downclock */
> > struct intel_link_m_n dp_m2_n2;
> > bool has_drrs;
> > - bool seamless_m_n;
> >
> > /* PSR is supported but might not be enabled due the lack of
> > enabled planes */
> > bool has_psr;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 05694e0b6143..ceab5b26b5e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2535,7 +2535,7 @@ intel_dp_drrs_compute_config(struct
> > intel_connector *connector,
> > int pixel_clock;
> >
> > if (has_seamless_m_n(connector))
> > - pipe_config->seamless_m_n = true;
> > + pipe_config->update_m_n = true;
> >
> > if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
> > if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config-
> > >cpu_transcoder))
> > --
> > 2.41.0
>
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section
2023-08-28 18:16 ` Manasi Navare
@ 2023-08-29 8:23 ` Ville Syrjälä
0 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjälä @ 2023-08-29 8:23 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Mon, Aug 28, 2023 at 11:16:13AM -0700, Manasi Navare wrote:
> By doing psr_unlock after the vblank evade, are we ensuring that even
> when VRR params change during the pipe update, psr unlock will
> happen after the actual vblank based on newly programmed VRR params?
The unlock will happen as soon as the new register values have been
written. The vblank will happen when it happens, could be asap or could
be much later.
I don't actually even know what this PSR lock is protecting, I suppose
it's trying to prevent muckery with the PSR hw state while the update
is being programmed. Shrug.
>
> Manasi
>
> On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Do the PSR unlock after the vblank evade critcal section is
> > fully over, not before.
> >
> > Cc: Manasi Navare <navaremanasi@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_crtc.c | 9 +++++----
> > 1 file changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 182c6dd64f47..5caa928e5ce9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -646,10 +646,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> > ktime_t end_vbl_time = ktime_get();
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > - intel_psr_unlock(new_crtc_state);
> > -
> > if (new_crtc_state->do_async_flip)
> > - return;
> > + goto out;
> >
> > trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end);
> >
> > @@ -709,7 +707,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> > local_irq_enable();
> >
> > if (intel_vgpu_active(dev_priv))
> > - return;
> > + goto out;
> >
> > if (crtc->debug.start_vbl_count &&
> > crtc->debug.start_vbl_count != end_vbl_count) {
> > @@ -724,4 +722,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> > }
> >
> > dbg_vblank_evade(crtc, end_vbl_time);
> > +
> > +out:
> > + intel_psr_unlock(new_crtc_state);
> > }
> > --
> > 2.41.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets
2023-08-28 18:47 ` Manasi Navare
@ 2023-08-29 8:26 ` Ville Syrjälä
2023-08-29 14:58 ` Manasi Navare
0 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjälä @ 2023-08-29 8:26 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Mon, Aug 28, 2023 at 11:47:49AM -0700, Manasi Navare wrote:
> On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > In order to reconcile seamless M/N updates with VRR we'll
> > need to defer the fastset VRR enable to happen after the
> > seamless M/N update (which happens during the vblank evade
> > critical section). So just push the VRR enable to be the last
> > thing during the update.
> >
> > This will also affect the vblank evasion as the transcoder
> > will now still be running with the old VRR state during
> > the vblank evasion. So just grab the timings always from the
> > old crtc state during any non-modeset commit, and also grab
> > the current state of VRR from the active timings (as we disable
> > VRR before vblank evasion during fastsets).
> >
> > This also fixes vblank evasion for seamless M/N updates as
> > we now properly account for the fact that the M/N update
> > happens after vblank evasion.
> >
> > Cc: Manasi Navare <navaremanasi@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_crtc.c | 35 ++++++++++++--------
> > drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++----
> > 2 files changed, 36 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index e46a15d59d79..1992e7060263 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -472,15 +472,31 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > struct intel_crtc *crtc,
> > int *min, int *max, int *vblank_start)
> > {
> > + const struct intel_crtc_state *old_crtc_state =
> > + intel_atomic_get_old_crtc_state(state, crtc);
> > const struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> > - const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> > + const struct intel_crtc_state *crtc_state;
> > + const struct drm_display_mode *adjusted_mode;
> >
> > - if (new_crtc_state->vrr.enable) {
> > - if (intel_vrr_is_push_sent(new_crtc_state))
> > - *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
> > + /*
> > + * During fastsets/etc. the transcoder is still
> > + * running with the old timings at this point.
> > + *
> > + * TODO: maybe just use the active timings here?
> > + */
> > + if (intel_crtc_needs_modeset(new_crtc_state))
> > + crtc_state = new_crtc_state;
> > + else
> > + crtc_state = old_crtc_state;
> > +
> > + adjusted_mode = &crtc_state->hw.adjusted_mode;
> > +
> > + if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> > + if (intel_vrr_is_push_sent(crtc_state))
> > + *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> > else
> > - *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
> > + *vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
> > } else {
> > *vblank_start = intel_mode_vblank_start(adjusted_mode);
> > }
> > @@ -710,15 +726,6 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
> > */
> > intel_vrr_send_push(new_crtc_state);
> >
> > - /*
> > - * Seamless M/N update may need to update frame timings.
> > - *
> > - * FIXME Should be synchronized with the start of vblank somehow...
> > - */
> > - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
> > - intel_crtc_update_active_timings(new_crtc_state,
> > - new_crtc_state->vrr.enable);
> > -
> > local_irq_enable();
> >
> > if (intel_vgpu_active(dev_priv))
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index cfad967b5684..632f1f58df9e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6476,6 +6476,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> > struct intel_crtc *crtc)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + const struct intel_crtc_state *old_crtc_state =
> > + intel_atomic_get_old_crtc_state(state, crtc);
> > const struct intel_crtc_state *new_crtc_state =
> > intel_atomic_get_new_crtc_state(state, crtc);
> >
> > @@ -6487,6 +6489,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> > if (DISPLAY_VER(dev_priv) >= 9 &&
> > !intel_crtc_needs_modeset(new_crtc_state))
> > skl_detach_scalers(new_crtc_state);
> > +
> > + if (vrr_enabling(old_crtc_state, new_crtc_state))
> > + intel_vrr_enable(new_crtc_state);
>
> Wouldnt we also need the condition here:
> new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
That is handled elsewhere already.
>
> So that we update VRR enable bit in the seamless_m_n fastset case as well.
> This will be needed later once we start updating the VRR params regs
> in fastset, since
> that otherwise ends up resetting VRR enable bit.
>
>
>
> > }
> >
> > static void intel_enable_crtc(struct intel_atomic_state *state,
> > @@ -6527,12 +6532,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > intel_dpt_configure(crtc);
> > }
> >
> > - if (vrr_enabling(old_crtc_state, new_crtc_state)) {
> > - intel_vrr_enable(new_crtc_state);
> > - intel_crtc_update_active_timings(new_crtc_state,
> > - new_crtc_state->vrr.enable);
> > - }
> > -
> > if (!modeset) {
> > if (new_crtc_state->preload_luts &&
> > intel_crtc_needs_color_update(new_crtc_state))
> > @@ -6569,6 +6568,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> >
> > intel_pipe_update_end(state, crtc);
> >
> > + /*
> > + * VRR/Seamless M/N update may need to update frame timings.
> > + *
> > + * FIXME Should be synchronized with the start of vblank somehow...
> > + */
> > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > + (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
> > + intel_crtc_update_active_timings(new_crtc_state,
> > + new_crtc_state->vrr.enable);
> > +
>
> So would the VRR min/max, flipline values also be updated here
> eventually for the fastset in seamless_m_n case?
No, it would be done earlier. Should be OK to do anywhere
between the VRR disable and enable really. Doesn't even need
to be inside the vblank evade critical section since VRR will
already have been disabled when we change these.
>
> Manasi
>
>
> > /*
> > * We usually enable FIFO underrun interrupts as part of the
> > * CRTC enable sequence during modesets. But when we inherit a
> > --
> > 2.41.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 2/6] drm/i915: Change intel_pipe_update_{start, end}() calling convention
2023-08-28 18:30 ` Manasi Navare
@ 2023-08-29 8:27 ` Ville Syrjälä
0 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjälä @ 2023-08-29 8:27 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Mon, Aug 28, 2023 at 11:30:25AM -0700, Manasi Navare wrote:
> On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We'll need to also look at the old crtc state in
> > intel_pipe_update_start() so change the calling convention to
> > just plumb in the full atomic state instead.
>
> I am guessing we would need the old crtc state to look at if VRR parameters
> were changed?
> Could we elaborate why we would need old crtc state so we better understand this
> change in the patch?
Details are in the patch that does those changes.
>
> Manasi
>
> >
> > Cc: Manasi Navare <navaremanasi@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_crtc.c | 18 ++++++++++++------
> > drivers/gpu/drm/i915/display/intel_crtc.h | 6 ++++--
> > drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> > 3 files changed, 18 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 5caa928e5ce9..461949b48411 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -470,7 +470,8 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
> >
> > /**
> > * intel_pipe_update_start() - start update of a set of display registers
> > - * @new_crtc_state: the new crtc state
> > + * @state: the atomic state
> > + * @crtc: the crtc
> > *
> > * Mark the start of an update to pipe registers that should be updated
> > * atomically regarding vblank. If the next vblank will happens within
> > @@ -480,10 +481,12 @@ static int intel_mode_vblank_start(const struct drm_display_mode *mode)
> > * until a subsequent call to intel_pipe_update_end(). That is done to
> > * avoid random delays.
> > */
> > -void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
> > +void intel_pipe_update_start(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + struct intel_crtc_state *new_crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> > long timeout = msecs_to_jiffies_timeout(1);
> > int scanline, min, max, vblank_start;
> > @@ -631,15 +634,18 @@ static void dbg_vblank_evade(struct intel_crtc *crtc, ktime_t end) {}
> >
> > /**
> > * intel_pipe_update_end() - end update of a set of display registers
> > - * @new_crtc_state: the new crtc state
> > + * @state: the atomic state
> > + * @crtc: the crtc
> > *
> > * Mark the end of an update started with intel_pipe_update_start(). This
> > * re-enables interrupts and verifies the update was actually completed
> > * before a vblank.
> > */
> > -void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
> > +void intel_pipe_update_end(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc)
> > {
> > - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> > + struct intel_crtc_state *new_crtc_state =
> > + intel_atomic_get_new_crtc_state(state, crtc);
> > enum pipe pipe = crtc->pipe;
> > int scanline_end = intel_get_crtc_scanline(crtc);
> > u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
> > index 51a4c8df9e65..22d7993d1f0b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.h
> > @@ -36,8 +36,10 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
> > u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
> > void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state);
> > void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state);
> > -void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state);
> > -void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
> > +void intel_pipe_update_start(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc);
> > +void intel_pipe_update_end(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc);
> > void intel_wait_for_vblank_workers(struct intel_atomic_state *state);
> > struct intel_crtc *intel_first_crtc(struct drm_i915_private *i915);
> > struct intel_crtc *intel_crtc_for_pipe(struct drm_i915_private *i915,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f6397462e4c2..cfad967b5684 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -6559,7 +6559,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > intel_crtc_planes_update_noarm(state, crtc);
> >
> > /* Perform vblank evasion around commit operation */
> > - intel_pipe_update_start(new_crtc_state);
> > + intel_pipe_update_start(state, crtc);
> >
> > commit_pipe_pre_planes(state, crtc);
> >
> > @@ -6567,7 +6567,7 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> >
> > commit_pipe_post_planes(state, crtc);
> >
> > - intel_pipe_update_end(new_crtc_state);
> > + intel_pipe_update_end(state, crtc);
> >
> > /*
> > * We usually enable FIFO underrun interrupts as part of the
> > --
> > 2.41.0
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour
2023-08-29 8:20 ` Ville Syrjälä
@ 2023-08-29 13:48 ` Golani, Mitulkumar Ajitkumar
2023-08-30 5:16 ` Ville Syrjälä
0 siblings, 1 reply; 27+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-08-29 13:48 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx@lists.freedesktop.org
Hi Ville,
Thanks for the inputs.
I encountered an interesting observation while validating the changes.
In scenarios where VRR is by default ON from the panel, I noticed that during the first-time enabling of VRR, a full modeset is required due to a fastset requirement mismatch, as indicated in the logs.
However, I also observed that after this, the function intel_crtc_needs_modeset returns 0, which typically implies a fastset operation.
Considering that both conditions can't hold simultaneously, there seems to be an inconsistency with underrun errors.
Could you kindly shed some light on this situation? I'm trying to align the log messages with the observed behavior and the function's return value.
Your insights would be greatly appreciated.
Regards,
Mitul
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: 29 August 2023 13:51
> To: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> behaviour
>
> On Mon, Aug 28, 2023 at 04:58:49PM +0000, Golani, Mitulkumar Ajitkumar
> wrote:
> > Hi Ville,
> >
> > > -----Original Message-----
> > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > Of Ville Syrjala
> > > Sent: 28 August 2023 11:12
> > > To: intel-gfx@lists.freedesktop.org
> > > Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> > > behaviour
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Make the seamless_m_n flag more like the update_pipe fastset flag,
> > > ie. the flag will only be set if we need to do the seamless M/N
> > > update, and in all other cases the flag is cleared. Also rename the
> > > flag to update_m_n to make it more clear it's similar to update_pipe.
> > >
> > > I believe special casing seamless_m_n like this makes sense as it
> > > also affects eg. vblank evasion. We can potentially avoid some
> > > vblank evasion tricks, simplify some checks, and hopefully will help with
> the VRR vs. M/N mess.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > > drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> > > drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++--------
> > > .../drm/i915/display/intel_display_types.h | 2 +-
> > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > 5 files changed, 17 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > index 7cf51dd8c056..aaddd8c0cfa0 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > @@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> > > drm_property_blob_get(crtc_state->post_csc_lut);
> > >
> > > crtc_state->update_pipe = false;
> > > + crtc_state->update_m_n = false;
> > > crtc_state->disable_lp_wm = false;
> > > crtc_state->disable_cxsr = false;
> > > crtc_state->update_wm_pre = false; diff --git
> > > a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > index 1992e7060263..a04076064f02 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > @@ -510,7 +510,7 @@ static void
> > > intel_crtc_vblank_evade_scanlines(struct
> > > intel_atomic_state *state,
> > > * M/N is double buffered on the transcoder's undelayed vblank,
> > > * so with seamless M/N we must evade both vblanks.
> > > */
> > > - if (new_crtc_state->seamless_m_n &&
> > > intel_crtc_needs_fastset(new_crtc_state))
> > > + if (new_crtc_state->update_m_n)
> > > *min -= adjusted_mode->crtc_vblank_start -
> > > adjusted_mode->crtc_vdisplay; }
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 632f1f58df9e..6196ef76390b 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const struct
> > > intel_crtc_state *current_config,
> > > PIPE_CONF_CHECK_X(lane_lat_optim_mask);
> > >
> > > if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
> > > - if (!fastset || !pipe_config->seamless_m_n)
> > > + if (!fastset || !pipe_config->update_m_n)
> > > PIPE_CONF_CHECK_M_N(dp_m_n);
> > > } else {
> > > PIPE_CONF_CHECK_M_N(dp_m_n);
> > > @@ -5307,7 +5307,7 @@ intel_pipe_config_compare(const struct
> > > intel_crtc_state *current_config,
> > > if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> > > PIPE_CONF_CHECK_I(pipe_bpp);
> > >
> > > - if (!fastset || !pipe_config->seamless_m_n) {
> > > + if (!fastset || !pipe_config->update_m_n) {
> > > PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> > > PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> > > }
> > > @@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct
> > > intel_atomic_state *state,
> > >
> > > crtc_state->uapi.mode_changed = true;
> > > crtc_state->update_pipe = false;
> > > + crtc_state->update_m_n = false;
> > >
> > > ret = drm_atomic_add_affected_connectors(&state->base,
> > > &crtc->base);
> > > @@ -5519,13 +5520,14 @@ static void intel_crtc_check_fastset(const
> > > struct intel_crtc_state *old_crtc_sta {
> > > struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc-
> > > >dev);
> > >
> > > - if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state,
> > > true)) {
> > > + if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state,
> > > true))
> > > drm_dbg_kms(&i915->drm, "fastset requirement not met,
> forcing
> > > full modeset\n");
> > > + else
> > > + new_crtc_state->uapi.mode_changed = false;
> > >
> > > - return;
> > > - }
> > > + if (intel_crtc_needs_modeset(new_crtc_state))
> > > + new_crtc_state->update_m_n = false;
> > >
> > > - new_crtc_state->uapi.mode_changed = false;
> > > if (!intel_crtc_needs_modeset(new_crtc_state))
> > > new_crtc_state->update_pipe = true; } @@ -6240,6 +6242,7
> @@ int
> > > intel_atomic_check(struct drm_device *dev,
> > > if (intel_cpu_transcoders_need_modeset(state,
> > > BIT(master))) {
> > > new_crtc_state->uapi.mode_changed = true;
> > > new_crtc_state->update_pipe = false;
> > > + new_crtc_state->update_m_n = false;
> > > }
> > > }
> > >
> > > @@ -6252,6 +6255,7 @@ int intel_atomic_check(struct drm_device
> *dev,
> > > if (intel_cpu_transcoders_need_modeset(state,
> > > trans)) {
> > > new_crtc_state->uapi.mode_changed = true;
> > > new_crtc_state->update_pipe = false;
> > > + new_crtc_state->update_m_n = false;
> > > }
> > > }
> > >
> > > @@ -6259,6 +6263,7 @@ int intel_atomic_check(struct drm_device
> *dev,
> > > if (intel_pipes_need_modeset(state, new_crtc_state-
> > > >bigjoiner_pipes)) {
> > > new_crtc_state->uapi.mode_changed = true;
> > > new_crtc_state->update_pipe = false;
> > > + new_crtc_state->update_m_n = false;
> > > }
> > > }
> > > }
> > > @@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const struct
> > > intel_crtc_state *old_crtc_state,
> > > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > > hsw_set_linetime_wm(new_crtc_state);
> > >
> > > - if (new_crtc_state->seamless_m_n)
> > > + if (new_crtc_state->update_m_n)
> > > intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state-
> > > >cpu_transcoder,
> > > &new_crtc_state->dp_m_n); }
> @@ -6573,8 +6578,7 @@
> > > static void intel_update_crtc(struct intel_atomic_state *state,
> > > *
> > > * FIXME Should be synchronized with the start of vblank
> > > somehow...
> > > */
> > > - if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > - (new_crtc_state->seamless_m_n &&
> > > intel_crtc_needs_fastset(new_crtc_state)))
> > > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > +new_crtc_state->update_m_n)
> > > intel_crtc_update_active_timings(new_crtc_state,
> > > new_crtc_state->vrr.enable);
> >
> > In the context where a Push has already been sent, should the update
> occur when we enable VRR itself? I'm curious about the rationale for not
> updating it immediately upon enabling VRR.
>
> The active timings should really be updated synchronously with the
> hardware latching the new values. But that is actually impossible so some
> race conditions will always remain.
>
> I haven't actually verified how the hardware behaves when we enable VRR.
> I assume the VRR_CTL will get latched at the next start of vblank as well.
> But we should really try to confirm that on actual hardware.
>
> The case where we have VRR already enabled while updating M/N might go
> badly with the current order of doing things as the vblank irq may trigger
> immediately upon push. So for that case it would be better to update the
> active timings before the push. Or perhaps we should just make sure VRR is
> always disabled around M/N updates...
>
> >
> > Regards,
> > Mitul
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 731f2ec04d5c..2367b030b469 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1083,6 +1083,7 @@ struct intel_crtc_state {
> > >
> > > unsigned fb_bits; /* framebuffers to flip */
> > > bool update_pipe; /* can a fast modeset be performed? */
> > > + bool update_m_n; /* update M/N seamlessly during fastset? */
> > > bool disable_cxsr;
> > > bool update_wm_pre, update_wm_post; /* watermarks are
> updated */
> > > bool fifo_changed; /* FIFO split is changed */ @@ -1195,7 +1196,6
> > > @@ struct intel_crtc_state {
> > > /* m2_n2 for eDP downclock */
> > > struct intel_link_m_n dp_m2_n2;
> > > bool has_drrs;
> > > - bool seamless_m_n;
> > >
> > > /* PSR is supported but might not be enabled due the lack of
> > > enabled planes */
> > > bool has_psr;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 05694e0b6143..ceab5b26b5e8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -2535,7 +2535,7 @@ intel_dp_drrs_compute_config(struct
> > > intel_connector *connector,
> > > int pixel_clock;
> > >
> > > if (has_seamless_m_n(connector))
> > > - pipe_config->seamless_m_n = true;
> > > + pipe_config->update_m_n = true;
> > >
> > > if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
> > > if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config-
> > > >cpu_transcoder))
> > > --
> > > 2.41.0
> >
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets
2023-08-29 8:26 ` Ville Syrjälä
@ 2023-08-29 14:58 ` Manasi Navare
2023-08-30 5:12 ` Ville Syrjälä
0 siblings, 1 reply; 27+ messages in thread
From: Manasi Navare @ 2023-08-29 14:58 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, Aug 29, 2023 at 1:26 AM Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
>
> On Mon, Aug 28, 2023 at 11:47:49AM -0700, Manasi Navare wrote:
> > On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
> > <ville.syrjala@linux.intel.com> wrote:
> > >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > In order to reconcile seamless M/N updates with VRR we'll
> > > need to defer the fastset VRR enable to happen after the
> > > seamless M/N update (which happens during the vblank evade
> > > critical section). So just push the VRR enable to be the last
> > > thing during the update.
> > >
> > > This will also affect the vblank evasion as the transcoder
> > > will now still be running with the old VRR state during
> > > the vblank evasion. So just grab the timings always from the
> > > old crtc state during any non-modeset commit, and also grab
> > > the current state of VRR from the active timings (as we disable
> > > VRR before vblank evasion during fastsets).
> > >
> > > This also fixes vblank evasion for seamless M/N updates as
> > > we now properly account for the fact that the M/N update
> > > happens after vblank evasion.
> > >
> > > Cc: Manasi Navare <navaremanasi@chromium.org>
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_crtc.c | 35 ++++++++++++--------
> > > drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++----
> > > 2 files changed, 36 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > index e46a15d59d79..1992e7060263 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > @@ -472,15 +472,31 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc,
> > > int *min, int *max, int *vblank_start)
> > > {
> > > + const struct intel_crtc_state *old_crtc_state =
> > > + intel_atomic_get_old_crtc_state(state, crtc);
> > > const struct intel_crtc_state *new_crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > > - const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> > > + const struct intel_crtc_state *crtc_state;
> > > + const struct drm_display_mode *adjusted_mode;
> > >
> > > - if (new_crtc_state->vrr.enable) {
> > > - if (intel_vrr_is_push_sent(new_crtc_state))
> > > - *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
> > > + /*
> > > + * During fastsets/etc. the transcoder is still
> > > + * running with the old timings at this point.
> > > + *
> > > + * TODO: maybe just use the active timings here?
> > > + */
> > > + if (intel_crtc_needs_modeset(new_crtc_state))
> > > + crtc_state = new_crtc_state;
> > > + else
> > > + crtc_state = old_crtc_state;
> > > +
> > > + adjusted_mode = &crtc_state->hw.adjusted_mode;
> > > +
> > > + if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> > > + if (intel_vrr_is_push_sent(crtc_state))
> > > + *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> > > else
> > > - *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
> > > + *vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
> > > } else {
> > > *vblank_start = intel_mode_vblank_start(adjusted_mode);
> > > }
> > > @@ -710,15 +726,6 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
> > > */
> > > intel_vrr_send_push(new_crtc_state);
> > >
> > > - /*
> > > - * Seamless M/N update may need to update frame timings.
> > > - *
> > > - * FIXME Should be synchronized with the start of vblank somehow...
> > > - */
> > > - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
> > > - intel_crtc_update_active_timings(new_crtc_state,
> > > - new_crtc_state->vrr.enable);
> > > -
> > > local_irq_enable();
> > >
> > > if (intel_vgpu_active(dev_priv))
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index cfad967b5684..632f1f58df9e 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -6476,6 +6476,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> > > struct intel_crtc *crtc)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > + const struct intel_crtc_state *old_crtc_state =
> > > + intel_atomic_get_old_crtc_state(state, crtc);
> > > const struct intel_crtc_state *new_crtc_state =
> > > intel_atomic_get_new_crtc_state(state, crtc);
> > >
> > > @@ -6487,6 +6489,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> > > if (DISPLAY_VER(dev_priv) >= 9 &&
> > > !intel_crtc_needs_modeset(new_crtc_state))
> > > skl_detach_scalers(new_crtc_state);
> > > +
> > > + if (vrr_enabling(old_crtc_state, new_crtc_state))
> > > + intel_vrr_enable(new_crtc_state);
> >
> > Wouldnt we also need the condition here:
> > new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
>
> That is handled elsewhere already.
>
> >
> > So that we update VRR enable bit in the seamless_m_n fastset case as well.
> > This will be needed later once we start updating the VRR params regs
> > in fastset, since
> > that otherwise ends up resetting VRR enable bit.
> >
> >
> >
> > > }
> > >
> > > static void intel_enable_crtc(struct intel_atomic_state *state,
> > > @@ -6527,12 +6532,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > > intel_dpt_configure(crtc);
> > > }
> > >
> > > - if (vrr_enabling(old_crtc_state, new_crtc_state)) {
> > > - intel_vrr_enable(new_crtc_state);
> > > - intel_crtc_update_active_timings(new_crtc_state,
> > > - new_crtc_state->vrr.enable);
> > > - }
> > > -
> > > if (!modeset) {
> > > if (new_crtc_state->preload_luts &&
> > > intel_crtc_needs_color_update(new_crtc_state))
> > > @@ -6569,6 +6568,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > >
> > > intel_pipe_update_end(state, crtc);
> > >
> > > + /*
> > > + * VRR/Seamless M/N update may need to update frame timings.
> > > + *
> > > + * FIXME Should be synchronized with the start of vblank somehow...
> > > + */
> > > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > + (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
> > > + intel_crtc_update_active_timings(new_crtc_state,
> > > + new_crtc_state->vrr.enable);
> > > +
> >
> > So would the VRR min/max, flipline values also be updated here
> > eventually for the fastset in seamless_m_n case?
>
> No, it would be done earlier. Should be OK to do anywhere
> between the VRR disable and enable really. Doesn't even need
> to be inside the vblank evade critical section since VRR will
> already have been disabled when we change these.
Thanks Ville for the clarification.
So when you mean by then the VRR would already be disabled in vblank
evade, you are saying
that vblank would have already terminated as per the flipline value?
With fastset we will only call update_crtc(), where do you think we
can update the transcode timings
to update the VRR parameters?
I guess we can update those up right before enabling VRR?
so have a condition like if (vrr_enabling || (seamless_m_n && fastset
&& vrr_params_changed)) : Update VRR params
Manasi
>
> >
> > Manasi
> >
> >
> > > /*
> > > * We usually enable FIFO underrun interrupts as part of the
> > > * CRTC enable sequence during modesets. But when we inherit a
> > > --
> > > 2.41.0
> > >
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets
2023-08-29 14:58 ` Manasi Navare
@ 2023-08-30 5:12 ` Ville Syrjälä
0 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjälä @ 2023-08-30 5:12 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Tue, Aug 29, 2023 at 07:58:18AM -0700, Manasi Navare wrote:
> On Tue, Aug 29, 2023 at 1:26 AM Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> >
> > On Mon, Aug 28, 2023 at 11:47:49AM -0700, Manasi Navare wrote:
> > > On Sun, Aug 27, 2023 at 10:41 PM Ville Syrjala
> > > <ville.syrjala@linux.intel.com> wrote:
> > > >
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > In order to reconcile seamless M/N updates with VRR we'll
> > > > need to defer the fastset VRR enable to happen after the
> > > > seamless M/N update (which happens during the vblank evade
> > > > critical section). So just push the VRR enable to be the last
> > > > thing during the update.
> > > >
> > > > This will also affect the vblank evasion as the transcoder
> > > > will now still be running with the old VRR state during
> > > > the vblank evasion. So just grab the timings always from the
> > > > old crtc state during any non-modeset commit, and also grab
> > > > the current state of VRR from the active timings (as we disable
> > > > VRR before vblank evasion during fastsets).
> > > >
> > > > This also fixes vblank evasion for seamless M/N updates as
> > > > we now properly account for the fact that the M/N update
> > > > happens after vblank evasion.
> > > >
> > > > Cc: Manasi Navare <navaremanasi@chromium.org>
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_crtc.c | 35 ++++++++++++--------
> > > > drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++----
> > > > 2 files changed, 36 insertions(+), 20 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > index e46a15d59d79..1992e7060263 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > @@ -472,15 +472,31 @@ static void intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> > > > struct intel_crtc *crtc,
> > > > int *min, int *max, int *vblank_start)
> > > > {
> > > > + const struct intel_crtc_state *old_crtc_state =
> > > > + intel_atomic_get_old_crtc_state(state, crtc);
> > > > const struct intel_crtc_state *new_crtc_state =
> > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > > - const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode;
> > > > + const struct intel_crtc_state *crtc_state;
> > > > + const struct drm_display_mode *adjusted_mode;
> > > >
> > > > - if (new_crtc_state->vrr.enable) {
> > > > - if (intel_vrr_is_push_sent(new_crtc_state))
> > > > - *vblank_start = intel_vrr_vmin_vblank_start(new_crtc_state);
> > > > + /*
> > > > + * During fastsets/etc. the transcoder is still
> > > > + * running with the old timings at this point.
> > > > + *
> > > > + * TODO: maybe just use the active timings here?
> > > > + */
> > > > + if (intel_crtc_needs_modeset(new_crtc_state))
> > > > + crtc_state = new_crtc_state;
> > > > + else
> > > > + crtc_state = old_crtc_state;
> > > > +
> > > > + adjusted_mode = &crtc_state->hw.adjusted_mode;
> > > > +
> > > > + if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> > > > + if (intel_vrr_is_push_sent(crtc_state))
> > > > + *vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> > > > else
> > > > - *vblank_start = intel_vrr_vmax_vblank_start(new_crtc_state);
> > > > + *vblank_start = intel_vrr_vmax_vblank_start(crtc_state);
> > > > } else {
> > > > *vblank_start = intel_mode_vblank_start(adjusted_mode);
> > > > }
> > > > @@ -710,15 +726,6 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
> > > > */
> > > > intel_vrr_send_push(new_crtc_state);
> > > >
> > > > - /*
> > > > - * Seamless M/N update may need to update frame timings.
> > > > - *
> > > > - * FIXME Should be synchronized with the start of vblank somehow...
> > > > - */
> > > > - if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
> > > > - intel_crtc_update_active_timings(new_crtc_state,
> > > > - new_crtc_state->vrr.enable);
> > > > -
> > > > local_irq_enable();
> > > >
> > > > if (intel_vgpu_active(dev_priv))
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index cfad967b5684..632f1f58df9e 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -6476,6 +6476,8 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> > > > struct intel_crtc *crtc)
> > > > {
> > > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > > + const struct intel_crtc_state *old_crtc_state =
> > > > + intel_atomic_get_old_crtc_state(state, crtc);
> > > > const struct intel_crtc_state *new_crtc_state =
> > > > intel_atomic_get_new_crtc_state(state, crtc);
> > > >
> > > > @@ -6487,6 +6489,9 @@ static void commit_pipe_post_planes(struct intel_atomic_state *state,
> > > > if (DISPLAY_VER(dev_priv) >= 9 &&
> > > > !intel_crtc_needs_modeset(new_crtc_state))
> > > > skl_detach_scalers(new_crtc_state);
> > > > +
> > > > + if (vrr_enabling(old_crtc_state, new_crtc_state))
> > > > + intel_vrr_enable(new_crtc_state);
> > >
> > > Wouldnt we also need the condition here:
> > > new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))
> >
> > That is handled elsewhere already.
> >
> > >
> > > So that we update VRR enable bit in the seamless_m_n fastset case as well.
> > > This will be needed later once we start updating the VRR params regs
> > > in fastset, since
> > > that otherwise ends up resetting VRR enable bit.
> > >
> > >
> > >
> > > > }
> > > >
> > > > static void intel_enable_crtc(struct intel_atomic_state *state,
> > > > @@ -6527,12 +6532,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > > > intel_dpt_configure(crtc);
> > > > }
> > > >
> > > > - if (vrr_enabling(old_crtc_state, new_crtc_state)) {
> > > > - intel_vrr_enable(new_crtc_state);
> > > > - intel_crtc_update_active_timings(new_crtc_state,
> > > > - new_crtc_state->vrr.enable);
> > > > - }
> > > > -
> > > > if (!modeset) {
> > > > if (new_crtc_state->preload_luts &&
> > > > intel_crtc_needs_color_update(new_crtc_state))
> > > > @@ -6569,6 +6568,16 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> > > >
> > > > intel_pipe_update_end(state, crtc);
> > > >
> > > > + /*
> > > > + * VRR/Seamless M/N update may need to update frame timings.
> > > > + *
> > > > + * FIXME Should be synchronized with the start of vblank somehow...
> > > > + */
> > > > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > + (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state)))
> > > > + intel_crtc_update_active_timings(new_crtc_state,
> > > > + new_crtc_state->vrr.enable);
> > > > +
> > >
> > > So would the VRR min/max, flipline values also be updated here
> > > eventually for the fastset in seamless_m_n case?
> >
> > No, it would be done earlier. Should be OK to do anywhere
> > between the VRR disable and enable really. Doesn't even need
> > to be inside the vblank evade critical section since VRR will
> > already have been disabled when we change these.
>
> Thanks Ville for the clarification.
> So when you mean by then the VRR would already be disabled in vblank
> evade, you are saying
> that vblank would have already terminated as per the flipline value?
No, I mean we've already called intel_vrr_disable() so VRR is
actually disabled.
>
> With fastset we will only call update_crtc(), where do you think we
> can update the transcode timings
> to update the VRR parameters?
> I guess we can update those up right before enabling VRR?
> so have a condition like if (vrr_enabling || (seamless_m_n && fastset
> && vrr_params_changed)) : Update VRR params
It should go into the !modeset path in intel_update_crtc(),
after the intel_pre_plane_update() (which is where the VRR
disable will happen).
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour
2023-08-29 13:48 ` Golani, Mitulkumar Ajitkumar
@ 2023-08-30 5:16 ` Ville Syrjälä
2023-08-30 6:51 ` Golani, Mitulkumar Ajitkumar
0 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjälä @ 2023-08-30 5:16 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar; +Cc: intel-gfx@lists.freedesktop.org
On Tue, Aug 29, 2023 at 01:48:18PM +0000, Golani, Mitulkumar Ajitkumar wrote:
> Hi Ville,
>
> Thanks for the inputs.
>
> I encountered an interesting observation while validating the changes.
> In scenarios where VRR is by default ON from the panel, I noticed that during the first-time enabling of VRR, a full modeset is required due to a fastset requirement mismatch, as indicated in the logs.
Which logs?
> However, I also observed that after this, the function intel_crtc_needs_modeset returns 0, which typically implies a fastset operation.
Any fastset always starts out as a full modeset, it will then be
promoted (or demoted?) to a fastset by intel_crtc_check_fastset()
if possible.
>
> Considering that both conditions can't hold simultaneously, there seems to be an inconsistency with underrun errors.
> Could you kindly shed some light on this situation? I'm trying to align the log messages with the observed behavior and the function's return value.
>
> Your insights would be greatly appreciated.
>
> Regards,
> Mitul
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: 29 August 2023 13:51
> > To: Golani, Mitulkumar Ajitkumar
> > <mitulkumar.ajitkumar.golani@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> > behaviour
> >
> > On Mon, Aug 28, 2023 at 04:58:49PM +0000, Golani, Mitulkumar Ajitkumar
> > wrote:
> > > Hi Ville,
> > >
> > > > -----Original Message-----
> > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> > > > Of Ville Syrjala
> > > > Sent: 28 August 2023 11:12
> > > > To: intel-gfx@lists.freedesktop.org
> > > > Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> > > > behaviour
> > > >
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >
> > > > Make the seamless_m_n flag more like the update_pipe fastset flag,
> > > > ie. the flag will only be set if we need to do the seamless M/N
> > > > update, and in all other cases the flag is cleared. Also rename the
> > > > flag to update_m_n to make it more clear it's similar to update_pipe.
> > > >
> > > > I believe special casing seamless_m_n like this makes sense as it
> > > > also affects eg. vblank evasion. We can potentially avoid some
> > > > vblank evasion tricks, simplify some checks, and hopefully will help with
> > the VRR vs. M/N mess.
> > > >
> > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > > > drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> > > > drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++--------
> > > > .../drm/i915/display/intel_display_types.h | 2 +-
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > > 5 files changed, 17 insertions(+), 12 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > index 7cf51dd8c056..aaddd8c0cfa0 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > @@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
> > > > drm_property_blob_get(crtc_state->post_csc_lut);
> > > >
> > > > crtc_state->update_pipe = false;
> > > > + crtc_state->update_m_n = false;
> > > > crtc_state->disable_lp_wm = false;
> > > > crtc_state->disable_cxsr = false;
> > > > crtc_state->update_wm_pre = false; diff --git
> > > > a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > index 1992e7060263..a04076064f02 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > @@ -510,7 +510,7 @@ static void
> > > > intel_crtc_vblank_evade_scanlines(struct
> > > > intel_atomic_state *state,
> > > > * M/N is double buffered on the transcoder's undelayed vblank,
> > > > * so with seamless M/N we must evade both vblanks.
> > > > */
> > > > - if (new_crtc_state->seamless_m_n &&
> > > > intel_crtc_needs_fastset(new_crtc_state))
> > > > + if (new_crtc_state->update_m_n)
> > > > *min -= adjusted_mode->crtc_vblank_start -
> > > > adjusted_mode->crtc_vdisplay; }
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > index 632f1f58df9e..6196ef76390b 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > @@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const struct
> > > > intel_crtc_state *current_config,
> > > > PIPE_CONF_CHECK_X(lane_lat_optim_mask);
> > > >
> > > > if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
> > > > - if (!fastset || !pipe_config->seamless_m_n)
> > > > + if (!fastset || !pipe_config->update_m_n)
> > > > PIPE_CONF_CHECK_M_N(dp_m_n);
> > > > } else {
> > > > PIPE_CONF_CHECK_M_N(dp_m_n);
> > > > @@ -5307,7 +5307,7 @@ intel_pipe_config_compare(const struct
> > > > intel_crtc_state *current_config,
> > > > if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> > > > PIPE_CONF_CHECK_I(pipe_bpp);
> > > >
> > > > - if (!fastset || !pipe_config->seamless_m_n) {
> > > > + if (!fastset || !pipe_config->update_m_n) {
> > > > PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> > > > PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> > > > }
> > > > @@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct
> > > > intel_atomic_state *state,
> > > >
> > > > crtc_state->uapi.mode_changed = true;
> > > > crtc_state->update_pipe = false;
> > > > + crtc_state->update_m_n = false;
> > > >
> > > > ret = drm_atomic_add_affected_connectors(&state->base,
> > > > &crtc->base);
> > > > @@ -5519,13 +5520,14 @@ static void intel_crtc_check_fastset(const
> > > > struct intel_crtc_state *old_crtc_sta {
> > > > struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc-
> > > > >dev);
> > > >
> > > > - if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state,
> > > > true)) {
> > > > + if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state,
> > > > true))
> > > > drm_dbg_kms(&i915->drm, "fastset requirement not met,
> > forcing
> > > > full modeset\n");
> > > > + else
> > > > + new_crtc_state->uapi.mode_changed = false;
> > > >
> > > > - return;
> > > > - }
> > > > + if (intel_crtc_needs_modeset(new_crtc_state))
> > > > + new_crtc_state->update_m_n = false;
> > > >
> > > > - new_crtc_state->uapi.mode_changed = false;
> > > > if (!intel_crtc_needs_modeset(new_crtc_state))
> > > > new_crtc_state->update_pipe = true; } @@ -6240,6 +6242,7
> > @@ int
> > > > intel_atomic_check(struct drm_device *dev,
> > > > if (intel_cpu_transcoders_need_modeset(state,
> > > > BIT(master))) {
> > > > new_crtc_state->uapi.mode_changed = true;
> > > > new_crtc_state->update_pipe = false;
> > > > + new_crtc_state->update_m_n = false;
> > > > }
> > > > }
> > > >
> > > > @@ -6252,6 +6255,7 @@ int intel_atomic_check(struct drm_device
> > *dev,
> > > > if (intel_cpu_transcoders_need_modeset(state,
> > > > trans)) {
> > > > new_crtc_state->uapi.mode_changed = true;
> > > > new_crtc_state->update_pipe = false;
> > > > + new_crtc_state->update_m_n = false;
> > > > }
> > > > }
> > > >
> > > > @@ -6259,6 +6263,7 @@ int intel_atomic_check(struct drm_device
> > *dev,
> > > > if (intel_pipes_need_modeset(state, new_crtc_state-
> > > > >bigjoiner_pipes)) {
> > > > new_crtc_state->uapi.mode_changed = true;
> > > > new_crtc_state->update_pipe = false;
> > > > + new_crtc_state->update_m_n = false;
> > > > }
> > > > }
> > > > }
> > > > @@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const struct
> > > > intel_crtc_state *old_crtc_state,
> > > > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > > > hsw_set_linetime_wm(new_crtc_state);
> > > >
> > > > - if (new_crtc_state->seamless_m_n)
> > > > + if (new_crtc_state->update_m_n)
> > > > intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state-
> > > > >cpu_transcoder,
> > > > &new_crtc_state->dp_m_n); }
> > @@ -6573,8 +6578,7 @@
> > > > static void intel_update_crtc(struct intel_atomic_state *state,
> > > > *
> > > > * FIXME Should be synchronized with the start of vblank
> > > > somehow...
> > > > */
> > > > - if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > - (new_crtc_state->seamless_m_n &&
> > > > intel_crtc_needs_fastset(new_crtc_state)))
> > > > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > +new_crtc_state->update_m_n)
> > > > intel_crtc_update_active_timings(new_crtc_state,
> > > > new_crtc_state->vrr.enable);
> > >
> > > In the context where a Push has already been sent, should the update
> > occur when we enable VRR itself? I'm curious about the rationale for not
> > updating it immediately upon enabling VRR.
> >
> > The active timings should really be updated synchronously with the
> > hardware latching the new values. But that is actually impossible so some
> > race conditions will always remain.
> >
> > I haven't actually verified how the hardware behaves when we enable VRR.
> > I assume the VRR_CTL will get latched at the next start of vblank as well.
> > But we should really try to confirm that on actual hardware.
> >
> > The case where we have VRR already enabled while updating M/N might go
> > badly with the current order of doing things as the vblank irq may trigger
> > immediately upon push. So for that case it would be better to update the
> > active timings before the push. Or perhaps we should just make sure VRR is
> > always disabled around M/N updates...
> >
> > >
> > > Regards,
> > > Mitul
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 731f2ec04d5c..2367b030b469 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1083,6 +1083,7 @@ struct intel_crtc_state {
> > > >
> > > > unsigned fb_bits; /* framebuffers to flip */
> > > > bool update_pipe; /* can a fast modeset be performed? */
> > > > + bool update_m_n; /* update M/N seamlessly during fastset? */
> > > > bool disable_cxsr;
> > > > bool update_wm_pre, update_wm_post; /* watermarks are
> > updated */
> > > > bool fifo_changed; /* FIFO split is changed */ @@ -1195,7 +1196,6
> > > > @@ struct intel_crtc_state {
> > > > /* m2_n2 for eDP downclock */
> > > > struct intel_link_m_n dp_m2_n2;
> > > > bool has_drrs;
> > > > - bool seamless_m_n;
> > > >
> > > > /* PSR is supported but might not be enabled due the lack of
> > > > enabled planes */
> > > > bool has_psr;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 05694e0b6143..ceab5b26b5e8 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -2535,7 +2535,7 @@ intel_dp_drrs_compute_config(struct
> > > > intel_connector *connector,
> > > > int pixel_clock;
> > > >
> > > > if (has_seamless_m_n(connector))
> > > > - pipe_config->seamless_m_n = true;
> > > > + pipe_config->update_m_n = true;
> > > >
> > > > if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
> > > > if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config-
> > > > >cpu_transcoder))
> > > > --
> > > > 2.41.0
> > >
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour
2023-08-30 5:16 ` Ville Syrjälä
@ 2023-08-30 6:51 ` Golani, Mitulkumar Ajitkumar
2023-08-30 6:58 ` Ville Syrjälä
0 siblings, 1 reply; 27+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-08-30 6:51 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx@lists.freedesktop.org
Hi Ville,
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: 30 August 2023 10:47
> To: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> behaviour
>
> On Tue, Aug 29, 2023 at 01:48:18PM +0000, Golani, Mitulkumar Ajitkumar
> wrote:
> > Hi Ville,
> >
> > Thanks for the inputs.
> >
> > I encountered an interesting observation while validating the changes.
> > In scenarios where VRR is by default ON from the panel, I noticed that
> during the first-time enabling of VRR, a full modeset is required due to a
> fastset requirement mismatch, as indicated in the logs.
>
> Which logs?
>
> > However, I also observed that after this, the function
> intel_crtc_needs_modeset returns 0, which typically implies a fastset
> operation.
>
> Any fastset always starts out as a full modeset, it will then be promoted (or
> demoted?) to a fastset by intel_crtc_check_fastset() if possible.
>
Thank you for your explanation. Considering the underrun issues observed during validation,
it seems plausible that for the initial computation of VRR parameters, a full modeset might be required
to ensure the accurate establishment of the baseline configuration. I appreciate your insight on this matter.
Regards,
Mitul
> >
> > Considering that both conditions can't hold simultaneously, there seems
> to be an inconsistency with underrun errors.
> > Could you kindly shed some light on this situation? I'm trying to align the
> log messages with the observed behavior and the function's return value.
> >
> > Your insights would be greatly appreciated.
> >
> > Regards,
> > Mitul
> >
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Sent: 29 August 2023 13:51
> > > To: Golani, Mitulkumar Ajitkumar
> > > <mitulkumar.ajitkumar.golani@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org
> > > Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n
> > > flag behaviour
> > >
> > > On Mon, Aug 28, 2023 at 04:58:49PM +0000, Golani, Mitulkumar
> > > Ajitkumar
> > > wrote:
> > > > Hi Ville,
> > > >
> > > > > -----Original Message-----
> > > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On
> > > > > Behalf Of Ville Syrjala
> > > > > Sent: 28 August 2023 11:12
> > > > > To: intel-gfx@lists.freedesktop.org
> > > > > Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n
> > > > > flag behaviour
> > > > >
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > >
> > > > > Make the seamless_m_n flag more like the update_pipe fastset
> > > > > flag, ie. the flag will only be set if we need to do the
> > > > > seamless M/N update, and in all other cases the flag is cleared.
> > > > > Also rename the flag to update_m_n to make it more clear it's
> similar to update_pipe.
> > > > >
> > > > > I believe special casing seamless_m_n like this makes sense as
> > > > > it also affects eg. vblank evasion. We can potentially avoid
> > > > > some vblank evasion tricks, simplify some checks, and hopefully
> > > > > will help with
> > > the VRR vs. M/N mess.
> > > > >
> > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > > > > drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> > > > > drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++------
> --
> > > > > .../drm/i915/display/intel_display_types.h | 2 +-
> > > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > > > 5 files changed, 17 insertions(+), 12 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > index 7cf51dd8c056..aaddd8c0cfa0 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > @@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc
> *crtc)
> > > > > drm_property_blob_get(crtc_state->post_csc_lut);
> > > > >
> > > > > crtc_state->update_pipe = false;
> > > > > + crtc_state->update_m_n = false;
> > > > > crtc_state->disable_lp_wm = false;
> > > > > crtc_state->disable_cxsr = false;
> > > > > crtc_state->update_wm_pre = false; diff --git
> > > > > a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > index 1992e7060263..a04076064f02 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > @@ -510,7 +510,7 @@ static void
> > > > > intel_crtc_vblank_evade_scanlines(struct
> > > > > intel_atomic_state *state,
> > > > > * M/N is double buffered on the transcoder's undelayed
> vblank,
> > > > > * so with seamless M/N we must evade both vblanks.
> > > > > */
> > > > > - if (new_crtc_state->seamless_m_n &&
> > > > > intel_crtc_needs_fastset(new_crtc_state))
> > > > > + if (new_crtc_state->update_m_n)
> > > > > *min -= adjusted_mode->crtc_vblank_start -
> > > > > adjusted_mode->crtc_vdisplay; }
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > index 632f1f58df9e..6196ef76390b 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > @@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const struct
> > > > > intel_crtc_state *current_config,
> > > > > PIPE_CONF_CHECK_X(lane_lat_optim_mask);
> > > > >
> > > > > if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
> > > > > - if (!fastset || !pipe_config->seamless_m_n)
> > > > > + if (!fastset || !pipe_config->update_m_n)
> > > > > PIPE_CONF_CHECK_M_N(dp_m_n);
> > > > > } else {
> > > > > PIPE_CONF_CHECK_M_N(dp_m_n);
> > > > > @@ -5307,7 +5307,7 @@ intel_pipe_config_compare(const struct
> > > > > intel_crtc_state *current_config,
> > > > > if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> > > > > PIPE_CONF_CHECK_I(pipe_bpp);
> > > > >
> > > > > - if (!fastset || !pipe_config->seamless_m_n) {
> > > > > + if (!fastset || !pipe_config->update_m_n) {
> > > > > PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> > > > > PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> > > > > }
> > > > > @@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct
> > > > > intel_atomic_state *state,
> > > > >
> > > > > crtc_state->uapi.mode_changed = true;
> > > > > crtc_state->update_pipe = false;
> > > > > + crtc_state->update_m_n = false;
> > > > >
> > > > > ret = drm_atomic_add_affected_connectors(&state-
> >base,
> > > > > &crtc->base);
> > > > > @@ -5519,13 +5520,14 @@ static void
> > > > > intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta {
> > > > > struct drm_i915_private *i915 =
> > > > > to_i915(old_crtc_state->uapi.crtc-
> > > > > >dev);
> > > > >
> > > > > - if (!intel_pipe_config_compare(old_crtc_state,
> new_crtc_state,
> > > > > true)) {
> > > > > + if (!intel_pipe_config_compare(old_crtc_state,
> new_crtc_state,
> > > > > true))
> > > > > drm_dbg_kms(&i915->drm, "fastset requirement not
> met,
> > > forcing
> > > > > full modeset\n");
> > > > > + else
> > > > > + new_crtc_state->uapi.mode_changed = false;
> > > > >
> > > > > - return;
> > > > > - }
> > > > > + if (intel_crtc_needs_modeset(new_crtc_state))
> > > > > + new_crtc_state->update_m_n = false;
> > > > >
> > > > > - new_crtc_state->uapi.mode_changed = false;
> > > > > if (!intel_crtc_needs_modeset(new_crtc_state))
> > > > > new_crtc_state->update_pipe = true; } @@ -6240,6
> +6242,7
> > > @@ int
> > > > > intel_atomic_check(struct drm_device *dev,
> > > > > if
> (intel_cpu_transcoders_need_modeset(state,
> > > > > BIT(master))) {
> > > > > new_crtc_state-
> >uapi.mode_changed = true;
> > > > > new_crtc_state->update_pipe =
> false;
> > > > > + new_crtc_state->update_m_n =
> false;
> > > > > }
> > > > > }
> > > > >
> > > > > @@ -6252,6 +6255,7 @@ int intel_atomic_check(struct drm_device
> > > *dev,
> > > > > if
> (intel_cpu_transcoders_need_modeset(state,
> > > > > trans)) {
> > > > > new_crtc_state-
> >uapi.mode_changed = true;
> > > > > new_crtc_state->update_pipe =
> false;
> > > > > + new_crtc_state->update_m_n =
> false;
> > > > > }
> > > > > }
> > > > >
> > > > > @@ -6259,6 +6263,7 @@ int intel_atomic_check(struct drm_device
> > > *dev,
> > > > > if (intel_pipes_need_modeset(state,
> new_crtc_state-
> > > > > >bigjoiner_pipes)) {
> > > > > new_crtc_state-
> >uapi.mode_changed = true;
> > > > > new_crtc_state->update_pipe =
> false;
> > > > > + new_crtc_state->update_m_n =
> false;
> > > > > }
> > > > > }
> > > > > }
> > > > > @@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const
> > > > > struct intel_crtc_state *old_crtc_state,
> > > > > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > > > > hsw_set_linetime_wm(new_crtc_state);
> > > > >
> > > > > - if (new_crtc_state->seamless_m_n)
> > > > > + if (new_crtc_state->update_m_n)
> > > > > intel_cpu_transcoder_set_m1_n1(crtc,
> new_crtc_state-
> > > > > >cpu_transcoder,
> > > > > &new_crtc_state-
> >dp_m_n); }
> > > @@ -6573,8 +6578,7 @@
> > > > > static void intel_update_crtc(struct intel_atomic_state *state,
> > > > > *
> > > > > * FIXME Should be synchronized with the start of vblank
> > > > > somehow...
> > > > > */
> > > > > - if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > > - (new_crtc_state->seamless_m_n &&
> > > > > intel_crtc_needs_fastset(new_crtc_state)))
> > > > > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > > +new_crtc_state->update_m_n)
> > > > > intel_crtc_update_active_timings(new_crtc_state,
> > > > > new_crtc_state-
> >vrr.enable);
> > > >
> > > > In the context where a Push has already been sent, should the
> > > > update
> > > occur when we enable VRR itself? I'm curious about the rationale for
> > > not updating it immediately upon enabling VRR.
> > >
> > > The active timings should really be updated synchronously with the
> > > hardware latching the new values. But that is actually impossible so
> > > some race conditions will always remain.
> > >
> > > I haven't actually verified how the hardware behaves when we enable
> VRR.
> > > I assume the VRR_CTL will get latched at the next start of vblank as well.
> > > But we should really try to confirm that on actual hardware.
> > >
> > > The case where we have VRR already enabled while updating M/N might
> > > go badly with the current order of doing things as the vblank irq
> > > may trigger immediately upon push. So for that case it would be
> > > better to update the active timings before the push. Or perhaps we
> > > should just make sure VRR is always disabled around M/N updates...
> > >
> > > >
> > > > Regards,
> > > > Mitul
> > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index 731f2ec04d5c..2367b030b469 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > @@ -1083,6 +1083,7 @@ struct intel_crtc_state {
> > > > >
> > > > > unsigned fb_bits; /* framebuffers to flip */
> > > > > bool update_pipe; /* can a fast modeset be performed? */
> > > > > + bool update_m_n; /* update M/N seamlessly during
> fastset? */
> > > > > bool disable_cxsr;
> > > > > bool update_wm_pre, update_wm_post; /* watermarks are
> > > updated */
> > > > > bool fifo_changed; /* FIFO split is changed */ @@ -1195,7
> > > > > +1196,6 @@ struct intel_crtc_state {
> > > > > /* m2_n2 for eDP downclock */
> > > > > struct intel_link_m_n dp_m2_n2;
> > > > > bool has_drrs;
> > > > > - bool seamless_m_n;
> > > > >
> > > > > /* PSR is supported but might not be enabled due the lack
> of
> > > > > enabled planes */
> > > > > bool has_psr;
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > index 05694e0b6143..ceab5b26b5e8 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > @@ -2535,7 +2535,7 @@ intel_dp_drrs_compute_config(struct
> > > > > intel_connector *connector,
> > > > > int pixel_clock;
> > > > >
> > > > > if (has_seamless_m_n(connector))
> > > > > - pipe_config->seamless_m_n = true;
> > > > > + pipe_config->update_m_n = true;
> > > > >
> > > > > if (!can_enable_drrs(connector, pipe_config,
> downclock_mode)) {
> > > > > if (intel_cpu_transcoder_has_m2_n2(i915,
> pipe_config-
> > > > > >cpu_transcoder))
> > > > > --
> > > > > 2.41.0
> > > >
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour
2023-08-30 6:51 ` Golani, Mitulkumar Ajitkumar
@ 2023-08-30 6:58 ` Ville Syrjälä
2023-08-30 7:32 ` Golani, Mitulkumar Ajitkumar
0 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjälä @ 2023-08-30 6:58 UTC (permalink / raw)
To: Golani, Mitulkumar Ajitkumar; +Cc: intel-gfx@lists.freedesktop.org
On Wed, Aug 30, 2023 at 06:51:25AM +0000, Golani, Mitulkumar Ajitkumar wrote:
> Hi Ville,
>
> > -----Original Message-----
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Sent: 30 August 2023 10:47
> > To: Golani, Mitulkumar Ajitkumar
> > <mitulkumar.ajitkumar.golani@intel.com>
> > Cc: intel-gfx@lists.freedesktop.org
> > Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> > behaviour
> >
> > On Tue, Aug 29, 2023 at 01:48:18PM +0000, Golani, Mitulkumar Ajitkumar
> > wrote:
> > > Hi Ville,
> > >
> > > Thanks for the inputs.
> > >
> > > I encountered an interesting observation while validating the changes.
> > > In scenarios where VRR is by default ON from the panel, I noticed that
> > during the first-time enabling of VRR, a full modeset is required due to a
> > fastset requirement mismatch, as indicated in the logs.
> >
> > Which logs?
> >
> > > However, I also observed that after this, the function
> > intel_crtc_needs_modeset returns 0, which typically implies a fastset
> > operation.
> >
> > Any fastset always starts out as a full modeset, it will then be promoted (or
> > demoted?) to a fastset by intel_crtc_check_fastset() if possible.
> >
>
> Thank you for your explanation. Considering the underrun issues observed during validation,
> it seems plausible that for the initial computation of VRR parameters, a full modeset might be required
> to ensure the accurate establishment of the baseline configuration. I appreciate your insight on this matter.
Are you saying that these patches alone are causing
underruns when enabling VRR?
>
> Regards,
> Mitul
>
> > >
> > > Considering that both conditions can't hold simultaneously, there seems
> > to be an inconsistency with underrun errors.
> > > Could you kindly shed some light on this situation? I'm trying to align the
> > log messages with the observed behavior and the function's return value.
> > >
> > > Your insights would be greatly appreciated.
> > >
> > > Regards,
> > > Mitul
> > >
> > > > -----Original Message-----
> > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Sent: 29 August 2023 13:51
> > > > To: Golani, Mitulkumar Ajitkumar
> > > > <mitulkumar.ajitkumar.golani@intel.com>
> > > > Cc: intel-gfx@lists.freedesktop.org
> > > > Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n
> > > > flag behaviour
> > > >
> > > > On Mon, Aug 28, 2023 at 04:58:49PM +0000, Golani, Mitulkumar
> > > > Ajitkumar
> > > > wrote:
> > > > > Hi Ville,
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On
> > > > > > Behalf Of Ville Syrjala
> > > > > > Sent: 28 August 2023 11:12
> > > > > > To: intel-gfx@lists.freedesktop.org
> > > > > > Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n
> > > > > > flag behaviour
> > > > > >
> > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > >
> > > > > > Make the seamless_m_n flag more like the update_pipe fastset
> > > > > > flag, ie. the flag will only be set if we need to do the
> > > > > > seamless M/N update, and in all other cases the flag is cleared.
> > > > > > Also rename the flag to update_m_n to make it more clear it's
> > similar to update_pipe.
> > > > > >
> > > > > > I believe special casing seamless_m_n like this makes sense as
> > > > > > it also affects eg. vblank evasion. We can potentially avoid
> > > > > > some vblank evasion tricks, simplify some checks, and hopefully
> > > > > > will help with
> > > > the VRR vs. M/N mess.
> > > > > >
> > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > ---
> > > > > > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > > > > > drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> > > > > > drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++------
> > --
> > > > > > .../drm/i915/display/intel_display_types.h | 2 +-
> > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > > > > 5 files changed, 17 insertions(+), 12 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > > index 7cf51dd8c056..aaddd8c0cfa0 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > > @@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct drm_crtc
> > *crtc)
> > > > > > drm_property_blob_get(crtc_state->post_csc_lut);
> > > > > >
> > > > > > crtc_state->update_pipe = false;
> > > > > > + crtc_state->update_m_n = false;
> > > > > > crtc_state->disable_lp_wm = false;
> > > > > > crtc_state->disable_cxsr = false;
> > > > > > crtc_state->update_wm_pre = false; diff --git
> > > > > > a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > index 1992e7060263..a04076064f02 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > @@ -510,7 +510,7 @@ static void
> > > > > > intel_crtc_vblank_evade_scanlines(struct
> > > > > > intel_atomic_state *state,
> > > > > > * M/N is double buffered on the transcoder's undelayed
> > vblank,
> > > > > > * so with seamless M/N we must evade both vblanks.
> > > > > > */
> > > > > > - if (new_crtc_state->seamless_m_n &&
> > > > > > intel_crtc_needs_fastset(new_crtc_state))
> > > > > > + if (new_crtc_state->update_m_n)
> > > > > > *min -= adjusted_mode->crtc_vblank_start -
> > > > > > adjusted_mode->crtc_vdisplay; }
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > index 632f1f58df9e..6196ef76390b 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > @@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const struct
> > > > > > intel_crtc_state *current_config,
> > > > > > PIPE_CONF_CHECK_X(lane_lat_optim_mask);
> > > > > >
> > > > > > if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
> > > > > > - if (!fastset || !pipe_config->seamless_m_n)
> > > > > > + if (!fastset || !pipe_config->update_m_n)
> > > > > > PIPE_CONF_CHECK_M_N(dp_m_n);
> > > > > > } else {
> > > > > > PIPE_CONF_CHECK_M_N(dp_m_n);
> > > > > > @@ -5307,7 +5307,7 @@ intel_pipe_config_compare(const struct
> > > > > > intel_crtc_state *current_config,
> > > > > > if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> > > > > > PIPE_CONF_CHECK_I(pipe_bpp);
> > > > > >
> > > > > > - if (!fastset || !pipe_config->seamless_m_n) {
> > > > > > + if (!fastset || !pipe_config->update_m_n) {
> > > > > > PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> > > > > > PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> > > > > > }
> > > > > > @@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct
> > > > > > intel_atomic_state *state,
> > > > > >
> > > > > > crtc_state->uapi.mode_changed = true;
> > > > > > crtc_state->update_pipe = false;
> > > > > > + crtc_state->update_m_n = false;
> > > > > >
> > > > > > ret = drm_atomic_add_affected_connectors(&state-
> > >base,
> > > > > > &crtc->base);
> > > > > > @@ -5519,13 +5520,14 @@ static void
> > > > > > intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_sta {
> > > > > > struct drm_i915_private *i915 =
> > > > > > to_i915(old_crtc_state->uapi.crtc-
> > > > > > >dev);
> > > > > >
> > > > > > - if (!intel_pipe_config_compare(old_crtc_state,
> > new_crtc_state,
> > > > > > true)) {
> > > > > > + if (!intel_pipe_config_compare(old_crtc_state,
> > new_crtc_state,
> > > > > > true))
> > > > > > drm_dbg_kms(&i915->drm, "fastset requirement not
> > met,
> > > > forcing
> > > > > > full modeset\n");
> > > > > > + else
> > > > > > + new_crtc_state->uapi.mode_changed = false;
> > > > > >
> > > > > > - return;
> > > > > > - }
> > > > > > + if (intel_crtc_needs_modeset(new_crtc_state))
> > > > > > + new_crtc_state->update_m_n = false;
> > > > > >
> > > > > > - new_crtc_state->uapi.mode_changed = false;
> > > > > > if (!intel_crtc_needs_modeset(new_crtc_state))
> > > > > > new_crtc_state->update_pipe = true; } @@ -6240,6
> > +6242,7
> > > > @@ int
> > > > > > intel_atomic_check(struct drm_device *dev,
> > > > > > if
> > (intel_cpu_transcoders_need_modeset(state,
> > > > > > BIT(master))) {
> > > > > > new_crtc_state-
> > >uapi.mode_changed = true;
> > > > > > new_crtc_state->update_pipe =
> > false;
> > > > > > + new_crtc_state->update_m_n =
> > false;
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > @@ -6252,6 +6255,7 @@ int intel_atomic_check(struct drm_device
> > > > *dev,
> > > > > > if
> > (intel_cpu_transcoders_need_modeset(state,
> > > > > > trans)) {
> > > > > > new_crtc_state-
> > >uapi.mode_changed = true;
> > > > > > new_crtc_state->update_pipe =
> > false;
> > > > > > + new_crtc_state->update_m_n =
> > false;
> > > > > > }
> > > > > > }
> > > > > >
> > > > > > @@ -6259,6 +6263,7 @@ int intel_atomic_check(struct drm_device
> > > > *dev,
> > > > > > if (intel_pipes_need_modeset(state,
> > new_crtc_state-
> > > > > > >bigjoiner_pipes)) {
> > > > > > new_crtc_state-
> > >uapi.mode_changed = true;
> > > > > > new_crtc_state->update_pipe =
> > false;
> > > > > > + new_crtc_state->update_m_n =
> > false;
> > > > > > }
> > > > > > }
> > > > > > }
> > > > > > @@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const
> > > > > > struct intel_crtc_state *old_crtc_state,
> > > > > > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > > > > > hsw_set_linetime_wm(new_crtc_state);
> > > > > >
> > > > > > - if (new_crtc_state->seamless_m_n)
> > > > > > + if (new_crtc_state->update_m_n)
> > > > > > intel_cpu_transcoder_set_m1_n1(crtc,
> > new_crtc_state-
> > > > > > >cpu_transcoder,
> > > > > > &new_crtc_state-
> > >dp_m_n); }
> > > > @@ -6573,8 +6578,7 @@
> > > > > > static void intel_update_crtc(struct intel_atomic_state *state,
> > > > > > *
> > > > > > * FIXME Should be synchronized with the start of vblank
> > > > > > somehow...
> > > > > > */
> > > > > > - if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > > > - (new_crtc_state->seamless_m_n &&
> > > > > > intel_crtc_needs_fastset(new_crtc_state)))
> > > > > > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > > > +new_crtc_state->update_m_n)
> > > > > > intel_crtc_update_active_timings(new_crtc_state,
> > > > > > new_crtc_state-
> > >vrr.enable);
> > > > >
> > > > > In the context where a Push has already been sent, should the
> > > > > update
> > > > occur when we enable VRR itself? I'm curious about the rationale for
> > > > not updating it immediately upon enabling VRR.
> > > >
> > > > The active timings should really be updated synchronously with the
> > > > hardware latching the new values. But that is actually impossible so
> > > > some race conditions will always remain.
> > > >
> > > > I haven't actually verified how the hardware behaves when we enable
> > VRR.
> > > > I assume the VRR_CTL will get latched at the next start of vblank as well.
> > > > But we should really try to confirm that on actual hardware.
> > > >
> > > > The case where we have VRR already enabled while updating M/N might
> > > > go badly with the current order of doing things as the vblank irq
> > > > may trigger immediately upon push. So for that case it would be
> > > > better to update the active timings before the push. Or perhaps we
> > > > should just make sure VRR is always disabled around M/N updates...
> > > >
> > > > >
> > > > > Regards,
> > > > > Mitul
> > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > index 731f2ec04d5c..2367b030b469 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > @@ -1083,6 +1083,7 @@ struct intel_crtc_state {
> > > > > >
> > > > > > unsigned fb_bits; /* framebuffers to flip */
> > > > > > bool update_pipe; /* can a fast modeset be performed? */
> > > > > > + bool update_m_n; /* update M/N seamlessly during
> > fastset? */
> > > > > > bool disable_cxsr;
> > > > > > bool update_wm_pre, update_wm_post; /* watermarks are
> > > > updated */
> > > > > > bool fifo_changed; /* FIFO split is changed */ @@ -1195,7
> > > > > > +1196,6 @@ struct intel_crtc_state {
> > > > > > /* m2_n2 for eDP downclock */
> > > > > > struct intel_link_m_n dp_m2_n2;
> > > > > > bool has_drrs;
> > > > > > - bool seamless_m_n;
> > > > > >
> > > > > > /* PSR is supported but might not be enabled due the lack
> > of
> > > > > > enabled planes */
> > > > > > bool has_psr;
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > index 05694e0b6143..ceab5b26b5e8 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > @@ -2535,7 +2535,7 @@ intel_dp_drrs_compute_config(struct
> > > > > > intel_connector *connector,
> > > > > > int pixel_clock;
> > > > > >
> > > > > > if (has_seamless_m_n(connector))
> > > > > > - pipe_config->seamless_m_n = true;
> > > > > > + pipe_config->update_m_n = true;
> > > > > >
> > > > > > if (!can_enable_drrs(connector, pipe_config,
> > downclock_mode)) {
> > > > > > if (intel_cpu_transcoder_has_m2_n2(i915,
> > pipe_config-
> > > > > > >cpu_transcoder))
> > > > > > --
> > > > > > 2.41.0
> > > > >
> > > >
> > > > --
> > > > Ville Syrjälä
> > > > Intel
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour
2023-08-30 6:58 ` Ville Syrjälä
@ 2023-08-30 7:32 ` Golani, Mitulkumar Ajitkumar
0 siblings, 0 replies; 27+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-08-30 7:32 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx@lists.freedesktop.org
Hi Ville,
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: 30 August 2023 12:29
> To: Golani, Mitulkumar Ajitkumar
> <mitulkumar.ajitkumar.golani@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag
> behaviour
>
> On Wed, Aug 30, 2023 at 06:51:25AM +0000, Golani, Mitulkumar Ajitkumar
> wrote:
> > Hi Ville,
> >
> > > -----Original Message-----
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Sent: 30 August 2023 10:47
> > > To: Golani, Mitulkumar Ajitkumar
> > > <mitulkumar.ajitkumar.golani@intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org
> > > Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n
> > > flag behaviour
> > >
> > > On Tue, Aug 29, 2023 at 01:48:18PM +0000, Golani, Mitulkumar
> > > Ajitkumar
> > > wrote:
> > > > Hi Ville,
> > > >
> > > > Thanks for the inputs.
> > > >
> > > > I encountered an interesting observation while validating the changes.
> > > > In scenarios where VRR is by default ON from the panel, I noticed
> > > > that
> > > during the first-time enabling of VRR, a full modeset is required
> > > due to a fastset requirement mismatch, as indicated in the logs.
> > >
> > > Which logs?
> > >
> > > > However, I also observed that after this, the function
> > > intel_crtc_needs_modeset returns 0, which typically implies a
> > > fastset operation.
> > >
> > > Any fastset always starts out as a full modeset, it will then be
> > > promoted (or
> > > demoted?) to a fastset by intel_crtc_check_fastset() if possible.
> > >
> >
> > Thank you for your explanation. Considering the underrun issues
> > observed during validation, it seems plausible that for the initial
> > computation of VRR parameters, a full modeset might be required to
> ensure the accurate establishment of the baseline configuration. I
> appreciate your insight on this matter.
>
> Are you saying that these patches alone are causing underruns when
> enabling VRR?
Currently we are getting underruns with this patch series. However this may be
exposing some other underlying problem in the driver. Which requires further investigation.
Regards,
Mitul
>
> >
> > Regards,
> > Mitul
> >
> > > >
> > > > Considering that both conditions can't hold simultaneously, there
> > > > seems
> > > to be an inconsistency with underrun errors.
> > > > Could you kindly shed some light on this situation? I'm trying to
> > > > align the
> > > log messages with the observed behavior and the function's return
> value.
> > > >
> > > > Your insights would be greatly appreciated.
> > > >
> > > > Regards,
> > > > Mitul
> > > >
> > > > > -----Original Message-----
> > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > Sent: 29 August 2023 13:51
> > > > > To: Golani, Mitulkumar Ajitkumar
> > > > > <mitulkumar.ajitkumar.golani@intel.com>
> > > > > Cc: intel-gfx@lists.freedesktop.org
> > > > > Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust
> > > > > seamless_m_n flag behaviour
> > > > >
> > > > > On Mon, Aug 28, 2023 at 04:58:49PM +0000, Golani, Mitulkumar
> > > > > Ajitkumar
> > > > > wrote:
> > > > > > Hi Ville,
> > > > > >
> > > > > > > -----Original Message-----
> > > > > > > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On
> > > > > > > Behalf Of Ville Syrjala
> > > > > > > Sent: 28 August 2023 11:12
> > > > > > > To: intel-gfx@lists.freedesktop.org
> > > > > > > Subject: [Intel-gfx] [PATCH 5/6] drm/i915: Adjust
> > > > > > > seamless_m_n flag behaviour
> > > > > > >
> > > > > > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > >
> > > > > > > Make the seamless_m_n flag more like the update_pipe fastset
> > > > > > > flag, ie. the flag will only be set if we need to do the
> > > > > > > seamless M/N update, and in all other cases the flag is cleared.
> > > > > > > Also rename the flag to update_m_n to make it more clear
> > > > > > > it's
> > > similar to update_pipe.
> > > > > > >
> > > > > > > I believe special casing seamless_m_n like this makes sense
> > > > > > > as it also affects eg. vblank evasion. We can potentially
> > > > > > > avoid some vblank evasion tricks, simplify some checks, and
> > > > > > > hopefully will help with
> > > > > the VRR vs. M/N mess.
> > > > > > >
> > > > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > > ---
> > > > > > > drivers/gpu/drm/i915/display/intel_atomic.c | 1 +
> > > > > > > drivers/gpu/drm/i915/display/intel_crtc.c | 2 +-
> > > > > > > drivers/gpu/drm/i915/display/intel_display.c | 22
> > > > > > > +++++++++++------
> > > --
> > > > > > > .../drm/i915/display/intel_display_types.h | 2 +-
> > > > > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > > > > > 5 files changed, 17 insertions(+), 12 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > > > b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > > > index 7cf51dd8c056..aaddd8c0cfa0 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > > > > > > @@ -259,6 +259,7 @@ intel_crtc_duplicate_state(struct
> > > > > > > drm_crtc
> > > *crtc)
> > > > > > > drm_property_blob_get(crtc_state->post_csc_lut);
> > > > > > >
> > > > > > > crtc_state->update_pipe = false;
> > > > > > > + crtc_state->update_m_n = false;
> > > > > > > crtc_state->disable_lp_wm = false;
> > > > > > > crtc_state->disable_cxsr = false;
> > > > > > > crtc_state->update_wm_pre = false; diff --git
> > > > > > > a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > index 1992e7060263..a04076064f02 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > > > > > > @@ -510,7 +510,7 @@ static void
> > > > > > > intel_crtc_vblank_evade_scanlines(struct
> > > > > > > intel_atomic_state *state,
> > > > > > > * M/N is double buffered on the transcoder's undelayed
> > > vblank,
> > > > > > > * so with seamless M/N we must evade both vblanks.
> > > > > > > */
> > > > > > > - if (new_crtc_state->seamless_m_n &&
> > > > > > > intel_crtc_needs_fastset(new_crtc_state))
> > > > > > > + if (new_crtc_state->update_m_n)
> > > > > > > *min -= adjusted_mode->crtc_vblank_start -
> > > > > > > adjusted_mode->crtc_vdisplay; }
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > index 632f1f58df9e..6196ef76390b 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > > > > > @@ -5170,7 +5170,7 @@ intel_pipe_config_compare(const
> struct
> > > > > > > intel_crtc_state *current_config,
> > > > > > > PIPE_CONF_CHECK_X(lane_lat_optim_mask);
> > > > > > >
> > > > > > > if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
> > > > > > > - if (!fastset || !pipe_config->seamless_m_n)
> > > > > > > + if (!fastset || !pipe_config->update_m_n)
> > > > > > > PIPE_CONF_CHECK_M_N(dp_m_n);
> > > > > > > } else {
> > > > > > > PIPE_CONF_CHECK_M_N(dp_m_n); @@ -5307,7
> +5307,7 @@
> > > > > > > intel_pipe_config_compare(const struct intel_crtc_state
> > > > > > > *current_config,
> > > > > > > if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
> > > > > > > PIPE_CONF_CHECK_I(pipe_bpp);
> > > > > > >
> > > > > > > - if (!fastset || !pipe_config->seamless_m_n) {
> > > > > > > + if (!fastset || !pipe_config->update_m_n) {
> > > > > > > PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
> > > > > > > PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
> > > > > > > }
> > > > > > > @@ -5402,6 +5402,7 @@ int intel_modeset_all_pipes(struct
> > > > > > > intel_atomic_state *state,
> > > > > > >
> > > > > > > crtc_state->uapi.mode_changed = true;
> > > > > > > crtc_state->update_pipe = false;
> > > > > > > + crtc_state->update_m_n = false;
> > > > > > >
> > > > > > > ret = drm_atomic_add_affected_connectors(&state-
> > > >base,
> > > > > > > &crtc->base);
> > > > > > > @@ -5519,13 +5520,14 @@ static void
> > > > > > > intel_crtc_check_fastset(const struct intel_crtc_state
> *old_crtc_sta {
> > > > > > > struct drm_i915_private *i915 =
> > > > > > > to_i915(old_crtc_state->uapi.crtc-
> > > > > > > >dev);
> > > > > > >
> > > > > > > - if (!intel_pipe_config_compare(old_crtc_state,
> > > new_crtc_state,
> > > > > > > true)) {
> > > > > > > + if (!intel_pipe_config_compare(old_crtc_state,
> > > new_crtc_state,
> > > > > > > true))
> > > > > > > drm_dbg_kms(&i915->drm, "fastset requirement not
> > > met,
> > > > > forcing
> > > > > > > full modeset\n");
> > > > > > > + else
> > > > > > > + new_crtc_state->uapi.mode_changed = false;
> > > > > > >
> > > > > > > - return;
> > > > > > > - }
> > > > > > > + if (intel_crtc_needs_modeset(new_crtc_state))
> > > > > > > + new_crtc_state->update_m_n = false;
> > > > > > >
> > > > > > > - new_crtc_state->uapi.mode_changed = false;
> > > > > > > if (!intel_crtc_needs_modeset(new_crtc_state))
> > > > > > > new_crtc_state->update_pipe = true; } @@ -6240,6
> > > +6242,7
> > > > > @@ int
> > > > > > > intel_atomic_check(struct drm_device *dev,
> > > > > > > if
> > > (intel_cpu_transcoders_need_modeset(state,
> > > > > > > BIT(master))) {
> > > > > > > new_crtc_state-
> > > >uapi.mode_changed = true;
> > > > > > > new_crtc_state->update_pipe =
> > > false;
> > > > > > > + new_crtc_state->update_m_n =
> > > false;
> > > > > > > }
> > > > > > > }
> > > > > > >
> > > > > > > @@ -6252,6 +6255,7 @@ int intel_atomic_check(struct
> > > > > > > drm_device
> > > > > *dev,
> > > > > > > if
> > > (intel_cpu_transcoders_need_modeset(state,
> > > > > > > trans)) {
> > > > > > > new_crtc_state-
> > > >uapi.mode_changed = true;
> > > > > > > new_crtc_state->update_pipe =
> > > false;
> > > > > > > + new_crtc_state->update_m_n =
> > > false;
> > > > > > > }
> > > > > > > }
> > > > > > >
> > > > > > > @@ -6259,6 +6263,7 @@ int intel_atomic_check(struct
> > > > > > > drm_device
> > > > > *dev,
> > > > > > > if (intel_pipes_need_modeset(state,
> > > new_crtc_state-
> > > > > > > >bigjoiner_pipes)) {
> > > > > > > new_crtc_state-
> > > >uapi.mode_changed = true;
> > > > > > > new_crtc_state->update_pipe =
> > > false;
> > > > > > > + new_crtc_state->update_m_n =
> > > false;
> > > > > > > }
> > > > > > > }
> > > > > > > }
> > > > > > > @@ -6437,7 +6442,7 @@ static void intel_pipe_fastset(const
> > > > > > > struct intel_crtc_state *old_crtc_state,
> > > > > > > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> > > > > > > hsw_set_linetime_wm(new_crtc_state);
> > > > > > >
> > > > > > > - if (new_crtc_state->seamless_m_n)
> > > > > > > + if (new_crtc_state->update_m_n)
> > > > > > > intel_cpu_transcoder_set_m1_n1(crtc,
> > > new_crtc_state-
> > > > > > > >cpu_transcoder,
> > > > > > > &new_crtc_state-
> > > >dp_m_n); }
> > > > > @@ -6573,8 +6578,7 @@
> > > > > > > static void intel_update_crtc(struct intel_atomic_state *state,
> > > > > > > *
> > > > > > > * FIXME Should be synchronized with the start of vblank
> > > > > > > somehow...
> > > > > > > */
> > > > > > > - if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > > > > - (new_crtc_state->seamless_m_n &&
> > > > > > > intel_crtc_needs_fastset(new_crtc_state)))
> > > > > > > + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> > > > > > > +new_crtc_state->update_m_n)
> > > > > > > intel_crtc_update_active_timings(new_crtc_state,
> > > > > > > new_crtc_state-
> > > >vrr.enable);
> > > > > >
> > > > > > In the context where a Push has already been sent, should the
> > > > > > update
> > > > > occur when we enable VRR itself? I'm curious about the rationale
> > > > > for not updating it immediately upon enabling VRR.
> > > > >
> > > > > The active timings should really be updated synchronously with
> > > > > the hardware latching the new values. But that is actually
> > > > > impossible so some race conditions will always remain.
> > > > >
> > > > > I haven't actually verified how the hardware behaves when we
> > > > > enable
> > > VRR.
> > > > > I assume the VRR_CTL will get latched at the next start of vblank as
> well.
> > > > > But we should really try to confirm that on actual hardware.
> > > > >
> > > > > The case where we have VRR already enabled while updating M/N
> > > > > might go badly with the current order of doing things as the
> > > > > vblank irq may trigger immediately upon push. So for that case
> > > > > it would be better to update the active timings before the push.
> > > > > Or perhaps we should just make sure VRR is always disabled around
> M/N updates...
> > > > >
> > > > > >
> > > > > > Regards,
> > > > > > Mitul
> > > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > index 731f2ec04d5c..2367b030b469 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > > @@ -1083,6 +1083,7 @@ struct intel_crtc_state {
> > > > > > >
> > > > > > > unsigned fb_bits; /* framebuffers to flip */
> > > > > > > bool update_pipe; /* can a fast modeset be performed? */
> > > > > > > + bool update_m_n; /* update M/N seamlessly during
> > > fastset? */
> > > > > > > bool disable_cxsr;
> > > > > > > bool update_wm_pre, update_wm_post; /* watermarks are
> > > > > updated */
> > > > > > > bool fifo_changed; /* FIFO split is changed */ @@ -1195,7
> > > > > > > +1196,6 @@ struct intel_crtc_state {
> > > > > > > /* m2_n2 for eDP downclock */
> > > > > > > struct intel_link_m_n dp_m2_n2;
> > > > > > > bool has_drrs;
> > > > > > > - bool seamless_m_n;
> > > > > > >
> > > > > > > /* PSR is supported but might not be enabled due the lack
> > > of
> > > > > > > enabled planes */
> > > > > > > bool has_psr;
> > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > > index 05694e0b6143..ceab5b26b5e8 100644
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > > > > @@ -2535,7 +2535,7 @@ intel_dp_drrs_compute_config(struct
> > > > > > > intel_connector *connector,
> > > > > > > int pixel_clock;
> > > > > > >
> > > > > > > if (has_seamless_m_n(connector))
> > > > > > > - pipe_config->seamless_m_n = true;
> > > > > > > + pipe_config->update_m_n = true;
> > > > > > >
> > > > > > > if (!can_enable_drrs(connector, pipe_config,
> > > downclock_mode)) {
> > > > > > > if (intel_cpu_transcoder_has_m2_n2(i915,
> > > pipe_config-
> > > > > > > >cpu_transcoder))
> > > > > > > --
> > > > > > > 2.41.0
> > > > > >
> > > > >
> > > > > --
> > > > > Ville Syrjälä
> > > > > Intel
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets
2023-08-28 5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets Ville Syrjala
2023-08-28 18:47 ` Manasi Navare
@ 2023-09-11 18:21 ` Golani, Mitulkumar Ajitkumar
1 sibling, 0 replies; 27+ messages in thread
From: Golani, Mitulkumar Ajitkumar @ 2023-09-11 18:21 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: 28 August 2023 11:12
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets
>
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In order to reconcile seamless M/N updates with VRR we'll need to defer the
> fastset VRR enable to happen after the seamless M/N update (which
> happens during the vblank evade critical section). So just push the VRR
> enable to be the last thing during the update.
>
> This will also affect the vblank evasion as the transcoder will now still be
> running with the old VRR state during the vblank evasion. So just grab the
> timings always from the old crtc state during any non-modeset commit, and
> also grab the current state of VRR from the active timings (as we disable VRR
> before vblank evasion during fastsets).
>
> This also fixes vblank evasion for seamless M/N updates as we now properly
> account for the fact that the M/N update happens after vblank evasion.
>
> Cc: Manasi Navare <navaremanasi@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 35 ++++++++++++--------
> drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++----
> 2 files changed, 36 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index e46a15d59d79..1992e7060263 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -472,15 +472,31 @@ static void
> intel_crtc_vblank_evade_scanlines(struct intel_atomic_state *state,
> struct intel_crtc *crtc,
> int *min, int *max, int
> *vblank_start) {
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> - const struct drm_display_mode *adjusted_mode = &new_crtc_state-
> >hw.adjusted_mode;
> + const struct intel_crtc_state *crtc_state;
> + const struct drm_display_mode *adjusted_mode;
>
> - if (new_crtc_state->vrr.enable) {
> - if (intel_vrr_is_push_sent(new_crtc_state))
> - *vblank_start =
> intel_vrr_vmin_vblank_start(new_crtc_state);
> + /*
> + * During fastsets/etc. the transcoder is still
> + * running with the old timings at this point.
> + *
> + * TODO: maybe just use the active timings here?
> + */
> + if (intel_crtc_needs_modeset(new_crtc_state))
> + crtc_state = new_crtc_state;
> + else
> + crtc_state = old_crtc_state;
> +
> + adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> + if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
> + if (intel_vrr_is_push_sent(crtc_state))
> + *vblank_start =
> intel_vrr_vmin_vblank_start(crtc_state);
> else
> - *vblank_start =
> intel_vrr_vmax_vblank_start(new_crtc_state);
> + *vblank_start =
> intel_vrr_vmax_vblank_start(crtc_state);
> } else {
> *vblank_start = intel_mode_vblank_start(adjusted_mode);
> }
> @@ -710,15 +726,6 @@ void intel_pipe_update_end(struct
> intel_atomic_state *state,
> */
> intel_vrr_send_push(new_crtc_state);
>
> - /*
> - * Seamless M/N update may need to update frame timings.
> - *
> - * FIXME Should be synchronized with the start of vblank somehow...
> - */
> - if (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state))
> - intel_crtc_update_active_timings(new_crtc_state,
> - new_crtc_state->vrr.enable);
> -
> local_irq_enable();
>
> if (intel_vgpu_active(dev_priv))
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index cfad967b5684..632f1f58df9e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6476,6 +6476,8 @@ static void commit_pipe_post_planes(struct
> intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> @@ -6487,6 +6489,9 @@ static void commit_pipe_post_planes(struct
> intel_atomic_state *state,
> if (DISPLAY_VER(dev_priv) >= 9 &&
> !intel_crtc_needs_modeset(new_crtc_state))
> skl_detach_scalers(new_crtc_state);
> +
> + if (vrr_enabling(old_crtc_state, new_crtc_state))
> + intel_vrr_enable(new_crtc_state);
> }
>
> static void intel_enable_crtc(struct intel_atomic_state *state, @@ -6527,12
> +6532,6 @@ static void intel_update_crtc(struct intel_atomic_state *state,
> intel_dpt_configure(crtc);
> }
>
> - if (vrr_enabling(old_crtc_state, new_crtc_state)) {
> - intel_vrr_enable(new_crtc_state);
> - intel_crtc_update_active_timings(new_crtc_state,
> - new_crtc_state->vrr.enable);
> - }
> -
> if (!modeset) {
> if (new_crtc_state->preload_luts &&
> intel_crtc_needs_color_update(new_crtc_state))
> @@ -6569,6 +6568,16 @@ static void intel_update_crtc(struct
> intel_atomic_state *state,
>
> intel_pipe_update_end(state, crtc);
>
> + /*
> + * VRR/Seamless M/N update may need to update frame timings.
> + *
> + * FIXME Should be synchronized with the start of vblank somehow...
> + */
> + if (vrr_enabling(old_crtc_state, new_crtc_state) ||
> + (new_crtc_state->seamless_m_n &&
> intel_crtc_needs_fastset(new_crtc_state)))
> + intel_crtc_update_active_timings(new_crtc_state,
> + new_crtc_state->vrr.enable);
> +
Change LGTM
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> /*
> * We usually enable FIFO underrun interrupts as part of the
> * CRTC enable sequence during modesets. But when we inherit a
> --
> 2.41.0
^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2023-09-11 18:21 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-08-28 5:41 [Intel-gfx] [PATCH 0/6] drm/i915: VRR and M/N stuff Ville Syrjala
2023-08-28 5:41 ` [Intel-gfx] [PATCH 1/6] drm/i915: Move psr unlock out from the pipe update critical section Ville Syrjala
2023-08-28 18:16 ` Manasi Navare
2023-08-29 8:23 ` Ville Syrjälä
2023-08-28 5:41 ` [Intel-gfx] [PATCH 2/6] drm/i915: Change intel_pipe_update_{start, end}() calling convention Ville Syrjala
2023-08-28 18:30 ` Manasi Navare
2023-08-29 8:27 ` Ville Syrjälä
2023-08-28 5:41 ` [Intel-gfx] [PATCH 3/6] drm/i915: Extract intel_crtc_vblank_evade_scanlines() Ville Syrjala
2023-08-28 18:31 ` Manasi Navare
2023-08-28 5:41 ` [Intel-gfx] [PATCH 4/6] drm/i915: Enable VRR later during fastsets Ville Syrjala
2023-08-28 18:47 ` Manasi Navare
2023-08-29 8:26 ` Ville Syrjälä
2023-08-29 14:58 ` Manasi Navare
2023-08-30 5:12 ` Ville Syrjälä
2023-09-11 18:21 ` Golani, Mitulkumar Ajitkumar
2023-08-28 5:41 ` [Intel-gfx] [PATCH 5/6] drm/i915: Adjust seamless_m_n flag behaviour Ville Syrjala
2023-08-28 16:58 ` Golani, Mitulkumar Ajitkumar
2023-08-29 8:20 ` Ville Syrjälä
2023-08-29 13:48 ` Golani, Mitulkumar Ajitkumar
2023-08-30 5:16 ` Ville Syrjälä
2023-08-30 6:51 ` Golani, Mitulkumar Ajitkumar
2023-08-30 6:58 ` Ville Syrjälä
2023-08-30 7:32 ` Golani, Mitulkumar Ajitkumar
2023-08-28 5:41 ` [Intel-gfx] [PATCH 6/6] drm/i915: Optimize out redundant M/N updates Ville Syrjala
2023-08-28 6:11 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: VRR and M/N stuff Patchwork
2023-08-28 6:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-08-28 8:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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