[PATCH 00/14] drm/i915: VLV/CHV DPIO register cleanup

[PATCH 00/14] drm/i915: VLV/CHV DPIO register cleanup

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Polish the VLV/CHV DPIO stuff and extract vlv_dpio_phy_regs.h
to declutter i915_reg.h a bit.

Ville Syrjälä (14):
  drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read
  drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/
  drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/
  drm/i915/dpio: Fix VLV DPIO PLL register dword numbering
  drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code
  drm/i915/dpio: Rename some variables
  drm/i915/dpio: s/port/ch/
  drm/i915/dpio: s/pipe/ch/
  drm/i915/dpio: Derive the phy from the port rather than pipe in
    encoder hooks
  drm/i915/dpio: Give VLV DPIO group register a clearer name
  drm/i915/dpio: Rename a few CHV DPIO PHY registers
  drm/i915/dpio: Clean up VLV/CHV DPIO PHY register defines
  drm/i915/dpio: Clean up the vlv/chv PHY register bits
  drm/i915/dpio: Extract vlv_dpio_phy_regs.h

 drivers/gpu/drm/i915/display/intel_display.c  |   1 +
 .../i915/display/intel_display_power_well.c   |  16 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 148 ++++----
 drivers/gpu/drm/i915/display/intel_dpll.c     | 260 +++++++------
 .../gpu/drm/i915/display/vlv_dpio_phy_regs.h  | 309 ++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 343 ------------------
 drivers/gpu/drm/i915/vlv_sideband.c           |   1 -
 7 files changed, 515 insertions(+), 563 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h

-- 
2.43.2

[PATCH 01/14] drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We don't use the result of the VLV_PCS01_DW8 read at all,
so don't read.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index c72b76b61dff..6cbee88e608f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1134,7 +1134,6 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	vlv_dpio_get(dev_priv);
 
 	/* Enable clock channels for this port */
-	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(port));
 	val = 0;
 	if (pipe)
 		val |= (1<<21);
-- 
2.43.2

[PATCH 02/14] drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Our VLV_REF_DW13 is actually VLV_REF_DW11. Rename it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 8 ++++----
 drivers/gpu/drm/i915/i915_reg.h           | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 49274d632716..6693beafe9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1880,19 +1880,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
 	reg_val |= 0x00000030;
 	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
 
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
+	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
 	reg_val &= 0x00ffffff;
 	reg_val |= 0x8c000000;
-	vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
+	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
 
 	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
 	reg_val &= 0xffffff00;
 	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
 
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
+	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
 	reg_val &= 0x00ffffff;
 	reg_val |= 0xb0000000;
-	vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
+	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
 }
 
 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8eb6c2bf4557..a2fadcbe0932 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -246,8 +246,8 @@
 #define _VLV_PLL_DW11_CH1		0x806c
 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
 
-/* Spec for ref block start counts at DW10 */
-#define VLV_REF_DW13			0x80ac
+/* Spec for ref block start counts at DW8 */
+#define VLV_REF_DW11			0x80ac
 
 #define VLV_CMN_DW0			0x8100
 
-- 
2.43.2

[PATCH 03/14] drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

VLV_PLL_DW9_BCAST is actually VLV_PCS_DW17_BCAST. The address
does kinda look like it goes to the PLL block on a first glance,
but broadcast is special and doesn't even exist for the PLL
(only PCS and TX have it).

The fact that we use a broadcast write here is a bit sketchy
IMO since we're now blasting the register to all PCS splines
across the whole PHY. So the PCS registers in the other channel
(ie. other pipe/port) will also be written. But I guess the
fact that we always write the same value should make this a nop
even if the other channel is already enabled (assuming the VBIOS/GOP
didn't screw up and use some other value...).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h           | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 6693beafe9c0..7e8aca3c87ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1920,7 +1920,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 		vlv_pllb_recal_opamp(dev_priv, phy);
 
 	/* Set up Tx target for periodic Rcomp update */
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9_BCAST, 0x0100000f);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
 
 	/* Disable target IRef on PLL */
 	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a2fadcbe0932..8f3c83d2ab8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -233,7 +233,6 @@
 #define _VLV_PLL_DW8_CH1		0x8060
 #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
 
-#define VLV_PLL_DW9_BCAST		0xc044
 #define _VLV_PLL_DW9_CH0		0x8044
 #define _VLV_PLL_DW9_CH1		0x8064
 #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
@@ -370,6 +369,8 @@
 #define _VLV_PCS_DW14_CH1		0x8438
 #define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
 
+#define VLV_PCS_DW17_BCAST		0xc044
+
 #define _VLV_PCS_DW23_CH0		0x825c
 #define _VLV_PCS_DW23_CH1		0x845c
 #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
-- 
2.43.2

[PATCH 04/14] drm/i915/dpio: Fix VLV DPIO PLL register dword numbering

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The spreadsheet defines the PLL register block as having
the dwords in the following order:

block   dwords    offsets
PLL1    0x0-0x7   0x00-0x1f
PLL2    0x0-0x7   0x20-0x2f
PLL1ext 0x10-0x1f 0x40-0x5f
PLL2ext 0x10-0x1f 0x60-0x7f

So dword indexes 0x8-0xf don't even exist. Renumber
our register defines to match.

Note that the spreadsheet used hex numbering whereas our
defiens are in decimal. Perhaps we should change that?

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 18 ++++++++---------
 drivers/gpu/drm/i915/i915_reg.h           | 24 +++++++++++------------
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7e8aca3c87ec..b95032651da0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1875,19 +1875,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
 	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
 	 * and set it to a reasonable value instead.
 	 */
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
+	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
 	reg_val &= 0xffffff00;
 	reg_val |= 0x00000030;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
 
 	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
 	reg_val &= 0x00ffffff;
 	reg_val |= 0x8c000000;
 	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
 
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
+	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
 	reg_val &= 0xffffff00;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
 
 	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
 	reg_val &= 0x00ffffff;
@@ -1923,9 +1923,9 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
 
 	/* Disable target IRef on PLL */
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe));
+	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
 	reg_val &= 0x00ffffff;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW8(pipe), reg_val);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
 
 	/* Disable fast lock */
 	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
@@ -1951,10 +1951,10 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->port_clock == 162000 ||
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 				 0x009f0003);
 	else
-		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 				 0x00d0000f);
 
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
@@ -1981,7 +1981,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 		coreclk |= 0x01000000;
 	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk);
 
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW11(pipe), 0x87871000);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(pipe), 0x87871000);
 
 	vlv_dpio_put(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f3c83d2ab8d..747221f8ac72 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -229,21 +229,21 @@
 #define _VLV_PLL_DW7_CH1		0x803c
 #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
 
-#define _VLV_PLL_DW8_CH0		0x8040
-#define _VLV_PLL_DW8_CH1		0x8060
-#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
+#define _VLV_PLL_DW16_CH0		0x8040
+#define _VLV_PLL_DW16_CH1		0x8060
+#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1)
 
-#define _VLV_PLL_DW9_CH0		0x8044
-#define _VLV_PLL_DW9_CH1		0x8064
-#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
+#define _VLV_PLL_DW17_CH0		0x8044
+#define _VLV_PLL_DW17_CH1		0x8064
+#define VLV_PLL_DW17(ch) _PIPE(ch, _VLV_PLL_DW17_CH0, _VLV_PLL_DW17_CH1)
 
-#define _VLV_PLL_DW10_CH0		0x8048
-#define _VLV_PLL_DW10_CH1		0x8068
-#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
+#define _VLV_PLL_DW18_CH0		0x8048
+#define _VLV_PLL_DW18_CH1		0x8068
+#define VLV_PLL_DW18(ch) _PIPE(ch, _VLV_PLL_DW18_CH0, _VLV_PLL_DW18_CH1)
 
-#define _VLV_PLL_DW11_CH0		0x804c
-#define _VLV_PLL_DW11_CH1		0x806c
-#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
+#define _VLV_PLL_DW19_CH0		0x804c
+#define _VLV_PLL_DW19_CH1		0x806c
+#define VLV_PLL_DW19(ch) _PIPE(ch, _VLV_PLL_DW19_CH0, _VLV_PLL_DW19_CH1)
 
 /* Spec for ref block start counts at DW8 */
 #define VLV_REF_DW11			0x80ac
-- 
2.43.2

[PATCH 05/14] drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Drop all the local variables for the DPLL dividers for vlv/chv
and just consult the state directly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 62 ++++++++++-------------
 1 file changed, 27 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index b95032651da0..01f800b6b30e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1899,20 +1899,13 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct dpll *clock = &crtc_state->dpll;
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	enum pipe pipe = crtc->pipe;
-	u32 mdiv;
-	u32 bestn, bestm1, bestm2, bestp1, bestp2;
-	u32 coreclk, reg_val;
+	u32 mdiv, coreclk, reg_val;
 
 	vlv_dpio_get(dev_priv);
 
-	bestn = crtc_state->dpll.n;
-	bestm1 = crtc_state->dpll.m1;
-	bestm2 = crtc_state->dpll.m2;
-	bestp1 = crtc_state->dpll.p1;
-	bestp2 = crtc_state->dpll.p2;
-
 	/* See eDP HDMI DPIO driver vbios notes doc */
 
 	/* PLL B needs special handling */
@@ -1931,10 +1924,12 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
 
 	/* Set idtafcrecal before PLL is enabled */
-	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
-	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
-	mdiv |= ((bestn << DPIO_N_SHIFT));
-	mdiv |= (1 << DPIO_K_SHIFT);
+	mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
+		(clock->m2 & DPIO_M2DIV_MASK) |
+		(clock->p1 << DPIO_P1_SHIFT) |
+		(clock->p2 << DPIO_P2_SHIFT) |
+		(clock->n << DPIO_N_SHIFT) |
+		(1 << DPIO_K_SHIFT);
 
 	/*
 	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
@@ -2030,19 +2025,14 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct dpll *clock = &crtc_state->dpll;
 	enum pipe pipe = crtc->pipe;
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
-	u32 loopfilter, tribuf_calcntr;
-	u32 bestm2, bestp1, bestp2, bestm2_frac;
-	u32 dpio_val;
-	int vco;
+	u32 dpio_val, loopfilter, tribuf_calcntr;
+	u32 m2_frac;
 
-	bestm2_frac = crtc_state->dpll.m2 & 0x3fffff;
-	bestm2 = crtc_state->dpll.m2 >> 22;
-	bestp1 = crtc_state->dpll.p1;
-	bestp2 = crtc_state->dpll.p2;
-	vco = crtc_state->dpll.vco;
+	m2_frac = clock->m2 & 0x3fffff;
 	dpio_val = 0;
 	loopfilter = 0;
 
@@ -2050,27 +2040,29 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 
 	/* p1 and p2 divider */
 	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port),
-			5 << DPIO_CHV_S1_DIV_SHIFT |
-			bestp1 << DPIO_CHV_P1_DIV_SHIFT |
-			bestp2 << DPIO_CHV_P2_DIV_SHIFT |
-			1 << DPIO_CHV_K_DIV_SHIFT);
+		       5 << DPIO_CHV_S1_DIV_SHIFT |
+		       clock->p1 << DPIO_CHV_P1_DIV_SHIFT |
+		       clock->p2 << DPIO_CHV_P2_DIV_SHIFT |
+		       1 << DPIO_CHV_K_DIV_SHIFT);
 
 	/* Feedback post-divider - m2 */
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), bestm2);
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port),
+		       clock->m2 >> 22);
 
 	/* Feedback refclk divider - n and m1 */
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port),
-			DPIO_CHV_M1_DIV_BY_2 |
-			1 << DPIO_CHV_N_DIV_SHIFT);
+		       DPIO_CHV_M1_DIV_BY_2 |
+		       1 << DPIO_CHV_N_DIV_SHIFT);
 
 	/* M2 fraction division */
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), bestm2_frac);
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port),
+		       m2_frac);
 
 	/* M2 fraction division enable */
 	dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
 	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
 	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
-	if (bestm2_frac)
+	if (m2_frac)
 		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val);
 
@@ -2079,22 +2071,22 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
 					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
 	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
-	if (!bestm2_frac)
+	if (!m2_frac)
 		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val);
 
 	/* Loop filter */
-	if (vco == 5400000) {
+	if (clock->vco == 5400000) {
 		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
 		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
 		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
 		tribuf_calcntr = 0x9;
-	} else if (vco <= 6200000) {
+	} else if (clock->vco <= 6200000) {
 		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
 		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
 		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
 		tribuf_calcntr = 0x9;
-	} else if (vco <= 6480000) {
+	} else if (clock->vco <= 6480000) {
 		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
 		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
 		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
-- 
2.43.2

[PATCH 06/14] drm/i915/dpio: Rename some variables

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use a constent 'tmp' as the variable name for the register
values during rmw when we don't deal with multiple registers
in parallel.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 97 +++++++++++------------
 1 file changed, 48 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 01f800b6b30e..0a738b491c40 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -514,23 +514,23 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
-	struct dpll clock;
-	u32 mdiv;
 	int refclk = 100000;
+	struct dpll clock;
+	u32 tmp;
 
 	/* In case of DSI, DPLL will not be used */
 	if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
 		return;
 
 	vlv_dpio_get(dev_priv);
-	mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
 	vlv_dpio_put(dev_priv);
 
-	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
-	clock.m2 = mdiv & DPIO_M2DIV_MASK;
-	clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
-	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
-	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
+	clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
+	clock.m2 = tmp & DPIO_M2DIV_MASK;
+	clock.n = (tmp >> DPIO_N_SHIFT) & 0xf;
+	clock.p1 = (tmp >> DPIO_P1_SHIFT) & 7;
+	clock.p2 = (tmp >> DPIO_P2_SHIFT) & 0x1f;
 
 	crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
 }
@@ -1869,30 +1869,30 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
 				 enum dpio_phy phy)
 {
-	u32 reg_val;
+	u32 tmp;
 
 	/*
 	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
 	 * and set it to a reasonable value instead.
 	 */
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
-	reg_val &= 0xffffff00;
-	reg_val |= 0x00000030;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+	tmp &= 0xffffff00;
+	tmp |= 0x00000030;
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
 
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
-	reg_val &= 0x00ffffff;
-	reg_val |= 0x8c000000;
-	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
+	tmp &= 0x00ffffff;
+	tmp |= 0x8c000000;
+	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
 
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
-	reg_val &= 0xffffff00;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+	tmp &= 0xffffff00;
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
 
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
-	reg_val &= 0x00ffffff;
-	reg_val |= 0xb0000000;
-	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
+	tmp &= 0x00ffffff;
+	tmp |= 0xb0000000;
+	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
 }
 
 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
@@ -1902,7 +1902,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	const struct dpll *clock = &crtc_state->dpll;
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	enum pipe pipe = crtc->pipe;
-	u32 mdiv, coreclk, reg_val;
+	u32 tmp, coreclk;
 
 	vlv_dpio_get(dev_priv);
 
@@ -1916,15 +1916,15 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
 
 	/* Disable target IRef on PLL */
-	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
-	reg_val &= 0x00ffffff;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
+	tmp &= 0x00ffffff;
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
 
 	/* Disable fast lock */
 	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
 
 	/* Set idtafcrecal before PLL is enabled */
-	mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
+	tmp = (clock->m1 << DPIO_M1DIV_SHIFT) |
 		(clock->m2 & DPIO_M2DIV_MASK) |
 		(clock->p1 << DPIO_P1_SHIFT) |
 		(clock->p2 << DPIO_P2_SHIFT) |
@@ -1936,11 +1936,11 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	 * but we don't support that).
 	 * Note: don't use the DAC post divider as it seems unstable.
 	 */
-	mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv);
+	tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
 
-	mdiv |= DPIO_ENABLE_CALIBRATION;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv);
+	tmp |= DPIO_ENABLE_CALIBRATION;
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
 
 	/* Set HBR and RBR LPF coefficients */
 	if (crtc_state->port_clock == 162000 ||
@@ -2029,11 +2029,10 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	enum dpio_channel port = vlv_pipe_to_channel(pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
-	u32 dpio_val, loopfilter, tribuf_calcntr;
+	u32 tmp, loopfilter, tribuf_calcntr;
 	u32 m2_frac;
 
 	m2_frac = clock->m2 & 0x3fffff;
-	dpio_val = 0;
 	loopfilter = 0;
 
 	vlv_dpio_get(dev_priv);
@@ -2059,21 +2058,21 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 		       m2_frac);
 
 	/* M2 fraction division enable */
-	dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
-	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
-	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
+	tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
+	tmp |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
 	if (m2_frac)
-		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val);
+		tmp |= DPIO_CHV_FRAC_DIV_EN;
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), tmp);
 
 	/* Program digital lock detect threshold */
-	dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port));
-	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
+	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port));
+	tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
 					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
-	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+	tmp |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
 	if (!m2_frac)
-		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val);
+		tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), tmp);
 
 	/* Loop filter */
 	if (clock->vco == 5400000) {
@@ -2100,10 +2099,10 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	}
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter);
 
-	dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port));
-	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
-	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), dpio_val);
+	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port));
+	tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
+	tmp |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), tmp);
 
 	/* AFC Recal */
 	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port),
-- 
2.43.2

[PATCH 07/14] drm/i915/dpio: s/port/ch/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Stop calling the DPIO PHY channel "port". Just say "ch", which
is already used in a bunch of places.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 44 +++++++--------
 drivers/gpu/drm/i915/display/intel_dpll.c     | 54 +++++++++----------
 2 files changed, 49 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 6cbee88e608f..e4a04c9b5b19 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1069,23 +1069,23 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 
 	vlv_dpio_get(dev_priv);
 
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x00000000);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port),
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x00000000);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
 			 uniqtranscale_reg_value);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
 
 	if (tx3_demph)
-		vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph);
+		vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
 
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x00030000);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x00030000);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
 
 	vlv_dpio_put(dev_priv);
 }
@@ -1096,25 +1096,25 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 
 	/* Program Tx lane resets to default */
 	vlv_dpio_get(dev_priv);
 
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port),
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
 			 DPIO_PCS_TX_LANE2_RESET |
 			 DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port),
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
 			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
 			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
 				 DPIO_PCS_CLK_SOFT_RESET);
 
 	/* Fix up inter-pair skew failure */
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(port), 0x00750f00);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(port), 0x00001500);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(port), 0x40400000);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x00001500);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x40400000);
 
 	vlv_dpio_put(dev_priv);
 }
@@ -1126,7 +1126,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
 	enum pipe pipe = crtc->pipe;
 	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
 	u32 val;
@@ -1140,11 +1140,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	else
 		val &= ~(1<<21);
 	val |= 0x001000c4;
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
 
 	/* Program lane clock */
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(port), 0x00760018);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(port), 0x00400888);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
 
 	vlv_dpio_put(dev_priv);
 }
@@ -1155,11 +1155,11 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
-	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
+	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 
 	vlv_dpio_get(dev_priv);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), 0x00000000);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), 0x00e00060);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), 0x00e00060);
 	vlv_dpio_put(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 0a738b491c40..743cc466ee39 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -539,7 +539,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);
+	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 	struct dpll clock;
@@ -551,11 +551,11 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 		return;
 
 	vlv_dpio_get(dev_priv);
-	cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(port));
-	pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(port));
-	pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(port));
-	pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(port));
-	pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
+	cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(ch));
+	pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(ch));
+	pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(ch));
+	pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(ch));
+	pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
 	vlv_dpio_put(dev_priv);
 
 	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
@@ -2027,7 +2027,7 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct dpll *clock = &crtc_state->dpll;
 	enum pipe pipe = crtc->pipe;
-	enum dpio_channel port = vlv_pipe_to_channel(pipe);
+	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	u32 tmp, loopfilter, tribuf_calcntr;
 	u32 m2_frac;
@@ -2038,41 +2038,41 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	vlv_dpio_get(dev_priv);
 
 	/* p1 and p2 divider */
-	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port),
+	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch),
 		       5 << DPIO_CHV_S1_DIV_SHIFT |
 		       clock->p1 << DPIO_CHV_P1_DIV_SHIFT |
 		       clock->p2 << DPIO_CHV_P2_DIV_SHIFT |
 		       1 << DPIO_CHV_K_DIV_SHIFT);
 
 	/* Feedback post-divider - m2 */
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port),
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch),
 		       clock->m2 >> 22);
 
 	/* Feedback refclk divider - n and m1 */
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port),
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch),
 		       DPIO_CHV_M1_DIV_BY_2 |
 		       1 << DPIO_CHV_N_DIV_SHIFT);
 
 	/* M2 fraction division */
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port),
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch),
 		       m2_frac);
 
 	/* M2 fraction division enable */
-	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
+	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
 	tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
 	tmp |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
 	if (m2_frac)
 		tmp |= DPIO_CHV_FRAC_DIV_EN;
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), tmp);
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp);
 
 	/* Program digital lock detect threshold */
-	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port));
+	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch));
 	tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
 					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
 	tmp |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
 	if (!m2_frac)
 		tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), tmp);
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp);
 
 	/* Loop filter */
 	if (clock->vco == 5400000) {
@@ -2097,17 +2097,17 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
 		tribuf_calcntr = 0;
 	}
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter);
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter);
 
-	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port));
+	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch));
 	tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
 	tmp |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
-	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), tmp);
+	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp);
 
 	/* AFC Recal */
-	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port),
-			vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)) |
-			DPIO_AFC_RECAL);
+	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch),
+		       vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)) |
+		       DPIO_AFC_RECAL);
 
 	vlv_dpio_put(dev_priv);
 }
@@ -2118,16 +2118,16 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 	enum pipe pipe = crtc->pipe;
-	enum dpio_channel port = vlv_pipe_to_channel(pipe);
+	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	u32 tmp;
 
 	vlv_dpio_get(dev_priv);
 
 	/* Enable back the 10bit clock to display controller */
-	tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port));
+	tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
 	tmp |= DPIO_DCLKP_EN;
-	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), tmp);
+	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), tmp);
 
 	vlv_dpio_put(dev_priv);
 
@@ -2246,7 +2246,7 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 {
-	enum dpio_channel port = vlv_pipe_to_channel(pipe);
+	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
 	u32 val;
 
@@ -2264,9 +2264,9 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	vlv_dpio_get(dev_priv);
 
 	/* Disable 10bit clock to display controller */
-	val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port));
+	val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
 	val &= ~DPIO_DCLKP_EN;
-	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), val);
+	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), val);
 
 	vlv_dpio_put(dev_priv);
 }
-- 
2.43.2

[PATCH 08/14] drm/i915/dpio: s/pipe/ch/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Stop using 'pipe' directly as the DPIO PHY channel. This
does happen to work on VLV since it just has the one PHY
with CH0==pipe A and CH1==pipe B. But explicitly converting
the thing to the right enum makes the whole thing less
confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 49 ++++++++++++-----------
 1 file changed, 25 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 743cc466ee39..861f4a735251 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -512,6 +512,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
 	int refclk = 100000;
@@ -523,7 +524,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 		return;
 
 	vlv_dpio_get(dev_priv);
-	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch));
 	vlv_dpio_put(dev_priv);
 
 	clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
@@ -1867,7 +1868,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
 }
 
 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
-				 enum dpio_phy phy)
+				 enum dpio_phy phy, enum dpio_channel ch)
 {
 	u32 tmp;
 
@@ -1875,19 +1876,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
 	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
 	 * and set it to a reasonable value instead.
 	 */
-	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
 	tmp &= 0xffffff00;
 	tmp |= 0x00000030;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
 
 	tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
 	tmp &= 0x00ffffff;
 	tmp |= 0x8c000000;
 	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
 
-	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
 	tmp &= 0xffffff00;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
 
 	tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
 	tmp &= 0x00ffffff;
@@ -1900,6 +1901,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct dpll *clock = &crtc_state->dpll;
+	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	enum pipe pipe = crtc->pipe;
 	u32 tmp, coreclk;
@@ -1910,15 +1912,15 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 
 	/* PLL B needs special handling */
 	if (pipe == PIPE_B)
-		vlv_pllb_recal_opamp(dev_priv, phy);
+		vlv_pllb_recal_opamp(dev_priv, phy, ch);
 
 	/* Set up Tx target for periodic Rcomp update */
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
 
 	/* Disable target IRef on PLL */
-	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
+	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(ch));
 	tmp &= 0x00ffffff;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(ch), tmp);
 
 	/* Disable fast lock */
 	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
@@ -1937,46 +1939,46 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	 * Note: don't use the DAC post divider as it seems unstable.
 	 */
 	tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
 
 	tmp |= DPIO_ENABLE_CALIBRATION;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
 
 	/* Set HBR and RBR LPF coefficients */
 	if (crtc_state->port_clock == 162000 ||
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
-		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
 				 0x009f0003);
 	else
-		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
 				 0x00d0000f);
 
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
 		/* Use SSC source */
 		if (pipe == PIPE_A)
-			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df40000);
 		else
-			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df70000);
 	} else { /* HDMI or VGA */
 		/* Use bend source */
 		if (pipe == PIPE_A)
-			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df70000);
 		else
-			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df40000);
 	}
 
-	coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(pipe));
+	coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(ch));
 	coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
 	if (intel_crtc_has_dp_encoder(crtc_state))
 		coreclk |= 0x01000000;
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(ch), coreclk);
 
-	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(pipe), 0x87871000);
+	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(ch), 0x87871000);
 
 	vlv_dpio_put(dev_priv);
 }
@@ -2026,8 +2028,7 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct dpll *clock = &crtc_state->dpll;
-	enum pipe pipe = crtc->pipe;
-	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
+	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
 	u32 tmp, loopfilter, tribuf_calcntr;
 	u32 m2_frac;
@@ -2117,9 +2118,9 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
-	enum pipe pipe = crtc->pipe;
-	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
+	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
 	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+	enum pipe pipe = crtc->pipe;
 	u32 tmp;
 
 	vlv_dpio_get(dev_priv);
-- 
2.43.2

[PATCH 09/14] drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In the encoder hooks we are dealing primarily with the encoder,
so derive the DPIO PHY from the encoder rather than the pipe.
Technically this doesn't matter as we can't cross connect
pipes<->port across PHY boundaries, but it does conveny the
intention more accurately.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 27 ++++++++-----------
 drivers/gpu/drm/i915/vlv_sideband.c           |  1 -
 2 files changed, 11 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index e4a04c9b5b19..4fafac534967 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -719,9 +719,8 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 	u32 val;
 	int i;
 
@@ -814,9 +813,9 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
 			      bool reset)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
-	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
+	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 	u32 val;
 
 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch));
@@ -861,7 +860,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 	enum pipe pipe = crtc->pipe;
 	unsigned int lane_mask =
 		intel_dp_unused_lane_mask(crtc_state->lane_count);
@@ -941,9 +940,8 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 	int data, i, stagger;
 	u32 val;
 
@@ -1030,8 +1028,8 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 			      const struct intel_crtc_state *old_crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
 	enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
-	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
 	u32 val;
 
 	vlv_dpio_get(dev_priv);
@@ -1068,9 +1066,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 
 	vlv_dpio_get(dev_priv);
 
@@ -1095,9 +1092,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 
 	/* Program Tx lane resets to default */
 	vlv_dpio_get(dev_priv);
@@ -1127,8 +1123,8 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
+	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 	enum pipe pipe = crtc->pipe;
-	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
 	u32 val;
 
 	vlv_dpio_get(dev_priv);
@@ -1154,9 +1150,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
-	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
+	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 
 	vlv_dpio_get(dev_priv);
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000);
diff --git a/drivers/gpu/drm/i915/vlv_sideband.c b/drivers/gpu/drm/i915/vlv_sideband.c
index ffa195560d0d..68291412f4cb 100644
--- a/drivers/gpu/drm/i915/vlv_sideband.c
+++ b/drivers/gpu/drm/i915/vlv_sideband.c
@@ -9,7 +9,6 @@
 #include "vlv_sideband.h"
 
 #include "display/intel_dpio_phy.h"
-#include "display/intel_display_types.h"
 
 /*
  * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
-- 
2.43.2

[PATCH 10/14] drm/i915/dpio: Give VLV DPIO group register a clearer name

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Include _GRP in VLV DPOP PHY group access register define
names. Makes it more obvious where the accesses will land.
Also matches the naming used by BXT already.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 34 +++----
 drivers/gpu/drm/i915/i915_reg.h               | 90 +++++++++----------
 2 files changed, 62 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 4fafac534967..791902ba729c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1071,18 +1071,18 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 
 	vlv_dpio_get(dev_priv);
 
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x00000000);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
 			 uniqtranscale_reg_value);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
 
 	if (tx3_demph)
 		vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
 
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x00030000);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);
 
 	vlv_dpio_put(dev_priv);
 }
@@ -1098,19 +1098,19 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
 	/* Program Tx lane resets to default */
 	vlv_dpio_get(dev_priv);
 
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
 			 DPIO_PCS_TX_LANE2_RESET |
 			 DPIO_PCS_TX_LANE1_RESET);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
 			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
 			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
 				 DPIO_PCS_CLK_SOFT_RESET);
 
 	/* Fix up inter-pair skew failure */
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x00001500);
-	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x40400000);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500);
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000);
 
 	vlv_dpio_put(dev_priv);
 }
@@ -1136,11 +1136,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	else
 		val &= ~(1<<21);
 	val |= 0x001000c4;
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val);
 
 	/* Program lane clock */
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);
 
 	vlv_dpio_put(dev_priv);
 }
@@ -1154,7 +1154,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
 	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
 
 	vlv_dpio_get(dev_priv);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000);
-	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), 0x00e00060);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);
 	vlv_dpio_put(dev_priv);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 747221f8ac72..3804ef4697d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -254,13 +254,13 @@
  * Per DDI channel DPIO regs
  */
 
-#define _VLV_PCS_DW0_CH0		0x8200
-#define _VLV_PCS_DW0_CH1		0x8400
+#define _VLV_PCS_DW0_CH0_GRP		0x8200
+#define _VLV_PCS_DW0_CH1_GRP		0x8400
 #define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
 #define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
 #define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
 #define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
-#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
+#define VLV_PCS_DW0_GRP(ch) _PORT(ch, _VLV_PCS_DW0_CH0_GRP, _VLV_PCS_DW0_CH1_GRP)
 
 #define _VLV_PCS01_DW0_CH0		0x200
 #define _VLV_PCS23_DW0_CH0		0x400
@@ -269,14 +269,14 @@
 #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
 #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
 
-#define _VLV_PCS_DW1_CH0		0x8204
-#define _VLV_PCS_DW1_CH1		0x8404
+#define _VLV_PCS_DW1_CH0_GRP		0x8204
+#define _VLV_PCS_DW1_CH1_GRP		0x8404
 #define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
 #define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
-#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
+#define VLV_PCS_DW1_GRP(ch) _PORT(ch, _VLV_PCS_DW1_CH0_GRP, _VLV_PCS_DW1_CH1_GRP)
 
 #define _VLV_PCS01_DW1_CH0		0x204
 #define _VLV_PCS23_DW1_CH0		0x404
@@ -285,11 +285,11 @@
 #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
 #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
 
-#define _VLV_PCS_DW8_CH0		0x8220
-#define _VLV_PCS_DW8_CH1		0x8420
+#define _VLV_PCS_DW8_CH0_GRP		0x8220
+#define _VLV_PCS_DW8_CH1_GRP		0x8420
 #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
 #define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
-#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
+#define VLV_PCS_DW8_GRP(ch) _PORT(ch, _VLV_PCS_DW8_CH0_GRP, _VLV_PCS_DW8_CH1_GRP)
 
 #define _VLV_PCS01_DW8_CH0		0x0220
 #define _VLV_PCS23_DW8_CH0		0x0420
@@ -298,15 +298,15 @@
 #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
 #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
 
-#define _VLV_PCS_DW9_CH0		0x8224
-#define _VLV_PCS_DW9_CH1		0x8424
+#define _VLV_PCS_DW9_CH0_GRP		0x8224
+#define _VLV_PCS_DW9_CH1_GRP		0x8424
 #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
 #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
 #define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
 #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
 #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
 #define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
-#define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
+#define VLV_PCS_DW9_GRP(ch) _PORT(ch, _VLV_PCS_DW9_CH0_GRP, _VLV_PCS_DW9_CH1_GRP)
 
 #define _VLV_PCS01_DW9_CH0		0x224
 #define _VLV_PCS23_DW9_CH0		0x424
@@ -315,8 +315,8 @@
 #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
 #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
 
-#define _CHV_PCS_DW10_CH0		0x8228
-#define _CHV_PCS_DW10_CH1		0x8428
+#define _CHV_PCS_DW10_CH0_GRP		0x8228
+#define _CHV_PCS_DW10_CH1_GRP		0x8428
 #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
 #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
 #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
@@ -325,7 +325,7 @@
 #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
 #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
 #define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
-#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
+#define CHV_PCS_DW10_GRP(ch) _PORT(ch, _CHV_PCS_DW10_CH0_GRP, _CHV_PCS_DW10_CH1_GRP)
 
 #define _VLV_PCS01_DW10_CH0		0x0228
 #define _VLV_PCS23_DW10_CH0		0x0428
@@ -334,13 +334,13 @@
 #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
 #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
 
-#define _VLV_PCS_DW11_CH0		0x822c
-#define _VLV_PCS_DW11_CH1		0x842c
+#define _VLV_PCS_DW11_CH0_GRP		0x822c
+#define _VLV_PCS_DW11_CH1_GRP		0x842c
 #define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
 #define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
 #define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
 #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
-#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
+#define VLV_PCS_DW11_GRP(ch) _PORT(ch, _VLV_PCS_DW11_CH0_GRP, _VLV_PCS_DW11_CH1_GRP)
 
 #define _VLV_PCS01_DW11_CH0		0x022c
 #define _VLV_PCS23_DW11_CH0		0x042c
@@ -356,64 +356,64 @@
 #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
 #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
 
-#define _VLV_PCS_DW12_CH0		0x8230
-#define _VLV_PCS_DW12_CH1		0x8430
+#define _VLV_PCS_DW12_CH0_GRP		0x8230
+#define _VLV_PCS_DW12_CH1_GRP		0x8430
 #define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
 #define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
 #define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
 #define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
 #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
-#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
+#define VLV_PCS_DW12_GRP(ch) _PORT(ch, _VLV_PCS_DW12_CH0_GRP, _VLV_PCS_DW12_CH1_GRP)
 
-#define _VLV_PCS_DW14_CH0		0x8238
-#define _VLV_PCS_DW14_CH1		0x8438
-#define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
+#define _VLV_PCS_DW14_CH0_GRP		0x8238
+#define _VLV_PCS_DW14_CH1_GRP		0x8438
+#define VLV_PCS_DW14_GRP(ch) _PORT(ch, _VLV_PCS_DW14_CH0_GRP, _VLV_PCS_DW14_CH1_GRP)
 
 #define VLV_PCS_DW17_BCAST		0xc044
 
-#define _VLV_PCS_DW23_CH0		0x825c
-#define _VLV_PCS_DW23_CH1		0x845c
-#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
+#define _VLV_PCS_DW23_CH0_GRP		0x825c
+#define _VLV_PCS_DW23_CH1_GRP		0x845c
+#define VLV_PCS_DW23_GRP(ch) _PORT(ch, _VLV_PCS_DW23_CH0_GRP, _VLV_PCS_DW23_CH1_GRP)
 
-#define _VLV_TX_DW2_CH0			0x8288
-#define _VLV_TX_DW2_CH1			0x8488
+#define _VLV_TX_DW2_CH0_GRP		0x8288
+#define _VLV_TX_DW2_CH1_GRP		0x8488
 #define   DPIO_SWING_MARGIN000_SHIFT	16
 #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
 #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
-#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
+#define VLV_TX_DW2_GRP(ch) _PORT(ch, _VLV_TX_DW2_CH0_GRP, _VLV_TX_DW2_CH1_GRP)
 
-#define _VLV_TX_DW3_CH0			0x828c
-#define _VLV_TX_DW3_CH1			0x848c
+#define _VLV_TX_DW3_CH0_GRP		0x828c
+#define _VLV_TX_DW3_CH1_GRP		0x848c
 /* The following bit for CHV phy */
 #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
 #define   DPIO_SWING_MARGIN101_SHIFT	16
 #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
-#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
+#define VLV_TX_DW3_GRP(ch) _PORT(ch, _VLV_TX_DW3_CH0_GRP, _VLV_TX_DW3_CH1_GRP)
 
-#define _VLV_TX_DW4_CH0			0x8290
-#define _VLV_TX_DW4_CH1			0x8490
+#define _VLV_TX_DW4_CH0_GRP		0x8290
+#define _VLV_TX_DW4_CH1_GRP		0x8490
 #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
 #define   DPIO_SWING_DEEMPH6P0_SHIFT	16
 #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
-#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
+#define VLV_TX_DW4_GRP(ch) _PORT(ch, _VLV_TX_DW4_CH0_GRP, _VLV_TX_DW4_CH1_GRP)
 
 #define _VLV_TX3_DW4_CH0		0x690
 #define _VLV_TX3_DW4_CH1		0x2a90
 #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
 
-#define _VLV_TX_DW5_CH0			0x8294
-#define _VLV_TX_DW5_CH1			0x8494
+#define _VLV_TX_DW5_CH0_GRP		0x8294
+#define _VLV_TX_DW5_CH1_GRP		0x8494
 #define   DPIO_TX_OCALINIT_EN		(1 << 31)
-#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
+#define VLV_TX_DW5_GRP(ch) _PORT(ch, _VLV_TX_DW5_CH0_GRP, _VLV_TX_DW5_CH1_GRP)
 
-#define _VLV_TX_DW11_CH0		0x82ac
-#define _VLV_TX_DW11_CH1		0x84ac
-#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
+#define _VLV_TX_DW11_CH0_GRP		0x82ac
+#define _VLV_TX_DW11_CH1_GRP		0x84ac
+#define VLV_TX_DW11_GRP(ch) _PORT(ch, _VLV_TX_DW11_CH0_GRP, _VLV_TX_DW11_CH1_GRP)
 
-#define _VLV_TX_DW14_CH0		0x82b8
-#define _VLV_TX_DW14_CH1		0x84b8
-#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
+#define _VLV_TX_DW14_CH0_GRP		0x82b8
+#define _VLV_TX_DW14_CH1_GRP		0x84b8
+#define VLV_TX_DW14_GRP(ch) _PORT(ch, _VLV_TX_DW14_CH0_GRP, _VLV_TX_DW14_CH1_GRP)
 
 /* CHV dpPhy registers */
 #define _CHV_PLL_DW0_CH0		0x8000
-- 
2.43.2

[PATCH 11/14] drm/i915/dpio: Rename a few CHV DPIO PHY registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Drop the leading underscore from the CHV PHY common lane
register definitons. We use these directly from actual
code so the underscore here is misleading as usually it indicates
an intermediate define that shouldn't be used directly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../i915/display/intel_display_power_well.c   |  8 +++----
 drivers/gpu/drm/i915/display/intel_dpio_phy.c | 16 ++++++-------
 drivers/gpu/drm/i915/i915_reg.h               | 23 +++++++++----------
 3 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e8a6e53fd551..49114afc9a61 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1442,9 +1442,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp);
 
 	if (id == VLV_DISP_PW_DPIO_CMN_BC) {
-		tmp = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW6_CH1);
+		tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1);
 		tmp |= DPIO_DYNPWRDOWNEN_CH1;
-		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW6_CH1, tmp);
+		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp);
 	} else {
 		/*
 		 * Force the non-existing CL2 off. BXT does this
@@ -1520,9 +1520,9 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
 		return;
 
 	if (ch == DPIO_CH0)
-		reg = _CHV_CMN_DW0_CH0;
+		reg = CHV_CMN_DW0_CH0;
 	else
-		reg = _CHV_CMN_DW6_CH1;
+		reg = CHV_CMN_DW6_CH1;
 
 	vlv_dpio_get(dev_priv);
 	val = vlv_dpio_read(dev_priv, phy, reg);
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 791902ba729c..89a51b420075 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -883,21 +883,21 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 
 	/* program left/right clock distribution */
 	if (pipe != PIPE_B) {
-		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
+		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
 		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
 		if (ch == DPIO_CH0)
 			val |= CHV_BUFLEFTENA1_FORCE;
 		if (ch == DPIO_CH1)
 			val |= CHV_BUFRIGHTENA1_FORCE;
-		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
+		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
 	} else {
-		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
+		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
 		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
 		if (ch == DPIO_CH0)
 			val |= CHV_BUFLEFTENA2_FORCE;
 		if (ch == DPIO_CH1)
 			val |= CHV_BUFRIGHTENA2_FORCE;
-		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
+		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
 	}
 
 	/* program clock channel usage */
@@ -1036,13 +1036,13 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
 
 	/* disable left/right clock distribution */
 	if (pipe != PIPE_B) {
-		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
+		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
 		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
-		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
+		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
 	} else {
-		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
+		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
 		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
-		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
+		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
 	}
 
 	vlv_dpio_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3804ef4697d5..b24ce3cff1a0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -459,13 +459,13 @@
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
 #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
 
-#define _CHV_CMN_DW0_CH0               0x8100
+#define CHV_CMN_DW0_CH0			0x8100
 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
 #define   DPIO_ALLDL_POWERDOWN			(1 << 1)
 #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
 
-#define _CHV_CMN_DW5_CH0               0x8114
+#define CHV_CMN_DW5_CH0			0x8114
 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
 #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
 #define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
@@ -475,18 +475,18 @@
 #define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
 #define   CHV_BUFLEFTENA1_MASK		(3 << 22)
 
-#define _CHV_CMN_DW13_CH0		0x8134
-#define _CHV_CMN_DW0_CH1		0x8080
+#define CHV_CMN_DW13_CH0		0x8134
+#define CHV_CMN_DW0_CH1			0x8080
 #define   DPIO_CHV_S1_DIV_SHIFT		21
 #define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
 #define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
 #define   DPIO_CHV_K_DIV_SHIFT		4
 #define   DPIO_PLL_FREQLOCK		(1 << 1)
 #define   DPIO_PLL_LOCK			(1 << 0)
-#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
+#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
 
-#define _CHV_CMN_DW14_CH0		0x8138
-#define _CHV_CMN_DW1_CH1		0x8084
+#define CHV_CMN_DW14_CH0		0x8138
+#define CHV_CMN_DW1_CH1			0x8084
 #define   DPIO_AFC_RECAL		(1 << 14)
 #define   DPIO_DCLKP_EN			(1 << 13)
 #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
@@ -497,16 +497,15 @@
 #define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
 #define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
 #define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
-#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
+#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
 
-#define _CHV_CMN_DW19_CH0		0x814c
-#define _CHV_CMN_DW6_CH1		0x8098
+#define CHV_CMN_DW19_CH0		0x814c
+#define CHV_CMN_DW6_CH1		0x8098
 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
 #define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
 #define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
-
-#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
+#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
 
 #define CHV_CMN_DW28			0x8170
 #define   DPIO_CL1POWERDOWNEN		(1 << 23)
-- 
2.43.2

[PATCH 12/14] drm/i915/dpio: Clean up VLV/CHV DPIO PHY register defines

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DPIO PHY registers follow clear numbering rules. Express
those in a few macros to get rid of the hand calculated
final offsets.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |   2 +-
 drivers/gpu/drm/i915/i915_reg.h               | 271 +++++++-----------
 2 files changed, 99 insertions(+), 174 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 89a51b420075..fa665d353df9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -1078,7 +1078,7 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
 	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
 
 	if (tx3_demph)
-		vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
+		vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph);
 
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b24ce3cff1a0..6d16f9944eff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -195,10 +195,22 @@
 #define  DPIO_SFR_BYPASS		(1 << 1)
 #define  DPIO_CMNRST			(1 << 0)
 
+#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
+#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
+#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
+#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
+#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
+#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4)
+#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
+#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4)
+#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
+
 /*
  * Per pipe/PLL DPIO regs
  */
-#define _VLV_PLL_DW3_CH0		0x800c
+#define VLV_PLL_DW3(ch)			_VLV_PLL((ch), 3)
 #define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
 #define   DPIO_POST_DIV_DAC		0
 #define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
@@ -211,10 +223,8 @@
 #define   DPIO_ENABLE_CALIBRATION	(1 << 11)
 #define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
 #define   DPIO_M2DIV_MASK		0xff
-#define _VLV_PLL_DW3_CH1		0x802c
-#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
 
-#define _VLV_PLL_DW5_CH0		0x8014
+#define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
 #define   DPIO_REFSEL_OVERRIDE		27
 #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
@@ -222,101 +232,60 @@
 #define   DPIO_PLL_REFCLK_SEL_MASK	3
 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
-#define _VLV_PLL_DW5_CH1		0x8034
-#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
 
-#define _VLV_PLL_DW7_CH0		0x801c
-#define _VLV_PLL_DW7_CH1		0x803c
-#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
+#define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)
 
-#define _VLV_PLL_DW16_CH0		0x8040
-#define _VLV_PLL_DW16_CH1		0x8060
-#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1)
+#define VLV_PLL_DW16(ch)		_VLV_PLL((ch), 16)
 
-#define _VLV_PLL_DW17_CH0		0x8044
-#define _VLV_PLL_DW17_CH1		0x8064
-#define VLV_PLL_DW17(ch) _PIPE(ch, _VLV_PLL_DW17_CH0, _VLV_PLL_DW17_CH1)
+#define VLV_PLL_DW17(ch)		_VLV_PLL((ch), 17)
 
-#define _VLV_PLL_DW18_CH0		0x8048
-#define _VLV_PLL_DW18_CH1		0x8068
-#define VLV_PLL_DW18(ch) _PIPE(ch, _VLV_PLL_DW18_CH0, _VLV_PLL_DW18_CH1)
+#define VLV_PLL_DW18(ch)		_VLV_PLL((ch), 18)
 
-#define _VLV_PLL_DW19_CH0		0x804c
-#define _VLV_PLL_DW19_CH1		0x806c
-#define VLV_PLL_DW19(ch) _PIPE(ch, _VLV_PLL_DW19_CH0, _VLV_PLL_DW19_CH1)
+#define VLV_PLL_DW19(ch)		_VLV_PLL((ch), 19)
 
-/* Spec for ref block start counts at DW8 */
-#define VLV_REF_DW11			0x80ac
+#define VLV_REF_DW11			_VLV_REF(11)
 
-#define VLV_CMN_DW0			0x8100
+#define VLV_CMN_DW0			_VLV_CMN(0)
 
 /*
  * Per DDI channel DPIO regs
  */
-
-#define _VLV_PCS_DW0_CH0_GRP		0x8200
-#define _VLV_PCS_DW0_CH1_GRP		0x8400
+#define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
+#define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
+#define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
 #define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
 #define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
 #define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
 #define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
-#define VLV_PCS_DW0_GRP(ch) _PORT(ch, _VLV_PCS_DW0_CH0_GRP, _VLV_PCS_DW0_CH1_GRP)
 
-#define _VLV_PCS01_DW0_CH0		0x200
-#define _VLV_PCS23_DW0_CH0		0x400
-#define _VLV_PCS01_DW0_CH1		0x2600
-#define _VLV_PCS23_DW0_CH1		0x2800
-#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
-#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
-
-#define _VLV_PCS_DW1_CH0_GRP		0x8204
-#define _VLV_PCS_DW1_CH1_GRP		0x8404
+#define VLV_PCS_DW1_GRP(ch)		_VLV_PCS_GRP((ch), 1)
+#define VLV_PCS01_DW1(ch)		_VLV_PCS((ch), 0, 1)
+#define VLV_PCS23_DW1(ch)		_VLV_PCS((ch), 1, 1)
 #define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
 #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
 #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
 #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
 #define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
-#define VLV_PCS_DW1_GRP(ch) _PORT(ch, _VLV_PCS_DW1_CH0_GRP, _VLV_PCS_DW1_CH1_GRP)
 
-#define _VLV_PCS01_DW1_CH0		0x204
-#define _VLV_PCS23_DW1_CH0		0x404
-#define _VLV_PCS01_DW1_CH1		0x2604
-#define _VLV_PCS23_DW1_CH1		0x2804
-#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
-#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
-
-#define _VLV_PCS_DW8_CH0_GRP		0x8220
-#define _VLV_PCS_DW8_CH1_GRP		0x8420
+#define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
+#define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
+#define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
 #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
 #define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
-#define VLV_PCS_DW8_GRP(ch) _PORT(ch, _VLV_PCS_DW8_CH0_GRP, _VLV_PCS_DW8_CH1_GRP)
 
-#define _VLV_PCS01_DW8_CH0		0x0220
-#define _VLV_PCS23_DW8_CH0		0x0420
-#define _VLV_PCS01_DW8_CH1		0x2620
-#define _VLV_PCS23_DW8_CH1		0x2820
-#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
-#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
-
-#define _VLV_PCS_DW9_CH0_GRP		0x8224
-#define _VLV_PCS_DW9_CH1_GRP		0x8424
+#define VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
+#define VLV_PCS01_DW9(ch)		_VLV_PCS((ch), 0, 9)
+#define VLV_PCS23_DW9(ch)		_VLV_PCS((ch), 1, 9)
 #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
 #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
 #define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
 #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
 #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
 #define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
-#define VLV_PCS_DW9_GRP(ch) _PORT(ch, _VLV_PCS_DW9_CH0_GRP, _VLV_PCS_DW9_CH1_GRP)
 
-#define _VLV_PCS01_DW9_CH0		0x224
-#define _VLV_PCS23_DW9_CH0		0x424
-#define _VLV_PCS01_DW9_CH1		0x2624
-#define _VLV_PCS23_DW9_CH1		0x2824
-#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
-#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
-
-#define _CHV_PCS_DW10_CH0_GRP		0x8228
-#define _CHV_PCS_DW10_CH1_GRP		0x8428
+#define VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
+#define VLV_PCS01_DW10(ch)		_VLV_PCS((ch), 0, 10)
+#define VLV_PCS23_DW10(ch)		_VLV_PCS((ch), 1, 10)
 #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
 #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
 #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
@@ -325,147 +294,104 @@
 #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
 #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
 #define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
-#define CHV_PCS_DW10_GRP(ch) _PORT(ch, _CHV_PCS_DW10_CH0_GRP, _CHV_PCS_DW10_CH1_GRP)
 
-#define _VLV_PCS01_DW10_CH0		0x0228
-#define _VLV_PCS23_DW10_CH0		0x0428
-#define _VLV_PCS01_DW10_CH1		0x2628
-#define _VLV_PCS23_DW10_CH1		0x2828
-#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
-#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
-
-#define _VLV_PCS_DW11_CH0_GRP		0x822c
-#define _VLV_PCS_DW11_CH1_GRP		0x842c
+#define VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
+#define VLV_PCS01_DW11(ch)		_VLV_PCS((ch), 0, 11)
+#define VLV_PCS23_DW11(ch)		_VLV_PCS((ch), 1, 11)
 #define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
 #define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
 #define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
 #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
-#define VLV_PCS_DW11_GRP(ch) _PORT(ch, _VLV_PCS_DW11_CH0_GRP, _VLV_PCS_DW11_CH1_GRP)
 
-#define _VLV_PCS01_DW11_CH0		0x022c
-#define _VLV_PCS23_DW11_CH0		0x042c
-#define _VLV_PCS01_DW11_CH1		0x262c
-#define _VLV_PCS23_DW11_CH1		0x282c
-#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
-#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
-
-#define _VLV_PCS01_DW12_CH0		0x0230
-#define _VLV_PCS23_DW12_CH0		0x0430
-#define _VLV_PCS01_DW12_CH1		0x2630
-#define _VLV_PCS23_DW12_CH1		0x2830
-#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
-#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
-
-#define _VLV_PCS_DW12_CH0_GRP		0x8230
-#define _VLV_PCS_DW12_CH1_GRP		0x8430
+#define VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
+#define VLV_PCS01_DW12(ch)		_VLV_PCS((ch), 0, 12)
+#define VLV_PCS23_DW12(ch)		_VLV_PCS((ch), 1, 12)
 #define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
 #define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
 #define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
 #define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
 #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
-#define VLV_PCS_DW12_GRP(ch) _PORT(ch, _VLV_PCS_DW12_CH0_GRP, _VLV_PCS_DW12_CH1_GRP)
 
-#define _VLV_PCS_DW14_CH0_GRP		0x8238
-#define _VLV_PCS_DW14_CH1_GRP		0x8438
-#define VLV_PCS_DW14_GRP(ch) _PORT(ch, _VLV_PCS_DW14_CH0_GRP, _VLV_PCS_DW14_CH1_GRP)
+#define VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
+#define VLV_PCS01_DW14(ch)		_VLV_PCS((ch), 0, 14)
+#define VLV_PCS23_DW14(ch)		_VLV_PCS((ch), 1, 14)
 
-#define VLV_PCS_DW17_BCAST		0xc044
+#define VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
+#define VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
+#define VLV_PCS01_DW17(ch)		_VLV_PCS((ch), 0, 17)
+#define VLV_PCS23_DW17(ch)		_VLV_PCS((ch), 1, 17)
 
-#define _VLV_PCS_DW23_CH0_GRP		0x825c
-#define _VLV_PCS_DW23_CH1_GRP		0x845c
-#define VLV_PCS_DW23_GRP(ch) _PORT(ch, _VLV_PCS_DW23_CH0_GRP, _VLV_PCS_DW23_CH1_GRP)
+#define VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
+#define VLV_PCS01_DW23(ch)		_VLV_PCS((ch), 0, 23)
+#define VLV_PCS23_DW23(ch)		_VLV_PCS((ch), 1, 23)
 
-#define _VLV_TX_DW2_CH0_GRP		0x8288
-#define _VLV_TX_DW2_CH1_GRP		0x8488
+#define VLV_TX_DW2_GRP(ch)		_VLV_TX_GRP((ch), 2)
+#define VLV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
 #define   DPIO_SWING_MARGIN000_SHIFT	16
 #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
 #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
-#define VLV_TX_DW2_GRP(ch) _PORT(ch, _VLV_TX_DW2_CH0_GRP, _VLV_TX_DW2_CH1_GRP)
 
-#define _VLV_TX_DW3_CH0_GRP		0x828c
-#define _VLV_TX_DW3_CH1_GRP		0x848c
+#define VLV_TX_DW3_GRP(ch)		_VLV_TX_GRP((ch), 3)
+#define VLV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
 /* The following bit for CHV phy */
 #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
 #define   DPIO_SWING_MARGIN101_SHIFT	16
 #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
-#define VLV_TX_DW3_GRP(ch) _PORT(ch, _VLV_TX_DW3_CH0_GRP, _VLV_TX_DW3_CH1_GRP)
 
-#define _VLV_TX_DW4_CH0_GRP		0x8290
-#define _VLV_TX_DW4_CH1_GRP		0x8490
+#define VLV_TX_DW4_GRP(ch)		_VLV_TX_GRP((ch), 4)
+#define VLV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
 #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
 #define   DPIO_SWING_DEEMPH6P0_SHIFT	16
 #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
-#define VLV_TX_DW4_GRP(ch) _PORT(ch, _VLV_TX_DW4_CH0_GRP, _VLV_TX_DW4_CH1_GRP)
 
-#define _VLV_TX3_DW4_CH0		0x690
-#define _VLV_TX3_DW4_CH1		0x2a90
-#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
-
-#define _VLV_TX_DW5_CH0_GRP		0x8294
-#define _VLV_TX_DW5_CH1_GRP		0x8494
+#define VLV_TX_DW5_GRP(ch)		_VLV_TX_GRP((ch), 5)
+#define VLV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
 #define   DPIO_TX_OCALINIT_EN		(1 << 31)
-#define VLV_TX_DW5_GRP(ch) _PORT(ch, _VLV_TX_DW5_CH0_GRP, _VLV_TX_DW5_CH1_GRP)
 
-#define _VLV_TX_DW11_CH0_GRP		0x82ac
-#define _VLV_TX_DW11_CH1_GRP		0x84ac
-#define VLV_TX_DW11_GRP(ch) _PORT(ch, _VLV_TX_DW11_CH0_GRP, _VLV_TX_DW11_CH1_GRP)
+#define VLV_TX_DW11_GRP(ch)		_VLV_TX_GRP((ch), 11)
+#define VLV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
 
-#define _VLV_TX_DW14_CH0_GRP		0x82b8
-#define _VLV_TX_DW14_CH1_GRP		0x84b8
-#define VLV_TX_DW14_GRP(ch) _PORT(ch, _VLV_TX_DW14_CH0_GRP, _VLV_TX_DW14_CH1_GRP)
+#define VLV_TX_DW14_GRP(ch)		_VLV_TX_GRP((ch), 14)
+#define VLV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
 
 /* CHV dpPhy registers */
-#define _CHV_PLL_DW0_CH0		0x8000
-#define _CHV_PLL_DW0_CH1		0x8180
-#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
+#define CHV_PLL_DW0(ch)			_CHV_PLL((ch), 0)
 
-#define _CHV_PLL_DW1_CH0		0x8004
-#define _CHV_PLL_DW1_CH1		0x8184
+#define CHV_PLL_DW1(ch)			_CHV_PLL((ch), 1)
 #define   DPIO_CHV_N_DIV_SHIFT		8
 #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
-#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
 
-#define _CHV_PLL_DW2_CH0		0x8008
-#define _CHV_PLL_DW2_CH1		0x8188
-#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
+#define CHV_PLL_DW2(ch)			_CHV_PLL((ch), 2)
 
-#define _CHV_PLL_DW3_CH0		0x800c
-#define _CHV_PLL_DW3_CH1		0x818c
+#define CHV_PLL_DW3(ch)			_CHV_PLL((ch), 3)
 #define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
 #define  DPIO_CHV_SECOND_MOD		(1 << 8)
 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
 #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
-#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
 
-#define _CHV_PLL_DW6_CH0		0x8018
-#define _CHV_PLL_DW6_CH1		0x8198
+#define CHV_PLL_DW6(ch)			_CHV_PLL((ch), 6)
 #define   DPIO_CHV_GAIN_CTRL_SHIFT	16
 #define	  DPIO_CHV_INT_COEFF_SHIFT	8
 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
-#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
 
-#define _CHV_PLL_DW8_CH0		0x8020
-#define _CHV_PLL_DW8_CH1		0x81A0
+#define CHV_PLL_DW8(ch)			_CHV_PLL((ch), 8)
 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
-#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
 
-#define _CHV_PLL_DW9_CH0		0x8024
-#define _CHV_PLL_DW9_CH1		0x81A4
+#define CHV_PLL_DW9(ch)			_CHV_PLL((ch), 9)
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
-#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
 
-#define CHV_CMN_DW0_CH0			0x8100
+#define CHV_CMN_DW0_CH0			_CHV_CMN(0, 0)
 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
 #define   DPIO_ALLDL_POWERDOWN			(1 << 1)
 #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
 
-#define CHV_CMN_DW5_CH0			0x8114
+#define CHV_CMN_DW5_CH0			_CHV_CMN(0, 5)
 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
 #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
 #define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
@@ -475,18 +401,18 @@
 #define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
 #define   CHV_BUFLEFTENA1_MASK		(3 << 22)
 
-#define CHV_CMN_DW13_CH0		0x8134
-#define CHV_CMN_DW0_CH1			0x8080
+#define CHV_CMN_DW13_CH0		_CHV_CMN(0, 13)
+#define CHV_CMN_DW0_CH1			_CHV_CMN(1, 0)
 #define   DPIO_CHV_S1_DIV_SHIFT		21
 #define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
 #define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
 #define   DPIO_CHV_K_DIV_SHIFT		4
 #define   DPIO_PLL_FREQLOCK		(1 << 1)
 #define   DPIO_PLL_LOCK			(1 << 0)
-#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
+#define CHV_CMN_DW13(ch)		_PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
 
-#define CHV_CMN_DW14_CH0		0x8138
-#define CHV_CMN_DW1_CH1			0x8084
+#define CHV_CMN_DW14_CH0		_CHV_CMN(0, 14)
+#define CHV_CMN_DW1_CH1			_CHV_CMN(1, 1)
 #define   DPIO_AFC_RECAL		(1 << 14)
 #define   DPIO_DCLKP_EN			(1 << 13)
 #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
@@ -497,17 +423,17 @@
 #define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
 #define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
 #define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
-#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
+#define CHV_CMN_DW14(ch)		_PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
 
-#define CHV_CMN_DW19_CH0		0x814c
-#define CHV_CMN_DW6_CH1		0x8098
+#define CHV_CMN_DW19_CH0		_CHV_CMN(0, 19)
+#define CHV_CMN_DW6_CH1			_CHV_CMN(1, 6)
 #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
 #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
 #define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
 #define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
-#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
+#define CHV_CMN_DW19(ch)		_PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
 
-#define CHV_CMN_DW28			0x8170
+#define CHV_CMN_DW28			_CHV_CMN(0, 28)
 #define   DPIO_CL1POWERDOWNEN		(1 << 23)
 #define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
 #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
@@ -515,27 +441,26 @@
 #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
 
-#define CHV_CMN_DW30			0x8178
+#define CHV_CMN_DW30			_CHV_CMN(0, 30)
 #define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
 #define   DPIO_LRC_BYPASS		(1 << 3)
 
-#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
-					(lane) * 0x200 + (offset))
+#define CHV_TX_DW0(ch, lane)		_VLV_TX((ch), (lane), 0)
+#define CHV_TX_DW1(ch, lane)		_VLV_TX((ch), (lane), 1)
+#define CHV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
+#define CHV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
+#define CHV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
+#define CHV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
+#define CHV_TX_DW6(ch, lane)		_VLV_TX((ch), (lane), 6)
+#define CHV_TX_DW7(ch, lane)		_VLV_TX((ch), (lane), 7)
+#define CHV_TX_DW8(ch, lane)		_VLV_TX((ch), (lane), 8)
+#define CHV_TX_DW9(ch, lane)		_VLV_TX((ch), (lane), 9)
+#define CHV_TX_DW10(ch, lane)		_VLV_TX((ch), (lane), 10)
 
-#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
-#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
-#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
-#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
-#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
-#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
-#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
-#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
-#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
-#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
-#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
-#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
+#define CHV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
 #define   DPIO_FRC_LATENCY_SHFIT	8
-#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
+
+#define CHV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
 #define   DPIO_UPAR_SHIFT		30
 
 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
-- 
2.43.2

[PATCH 13/14] drm/i915/dpio: Clean up the vlv/chv PHY register bits

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use REG_BIT() & co. for the vlv/chv DPIO PHY registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../i915/display/intel_display_power_well.c   |   7 +-
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  59 ++--
 drivers/gpu/drm/i915/display/intel_dpll.c     |  85 +++--
 drivers/gpu/drm/i915/i915_reg.h               | 294 ++++++++++--------
 4 files changed, 236 insertions(+), 209 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 49114afc9a61..e4ba6efc90e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1553,10 +1553,11 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
 	}
 
 	if (ch == DPIO_CH0)
-		actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
+		actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 |
+				       DPIO_ALLDL_POWERDOWN_CH0, val);
 	else
-		actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
-	actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
+		actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 |
+				       DPIO_ALLDL_POWERDOWN_CH1, val);
 
 	drm_WARN(&dev_priv->drm, actual != expected,
 		 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index fa665d353df9..11875d18a8fc 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -757,7 +757,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 	for (i = 0; i < crtc_state->lane_count; i++) {
 		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i));
 		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
-		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
+		val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value);
 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val);
 	}
 
@@ -766,15 +766,15 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
 		val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i));
 
 		val &= ~DPIO_SWING_MARGIN000_MASK;
-		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
+		val |= DPIO_SWING_MARGIN000(margin_reg_value);
 
 		/*
 		 * Supposedly this value shouldn't matter when unique transition
 		 * scale is disabled, but in fact it does matter. Let's just
 		 * always program the same value and hope it's OK.
 		 */
-		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
-		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
+		val &= ~DPIO_UNIQ_TRANS_SCALE_MASK;
+		val |= DPIO_UNIQ_TRANS_SCALE(0x9a);
 
 		vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val);
 	}
@@ -902,20 +902,20 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 
 	/* program clock channel usage */
 	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch));
-	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-	if (pipe != PIPE_B)
-		val &= ~CHV_PCS_USEDCLKCHANNEL;
+	val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;
+	if (pipe == PIPE_B)
+		val |= DPIO_PCS_USEDCLKCHANNEL;
 	else
-		val |= CHV_PCS_USEDCLKCHANNEL;
+		val &= ~DPIO_PCS_USEDCLKCHANNEL;
 	vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val);
 
 	if (crtc_state->lane_count > 2) {
 		val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch));
-		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
-		if (pipe != PIPE_B)
-			val &= ~CHV_PCS_USEDCLKCHANNEL;
+		val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;
+		if (pipe == PIPE_B)
+			val |= DPIO_PCS_USEDCLKCHANNEL;
 		else
-			val |= CHV_PCS_USEDCLKCHANNEL;
+			val &= ~DPIO_PCS_USEDCLKCHANNEL;
 		vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val);
 	}
 
@@ -925,10 +925,10 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
 	 * pick the CL based on the port.
 	 */
 	val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch));
-	if (pipe != PIPE_B)
-		val &= ~CHV_CMN_USEDCLKCHANNEL;
-	else
+	if (pipe == PIPE_B)
 		val |= CHV_CMN_USEDCLKCHANNEL;
+	else
+		val &= ~CHV_CMN_USEDCLKCHANNEL;
 	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val);
 
 	vlv_dpio_put(dev_priv);
@@ -962,11 +962,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	for (i = 0; i < crtc_state->lane_count; i++) {
 		/* Set the upar bit */
 		if (crtc_state->lane_count == 1)
-			data = 0x0;
+			data = 0;
 		else
-			data = (i == 1) ? 0x0 : 0x1;
-		vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i),
-				data << DPIO_UPAR_SHIFT);
+			data = (i == 1) ? 0 : DPIO_UPAR;
+		vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data);
 	}
 
 	/* Data lane stagger programming */
@@ -1099,13 +1098,13 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
 	vlv_dpio_get(dev_priv);
 
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
-			 DPIO_PCS_TX_LANE2_RESET |
-			 DPIO_PCS_TX_LANE1_RESET);
+		       DPIO_PCS_TX_LANE2_RESET |
+		       DPIO_PCS_TX_LANE1_RESET);
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
-			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
-			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
-			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
-				 DPIO_PCS_CLK_SOFT_RESET);
+		       DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
+		       DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
+		       DPIO_PCS_CLK_DATAWIDTH_8_10 |
+		       DPIO_PCS_CLK_SOFT_RESET);
 
 	/* Fix up inter-pair skew failure */
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);
@@ -1130,12 +1129,10 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
 	vlv_dpio_get(dev_priv);
 
 	/* Enable clock channels for this port */
-	val = 0;
-	if (pipe)
-		val |= (1<<21);
-	else
-		val &= ~(1<<21);
-	val |= 0x001000c4;
+	val = DPIO_PCS_USEDCLKCHANNEL_OVRRIDE;
+	if (pipe == PIPE_B)
+		val |= DPIO_PCS_USEDCLKCHANNEL;
+	val |= 0xc4;
 	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val);
 
 	/* Program lane clock */
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 861f4a735251..c2ee95993a96 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -527,11 +527,11 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch));
 	vlv_dpio_put(dev_priv);
 
-	clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
-	clock.m2 = tmp & DPIO_M2DIV_MASK;
-	clock.n = (tmp >> DPIO_N_SHIFT) & 0xf;
-	clock.p1 = (tmp >> DPIO_P1_SHIFT) & 7;
-	clock.p2 = (tmp >> DPIO_P2_SHIFT) & 0x1f;
+	clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);
+	clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp);
+	clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp);
+	clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp);
+	clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp);
 
 	crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
 }
@@ -559,13 +559,13 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
 	pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
 	vlv_dpio_put(dev_priv);
 
-	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
-	clock.m2 = (pll_dw0 & 0xff) << 22;
+	clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
+	clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22;
 	if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
-		clock.m2 |= pll_dw2 & 0x3fffff;
-	clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
-	clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
-	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
+		clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2);
+	clock.n = REG_FIELD_GET(DPIO_CHV_N_DIV_MASK, pll_dw1);
+	clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13);
+	clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13);
 
 	crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock);
 }
@@ -1926,19 +1926,19 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
 
 	/* Set idtafcrecal before PLL is enabled */
-	tmp = (clock->m1 << DPIO_M1DIV_SHIFT) |
-		(clock->m2 & DPIO_M2DIV_MASK) |
-		(clock->p1 << DPIO_P1_SHIFT) |
-		(clock->p2 << DPIO_P2_SHIFT) |
-		(clock->n << DPIO_N_SHIFT) |
-		(1 << DPIO_K_SHIFT);
+	tmp = DPIO_M1_DIV(clock->m1) |
+		DPIO_M2_DIV(clock->m2) |
+		DPIO_P1_DIV(clock->p1) |
+		DPIO_P2_DIV(clock->p2) |
+		DPIO_N_DIV(clock->n) |
+		DPIO_K_DIV(1);
 
 	/*
 	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
 	 * but we don't support that).
 	 * Note: don't use the DAC post divider as it seems unstable.
 	 */
-	tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
+	tmp |= DPIO_S1_DIV(DPIO_S1_DIV_HDMIDP);
 	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
 
 	tmp |= DPIO_ENABLE_CALIBRATION;
@@ -2034,34 +2034,33 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	u32 m2_frac;
 
 	m2_frac = clock->m2 & 0x3fffff;
-	loopfilter = 0;
 
 	vlv_dpio_get(dev_priv);
 
 	/* p1 and p2 divider */
 	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch),
-		       5 << DPIO_CHV_S1_DIV_SHIFT |
-		       clock->p1 << DPIO_CHV_P1_DIV_SHIFT |
-		       clock->p2 << DPIO_CHV_P2_DIV_SHIFT |
-		       1 << DPIO_CHV_K_DIV_SHIFT);
+		       DPIO_CHV_S1_DIV(5) |
+		       DPIO_CHV_P1_DIV(clock->p1) |
+		       DPIO_CHV_P2_DIV(clock->p2) |
+		       DPIO_CHV_K_DIV(1));
 
 	/* Feedback post-divider - m2 */
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch),
-		       clock->m2 >> 22);
+		       DPIO_CHV_M2_DIV(clock->m2 >> 22));
 
 	/* Feedback refclk divider - n and m1 */
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch),
-		       DPIO_CHV_M1_DIV_BY_2 |
-		       1 << DPIO_CHV_N_DIV_SHIFT);
+		       DPIO_CHV_M1_DIV(DPIO_CHV_M1_DIV_BY_2) |
+		       DPIO_CHV_N_DIV(1));
 
 	/* M2 fraction division */
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch),
-		       m2_frac);
+		       DPIO_CHV_M2_FRAC_DIV(m2_frac));
 
 	/* M2 fraction division enable */
 	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
 	tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
-	tmp |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
+	tmp |= DPIO_CHV_FEEDFWD_GAIN(2);
 	if (m2_frac)
 		tmp |= DPIO_CHV_FRAC_DIV_EN;
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp);
@@ -2069,40 +2068,40 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
 	/* Program digital lock detect threshold */
 	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch));
 	tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
-					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
-	tmp |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
+		      DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
+	tmp |= DPIO_CHV_INT_LOCK_THRESHOLD(0x5);
 	if (!m2_frac)
 		tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp);
 
 	/* Loop filter */
 	if (clock->vco == 5400000) {
-		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
-		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
-		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		loopfilter = DPIO_CHV_PROP_COEFF(0x3) |
+			DPIO_CHV_INT_COEFF(0x8) |
+			DPIO_CHV_GAIN_CTRL(0x1);
 		tribuf_calcntr = 0x9;
 	} else if (clock->vco <= 6200000) {
-		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
-		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
-		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		loopfilter = DPIO_CHV_PROP_COEFF(0x5) |
+			DPIO_CHV_INT_COEFF(0xB) |
+			DPIO_CHV_GAIN_CTRL(0x3);
 		tribuf_calcntr = 0x9;
 	} else if (clock->vco <= 6480000) {
-		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
-		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
-		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		loopfilter = DPIO_CHV_PROP_COEFF(0x4) |
+			DPIO_CHV_INT_COEFF(0x9) |
+			DPIO_CHV_GAIN_CTRL(0x3);
 		tribuf_calcntr = 0x8;
 	} else {
 		/* Not supported. Apply the same limits as in the max case */
-		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
-		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
-		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
+		loopfilter = DPIO_CHV_PROP_COEFF(0x4) |
+			DPIO_CHV_INT_COEFF(0x9) |
+			DPIO_CHV_GAIN_CTRL(0x3);
 		tribuf_calcntr = 0;
 	}
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter);
 
 	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch));
 	tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
-	tmp |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
+	tmp |= DPIO_CHV_TDC_TARGET_CNT(tribuf_calcntr);
 	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp);
 
 	/* AFC Recal */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6d16f9944eff..a2313658ecae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -211,27 +211,33 @@
  * Per pipe/PLL DPIO regs
  */
 #define VLV_PLL_DW3(ch)			_VLV_PLL((ch), 3)
-#define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
-#define   DPIO_POST_DIV_DAC		0
-#define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
-#define   DPIO_POST_DIV_LVDS1		2
-#define   DPIO_POST_DIV_LVDS2		3
-#define   DPIO_K_SHIFT			(24) /* 4 bits */
-#define   DPIO_P1_SHIFT			(21) /* 3 bits */
-#define   DPIO_P2_SHIFT			(16) /* 5 bits */
-#define   DPIO_N_SHIFT			(12) /* 4 bits */
-#define   DPIO_ENABLE_CALIBRATION	(1 << 11)
-#define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
-#define   DPIO_M2DIV_MASK		0xff
+#define   DPIO_S1_DIV_MASK		REG_GENMASK(30, 28)
+#define   DPIO_S1_DIV(s1)		REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
+#define   DPIO_S1_DIV_DAC		0 /* 10, DAC 25-225M rate */
+#define   DPIO_S1_DIV_HDMIDP		1 /* 5, DAC 225-400M rate */
+#define   DPIO_S1_DIV_LVDS1		2 /* 14 */
+#define   DPIO_S1_DIV_LVDS2		3 /* 7 */
+#define   DPIO_K_DIV_MASK		REG_GENMASK(27, 24)
+#define   DPIO_K_DIV(k)			REG_FIELD_PREP(DPIO_K_DIV_MASK, (k))
+#define   DPIO_P1_DIV_MASK		REG_GENMASK(23, 21)
+#define   DPIO_P1_DIV(p1)		REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
+#define   DPIO_P2_DIV_MASK		REG_GENMASK(20, 16)
+#define   DPIO_P2_DIV(p2)		REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
+#define   DPIO_N_DIV_MASK		REG_GENMASK(15, 12)
+#define   DPIO_N_DIV(n)			REG_FIELD_PREP(DPIO_N_DIV_MASK, (n))
+#define   DPIO_ENABLE_CALIBRATION	REG_BIT(11)
+#define   DPIO_M1_DIV_MASK		REG_GENMASK(10, 8)
+#define   DPIO_M1_DIV(m1)		REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1))
+#define   DPIO_M2_DIV_MASK		REG_GENMASK(7, 0)
+#define   DPIO_M2_DIV(m2)		REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2))
 
 #define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
-#define   DPIO_REFSEL_OVERRIDE		27
-#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
-#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
-#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
-#define   DPIO_PLL_REFCLK_SEL_MASK	3
-#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
-#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
+#define   DPIO_REFSEL_OVERRIDE		REG_BIT(27)
+#define   DPIO_PLL_MODESEL_MASK		REG_GENMASK(26, 24)
+#define   DPIO_BIAS_CURRENT_CTL_MASK	REG_GENMASK(22, 20) /* always 0x7 */
+#define   DPIO_PLL_REFCLK_SEL_MASK	REG_GENMASK(17, 16)
+#define   DPIO_DRIVER_CTL_MASK		REG_GENMASK(15, 12) /* always set to 0x8 */
+#define   DPIO_CLK_BIAS_CTL_MASK	REG_GENMASK(11, 8) /* always set to 0x5 */
 
 #define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)
 
@@ -253,101 +259,110 @@
 #define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
 #define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
 #define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
-#define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
-#define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
-#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
-#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
+#define   DPIO_PCS_TX_LANE2_RESET	REG_BIT(16)
+#define   DPIO_PCS_TX_LANE1_RESET	REG_BIT(7)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER2	REG_BIT(4)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	REG_BIT(3)
 
-#define VLV_PCS_DW1_GRP(ch)		_VLV_PCS_GRP((ch), 1)
-#define VLV_PCS01_DW1(ch)		_VLV_PCS((ch), 0, 1)
-#define VLV_PCS23_DW1(ch)		_VLV_PCS((ch), 1, 1)
-#define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
-#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
-#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
-#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
-#define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
+#define VLV_PCS_DW1_GRP(ch)		 _VLV_PCS_GRP((ch), 1)
+#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
+#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1)
+#define   CHV_PCS_REQ_SOFTRESET_EN		REG_BIT(23)
+#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN		REG_BIT(22)
+#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN	REG_BIT(21)
+#define   DPIO_PCS_CLK_DATAWIDTH_MASK		REG_GENMASK(7, 6)
+#define   DPIO_PCS_CLK_DATAWIDTH_8_10		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)
+#define   DPIO_PCS_CLK_DATAWIDTH_16_20		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
+#define   DPIO_PCS_CLK_DATAWIDTH_32_40		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)
+#define   DPIO_PCS_CLK_SOFT_RESET		REG_BIT(5)
 
 #define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
 #define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
 #define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
-#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
-#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
+#define   DPIO_PCS_USEDCLKCHANNEL		REG_BIT(21)
+#define   DPIO_PCS_USEDCLKCHANNEL_OVRRIDE	REG_BIT(20)
 
-#define VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
+#define	VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
 #define VLV_PCS01_DW9(ch)		_VLV_PCS((ch), 0, 9)
 #define VLV_PCS23_DW9(ch)		_VLV_PCS((ch), 1, 9)
-#define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
-#define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
-#define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
-#define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
-#define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
-#define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
+#define   DPIO_PCS_TX2MARGIN_MASK	REG_GENMASK(15, 13)
+#define   DPIO_PCS_TX2MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0)
+#define   DPIO_PCS_TX2MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1)
+#define   DPIO_PCS_TX1MARGIN_MASK	REG_GENMASK(12, 10)
+#define   DPIO_PCS_TX1MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0)
+#define   DPIO_PCS_TX1MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1)
 
-#define VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
+#define	VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
 #define VLV_PCS01_DW10(ch)		_VLV_PCS((ch), 0, 10)
 #define VLV_PCS23_DW10(ch)		_VLV_PCS((ch), 1, 10)
-#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
-#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
-#define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
-#define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
-#define   DPIO_PCS_TX2DEEMP_6P0		(2 << 24)
-#define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
-#define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
-#define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
+#define   DPIO_PCS_SWING_CALC_TX1_TX3	REG_BIT(31)
+#define   DPIO_PCS_SWING_CALC_TX0_TX2	REG_BIT(30)
+#define   DPIO_PCS_TX2DEEMP_MASK	REG_GENMASK(27, 24)
+#define   DPIO_PCS_TX2DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0)
+#define   DPIO_PCS_TX2DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2)
+#define   DPIO_PCS_TX1DEEMP_MASK	REG_GENMASK(19, 16)
+#define   DPIO_PCS_TX1DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0)
+#define   DPIO_PCS_TX1DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2)
 
-#define VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
+#define	VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
 #define VLV_PCS01_DW11(ch)		_VLV_PCS((ch), 0, 11)
 #define VLV_PCS23_DW11(ch)		_VLV_PCS((ch), 1, 11)
-#define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
-#define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
-#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
-#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
+#define   DPIO_TX2_STAGGER_MASK_MASK	REG_GENMASK(28, 24)
+#define   DPIO_TX2_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x))
+#define   DPIO_LANEDESKEW_STRAP_OVRD	REG_BIT(3)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER	REG_BIT(1)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER	REG_BIT(0)
 
-#define VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
+#define	VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
 #define VLV_PCS01_DW12(ch)		_VLV_PCS((ch), 0, 12)
 #define VLV_PCS23_DW12(ch)		_VLV_PCS((ch), 1, 12)
-#define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
-#define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
-#define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
-#define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
-#define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
+#define   DPIO_TX2_STAGGER_MULT_MASK	REG_GENMASK(22, 20)
+#define   DPIO_TX2_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x))
+#define   DPIO_TX1_STAGGER_MULT_MASK	REG_GENMASK(20, 16)
+#define   DPIO_TX1_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x))
+#define   DPIO_TX1_STAGGER_MASK_MASK	REG_GENMASK(12, 8)
+#define   DPIO_TX1_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x))
+#define   DPIO_LANESTAGGER_STRAP_OVRD	REG_BIT(6)
+#define   DPIO_LANESTAGGER_STRAP_MASK	REG_GENMASK(4, 0)
+#define   DPIO_LANESTAGGER_STRAP(x)	REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x))
 
-#define VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
+#define	VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
 #define VLV_PCS01_DW14(ch)		_VLV_PCS((ch), 0, 14)
 #define VLV_PCS23_DW14(ch)		_VLV_PCS((ch), 1, 14)
 
-#define VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
-#define VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
+#define	VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
+#define	VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
 #define VLV_PCS01_DW17(ch)		_VLV_PCS((ch), 0, 17)
 #define VLV_PCS23_DW17(ch)		_VLV_PCS((ch), 1, 17)
 
-#define VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
+#define	VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
 #define VLV_PCS01_DW23(ch)		_VLV_PCS((ch), 0, 23)
 #define VLV_PCS23_DW23(ch)		_VLV_PCS((ch), 1, 23)
 
 #define VLV_TX_DW2_GRP(ch)		_VLV_TX_GRP((ch), 2)
 #define VLV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
-#define   DPIO_SWING_MARGIN000_SHIFT	16
-#define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
-#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
+#define   DPIO_SWING_MARGIN000_MASK	REG_GENMASK(23, 16)
+#define   DPIO_SWING_MARGIN000(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x))
+#define   DPIO_UNIQ_TRANS_SCALE_MASK	REG_GENMASK(15, 8)
+#define   DPIO_UNIQ_TRANS_SCALE(x)	REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x))
 
 #define VLV_TX_DW3_GRP(ch)		_VLV_TX_GRP((ch), 3)
 #define VLV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
 /* The following bit for CHV phy */
-#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
-#define   DPIO_SWING_MARGIN101_SHIFT	16
-#define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
+#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	REG_BIT(27)
+#define   DPIO_SWING_MARGIN101_MASK	REG_GENMASK(23, 16)
+#define   DPIO_SWING_MARGIN101(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x))
 
 #define VLV_TX_DW4_GRP(ch)		_VLV_TX_GRP((ch), 4)
 #define VLV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
-#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
-#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
-#define   DPIO_SWING_DEEMPH6P0_SHIFT	16
-#define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
+#define   DPIO_SWING_DEEMPH9P5_MASK	REG_GENMASK(31, 24)
+#define   DPIO_SWING_DEEMPH9P5(x)	REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x))
+#define   DPIO_SWING_DEEMPH6P0_MASK	REG_GENMASK(23, 16)
+#define   DPIO_SWING_DEEMPH6P0_SHIFT	REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x))
 
 #define VLV_TX_DW5_GRP(ch)		_VLV_TX_GRP((ch), 5)
 #define VLV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
-#define   DPIO_TX_OCALINIT_EN		(1 << 31)
+#define   DPIO_TX_OCALINIT_EN		REG_BIT(31)
 
 #define VLV_TX_DW11_GRP(ch)		_VLV_TX_GRP((ch), 11)
 #define VLV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
@@ -357,93 +372,107 @@
 
 /* CHV dpPhy registers */
 #define CHV_PLL_DW0(ch)			_CHV_PLL((ch), 0)
+#define   DPIO_CHV_M2_DIV_MASK		REG_GENMASK(7, 0)
+#define   DPIO_CHV_M2_DIV(m2)		REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2))
 
 #define CHV_PLL_DW1(ch)			_CHV_PLL((ch), 1)
-#define   DPIO_CHV_N_DIV_SHIFT		8
-#define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
+#define   DPIO_CHV_N_DIV_MASK		REG_GENMASK(11, 8)
+#define   DPIO_CHV_N_DIV(n)		REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n))
+#define   DPIO_CHV_M1_DIV_MASK		REG_GENMASK(2, 0)
+#define   DPIO_CHV_M1_DIV(m1)		REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1))
+#define   DPIO_CHV_M1_DIV_BY_2		0
 
 #define CHV_PLL_DW2(ch)			_CHV_PLL((ch), 2)
+#define   DPIO_CHV_M2_FRAC_DIV_MASK	REG_GENMASK(21, 0)
+#define   DPIO_CHV_M2_FRAC_DIV(m2_frac)	REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac))
 
 #define CHV_PLL_DW3(ch)			_CHV_PLL((ch), 3)
-#define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
-#define  DPIO_CHV_FIRST_MOD		(0 << 8)
-#define  DPIO_CHV_SECOND_MOD		(1 << 8)
-#define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
-#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
+#define   DPIO_CHV_FRAC_DIV_EN		REG_BIT(16)
+#define   DPIO_CHV_SECOND_MOD		REG_BIT(8)
+#define   DPIO_CHV_FEEDFWD_GAIN_MASK	REG_GENMASK(3, 0)
+#define   DPIO_CHV_FEEDFWD_GAIN(x)	REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x))
 
 #define CHV_PLL_DW6(ch)			_CHV_PLL((ch), 6)
-#define   DPIO_CHV_GAIN_CTRL_SHIFT	16
-#define	  DPIO_CHV_INT_COEFF_SHIFT	8
-#define   DPIO_CHV_PROP_COEFF_SHIFT	0
+#define   DPIO_CHV_GAIN_CTRL_MASK	REG_GENMASK(18, 16)
+#define   DPIO_CHV_GAIN_CTRL(x)		REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x))
+#define   DPIO_CHV_INT_COEFF_MASK	REG_GENMASK(12, 8)
+#define   DPIO_CHV_INT_COEFF(x)		REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x))
+#define   DPIO_CHV_PROP_COEFF_MASK	REG_GENMASK(3, 0)
+#define   DPIO_CHV_PROP_COEFF(x)	REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x))
 
 #define CHV_PLL_DW8(ch)			_CHV_PLL((ch), 8)
-#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
-#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
+#define   DPIO_CHV_TDC_TARGET_CNT_MASK	REG_GENMASK(9, 0)
+#define   DPIO_CHV_TDC_TARGET_CNT(x)	REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x))
 
 #define CHV_PLL_DW9(ch)			_CHV_PLL((ch), 9)
-#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
-#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
-#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
+#define   DPIO_CHV_INT_LOCK_THRESHOLD_MASK		REG_GENMASK(3, 1)
+#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))
+#define   DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	REG_BIT(0) /* 1: coarse & 0 : fine  */
 
 #define CHV_CMN_DW0_CH0			_CHV_CMN(0, 0)
-#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
-#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
-#define   DPIO_ALLDL_POWERDOWN			(1 << 1)
-#define   DPIO_ANYDL_POWERDOWN			(1 << 0)
+#define   DPIO_ALLDL_POWERDOWN_CH0	REG_BIT(19)
+#define   DPIO_ANYDL_POWERDOWN_CH0	REG_BIT(18)
+#define   DPIO_ALLDL_POWERDOWN		BIT(1)
+#define   DPIO_ANYDL_POWERDOWN		BIT(0)
 
 #define CHV_CMN_DW5_CH0			_CHV_CMN(0, 5)
-#define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
-#define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
-#define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
-#define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
-#define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
-#define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
-#define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
-#define   CHV_BUFLEFTENA1_MASK		(3 << 22)
+#define   CHV_BUFRIGHTENA1_MASK		REG_GENMASK(21, 20)
+#define   CHV_BUFRIGHTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0)
+#define   CHV_BUFRIGHTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1)
+#define   CHV_BUFRIGHTENA1_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3)
+#define   CHV_BUFLEFTENA1_MASK		REG_GENMASK(23, 22)
+#define   CHV_BUFLEFTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0)
+#define   CHV_BUFLEFTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1)
+#define   CHV_BUFLEFTENA1_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3)
 
 #define CHV_CMN_DW13_CH0		_CHV_CMN(0, 13)
 #define CHV_CMN_DW0_CH1			_CHV_CMN(1, 0)
-#define   DPIO_CHV_S1_DIV_SHIFT		21
-#define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
-#define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
-#define   DPIO_CHV_K_DIV_SHIFT		4
-#define   DPIO_PLL_FREQLOCK		(1 << 1)
-#define   DPIO_PLL_LOCK			(1 << 0)
+#define   DPIO_CHV_S1_DIV_MASK		REG_GENMASK(23, 21)
+#define   DPIO_CHV_S1_DIV(s1)		REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1))
+#define   DPIO_CHV_P1_DIV_MASK		REG_GENMASK(15, 13)
+#define   DPIO_CHV_P1_DIV(p1)		REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1))
+#define   DPIO_CHV_P2_DIV_MASK		REG_GENMASK(12, 8)
+#define   DPIO_CHV_P2_DIV(p2)		REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2))
+#define   DPIO_CHV_K_DIV_MASK		REG_GENMASK(7, 4)
+#define   DPIO_CHV_K_DIV(k)		REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))
+#define   DPIO_PLL_FREQLOCK		REG_BIT(1)
+#define   DPIO_PLL_LOCK			REG_BIT(0)
 #define CHV_CMN_DW13(ch)		_PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
 
 #define CHV_CMN_DW14_CH0		_CHV_CMN(0, 14)
 #define CHV_CMN_DW1_CH1			_CHV_CMN(1, 1)
-#define   DPIO_AFC_RECAL		(1 << 14)
-#define   DPIO_DCLKP_EN			(1 << 13)
-#define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
-#define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
-#define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
-#define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
-#define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
-#define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
-#define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
-#define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
+#define   DPIO_AFC_RECAL		REG_BIT(14)
+#define   DPIO_DCLKP_EN			REG_BIT(13)
+#define   CHV_BUFLEFTENA2_MASK		REG_GENMASK(18, 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0)
+#define   CHV_BUFLEFTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1)
+#define   CHV_BUFLEFTENA2_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3)
+#define   CHV_BUFRIGHTENA2_MASK		REG_GENMASK(20, 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0)
+#define   CHV_BUFRIGHTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1)
+#define   CHV_BUFRIGHTENA2_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3)
 #define CHV_CMN_DW14(ch)		_PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
 
 #define CHV_CMN_DW19_CH0		_CHV_CMN(0, 19)
 #define CHV_CMN_DW6_CH1			_CHV_CMN(1, 6)
-#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
-#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
-#define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
-#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
+#define   DPIO_ALLDL_POWERDOWN_CH1	REG_BIT(30) /* CL2 DW6 only */
+#define   DPIO_ANYDL_POWERDOWN_CH1	REG_BIT(29) /* CL2 DW6 only */
+#define   DPIO_DYNPWRDOWNEN_CH1		REG_BIT(28) /* CL2 DW6 only */
+#define   CHV_CMN_USEDCLKCHANNEL	REG_BIT(13)
 #define CHV_CMN_DW19(ch)		_PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
 
 #define CHV_CMN_DW28			_CHV_CMN(0, 28)
-#define   DPIO_CL1POWERDOWNEN		(1 << 23)
-#define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
-#define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
-#define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
-#define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
-#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
+#define   DPIO_CL1POWERDOWNEN			REG_BIT(23)
+#define   DPIO_DYNPWRDOWNEN_CH0			REG_BIT(22)
+#define   DPIO_SUS_CLK_CONFIG_MASK		REG_GENMASK(1, 0)
+#define   DPIO_SUS_CLK_CONFIG_ON		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0)
+#define   DPIO_SUS_CLK_CONFIG_CLKREQ		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1)
+#define   DPIO_SUS_CLK_CONFIG_GATE		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2)
+#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3)
 
 #define CHV_CMN_DW30			_CHV_CMN(0, 30)
-#define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
-#define   DPIO_LRC_BYPASS		(1 << 3)
+#define   DPIO_CL2_LDOFUSE_PWRENB	REG_BIT(6)
+#define   DPIO_LRC_BYPASS		REG_BIT(3)
 
 #define CHV_TX_DW0(ch, lane)		_VLV_TX((ch), (lane), 0)
 #define CHV_TX_DW1(ch, lane)		_VLV_TX((ch), (lane), 1)
@@ -458,10 +487,11 @@
 #define CHV_TX_DW10(ch, lane)		_VLV_TX((ch), (lane), 10)
 
 #define CHV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
-#define   DPIO_FRC_LATENCY_SHFIT	8
+#define   DPIO_FRC_LATENCY_MASK		REG_GENMASK(10, 8)
+#define   DPIO_FRC_LATENCY(x)		REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x))
 
 #define CHV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
-#define   DPIO_UPAR_SHIFT		30
+#define   DPIO_UPAR			REG_BIT(30)
 
 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
 #define  MIPIO_RST_CTRL				(1 << 2)
-- 
2.43.2

[PATCH 14/14] drm/i915/dpio: Extract vlv_dpio_phy_regs.h

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the VLV/CHV DPIO PHY sideband registers to their own file.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |   1 +
 .../i915/display/intel_display_power_well.c   |   1 +
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |   1 +
 drivers/gpu/drm/i915/display/intel_dpll.c     |   1 +
 .../gpu/drm/i915/display/vlv_dpio_phy_regs.h  | 309 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 298 -----------------
 6 files changed, 313 insertions(+), 298 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 96ed1490fec7..59f989207c74 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -120,6 +120,7 @@
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 #include "skl_watermark.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_dsi.h"
 #include "vlv_dsi_pll.h"
 #include "vlv_dsi_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index e4ba6efc90e6..83f616097a29 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -27,6 +27,7 @@
 #include "intel_tc.h"
 #include "intel_vga.h"
 #include "skl_watermark.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_sideband.h"
 #include "vlv_sideband_reg.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 11875d18a8fc..d20e4e9cf7f7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -30,6 +30,7 @@
 #include "intel_display_types.h"
 #include "intel_dp.h"
 #include "intel_dpio_phy.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_sideband.h"
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index c2ee95993a96..a981f45facb3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -20,6 +20,7 @@
 #include "intel_panel.h"
 #include "intel_pps.h"
 #include "intel_snps_phy.h"
+#include "vlv_dpio_phy_regs.h"
 #include "vlv_sideband.h"
 
 struct intel_dpll_funcs {
diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
new file mode 100644
index 000000000000..477506f0b2cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __VLV_DPIO_PHY_REGS_H__
+#define __VLV_DPIO_PHY_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
+#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
+#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
+#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
+#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
+#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4)
+#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
+#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4)
+#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
+#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
+
+/*
+ * Per pipe/PLL DPIO regs
+ */
+#define VLV_PLL_DW3(ch)			_VLV_PLL((ch), 3)
+#define   DPIO_S1_DIV_MASK		REG_GENMASK(30, 28)
+#define   DPIO_S1_DIV(s1)		REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
+#define   DPIO_S1_DIV_DAC		0 /* 10, DAC 25-225M rate */
+#define   DPIO_S1_DIV_HDMIDP		1 /* 5, DAC 225-400M rate */
+#define   DPIO_S1_DIV_LVDS1		2 /* 14 */
+#define   DPIO_S1_DIV_LVDS2		3 /* 7 */
+#define   DPIO_K_DIV_MASK		REG_GENMASK(27, 24)
+#define   DPIO_K_DIV(k)			REG_FIELD_PREP(DPIO_K_DIV_MASK, (k))
+#define   DPIO_P1_DIV_MASK		REG_GENMASK(23, 21)
+#define   DPIO_P1_DIV(p1)		REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
+#define   DPIO_P2_DIV_MASK		REG_GENMASK(20, 16)
+#define   DPIO_P2_DIV(p2)		REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
+#define   DPIO_N_DIV_MASK		REG_GENMASK(15, 12)
+#define   DPIO_N_DIV(n)			REG_FIELD_PREP(DPIO_N_DIV_MASK, (n))
+#define   DPIO_ENABLE_CALIBRATION	REG_BIT(11)
+#define   DPIO_M1_DIV_MASK		REG_GENMASK(10, 8)
+#define   DPIO_M1_DIV(m1)		REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1))
+#define   DPIO_M2_DIV_MASK		REG_GENMASK(7, 0)
+#define   DPIO_M2_DIV(m2)		REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2))
+
+#define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
+#define   DPIO_REFSEL_OVERRIDE		REG_BIT(27)
+#define   DPIO_PLL_MODESEL_MASK		REG_GENMASK(26, 24)
+#define   DPIO_BIAS_CURRENT_CTL_MASK	REG_GENMASK(22, 20) /* always 0x7 */
+#define   DPIO_PLL_REFCLK_SEL_MASK	REG_GENMASK(17, 16)
+#define   DPIO_DRIVER_CTL_MASK		REG_GENMASK(15, 12) /* always set to 0x8 */
+#define   DPIO_CLK_BIAS_CTL_MASK	REG_GENMASK(11, 8) /* always set to 0x5 */
+
+#define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)
+
+#define VLV_PLL_DW16(ch)		_VLV_PLL((ch), 16)
+
+#define VLV_PLL_DW17(ch)		_VLV_PLL((ch), 17)
+
+#define VLV_PLL_DW18(ch)		_VLV_PLL((ch), 18)
+
+#define VLV_PLL_DW19(ch)		_VLV_PLL((ch), 19)
+
+#define VLV_REF_DW11			_VLV_REF(11)
+
+#define VLV_CMN_DW0			_VLV_CMN(0)
+
+/*
+ * Per DDI channel DPIO regs
+ */
+#define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
+#define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
+#define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
+#define   DPIO_PCS_TX_LANE2_RESET	REG_BIT(16)
+#define   DPIO_PCS_TX_LANE1_RESET	REG_BIT(7)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER2	REG_BIT(4)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	REG_BIT(3)
+
+#define VLV_PCS_DW1_GRP(ch)		 _VLV_PCS_GRP((ch), 1)
+#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
+#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1)
+#define   CHV_PCS_REQ_SOFTRESET_EN		REG_BIT(23)
+#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN		REG_BIT(22)
+#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN	REG_BIT(21)
+#define   DPIO_PCS_CLK_DATAWIDTH_MASK		REG_GENMASK(7, 6)
+#define   DPIO_PCS_CLK_DATAWIDTH_8_10		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)
+#define   DPIO_PCS_CLK_DATAWIDTH_16_20		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
+#define   DPIO_PCS_CLK_DATAWIDTH_32_40		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)
+#define   DPIO_PCS_CLK_SOFT_RESET		REG_BIT(5)
+
+#define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
+#define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
+#define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
+#define   DPIO_PCS_USEDCLKCHANNEL		REG_BIT(21)
+#define   DPIO_PCS_USEDCLKCHANNEL_OVRRIDE	REG_BIT(20)
+
+#define	VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
+#define VLV_PCS01_DW9(ch)		_VLV_PCS((ch), 0, 9)
+#define VLV_PCS23_DW9(ch)		_VLV_PCS((ch), 1, 9)
+#define   DPIO_PCS_TX2MARGIN_MASK	REG_GENMASK(15, 13)
+#define   DPIO_PCS_TX2MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0)
+#define   DPIO_PCS_TX2MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1)
+#define   DPIO_PCS_TX1MARGIN_MASK	REG_GENMASK(12, 10)
+#define   DPIO_PCS_TX1MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0)
+#define   DPIO_PCS_TX1MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1)
+
+#define	VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
+#define VLV_PCS01_DW10(ch)		_VLV_PCS((ch), 0, 10)
+#define VLV_PCS23_DW10(ch)		_VLV_PCS((ch), 1, 10)
+#define   DPIO_PCS_SWING_CALC_TX1_TX3	REG_BIT(31)
+#define   DPIO_PCS_SWING_CALC_TX0_TX2	REG_BIT(30)
+#define   DPIO_PCS_TX2DEEMP_MASK	REG_GENMASK(27, 24)
+#define   DPIO_PCS_TX2DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0)
+#define   DPIO_PCS_TX2DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2)
+#define   DPIO_PCS_TX1DEEMP_MASK	REG_GENMASK(19, 16)
+#define   DPIO_PCS_TX1DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0)
+#define   DPIO_PCS_TX1DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2)
+
+#define	VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
+#define VLV_PCS01_DW11(ch)		_VLV_PCS((ch), 0, 11)
+#define VLV_PCS23_DW11(ch)		_VLV_PCS((ch), 1, 11)
+#define   DPIO_TX2_STAGGER_MASK_MASK	REG_GENMASK(28, 24)
+#define   DPIO_TX2_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x))
+#define   DPIO_LANEDESKEW_STRAP_OVRD	REG_BIT(3)
+#define   DPIO_LEFT_TXFIFO_RST_MASTER	REG_BIT(1)
+#define   DPIO_RIGHT_TXFIFO_RST_MASTER	REG_BIT(0)
+
+#define	VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
+#define VLV_PCS01_DW12(ch)		_VLV_PCS((ch), 0, 12)
+#define VLV_PCS23_DW12(ch)		_VLV_PCS((ch), 1, 12)
+#define   DPIO_TX2_STAGGER_MULT_MASK	REG_GENMASK(22, 20)
+#define   DPIO_TX2_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x))
+#define   DPIO_TX1_STAGGER_MULT_MASK	REG_GENMASK(20, 16)
+#define   DPIO_TX1_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x))
+#define   DPIO_TX1_STAGGER_MASK_MASK	REG_GENMASK(12, 8)
+#define   DPIO_TX1_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x))
+#define   DPIO_LANESTAGGER_STRAP_OVRD	REG_BIT(6)
+#define   DPIO_LANESTAGGER_STRAP_MASK	REG_GENMASK(4, 0)
+#define   DPIO_LANESTAGGER_STRAP(x)	REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x))
+
+#define	VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
+#define VLV_PCS01_DW14(ch)		_VLV_PCS((ch), 0, 14)
+#define VLV_PCS23_DW14(ch)		_VLV_PCS((ch), 1, 14)
+
+#define	VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
+#define	VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
+#define VLV_PCS01_DW17(ch)		_VLV_PCS((ch), 0, 17)
+#define VLV_PCS23_DW17(ch)		_VLV_PCS((ch), 1, 17)
+
+#define	VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
+#define VLV_PCS01_DW23(ch)		_VLV_PCS((ch), 0, 23)
+#define VLV_PCS23_DW23(ch)		_VLV_PCS((ch), 1, 23)
+
+#define VLV_TX_DW2_GRP(ch)		_VLV_TX_GRP((ch), 2)
+#define VLV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
+#define   DPIO_SWING_MARGIN000_MASK	REG_GENMASK(23, 16)
+#define   DPIO_SWING_MARGIN000(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x))
+#define   DPIO_UNIQ_TRANS_SCALE_MASK	REG_GENMASK(15, 8)
+#define   DPIO_UNIQ_TRANS_SCALE(x)	REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x))
+
+#define VLV_TX_DW3_GRP(ch)		_VLV_TX_GRP((ch), 3)
+#define VLV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
+/* The following bit for CHV phy */
+#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	REG_BIT(27)
+#define   DPIO_SWING_MARGIN101_MASK	REG_GENMASK(23, 16)
+#define   DPIO_SWING_MARGIN101(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x))
+
+#define VLV_TX_DW4_GRP(ch)		_VLV_TX_GRP((ch), 4)
+#define VLV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
+#define   DPIO_SWING_DEEMPH9P5_MASK	REG_GENMASK(31, 24)
+#define   DPIO_SWING_DEEMPH9P5(x)	REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x))
+#define   DPIO_SWING_DEEMPH6P0_MASK	REG_GENMASK(23, 16)
+#define   DPIO_SWING_DEEMPH6P0_SHIFT	REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x))
+
+#define VLV_TX_DW5_GRP(ch)		_VLV_TX_GRP((ch), 5)
+#define VLV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
+#define   DPIO_TX_OCALINIT_EN		REG_BIT(31)
+
+#define VLV_TX_DW11_GRP(ch)		_VLV_TX_GRP((ch), 11)
+#define VLV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
+
+#define VLV_TX_DW14_GRP(ch)		_VLV_TX_GRP((ch), 14)
+#define VLV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
+
+/* CHV dpPhy registers */
+#define CHV_PLL_DW0(ch)			_CHV_PLL((ch), 0)
+#define   DPIO_CHV_M2_DIV_MASK		REG_GENMASK(7, 0)
+#define   DPIO_CHV_M2_DIV(m2)		REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2))
+
+#define CHV_PLL_DW1(ch)			_CHV_PLL((ch), 1)
+#define   DPIO_CHV_N_DIV_MASK		REG_GENMASK(11, 8)
+#define   DPIO_CHV_N_DIV(n)		REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n))
+#define   DPIO_CHV_M1_DIV_MASK		REG_GENMASK(2, 0)
+#define   DPIO_CHV_M1_DIV(m1)		REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1))
+#define   DPIO_CHV_M1_DIV_BY_2		0
+
+#define CHV_PLL_DW2(ch)			_CHV_PLL((ch), 2)
+#define   DPIO_CHV_M2_FRAC_DIV_MASK	REG_GENMASK(21, 0)
+#define   DPIO_CHV_M2_FRAC_DIV(m2_frac)	REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac))
+
+#define CHV_PLL_DW3(ch)			_CHV_PLL((ch), 3)
+#define   DPIO_CHV_FRAC_DIV_EN		REG_BIT(16)
+#define   DPIO_CHV_SECOND_MOD		REG_BIT(8)
+#define   DPIO_CHV_FEEDFWD_GAIN_MASK	REG_GENMASK(3, 0)
+#define   DPIO_CHV_FEEDFWD_GAIN(x)	REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x))
+
+#define CHV_PLL_DW6(ch)			_CHV_PLL((ch), 6)
+#define   DPIO_CHV_GAIN_CTRL_MASK	REG_GENMASK(18, 16)
+#define   DPIO_CHV_GAIN_CTRL(x)		REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x))
+#define   DPIO_CHV_INT_COEFF_MASK	REG_GENMASK(12, 8)
+#define   DPIO_CHV_INT_COEFF(x)		REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x))
+#define   DPIO_CHV_PROP_COEFF_MASK	REG_GENMASK(3, 0)
+#define   DPIO_CHV_PROP_COEFF(x)	REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x))
+
+#define CHV_PLL_DW8(ch)			_CHV_PLL((ch), 8)
+#define   DPIO_CHV_TDC_TARGET_CNT_MASK	REG_GENMASK(9, 0)
+#define   DPIO_CHV_TDC_TARGET_CNT(x)	REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x))
+
+#define CHV_PLL_DW9(ch)			_CHV_PLL((ch), 9)
+#define   DPIO_CHV_INT_LOCK_THRESHOLD_MASK		REG_GENMASK(3, 1)
+#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))
+#define   DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	REG_BIT(0) /* 1: coarse & 0 : fine  */
+
+#define CHV_CMN_DW0_CH0			_CHV_CMN(0, 0)
+#define   DPIO_ALLDL_POWERDOWN_CH0	REG_BIT(19)
+#define   DPIO_ANYDL_POWERDOWN_CH0	REG_BIT(18)
+#define   DPIO_ALLDL_POWERDOWN		BIT(1)
+#define   DPIO_ANYDL_POWERDOWN		BIT(0)
+
+#define CHV_CMN_DW5_CH0			_CHV_CMN(0, 5)
+#define   CHV_BUFRIGHTENA1_MASK		REG_GENMASK(21, 20)
+#define   CHV_BUFRIGHTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0)
+#define   CHV_BUFRIGHTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1)
+#define   CHV_BUFRIGHTENA1_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3)
+#define   CHV_BUFLEFTENA1_MASK		REG_GENMASK(23, 22)
+#define   CHV_BUFLEFTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0)
+#define   CHV_BUFLEFTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1)
+#define   CHV_BUFLEFTENA1_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3)
+
+#define CHV_CMN_DW13_CH0		_CHV_CMN(0, 13)
+#define CHV_CMN_DW0_CH1			_CHV_CMN(1, 0)
+#define   DPIO_CHV_S1_DIV_MASK		REG_GENMASK(23, 21)
+#define   DPIO_CHV_S1_DIV(s1)		REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1))
+#define   DPIO_CHV_P1_DIV_MASK		REG_GENMASK(15, 13)
+#define   DPIO_CHV_P1_DIV(p1)		REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1))
+#define   DPIO_CHV_P2_DIV_MASK		REG_GENMASK(12, 8)
+#define   DPIO_CHV_P2_DIV(p2)		REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2))
+#define   DPIO_CHV_K_DIV_MASK		REG_GENMASK(7, 4)
+#define   DPIO_CHV_K_DIV(k)		REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))
+#define   DPIO_PLL_FREQLOCK		REG_BIT(1)
+#define   DPIO_PLL_LOCK			REG_BIT(0)
+#define CHV_CMN_DW13(ch)		_PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
+
+#define CHV_CMN_DW14_CH0		_CHV_CMN(0, 14)
+#define CHV_CMN_DW1_CH1			_CHV_CMN(1, 1)
+#define   DPIO_AFC_RECAL		REG_BIT(14)
+#define   DPIO_DCLKP_EN			REG_BIT(13)
+#define   CHV_BUFLEFTENA2_MASK		REG_GENMASK(18, 17) /* CL2 DW1 only */
+#define   CHV_BUFLEFTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0)
+#define   CHV_BUFLEFTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1)
+#define   CHV_BUFLEFTENA2_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3)
+#define   CHV_BUFRIGHTENA2_MASK		REG_GENMASK(20, 19) /* CL2 DW1 only */
+#define   CHV_BUFRIGHTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0)
+#define   CHV_BUFRIGHTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1)
+#define   CHV_BUFRIGHTENA2_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3)
+#define CHV_CMN_DW14(ch)		_PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
+
+#define CHV_CMN_DW19_CH0		_CHV_CMN(0, 19)
+#define CHV_CMN_DW6_CH1			_CHV_CMN(1, 6)
+#define   DPIO_ALLDL_POWERDOWN_CH1	REG_BIT(30) /* CL2 DW6 only */
+#define   DPIO_ANYDL_POWERDOWN_CH1	REG_BIT(29) /* CL2 DW6 only */
+#define   DPIO_DYNPWRDOWNEN_CH1		REG_BIT(28) /* CL2 DW6 only */
+#define   CHV_CMN_USEDCLKCHANNEL	REG_BIT(13)
+#define CHV_CMN_DW19(ch)		_PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
+
+#define CHV_CMN_DW28			_CHV_CMN(0, 28)
+#define   DPIO_CL1POWERDOWNEN			REG_BIT(23)
+#define   DPIO_DYNPWRDOWNEN_CH0			REG_BIT(22)
+#define   DPIO_SUS_CLK_CONFIG_MASK		REG_GENMASK(1, 0)
+#define   DPIO_SUS_CLK_CONFIG_ON		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0)
+#define   DPIO_SUS_CLK_CONFIG_CLKREQ		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1)
+#define   DPIO_SUS_CLK_CONFIG_GATE		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2)
+#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3)
+
+#define CHV_CMN_DW30			_CHV_CMN(0, 30)
+#define   DPIO_CL2_LDOFUSE_PWRENB	REG_BIT(6)
+#define   DPIO_LRC_BYPASS		REG_BIT(3)
+
+#define CHV_TX_DW0(ch, lane)		_VLV_TX((ch), (lane), 0)
+#define CHV_TX_DW1(ch, lane)		_VLV_TX((ch), (lane), 1)
+#define CHV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
+#define CHV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
+#define CHV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
+#define CHV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
+#define CHV_TX_DW6(ch, lane)		_VLV_TX((ch), (lane), 6)
+#define CHV_TX_DW7(ch, lane)		_VLV_TX((ch), (lane), 7)
+#define CHV_TX_DW8(ch, lane)		_VLV_TX((ch), (lane), 8)
+#define CHV_TX_DW9(ch, lane)		_VLV_TX((ch), (lane), 9)
+#define CHV_TX_DW10(ch, lane)		_VLV_TX((ch), (lane), 10)
+
+#define CHV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
+#define   DPIO_FRC_LATENCY_MASK		REG_GENMASK(10, 8)
+#define   DPIO_FRC_LATENCY(x)		REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x))
+
+#define CHV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
+#define   DPIO_UPAR			REG_BIT(30)
+
+#endif /* __VLV_DPIO_PHY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a2313658ecae..481ae5529ba2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -195,304 +195,6 @@
 #define  DPIO_SFR_BYPASS		(1 << 1)
 #define  DPIO_CMNRST			(1 << 0)
 
-#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
-#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
-#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
-#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
-#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
-#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4)
-#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
-#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
-#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4)
-#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
-#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
-
-/*
- * Per pipe/PLL DPIO regs
- */
-#define VLV_PLL_DW3(ch)			_VLV_PLL((ch), 3)
-#define   DPIO_S1_DIV_MASK		REG_GENMASK(30, 28)
-#define   DPIO_S1_DIV(s1)		REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
-#define   DPIO_S1_DIV_DAC		0 /* 10, DAC 25-225M rate */
-#define   DPIO_S1_DIV_HDMIDP		1 /* 5, DAC 225-400M rate */
-#define   DPIO_S1_DIV_LVDS1		2 /* 14 */
-#define   DPIO_S1_DIV_LVDS2		3 /* 7 */
-#define   DPIO_K_DIV_MASK		REG_GENMASK(27, 24)
-#define   DPIO_K_DIV(k)			REG_FIELD_PREP(DPIO_K_DIV_MASK, (k))
-#define   DPIO_P1_DIV_MASK		REG_GENMASK(23, 21)
-#define   DPIO_P1_DIV(p1)		REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
-#define   DPIO_P2_DIV_MASK		REG_GENMASK(20, 16)
-#define   DPIO_P2_DIV(p2)		REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
-#define   DPIO_N_DIV_MASK		REG_GENMASK(15, 12)
-#define   DPIO_N_DIV(n)			REG_FIELD_PREP(DPIO_N_DIV_MASK, (n))
-#define   DPIO_ENABLE_CALIBRATION	REG_BIT(11)
-#define   DPIO_M1_DIV_MASK		REG_GENMASK(10, 8)
-#define   DPIO_M1_DIV(m1)		REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1))
-#define   DPIO_M2_DIV_MASK		REG_GENMASK(7, 0)
-#define   DPIO_M2_DIV(m2)		REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2))
-
-#define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
-#define   DPIO_REFSEL_OVERRIDE		REG_BIT(27)
-#define   DPIO_PLL_MODESEL_MASK		REG_GENMASK(26, 24)
-#define   DPIO_BIAS_CURRENT_CTL_MASK	REG_GENMASK(22, 20) /* always 0x7 */
-#define   DPIO_PLL_REFCLK_SEL_MASK	REG_GENMASK(17, 16)
-#define   DPIO_DRIVER_CTL_MASK		REG_GENMASK(15, 12) /* always set to 0x8 */
-#define   DPIO_CLK_BIAS_CTL_MASK	REG_GENMASK(11, 8) /* always set to 0x5 */
-
-#define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)
-
-#define VLV_PLL_DW16(ch)		_VLV_PLL((ch), 16)
-
-#define VLV_PLL_DW17(ch)		_VLV_PLL((ch), 17)
-
-#define VLV_PLL_DW18(ch)		_VLV_PLL((ch), 18)
-
-#define VLV_PLL_DW19(ch)		_VLV_PLL((ch), 19)
-
-#define VLV_REF_DW11			_VLV_REF(11)
-
-#define VLV_CMN_DW0			_VLV_CMN(0)
-
-/*
- * Per DDI channel DPIO regs
- */
-#define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
-#define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
-#define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
-#define   DPIO_PCS_TX_LANE2_RESET	REG_BIT(16)
-#define   DPIO_PCS_TX_LANE1_RESET	REG_BIT(7)
-#define   DPIO_LEFT_TXFIFO_RST_MASTER2	REG_BIT(4)
-#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	REG_BIT(3)
-
-#define VLV_PCS_DW1_GRP(ch)		 _VLV_PCS_GRP((ch), 1)
-#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
-#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1)
-#define   CHV_PCS_REQ_SOFTRESET_EN		REG_BIT(23)
-#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN		REG_BIT(22)
-#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN	REG_BIT(21)
-#define   DPIO_PCS_CLK_DATAWIDTH_MASK		REG_GENMASK(7, 6)
-#define   DPIO_PCS_CLK_DATAWIDTH_8_10		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)
-#define   DPIO_PCS_CLK_DATAWIDTH_16_20		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
-#define   DPIO_PCS_CLK_DATAWIDTH_32_40		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)
-#define   DPIO_PCS_CLK_SOFT_RESET		REG_BIT(5)
-
-#define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
-#define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
-#define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
-#define   DPIO_PCS_USEDCLKCHANNEL		REG_BIT(21)
-#define   DPIO_PCS_USEDCLKCHANNEL_OVRRIDE	REG_BIT(20)
-
-#define	VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
-#define VLV_PCS01_DW9(ch)		_VLV_PCS((ch), 0, 9)
-#define VLV_PCS23_DW9(ch)		_VLV_PCS((ch), 1, 9)
-#define   DPIO_PCS_TX2MARGIN_MASK	REG_GENMASK(15, 13)
-#define   DPIO_PCS_TX2MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0)
-#define   DPIO_PCS_TX2MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1)
-#define   DPIO_PCS_TX1MARGIN_MASK	REG_GENMASK(12, 10)
-#define   DPIO_PCS_TX1MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0)
-#define   DPIO_PCS_TX1MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1)
-
-#define	VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
-#define VLV_PCS01_DW10(ch)		_VLV_PCS((ch), 0, 10)
-#define VLV_PCS23_DW10(ch)		_VLV_PCS((ch), 1, 10)
-#define   DPIO_PCS_SWING_CALC_TX1_TX3	REG_BIT(31)
-#define   DPIO_PCS_SWING_CALC_TX0_TX2	REG_BIT(30)
-#define   DPIO_PCS_TX2DEEMP_MASK	REG_GENMASK(27, 24)
-#define   DPIO_PCS_TX2DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0)
-#define   DPIO_PCS_TX2DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2)
-#define   DPIO_PCS_TX1DEEMP_MASK	REG_GENMASK(19, 16)
-#define   DPIO_PCS_TX1DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0)
-#define   DPIO_PCS_TX1DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2)
-
-#define	VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
-#define VLV_PCS01_DW11(ch)		_VLV_PCS((ch), 0, 11)
-#define VLV_PCS23_DW11(ch)		_VLV_PCS((ch), 1, 11)
-#define   DPIO_TX2_STAGGER_MASK_MASK	REG_GENMASK(28, 24)
-#define   DPIO_TX2_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x))
-#define   DPIO_LANEDESKEW_STRAP_OVRD	REG_BIT(3)
-#define   DPIO_LEFT_TXFIFO_RST_MASTER	REG_BIT(1)
-#define   DPIO_RIGHT_TXFIFO_RST_MASTER	REG_BIT(0)
-
-#define	VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
-#define VLV_PCS01_DW12(ch)		_VLV_PCS((ch), 0, 12)
-#define VLV_PCS23_DW12(ch)		_VLV_PCS((ch), 1, 12)
-#define   DPIO_TX2_STAGGER_MULT_MASK	REG_GENMASK(22, 20)
-#define   DPIO_TX2_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x))
-#define   DPIO_TX1_STAGGER_MULT_MASK	REG_GENMASK(20, 16)
-#define   DPIO_TX1_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x))
-#define   DPIO_TX1_STAGGER_MASK_MASK	REG_GENMASK(12, 8)
-#define   DPIO_TX1_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x))
-#define   DPIO_LANESTAGGER_STRAP_OVRD	REG_BIT(6)
-#define   DPIO_LANESTAGGER_STRAP_MASK	REG_GENMASK(4, 0)
-#define   DPIO_LANESTAGGER_STRAP(x)	REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x))
-
-#define	VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
-#define VLV_PCS01_DW14(ch)		_VLV_PCS((ch), 0, 14)
-#define VLV_PCS23_DW14(ch)		_VLV_PCS((ch), 1, 14)
-
-#define	VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
-#define	VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
-#define VLV_PCS01_DW17(ch)		_VLV_PCS((ch), 0, 17)
-#define VLV_PCS23_DW17(ch)		_VLV_PCS((ch), 1, 17)
-
-#define	VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
-#define VLV_PCS01_DW23(ch)		_VLV_PCS((ch), 0, 23)
-#define VLV_PCS23_DW23(ch)		_VLV_PCS((ch), 1, 23)
-
-#define VLV_TX_DW2_GRP(ch)		_VLV_TX_GRP((ch), 2)
-#define VLV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
-#define   DPIO_SWING_MARGIN000_MASK	REG_GENMASK(23, 16)
-#define   DPIO_SWING_MARGIN000(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x))
-#define   DPIO_UNIQ_TRANS_SCALE_MASK	REG_GENMASK(15, 8)
-#define   DPIO_UNIQ_TRANS_SCALE(x)	REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x))
-
-#define VLV_TX_DW3_GRP(ch)		_VLV_TX_GRP((ch), 3)
-#define VLV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
-/* The following bit for CHV phy */
-#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	REG_BIT(27)
-#define   DPIO_SWING_MARGIN101_MASK	REG_GENMASK(23, 16)
-#define   DPIO_SWING_MARGIN101(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x))
-
-#define VLV_TX_DW4_GRP(ch)		_VLV_TX_GRP((ch), 4)
-#define VLV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
-#define   DPIO_SWING_DEEMPH9P5_MASK	REG_GENMASK(31, 24)
-#define   DPIO_SWING_DEEMPH9P5(x)	REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x))
-#define   DPIO_SWING_DEEMPH6P0_MASK	REG_GENMASK(23, 16)
-#define   DPIO_SWING_DEEMPH6P0_SHIFT	REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x))
-
-#define VLV_TX_DW5_GRP(ch)		_VLV_TX_GRP((ch), 5)
-#define VLV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
-#define   DPIO_TX_OCALINIT_EN		REG_BIT(31)
-
-#define VLV_TX_DW11_GRP(ch)		_VLV_TX_GRP((ch), 11)
-#define VLV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
-
-#define VLV_TX_DW14_GRP(ch)		_VLV_TX_GRP((ch), 14)
-#define VLV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
-
-/* CHV dpPhy registers */
-#define CHV_PLL_DW0(ch)			_CHV_PLL((ch), 0)
-#define   DPIO_CHV_M2_DIV_MASK		REG_GENMASK(7, 0)
-#define   DPIO_CHV_M2_DIV(m2)		REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2))
-
-#define CHV_PLL_DW1(ch)			_CHV_PLL((ch), 1)
-#define   DPIO_CHV_N_DIV_MASK		REG_GENMASK(11, 8)
-#define   DPIO_CHV_N_DIV(n)		REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n))
-#define   DPIO_CHV_M1_DIV_MASK		REG_GENMASK(2, 0)
-#define   DPIO_CHV_M1_DIV(m1)		REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1))
-#define   DPIO_CHV_M1_DIV_BY_2		0
-
-#define CHV_PLL_DW2(ch)			_CHV_PLL((ch), 2)
-#define   DPIO_CHV_M2_FRAC_DIV_MASK	REG_GENMASK(21, 0)
-#define   DPIO_CHV_M2_FRAC_DIV(m2_frac)	REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac))
-
-#define CHV_PLL_DW3(ch)			_CHV_PLL((ch), 3)
-#define   DPIO_CHV_FRAC_DIV_EN		REG_BIT(16)
-#define   DPIO_CHV_SECOND_MOD		REG_BIT(8)
-#define   DPIO_CHV_FEEDFWD_GAIN_MASK	REG_GENMASK(3, 0)
-#define   DPIO_CHV_FEEDFWD_GAIN(x)	REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x))
-
-#define CHV_PLL_DW6(ch)			_CHV_PLL((ch), 6)
-#define   DPIO_CHV_GAIN_CTRL_MASK	REG_GENMASK(18, 16)
-#define   DPIO_CHV_GAIN_CTRL(x)		REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x))
-#define   DPIO_CHV_INT_COEFF_MASK	REG_GENMASK(12, 8)
-#define   DPIO_CHV_INT_COEFF(x)		REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x))
-#define   DPIO_CHV_PROP_COEFF_MASK	REG_GENMASK(3, 0)
-#define   DPIO_CHV_PROP_COEFF(x)	REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x))
-
-#define CHV_PLL_DW8(ch)			_CHV_PLL((ch), 8)
-#define   DPIO_CHV_TDC_TARGET_CNT_MASK	REG_GENMASK(9, 0)
-#define   DPIO_CHV_TDC_TARGET_CNT(x)	REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x))
-
-#define CHV_PLL_DW9(ch)			_CHV_PLL((ch), 9)
-#define   DPIO_CHV_INT_LOCK_THRESHOLD_MASK		REG_GENMASK(3, 1)
-#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))
-#define   DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	REG_BIT(0) /* 1: coarse & 0 : fine  */
-
-#define CHV_CMN_DW0_CH0			_CHV_CMN(0, 0)
-#define   DPIO_ALLDL_POWERDOWN_CH0	REG_BIT(19)
-#define   DPIO_ANYDL_POWERDOWN_CH0	REG_BIT(18)
-#define   DPIO_ALLDL_POWERDOWN		BIT(1)
-#define   DPIO_ANYDL_POWERDOWN		BIT(0)
-
-#define CHV_CMN_DW5_CH0			_CHV_CMN(0, 5)
-#define   CHV_BUFRIGHTENA1_MASK		REG_GENMASK(21, 20)
-#define   CHV_BUFRIGHTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0)
-#define   CHV_BUFRIGHTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1)
-#define   CHV_BUFRIGHTENA1_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3)
-#define   CHV_BUFLEFTENA1_MASK		REG_GENMASK(23, 22)
-#define   CHV_BUFLEFTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0)
-#define   CHV_BUFLEFTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1)
-#define   CHV_BUFLEFTENA1_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3)
-
-#define CHV_CMN_DW13_CH0		_CHV_CMN(0, 13)
-#define CHV_CMN_DW0_CH1			_CHV_CMN(1, 0)
-#define   DPIO_CHV_S1_DIV_MASK		REG_GENMASK(23, 21)
-#define   DPIO_CHV_S1_DIV(s1)		REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1))
-#define   DPIO_CHV_P1_DIV_MASK		REG_GENMASK(15, 13)
-#define   DPIO_CHV_P1_DIV(p1)		REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1))
-#define   DPIO_CHV_P2_DIV_MASK		REG_GENMASK(12, 8)
-#define   DPIO_CHV_P2_DIV(p2)		REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2))
-#define   DPIO_CHV_K_DIV_MASK		REG_GENMASK(7, 4)
-#define   DPIO_CHV_K_DIV(k)		REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))
-#define   DPIO_PLL_FREQLOCK		REG_BIT(1)
-#define   DPIO_PLL_LOCK			REG_BIT(0)
-#define CHV_CMN_DW13(ch)		_PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
-
-#define CHV_CMN_DW14_CH0		_CHV_CMN(0, 14)
-#define CHV_CMN_DW1_CH1			_CHV_CMN(1, 1)
-#define   DPIO_AFC_RECAL		REG_BIT(14)
-#define   DPIO_DCLKP_EN			REG_BIT(13)
-#define   CHV_BUFLEFTENA2_MASK		REG_GENMASK(18, 17) /* CL2 DW1 only */
-#define   CHV_BUFLEFTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0)
-#define   CHV_BUFLEFTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1)
-#define   CHV_BUFLEFTENA2_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3)
-#define   CHV_BUFRIGHTENA2_MASK		REG_GENMASK(20, 19) /* CL2 DW1 only */
-#define   CHV_BUFRIGHTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0)
-#define   CHV_BUFRIGHTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1)
-#define   CHV_BUFRIGHTENA2_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3)
-#define CHV_CMN_DW14(ch)		_PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
-
-#define CHV_CMN_DW19_CH0		_CHV_CMN(0, 19)
-#define CHV_CMN_DW6_CH1			_CHV_CMN(1, 6)
-#define   DPIO_ALLDL_POWERDOWN_CH1	REG_BIT(30) /* CL2 DW6 only */
-#define   DPIO_ANYDL_POWERDOWN_CH1	REG_BIT(29) /* CL2 DW6 only */
-#define   DPIO_DYNPWRDOWNEN_CH1		REG_BIT(28) /* CL2 DW6 only */
-#define   CHV_CMN_USEDCLKCHANNEL	REG_BIT(13)
-#define CHV_CMN_DW19(ch)		_PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
-
-#define CHV_CMN_DW28			_CHV_CMN(0, 28)
-#define   DPIO_CL1POWERDOWNEN			REG_BIT(23)
-#define   DPIO_DYNPWRDOWNEN_CH0			REG_BIT(22)
-#define   DPIO_SUS_CLK_CONFIG_MASK		REG_GENMASK(1, 0)
-#define   DPIO_SUS_CLK_CONFIG_ON		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0)
-#define   DPIO_SUS_CLK_CONFIG_CLKREQ		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1)
-#define   DPIO_SUS_CLK_CONFIG_GATE		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2)
-#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3)
-
-#define CHV_CMN_DW30			_CHV_CMN(0, 30)
-#define   DPIO_CL2_LDOFUSE_PWRENB	REG_BIT(6)
-#define   DPIO_LRC_BYPASS		REG_BIT(3)
-
-#define CHV_TX_DW0(ch, lane)		_VLV_TX((ch), (lane), 0)
-#define CHV_TX_DW1(ch, lane)		_VLV_TX((ch), (lane), 1)
-#define CHV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
-#define CHV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
-#define CHV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
-#define CHV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
-#define CHV_TX_DW6(ch, lane)		_VLV_TX((ch), (lane), 6)
-#define CHV_TX_DW7(ch, lane)		_VLV_TX((ch), (lane), 7)
-#define CHV_TX_DW8(ch, lane)		_VLV_TX((ch), (lane), 8)
-#define CHV_TX_DW9(ch, lane)		_VLV_TX((ch), (lane), 9)
-#define CHV_TX_DW10(ch, lane)		_VLV_TX((ch), (lane), 10)
-
-#define CHV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
-#define   DPIO_FRC_LATENCY_MASK		REG_GENMASK(10, 8)
-#define   DPIO_FRC_LATENCY(x)		REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x))
-
-#define CHV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
-#define   DPIO_UPAR			REG_BIT(30)
-
 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
 #define  MIPIO_RST_CTRL				(1 << 2)
 
-- 
2.43.2

Re: [PATCH 01/14] drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We don't use the result of the VLV_PCS01_DW8 read at all,
> so don't read.

Mmmh, maybe the intention was to be a rmw? Since this appears to have
worked, okay.

This part becomes a bit pointless:

	else
		val &= ~(1<<21);

but it was already there and you seem to clean this up in patch 13 so
*shrug*.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index c72b76b61dff..6cbee88e608f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1134,7 +1134,6 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
>  	vlv_dpio_get(dev_priv);
>  
>  	/* Enable clock channels for this port */
> -	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(port));
>  	val = 0;
>  	if (pipe)
>  		val |= (1<<21);

-- 
Jani Nikula, Intel

Re: [PATCH 02/14] drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Our VLV_REF_DW13 is actually VLV_REF_DW11. Rename it.

I'll take your word for it. The patch does what the commit message says,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 8 ++++----
>  drivers/gpu/drm/i915/i915_reg.h           | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 49274d632716..6693beafe9c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1880,19 +1880,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
>  	reg_val |= 0x00000030;
>  	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
>  
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
> +	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>  	reg_val &= 0x00ffffff;
>  	reg_val |= 0x8c000000;
> -	vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
> +	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
>  
>  	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
>  	reg_val &= 0xffffff00;
>  	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
>  
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
> +	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>  	reg_val &= 0x00ffffff;
>  	reg_val |= 0xb0000000;
> -	vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
> +	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
>  }
>  
>  static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8eb6c2bf4557..a2fadcbe0932 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -246,8 +246,8 @@
>  #define _VLV_PLL_DW11_CH1		0x806c
>  #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
>  
> -/* Spec for ref block start counts at DW10 */
> -#define VLV_REF_DW13			0x80ac
> +/* Spec for ref block start counts at DW8 */
> +#define VLV_REF_DW11			0x80ac
>  
>  #define VLV_CMN_DW0			0x8100

-- 
Jani Nikula, Intel

Re: [PATCH 03/14] drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> VLV_PLL_DW9_BCAST is actually VLV_PCS_DW17_BCAST. The address
> does kinda look like it goes to the PLL block on a first glance,
> but broadcast is special and doesn't even exist for the PLL
> (only PCS and TX have it).
>
> The fact that we use a broadcast write here is a bit sketchy
> IMO since we're now blasting the register to all PCS splines
> across the whole PHY. So the PCS registers in the other channel
> (ie. other pipe/port) will also be written. But I guess the
> fact that we always write the same value should make this a nop
> even if the other channel is already enabled (assuming the VBIOS/GOP
> didn't screw up and use some other value...).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I'll take your word for it. The patch does what the commit message says,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h           | 3 ++-
>  2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 6693beafe9c0..7e8aca3c87ec 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1920,7 +1920,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  		vlv_pllb_recal_opamp(dev_priv, phy);
>  
>  	/* Set up Tx target for periodic Rcomp update */
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9_BCAST, 0x0100000f);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
>  
>  	/* Disable target IRef on PLL */
>  	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a2fadcbe0932..8f3c83d2ab8d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -233,7 +233,6 @@
>  #define _VLV_PLL_DW8_CH1		0x8060
>  #define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
>  
> -#define VLV_PLL_DW9_BCAST		0xc044
>  #define _VLV_PLL_DW9_CH0		0x8044
>  #define _VLV_PLL_DW9_CH1		0x8064
>  #define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
> @@ -370,6 +369,8 @@
>  #define _VLV_PCS_DW14_CH1		0x8438
>  #define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
>  
> +#define VLV_PCS_DW17_BCAST		0xc044
> +
>  #define _VLV_PCS_DW23_CH0		0x825c
>  #define _VLV_PCS_DW23_CH1		0x845c
>  #define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)

-- 
Jani Nikula, Intel

Re: [PATCH 04/14] drm/i915/dpio: Fix VLV DPIO PLL register dword numbering

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The spreadsheet defines the PLL register block as having
> the dwords in the following order:
>
> block   dwords    offsets
> PLL1    0x0-0x7   0x00-0x1f
> PLL2    0x0-0x7   0x20-0x2f
> PLL1ext 0x10-0x1f 0x40-0x5f
> PLL2ext 0x10-0x1f 0x60-0x7f
>
> So dword indexes 0x8-0xf don't even exist. Renumber
> our register defines to match.
>
> Note that the spreadsheet used hex numbering whereas our
> defiens are in decimal. Perhaps we should change that?
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

I am, again, taking your word for it, instead of going on a wild goose
chase trying to find all the specs. The patch matches the commit
message,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 18 ++++++++---------
>  drivers/gpu/drm/i915/i915_reg.h           | 24 +++++++++++------------
>  2 files changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 7e8aca3c87ec..b95032651da0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1875,19 +1875,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
>  	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
>  	 * and set it to a reasonable value instead.
>  	 */
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
> +	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
>  	reg_val &= 0xffffff00;
>  	reg_val |= 0x00000030;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
>  
>  	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>  	reg_val &= 0x00ffffff;
>  	reg_val |= 0x8c000000;
>  	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
>  
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
> +	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
>  	reg_val &= 0xffffff00;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
>  
>  	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>  	reg_val &= 0x00ffffff;
> @@ -1923,9 +1923,9 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
>  
>  	/* Disable target IRef on PLL */
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe));
> +	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
>  	reg_val &= 0x00ffffff;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW8(pipe), reg_val);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
>  
>  	/* Disable fast lock */
>  	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
> @@ -1951,10 +1951,10 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->port_clock == 162000 ||
>  	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
>  	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> -		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
> +		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
>  				 0x009f0003);
>  	else
> -		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe),
> +		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
>  				 0x00d0000f);
>  
>  	if (intel_crtc_has_dp_encoder(crtc_state)) {
> @@ -1981,7 +1981,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  		coreclk |= 0x01000000;
>  	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk);
>  
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW11(pipe), 0x87871000);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(pipe), 0x87871000);
>  
>  	vlv_dpio_put(dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8f3c83d2ab8d..747221f8ac72 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -229,21 +229,21 @@
>  #define _VLV_PLL_DW7_CH1		0x803c
>  #define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
>  
> -#define _VLV_PLL_DW8_CH0		0x8040
> -#define _VLV_PLL_DW8_CH1		0x8060
> -#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
> +#define _VLV_PLL_DW16_CH0		0x8040
> +#define _VLV_PLL_DW16_CH1		0x8060
> +#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1)
>  
> -#define _VLV_PLL_DW9_CH0		0x8044
> -#define _VLV_PLL_DW9_CH1		0x8064
> -#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
> +#define _VLV_PLL_DW17_CH0		0x8044
> +#define _VLV_PLL_DW17_CH1		0x8064
> +#define VLV_PLL_DW17(ch) _PIPE(ch, _VLV_PLL_DW17_CH0, _VLV_PLL_DW17_CH1)
>  
> -#define _VLV_PLL_DW10_CH0		0x8048
> -#define _VLV_PLL_DW10_CH1		0x8068
> -#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
> +#define _VLV_PLL_DW18_CH0		0x8048
> +#define _VLV_PLL_DW18_CH1		0x8068
> +#define VLV_PLL_DW18(ch) _PIPE(ch, _VLV_PLL_DW18_CH0, _VLV_PLL_DW18_CH1)
>  
> -#define _VLV_PLL_DW11_CH0		0x804c
> -#define _VLV_PLL_DW11_CH1		0x806c
> -#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
> +#define _VLV_PLL_DW19_CH0		0x804c
> +#define _VLV_PLL_DW19_CH1		0x806c
> +#define VLV_PLL_DW19(ch) _PIPE(ch, _VLV_PLL_DW19_CH0, _VLV_PLL_DW19_CH1)
>  
>  /* Spec for ref block start counts at DW8 */
>  #define VLV_REF_DW11			0x80ac

-- 
Jani Nikula, Intel

Re: [PATCH 05/14] drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Drop all the local variables for the DPLL dividers for vlv/chv
> and just consult the state directly.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 62 ++++++++++-------------
>  1 file changed, 27 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index b95032651da0..01f800b6b30e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1899,20 +1899,13 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct dpll *clock = &crtc_state->dpll;
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	enum pipe pipe = crtc->pipe;
> -	u32 mdiv;
> -	u32 bestn, bestm1, bestm2, bestp1, bestp2;
> -	u32 coreclk, reg_val;
> +	u32 mdiv, coreclk, reg_val;
>  
>  	vlv_dpio_get(dev_priv);
>  
> -	bestn = crtc_state->dpll.n;
> -	bestm1 = crtc_state->dpll.m1;
> -	bestm2 = crtc_state->dpll.m2;
> -	bestp1 = crtc_state->dpll.p1;
> -	bestp2 = crtc_state->dpll.p2;
> -
>  	/* See eDP HDMI DPIO driver vbios notes doc */
>  
>  	/* PLL B needs special handling */
> @@ -1931,10 +1924,12 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
>  
>  	/* Set idtafcrecal before PLL is enabled */
> -	mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
> -	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
> -	mdiv |= ((bestn << DPIO_N_SHIFT));
> -	mdiv |= (1 << DPIO_K_SHIFT);
> +	mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
> +		(clock->m2 & DPIO_M2DIV_MASK) |
> +		(clock->p1 << DPIO_P1_SHIFT) |
> +		(clock->p2 << DPIO_P2_SHIFT) |
> +		(clock->n << DPIO_N_SHIFT) |
> +		(1 << DPIO_K_SHIFT);
>  
>  	/*
>  	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
> @@ -2030,19 +2025,14 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct dpll *clock = &crtc_state->dpll;
>  	enum pipe pipe = crtc->pipe;
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> -	u32 loopfilter, tribuf_calcntr;
> -	u32 bestm2, bestp1, bestp2, bestm2_frac;
> -	u32 dpio_val;
> -	int vco;
> +	u32 dpio_val, loopfilter, tribuf_calcntr;
> +	u32 m2_frac;
>  
> -	bestm2_frac = crtc_state->dpll.m2 & 0x3fffff;
> -	bestm2 = crtc_state->dpll.m2 >> 22;
> -	bestp1 = crtc_state->dpll.p1;
> -	bestp2 = crtc_state->dpll.p2;
> -	vco = crtc_state->dpll.vco;
> +	m2_frac = clock->m2 & 0x3fffff;
>  	dpio_val = 0;
>  	loopfilter = 0;
>  
> @@ -2050,27 +2040,29 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  
>  	/* p1 and p2 divider */
>  	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port),
> -			5 << DPIO_CHV_S1_DIV_SHIFT |
> -			bestp1 << DPIO_CHV_P1_DIV_SHIFT |
> -			bestp2 << DPIO_CHV_P2_DIV_SHIFT |
> -			1 << DPIO_CHV_K_DIV_SHIFT);
> +		       5 << DPIO_CHV_S1_DIV_SHIFT |
> +		       clock->p1 << DPIO_CHV_P1_DIV_SHIFT |
> +		       clock->p2 << DPIO_CHV_P2_DIV_SHIFT |
> +		       1 << DPIO_CHV_K_DIV_SHIFT);
>  
>  	/* Feedback post-divider - m2 */
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), bestm2);
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port),
> +		       clock->m2 >> 22);
>  
>  	/* Feedback refclk divider - n and m1 */
>  	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port),
> -			DPIO_CHV_M1_DIV_BY_2 |
> -			1 << DPIO_CHV_N_DIV_SHIFT);
> +		       DPIO_CHV_M1_DIV_BY_2 |
> +		       1 << DPIO_CHV_N_DIV_SHIFT);
>  
>  	/* M2 fraction division */
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), bestm2_frac);
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port),
> +		       m2_frac);
>  
>  	/* M2 fraction division enable */
>  	dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
>  	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
>  	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
> -	if (bestm2_frac)
> +	if (m2_frac)
>  		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
>  	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val);
>  
> @@ -2079,22 +2071,22 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
>  					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
>  	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
> -	if (!bestm2_frac)
> +	if (!m2_frac)
>  		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
>  	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val);
>  
>  	/* Loop filter */
> -	if (vco == 5400000) {
> +	if (clock->vco == 5400000) {
>  		loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
>  		loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
>  		loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
>  		tribuf_calcntr = 0x9;
> -	} else if (vco <= 6200000) {
> +	} else if (clock->vco <= 6200000) {
>  		loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
>  		loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
>  		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
>  		tribuf_calcntr = 0x9;
> -	} else if (vco <= 6480000) {
> +	} else if (clock->vco <= 6480000) {
>  		loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
>  		loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
>  		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);

-- 
Jani Nikula, Intel

Re: [PATCH 06/14] drm/i915/dpio: Rename some variables

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use a constent 'tmp' as the variable name for the register

*consistent

> values during rmw when we don't deal with multiple registers
> in parallel.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 97 +++++++++++------------
>  1 file changed, 48 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 01f800b6b30e..0a738b491c40 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -514,23 +514,23 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
> -	struct dpll clock;
> -	u32 mdiv;
>  	int refclk = 100000;
> +	struct dpll clock;
> +	u32 tmp;
>  
>  	/* In case of DSI, DPLL will not be used */
>  	if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)
>  		return;
>  
>  	vlv_dpio_get(dev_priv);
> -	mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
>  	vlv_dpio_put(dev_priv);
>  
> -	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
> -	clock.m2 = mdiv & DPIO_M2DIV_MASK;
> -	clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
> -	clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
> -	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
> +	clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
> +	clock.m2 = tmp & DPIO_M2DIV_MASK;
> +	clock.n = (tmp >> DPIO_N_SHIFT) & 0xf;
> +	clock.p1 = (tmp >> DPIO_P1_SHIFT) & 7;
> +	clock.p2 = (tmp >> DPIO_P2_SHIFT) & 0x1f;
>  
>  	crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock);
>  }
> @@ -1869,30 +1869,30 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
>  static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
>  				 enum dpio_phy phy)
>  {
> -	u32 reg_val;
> +	u32 tmp;
>  
>  	/*
>  	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
>  	 * and set it to a reasonable value instead.
>  	 */
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> -	reg_val &= 0xffffff00;
> -	reg_val |= 0x00000030;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> +	tmp &= 0xffffff00;
> +	tmp |= 0x00000030;
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
>  
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> -	reg_val &= 0x00ffffff;
> -	reg_val |= 0x8c000000;
> -	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> +	tmp &= 0x00ffffff;
> +	tmp |= 0x8c000000;
> +	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
>  
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> -	reg_val &= 0xffffff00;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), reg_val);
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> +	tmp &= 0xffffff00;
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
>  
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> -	reg_val &= 0x00ffffff;
> -	reg_val |= 0xb0000000;
> -	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
> +	tmp &= 0x00ffffff;
> +	tmp |= 0xb0000000;
> +	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
>  }
>  
>  static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
> @@ -1902,7 +1902,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	const struct dpll *clock = &crtc_state->dpll;
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	enum pipe pipe = crtc->pipe;
> -	u32 mdiv, coreclk, reg_val;
> +	u32 tmp, coreclk;
>  
>  	vlv_dpio_get(dev_priv);
>  
> @@ -1916,15 +1916,15 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
>  
>  	/* Disable target IRef on PLL */
> -	reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
> -	reg_val &= 0x00ffffff;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), reg_val);
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
> +	tmp &= 0x00ffffff;
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
>  
>  	/* Disable fast lock */
>  	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
>  
>  	/* Set idtafcrecal before PLL is enabled */
> -	mdiv = (clock->m1 << DPIO_M1DIV_SHIFT) |
> +	tmp = (clock->m1 << DPIO_M1DIV_SHIFT) |
>  		(clock->m2 & DPIO_M2DIV_MASK) |
>  		(clock->p1 << DPIO_P1_SHIFT) |
>  		(clock->p2 << DPIO_P2_SHIFT) |
> @@ -1936,11 +1936,11 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	 * but we don't support that).
>  	 * Note: don't use the DAC post divider as it seems unstable.
>  	 */
> -	mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv);
> +	tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
>  
> -	mdiv |= DPIO_ENABLE_CALIBRATION;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv);
> +	tmp |= DPIO_ENABLE_CALIBRATION;
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
>  
>  	/* Set HBR and RBR LPF coefficients */
>  	if (crtc_state->port_clock == 162000 ||
> @@ -2029,11 +2029,10 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	enum pipe pipe = crtc->pipe;
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> -	u32 dpio_val, loopfilter, tribuf_calcntr;
> +	u32 tmp, loopfilter, tribuf_calcntr;
>  	u32 m2_frac;
>  
>  	m2_frac = clock->m2 & 0x3fffff;
> -	dpio_val = 0;
>  	loopfilter = 0;
>  
>  	vlv_dpio_get(dev_priv);
> @@ -2059,21 +2058,21 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  		       m2_frac);
>  
>  	/* M2 fraction division enable */
> -	dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
> -	dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
> -	dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
> +	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
> +	tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
> +	tmp |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
>  	if (m2_frac)
> -		dpio_val |= DPIO_CHV_FRAC_DIV_EN;
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val);
> +		tmp |= DPIO_CHV_FRAC_DIV_EN;
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), tmp);
>  
>  	/* Program digital lock detect threshold */
> -	dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port));
> -	dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
> +	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port));
> +	tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
>  					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
> -	dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
> +	tmp |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
>  	if (!m2_frac)
> -		dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val);
> +		tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), tmp);
>  
>  	/* Loop filter */
>  	if (clock->vco == 5400000) {
> @@ -2100,10 +2099,10 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	}
>  	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter);
>  
> -	dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port));
> -	dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
> -	dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), dpio_val);
> +	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port));
> +	tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
> +	tmp |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), tmp);
>  
>  	/* AFC Recal */
>  	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port),

-- 
Jani Nikula, Intel

Re: [PATCH 07/14] drm/i915/dpio: s/port/ch/

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop calling the DPIO PHY channel "port". Just say "ch", which
> is already used in a bunch of places.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 44 +++++++--------
>  drivers/gpu/drm/i915/display/intel_dpll.c     | 54 +++++++++----------
>  2 files changed, 49 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 6cbee88e608f..e4a04c9b5b19 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1069,23 +1069,23 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> +	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  
>  	vlv_dpio_get(dev_priv);
>  
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x00000000);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port),
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x00000000);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
>  			 uniqtranscale_reg_value);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
>  
>  	if (tx3_demph)
> -		vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph);
> +		vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
>  
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x00030000);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x00030000);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
>  
>  	vlv_dpio_put(dev_priv);
>  }
> @@ -1096,25 +1096,25 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> +	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  
>  	/* Program Tx lane resets to default */
>  	vlv_dpio_get(dev_priv);
>  
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port),
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
>  			 DPIO_PCS_TX_LANE2_RESET |
>  			 DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port),
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
>  			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
>  			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
>  			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
>  				 DPIO_PCS_CLK_SOFT_RESET);
>  
>  	/* Fix up inter-pair skew failure */
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(port), 0x00750f00);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(port), 0x00001500);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(port), 0x40400000);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x00001500);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x40400000);
>  
>  	vlv_dpio_put(dev_priv);
>  }
> @@ -1126,7 +1126,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> +	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>  	enum pipe pipe = crtc->pipe;
>  	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
>  	u32 val;
> @@ -1140,11 +1140,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
>  	else
>  		val &= ~(1<<21);
>  	val |= 0x001000c4;
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
>  
>  	/* Program lane clock */
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(port), 0x00760018);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(port), 0x00400888);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
>  
>  	vlv_dpio_put(dev_priv);
>  }
> @@ -1155,11 +1155,11 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> -	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
> +	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  
>  	vlv_dpio_get(dev_priv);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), 0x00000000);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), 0x00e00060);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), 0x00e00060);
>  	vlv_dpio_put(dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 0a738b491c40..743cc466ee39 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -539,7 +539,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe);
> +	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
>  	struct dpll clock;
> @@ -551,11 +551,11 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state)
>  		return;
>  
>  	vlv_dpio_get(dev_priv);
> -	cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(port));
> -	pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(port));
> -	pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(port));
> -	pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(port));
> -	pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
> +	cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(ch));
> +	pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(ch));
> +	pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(ch));
> +	pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(ch));
> +	pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
>  	vlv_dpio_put(dev_priv);
>  
>  	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
> @@ -2027,7 +2027,7 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct dpll *clock = &crtc_state->dpll;
>  	enum pipe pipe = crtc->pipe;
> -	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> +	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	u32 tmp, loopfilter, tribuf_calcntr;
>  	u32 m2_frac;
> @@ -2038,41 +2038,41 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	vlv_dpio_get(dev_priv);
>  
>  	/* p1 and p2 divider */
> -	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port),
> +	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch),
>  		       5 << DPIO_CHV_S1_DIV_SHIFT |
>  		       clock->p1 << DPIO_CHV_P1_DIV_SHIFT |
>  		       clock->p2 << DPIO_CHV_P2_DIV_SHIFT |
>  		       1 << DPIO_CHV_K_DIV_SHIFT);
>  
>  	/* Feedback post-divider - m2 */
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port),
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch),
>  		       clock->m2 >> 22);
>  
>  	/* Feedback refclk divider - n and m1 */
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port),
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch),
>  		       DPIO_CHV_M1_DIV_BY_2 |
>  		       1 << DPIO_CHV_N_DIV_SHIFT);
>  
>  	/* M2 fraction division */
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port),
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch),
>  		       m2_frac);
>  
>  	/* M2 fraction division enable */
> -	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port));
> +	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch));
>  	tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
>  	tmp |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
>  	if (m2_frac)
>  		tmp |= DPIO_CHV_FRAC_DIV_EN;
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), tmp);
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp);
>  
>  	/* Program digital lock detect threshold */
> -	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port));
> +	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch));
>  	tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
>  					DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
>  	tmp |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
>  	if (!m2_frac)
>  		tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), tmp);
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp);
>  
>  	/* Loop filter */
>  	if (clock->vco == 5400000) {
> @@ -2097,17 +2097,17 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  		loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
>  		tribuf_calcntr = 0;
>  	}
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter);
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter);
>  
> -	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port));
> +	tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch));
>  	tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
>  	tmp |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
> -	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), tmp);
> +	vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp);
>  
>  	/* AFC Recal */
> -	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port),
> -			vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)) |
> -			DPIO_AFC_RECAL);
> +	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch),
> +		       vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)) |
> +		       DPIO_AFC_RECAL);
>  
>  	vlv_dpio_put(dev_priv);
>  }
> @@ -2118,16 +2118,16 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
>  	enum pipe pipe = crtc->pipe;
> -	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> +	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	u32 tmp;
>  
>  	vlv_dpio_get(dev_priv);
>  
>  	/* Enable back the 10bit clock to display controller */
> -	tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port));
> +	tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
>  	tmp |= DPIO_DCLKP_EN;
> -	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), tmp);
> +	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), tmp);
>  
>  	vlv_dpio_put(dev_priv);
>  
> @@ -2246,7 +2246,7 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  {
> -	enum dpio_channel port = vlv_pipe_to_channel(pipe);
> +	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
>  	u32 val;
>  
> @@ -2264,9 +2264,9 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	vlv_dpio_get(dev_priv);
>  
>  	/* Disable 10bit clock to display controller */
> -	val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port));
> +	val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch));
>  	val &= ~DPIO_DCLKP_EN;
> -	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), val);
> +	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), val);
>  
>  	vlv_dpio_put(dev_priv);
>  }

-- 
Jani Nikula, Intel

✗ Fi.CI.CHECKPATCH: warning for drm/i915: VLV/CHV DPIO register cleanup

[Patchwork]

== Series Details ==

Series: drm/i915: VLV/CHV DPIO register cleanup
URL   : https://patchwork.freedesktop.org/series/132691/
State : warning

== Summary ==

Error: dim checkpatch failed
184896913edd drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read
a2f8a671697e drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/
86c9cdd31e2c drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/
539c41fc43a2 drm/i915/dpio: Fix VLV DPIO PLL register dword numbering
-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1955:
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 				 0x009f0003);

-:77: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#77: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1958:
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 				 0x00d0000f);

total: 0 errors, 0 warnings, 2 checks, 87 lines checked
23005c4598b0 drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code
e9958d5045c7 drm/i915/dpio: Rename some variables
aeed158347d0 drm/i915/dpio: s/port/ch/
-:34: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#34: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1080:
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
 			 uniqtranscale_reg_value);

-:64: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#64: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1106:
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
 			 DPIO_PCS_TX_LANE2_RESET |

-:68: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#68: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1109:
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |

total: 0 errors, 0 warnings, 3 checks, 241 lines checked
079148d63725 drm/i915/dpio: s/pipe/ch/
-:115: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#115: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1952:
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
 				 0x009f0003);

-:119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#119: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1955:
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
 				 0x00d0000f);

-:126: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#126: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1961:
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df40000);

-:130: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#130: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1964:
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df70000);

-:136: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#136: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1969:
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df70000);

-:140: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#140: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1972:
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df40000);

total: 0 errors, 0 warnings, 6 checks, 148 lines checked
accdf36188da drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooks
fa7e0411e89e drm/i915/dpio: Give VLV DPIO group register a clearer name
-:29: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#29: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1077:
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
 			 uniqtranscale_reg_value);

-:51: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#51: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1102:
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
 			 DPIO_PCS_TX_LANE2_RESET |

-:55: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#55: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1105:
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |

total: 0 errors, 0 warnings, 3 checks, 262 lines checked
d14f54c49025 drm/i915/dpio: Rename a few CHV DPIO PHY registers
9376db9e9866 drm/i915/dpio: Clean up VLV/CHV DPIO PHY register defines
655636fc383b drm/i915/dpio: Clean up the vlv/chv PHY register bits
-:608: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#608: FILE: drivers/gpu/drm/i915/i915_reg.h:409:
+#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))

total: 0 errors, 1 warnings, 0 checks, 686 lines checked
7bd6e1c1f6b0 drm/i915/dpio: Extract vlv_dpio_phy_regs.h
-:62: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#62: 
new file mode 100644

-:288: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#288: FILE: drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h:222:
+#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))

total: 0 errors, 2 warnings, 0 checks, 641 lines checked

Re: [PATCH 08/14] drm/i915/dpio: s/pipe/ch/

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stop using 'pipe' directly as the DPIO PHY channel. This
> does happen to work on VLV since it just has the one PHY
> with CH0==pipe A and CH1==pipe B. But explicitly converting
> the thing to the right enum makes the whole thing less
> confusing.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 49 ++++++++++++-----------
>  1 file changed, 25 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 743cc466ee39..861f4a735251 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -512,6 +512,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
>  	int refclk = 100000;
> @@ -523,7 +524,7 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state)
>  		return;
>  
>  	vlv_dpio_get(dev_priv);
> -	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe));
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch));
>  	vlv_dpio_put(dev_priv);
>  
>  	clock.m1 = (tmp >> DPIO_M1DIV_SHIFT) & 7;
> @@ -1867,7 +1868,7 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state)
>  }
>  
>  static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
> -				 enum dpio_phy phy)
> +				 enum dpio_phy phy, enum dpio_channel ch)
>  {
>  	u32 tmp;
>  
> @@ -1875,19 +1876,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
>  	 * PLLB opamp always calibrates to max value of 0x3f, force enable it
>  	 * and set it to a reasonable value instead.
>  	 */
> -	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
>  	tmp &= 0xffffff00;
>  	tmp |= 0x00000030;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
>  
>  	tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>  	tmp &= 0x00ffffff;
>  	tmp |= 0x8c000000;
>  	vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp);
>  
> -	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(1));
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch));
>  	tmp &= 0xffffff00;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(1), tmp);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp);
>  
>  	tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
>  	tmp &= 0x00ffffff;
> @@ -1900,6 +1901,7 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct dpll *clock = &crtc_state->dpll;
> +	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	enum pipe pipe = crtc->pipe;
>  	u32 tmp, coreclk;
> @@ -1910,15 +1912,15 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  
>  	/* PLL B needs special handling */
>  	if (pipe == PIPE_B)
> -		vlv_pllb_recal_opamp(dev_priv, phy);
> +		vlv_pllb_recal_opamp(dev_priv, phy, ch);
>  
>  	/* Set up Tx target for periodic Rcomp update */
>  	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f);
>  
>  	/* Disable target IRef on PLL */
> -	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(pipe));
> +	tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(ch));
>  	tmp &= 0x00ffffff;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(pipe), tmp);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(ch), tmp);
>  
>  	/* Disable fast lock */
>  	vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610);
> @@ -1937,46 +1939,46 @@ static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	 * Note: don't use the DAC post divider as it seems unstable.
>  	 */
>  	tmp |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
>  
>  	tmp |= DPIO_ENABLE_CALIBRATION;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), tmp);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp);
>  
>  	/* Set HBR and RBR LPF coefficients */
>  	if (crtc_state->port_clock == 162000 ||
>  	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) ||
>  	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> -		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
> +		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
>  				 0x009f0003);
>  	else
> -		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
> +		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
>  				 0x00d0000f);
>  
>  	if (intel_crtc_has_dp_encoder(crtc_state)) {
>  		/* Use SSC source */
>  		if (pipe == PIPE_A)
> -			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
> +			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
>  					 0x0df40000);
>  		else
> -			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
> +			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
>  					 0x0df70000);
>  	} else { /* HDMI or VGA */
>  		/* Use bend source */
>  		if (pipe == PIPE_A)
> -			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
> +			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
>  					 0x0df70000);
>  		else
> -			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe),
> +			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
>  					 0x0df40000);
>  	}
>  
> -	coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(pipe));
> +	coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(ch));
>  	coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
>  	if (intel_crtc_has_dp_encoder(crtc_state))
>  		coreclk |= 0x01000000;
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(ch), coreclk);
>  
> -	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(pipe), 0x87871000);
> +	vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(ch), 0x87871000);
>  
>  	vlv_dpio_put(dev_priv);
>  }
> @@ -2026,8 +2028,7 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct dpll *clock = &crtc_state->dpll;
> -	enum pipe pipe = crtc->pipe;
> -	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
> +	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
>  	u32 tmp, loopfilter, tribuf_calcntr;
>  	u32 m2_frac;
> @@ -2117,9 +2118,9 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state)
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx;
> -	enum pipe pipe = crtc->pipe;
> -	enum dpio_channel ch = vlv_pipe_to_channel(pipe);
> +	enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe);
>  	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> +	enum pipe pipe = crtc->pipe;
>  	u32 tmp;
>  
>  	vlv_dpio_get(dev_priv);

-- 
Jani Nikula, Intel

✓ Fi.CI.BAT: success for drm/i915: VLV/CHV DPIO register cleanup

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1787 bytes --]

== Series Details ==

Series: drm/i915: VLV/CHV DPIO register cleanup
URL   : https://patchwork.freedesktop.org/series/132691/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14624 -> Patchwork_132691v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/index.html

Participating hosts (31 -> 30)
------------------------------

  Missing    (1): fi-apl-guc 

Known issues
------------

  Here are the changes found in Patchwork_132691v1 that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@i915_module_load@reload:
    - fi-kbl-7567u:       [DMESG-WARN][1] ([i915#10636] / [i915#180] / [i915#1982] / [i915#8585]) -> [DMESG-WARN][2] ([i915#10636] / [i915#180] / [i915#8585])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14624/fi-kbl-7567u/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/fi-kbl-7567u/igt@i915_module_load@reload.html

  
  [i915#10636]: https://gitlab.freedesktop.org/drm/intel/issues/10636
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#8585]: https://gitlab.freedesktop.org/drm/intel/issues/8585


Build changes
-------------

  * Linux: CI_DRM_14624 -> Patchwork_132691v1

  CI-20190529: 20190529
  CI_DRM_14624: ff2f70f345aaee3cbcf93a3a06ff3a5ab88e1d7a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7814: 7814
  Patchwork_132691v1: ff2f70f345aaee3cbcf93a3a06ff3a5ab88e1d7a @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/index.html

[-- Attachment #2: Type: text/html, Size: 2559 bytes --]

Re: [PATCH 09/14] drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooks

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> In the encoder hooks we are dealing primarily with the encoder,
> so derive the DPIO PHY from the encoder rather than the pipe.
> Technically this doesn't matter as we can't cross connect
> pipes<->port across PHY boundaries, but it does conveny the
> intention more accurately.

I'll note that for most places converting vlv_dig_port_to_* to
vlv_encoder_to_* would be more convenient in the caller side. We have
the encoder available where they're needed, and in many places we use
enc_to_dig_port(encoder) just to be able to use vlv_dig_port_to_*.

I'd just convert them to vlv_encoder_to_*.

Regardless, this does what it says on the tin,

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

Oh, one comment inline near the end.

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 27 ++++++++-----------
>  drivers/gpu/drm/i915/vlv_sideband.c           |  1 -
>  2 files changed, 11 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index e4a04c9b5b19..4fafac534967 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -719,9 +719,8 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> -	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> +	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  	u32 val;
>  	int i;
>  
> @@ -814,9 +813,9 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder,
>  			      bool reset)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
> -	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> +	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> +	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  	u32 val;
>  
>  	val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch));
> @@ -861,7 +860,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> -	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> +	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  	enum pipe pipe = crtc->pipe;
>  	unsigned int lane_mask =
>  		intel_dp_unused_lane_mask(crtc_state->lane_count);
> @@ -941,9 +940,8 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> -	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> +	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  	int data, i, stagger;
>  	u32 val;
>  
> @@ -1030,8 +1028,8 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *old_crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
>  	enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
> -	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
>  	u32 val;
>  
>  	vlv_dpio_get(dev_priv);
> @@ -1068,9 +1066,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> -	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> +	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  
>  	vlv_dpio_get(dev_priv);
>  
> @@ -1095,9 +1092,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> -	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> +	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  
>  	/* Program Tx lane resets to default */
>  	vlv_dpio_get(dev_priv);
> @@ -1127,8 +1123,8 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> +	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  	enum pipe pipe = crtc->pipe;
> -	enum dpio_phy phy = vlv_pipe_to_phy(pipe);
>  	u32 val;
>  
>  	vlv_dpio_get(dev_priv);
> @@ -1154,9 +1150,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>  	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
> -	enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
> +	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  
>  	vlv_dpio_get(dev_priv);
>  	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000);
> diff --git a/drivers/gpu/drm/i915/vlv_sideband.c b/drivers/gpu/drm/i915/vlv_sideband.c
> index ffa195560d0d..68291412f4cb 100644
> --- a/drivers/gpu/drm/i915/vlv_sideband.c
> +++ b/drivers/gpu/drm/i915/vlv_sideband.c
> @@ -9,7 +9,6 @@
>  #include "vlv_sideband.h"
>  
>  #include "display/intel_dpio_phy.h"
> -#include "display/intel_display_types.h"

I guess this should be done in some other patch?

>  
>  /*
>   * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and

-- 
Jani Nikula, Intel

Re: [PATCH 10/14] drm/i915/dpio: Give VLV DPIO group register a clearer name

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Include _GRP in VLV DPOP PHY group access register define

*DPIO

> names. Makes it more obvious where the accesses will land.
> Also matches the naming used by BXT already.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 34 +++----
>  drivers/gpu/drm/i915/i915_reg.h               | 90 +++++++++----------
>  2 files changed, 62 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 4fafac534967..791902ba729c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1071,18 +1071,18 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  
>  	vlv_dpio_get(dev_priv);
>  
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), 0x00000000);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch), demph_reg_value);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
>  			 uniqtranscale_reg_value);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(ch), 0x0C782040);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
>  
>  	if (tx3_demph)
>  		vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
>  
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(ch), 0x00030000);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(ch), preemph_reg_value);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(ch), DPIO_TX_OCALINIT_EN);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN);
>  
>  	vlv_dpio_put(dev_priv);
>  }
> @@ -1098,19 +1098,19 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
>  	/* Program Tx lane resets to default */
>  	vlv_dpio_get(dev_priv);
>  
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
>  			 DPIO_PCS_TX_LANE2_RESET |
>  			 DPIO_PCS_TX_LANE1_RESET);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
>  			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
>  			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
>  			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
>  				 DPIO_PCS_CLK_SOFT_RESET);
>  
>  	/* Fix up inter-pair skew failure */
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(ch), 0x00750f00);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(ch), 0x00001500);
> -	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(ch), 0x40400000);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500);
> +	vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000);
>  
>  	vlv_dpio_put(dev_priv);
>  }
> @@ -1136,11 +1136,11 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
>  	else
>  		val &= ~(1<<21);
>  	val |= 0x001000c4;
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(ch), val);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val);
>  
>  	/* Program lane clock */
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(ch), 0x00760018);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(ch), 0x00400888);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888);
>  
>  	vlv_dpio_put(dev_priv);
>  }
> @@ -1154,7 +1154,7 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
>  	enum dpio_phy phy = vlv_dig_port_to_phy(dig_port);
>  
>  	vlv_dpio_get(dev_priv);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch), 0x00000000);
> -	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch), 0x00e00060);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000);
> +	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060);
>  	vlv_dpio_put(dev_priv);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 747221f8ac72..3804ef4697d5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -254,13 +254,13 @@
>   * Per DDI channel DPIO regs
>   */
>  
> -#define _VLV_PCS_DW0_CH0		0x8200
> -#define _VLV_PCS_DW0_CH1		0x8400
> +#define _VLV_PCS_DW0_CH0_GRP		0x8200
> +#define _VLV_PCS_DW0_CH1_GRP		0x8400
>  #define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
>  #define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
>  #define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
>  #define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
> -#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
> +#define VLV_PCS_DW0_GRP(ch) _PORT(ch, _VLV_PCS_DW0_CH0_GRP, _VLV_PCS_DW0_CH1_GRP)
>  
>  #define _VLV_PCS01_DW0_CH0		0x200
>  #define _VLV_PCS23_DW0_CH0		0x400
> @@ -269,14 +269,14 @@
>  #define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
>  #define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
>  
> -#define _VLV_PCS_DW1_CH0		0x8204
> -#define _VLV_PCS_DW1_CH1		0x8404
> +#define _VLV_PCS_DW1_CH0_GRP		0x8204
> +#define _VLV_PCS_DW1_CH1_GRP		0x8404
>  #define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
>  #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
>  #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
>  #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
>  #define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
> -#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
> +#define VLV_PCS_DW1_GRP(ch) _PORT(ch, _VLV_PCS_DW1_CH0_GRP, _VLV_PCS_DW1_CH1_GRP)
>  
>  #define _VLV_PCS01_DW1_CH0		0x204
>  #define _VLV_PCS23_DW1_CH0		0x404
> @@ -285,11 +285,11 @@
>  #define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
>  #define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
>  
> -#define _VLV_PCS_DW8_CH0		0x8220
> -#define _VLV_PCS_DW8_CH1		0x8420
> +#define _VLV_PCS_DW8_CH0_GRP		0x8220
> +#define _VLV_PCS_DW8_CH1_GRP		0x8420
>  #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
>  #define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
> -#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
> +#define VLV_PCS_DW8_GRP(ch) _PORT(ch, _VLV_PCS_DW8_CH0_GRP, _VLV_PCS_DW8_CH1_GRP)
>  
>  #define _VLV_PCS01_DW8_CH0		0x0220
>  #define _VLV_PCS23_DW8_CH0		0x0420
> @@ -298,15 +298,15 @@
>  #define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
>  #define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
>  
> -#define _VLV_PCS_DW9_CH0		0x8224
> -#define _VLV_PCS_DW9_CH1		0x8424
> +#define _VLV_PCS_DW9_CH0_GRP		0x8224
> +#define _VLV_PCS_DW9_CH1_GRP		0x8424
>  #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
>  #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
>  #define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
>  #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
>  #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
>  #define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
> -#define	VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
> +#define VLV_PCS_DW9_GRP(ch) _PORT(ch, _VLV_PCS_DW9_CH0_GRP, _VLV_PCS_DW9_CH1_GRP)
>  
>  #define _VLV_PCS01_DW9_CH0		0x224
>  #define _VLV_PCS23_DW9_CH0		0x424
> @@ -315,8 +315,8 @@
>  #define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
>  #define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
>  
> -#define _CHV_PCS_DW10_CH0		0x8228
> -#define _CHV_PCS_DW10_CH1		0x8428
> +#define _CHV_PCS_DW10_CH0_GRP		0x8228
> +#define _CHV_PCS_DW10_CH1_GRP		0x8428
>  #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
>  #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
>  #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
> @@ -325,7 +325,7 @@
>  #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
>  #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
>  #define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
> -#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
> +#define CHV_PCS_DW10_GRP(ch) _PORT(ch, _CHV_PCS_DW10_CH0_GRP, _CHV_PCS_DW10_CH1_GRP)
>  
>  #define _VLV_PCS01_DW10_CH0		0x0228
>  #define _VLV_PCS23_DW10_CH0		0x0428
> @@ -334,13 +334,13 @@
>  #define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
>  #define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
>  
> -#define _VLV_PCS_DW11_CH0		0x822c
> -#define _VLV_PCS_DW11_CH1		0x842c
> +#define _VLV_PCS_DW11_CH0_GRP		0x822c
> +#define _VLV_PCS_DW11_CH1_GRP		0x842c
>  #define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
>  #define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
>  #define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
>  #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
> -#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
> +#define VLV_PCS_DW11_GRP(ch) _PORT(ch, _VLV_PCS_DW11_CH0_GRP, _VLV_PCS_DW11_CH1_GRP)
>  
>  #define _VLV_PCS01_DW11_CH0		0x022c
>  #define _VLV_PCS23_DW11_CH0		0x042c
> @@ -356,64 +356,64 @@
>  #define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
>  #define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
>  
> -#define _VLV_PCS_DW12_CH0		0x8230
> -#define _VLV_PCS_DW12_CH1		0x8430
> +#define _VLV_PCS_DW12_CH0_GRP		0x8230
> +#define _VLV_PCS_DW12_CH1_GRP		0x8430
>  #define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
>  #define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
>  #define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
>  #define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
>  #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
> -#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
> +#define VLV_PCS_DW12_GRP(ch) _PORT(ch, _VLV_PCS_DW12_CH0_GRP, _VLV_PCS_DW12_CH1_GRP)
>  
> -#define _VLV_PCS_DW14_CH0		0x8238
> -#define _VLV_PCS_DW14_CH1		0x8438
> -#define	VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
> +#define _VLV_PCS_DW14_CH0_GRP		0x8238
> +#define _VLV_PCS_DW14_CH1_GRP		0x8438
> +#define VLV_PCS_DW14_GRP(ch) _PORT(ch, _VLV_PCS_DW14_CH0_GRP, _VLV_PCS_DW14_CH1_GRP)
>  
>  #define VLV_PCS_DW17_BCAST		0xc044
>  
> -#define _VLV_PCS_DW23_CH0		0x825c
> -#define _VLV_PCS_DW23_CH1		0x845c
> -#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
> +#define _VLV_PCS_DW23_CH0_GRP		0x825c
> +#define _VLV_PCS_DW23_CH1_GRP		0x845c
> +#define VLV_PCS_DW23_GRP(ch) _PORT(ch, _VLV_PCS_DW23_CH0_GRP, _VLV_PCS_DW23_CH1_GRP)
>  
> -#define _VLV_TX_DW2_CH0			0x8288
> -#define _VLV_TX_DW2_CH1			0x8488
> +#define _VLV_TX_DW2_CH0_GRP		0x8288
> +#define _VLV_TX_DW2_CH1_GRP		0x8488
>  #define   DPIO_SWING_MARGIN000_SHIFT	16
>  #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
>  #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
> -#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
> +#define VLV_TX_DW2_GRP(ch) _PORT(ch, _VLV_TX_DW2_CH0_GRP, _VLV_TX_DW2_CH1_GRP)
>  
> -#define _VLV_TX_DW3_CH0			0x828c
> -#define _VLV_TX_DW3_CH1			0x848c
> +#define _VLV_TX_DW3_CH0_GRP		0x828c
> +#define _VLV_TX_DW3_CH1_GRP		0x848c
>  /* The following bit for CHV phy */
>  #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
>  #define   DPIO_SWING_MARGIN101_SHIFT	16
>  #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
> -#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
> +#define VLV_TX_DW3_GRP(ch) _PORT(ch, _VLV_TX_DW3_CH0_GRP, _VLV_TX_DW3_CH1_GRP)
>  
> -#define _VLV_TX_DW4_CH0			0x8290
> -#define _VLV_TX_DW4_CH1			0x8490
> +#define _VLV_TX_DW4_CH0_GRP		0x8290
> +#define _VLV_TX_DW4_CH1_GRP		0x8490
>  #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
>  #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
>  #define   DPIO_SWING_DEEMPH6P0_SHIFT	16
>  #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
> -#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
> +#define VLV_TX_DW4_GRP(ch) _PORT(ch, _VLV_TX_DW4_CH0_GRP, _VLV_TX_DW4_CH1_GRP)
>  
>  #define _VLV_TX3_DW4_CH0		0x690
>  #define _VLV_TX3_DW4_CH1		0x2a90
>  #define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
>  
> -#define _VLV_TX_DW5_CH0			0x8294
> -#define _VLV_TX_DW5_CH1			0x8494
> +#define _VLV_TX_DW5_CH0_GRP		0x8294
> +#define _VLV_TX_DW5_CH1_GRP		0x8494
>  #define   DPIO_TX_OCALINIT_EN		(1 << 31)
> -#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
> +#define VLV_TX_DW5_GRP(ch) _PORT(ch, _VLV_TX_DW5_CH0_GRP, _VLV_TX_DW5_CH1_GRP)
>  
> -#define _VLV_TX_DW11_CH0		0x82ac
> -#define _VLV_TX_DW11_CH1		0x84ac
> -#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
> +#define _VLV_TX_DW11_CH0_GRP		0x82ac
> +#define _VLV_TX_DW11_CH1_GRP		0x84ac
> +#define VLV_TX_DW11_GRP(ch) _PORT(ch, _VLV_TX_DW11_CH0_GRP, _VLV_TX_DW11_CH1_GRP)
>  
> -#define _VLV_TX_DW14_CH0		0x82b8
> -#define _VLV_TX_DW14_CH1		0x84b8
> -#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
> +#define _VLV_TX_DW14_CH0_GRP		0x82b8
> +#define _VLV_TX_DW14_CH1_GRP		0x84b8
> +#define VLV_TX_DW14_GRP(ch) _PORT(ch, _VLV_TX_DW14_CH0_GRP, _VLV_TX_DW14_CH1_GRP)
>  
>  /* CHV dpPhy registers */
>  #define _CHV_PLL_DW0_CH0		0x8000

-- 
Jani Nikula, Intel

Re: [PATCH 11/14] drm/i915/dpio: Rename a few CHV DPIO PHY registers

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Drop the leading underscore from the CHV PHY common lane
> register definitons. We use these directly from actual

*definitions

> code so the underscore here is misleading as usually it indicates
> an intermediate define that shouldn't be used directly.

I could go either this way, or to using the parametrized definitions and
passing the channel.

*shrug*

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../i915/display/intel_display_power_well.c   |  8 +++----
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c | 16 ++++++-------
>  drivers/gpu/drm/i915/i915_reg.h               | 23 +++++++++----------
>  3 files changed, 23 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index e8a6e53fd551..49114afc9a61 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1442,9 +1442,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
>  	vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp);
>  
>  	if (id == VLV_DISP_PW_DPIO_CMN_BC) {
> -		tmp = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW6_CH1);
> +		tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1);
>  		tmp |= DPIO_DYNPWRDOWNEN_CH1;
> -		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW6_CH1, tmp);
> +		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp);
>  	} else {
>  		/*
>  		 * Force the non-existing CL2 off. BXT does this
> @@ -1520,9 +1520,9 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
>  		return;
>  
>  	if (ch == DPIO_CH0)
> -		reg = _CHV_CMN_DW0_CH0;
> +		reg = CHV_CMN_DW0_CH0;
>  	else
> -		reg = _CHV_CMN_DW6_CH1;
> +		reg = CHV_CMN_DW6_CH1;
>  
>  	vlv_dpio_get(dev_priv);
>  	val = vlv_dpio_read(dev_priv, phy, reg);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 791902ba729c..89a51b420075 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -883,21 +883,21 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
>  
>  	/* program left/right clock distribution */
>  	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
> +		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
>  		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
>  		if (ch == DPIO_CH0)
>  			val |= CHV_BUFLEFTENA1_FORCE;
>  		if (ch == DPIO_CH1)
>  			val |= CHV_BUFRIGHTENA1_FORCE;
> -		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
> +		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
>  	} else {
> -		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
> +		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
>  		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
>  		if (ch == DPIO_CH0)
>  			val |= CHV_BUFLEFTENA2_FORCE;
>  		if (ch == DPIO_CH1)
>  			val |= CHV_BUFRIGHTENA2_FORCE;
> -		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
> +		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
>  	}
>  
>  	/* program clock channel usage */
> @@ -1036,13 +1036,13 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
>  
>  	/* disable left/right clock distribution */
>  	if (pipe != PIPE_B) {
> -		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
> +		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0);
>  		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
> -		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
> +		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val);
>  	} else {
> -		val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
> +		val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1);
>  		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
> -		vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
> +		vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val);
>  	}
>  
>  	vlv_dpio_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3804ef4697d5..b24ce3cff1a0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -459,13 +459,13 @@
>  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
>  #define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
>  
> -#define _CHV_CMN_DW0_CH0               0x8100
> +#define CHV_CMN_DW0_CH0			0x8100
>  #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
>  #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
>  #define   DPIO_ALLDL_POWERDOWN			(1 << 1)
>  #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
>  
> -#define _CHV_CMN_DW5_CH0               0x8114
> +#define CHV_CMN_DW5_CH0			0x8114
>  #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
>  #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
>  #define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
> @@ -475,18 +475,18 @@
>  #define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
>  #define   CHV_BUFLEFTENA1_MASK		(3 << 22)
>  
> -#define _CHV_CMN_DW13_CH0		0x8134
> -#define _CHV_CMN_DW0_CH1		0x8080
> +#define CHV_CMN_DW13_CH0		0x8134
> +#define CHV_CMN_DW0_CH1			0x8080
>  #define   DPIO_CHV_S1_DIV_SHIFT		21
>  #define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
>  #define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
>  #define   DPIO_CHV_K_DIV_SHIFT		4
>  #define   DPIO_PLL_FREQLOCK		(1 << 1)
>  #define   DPIO_PLL_LOCK			(1 << 0)
> -#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
> +#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
>  
> -#define _CHV_CMN_DW14_CH0		0x8138
> -#define _CHV_CMN_DW1_CH1		0x8084
> +#define CHV_CMN_DW14_CH0		0x8138
> +#define CHV_CMN_DW1_CH1			0x8084
>  #define   DPIO_AFC_RECAL		(1 << 14)
>  #define   DPIO_DCLKP_EN			(1 << 13)
>  #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
> @@ -497,16 +497,15 @@
>  #define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
>  #define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
>  #define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
> -#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
> +#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
>  
> -#define _CHV_CMN_DW19_CH0		0x814c
> -#define _CHV_CMN_DW6_CH1		0x8098
> +#define CHV_CMN_DW19_CH0		0x814c
> +#define CHV_CMN_DW6_CH1		0x8098
>  #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
>  #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
>  #define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
>  #define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
> -
> -#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
> +#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
>  
>  #define CHV_CMN_DW28			0x8170
>  #define   DPIO_CL1POWERDOWNEN		(1 << 23)

-- 
Jani Nikula, Intel

Re: [PATCH 13/14] drm/i915/dpio: Clean up the vlv/chv PHY register bits

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. for the vlv/chv DPIO PHY registers.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

What a PITA patch to review!

A couple of comments inline, overall

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

[snip]

>  #define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
> -#define   DPIO_REFSEL_OVERRIDE		27
> -#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
> -#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */

Here the shift is 21...

> -#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
> -#define   DPIO_PLL_REFCLK_SEL_MASK	3
> -#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
> -#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
> +#define   DPIO_REFSEL_OVERRIDE		REG_BIT(27)
> +#define   DPIO_PLL_MODESEL_MASK		REG_GENMASK(26, 24)
> +#define   DPIO_BIAS_CURRENT_CTL_MASK	REG_GENMASK(22, 20) /* always 0x7 */

...and here it's 20. Is this is a fix to match spec or an accident?

Code offers no help as it's unused afaict.

> +#define   DPIO_PLL_REFCLK_SEL_MASK	REG_GENMASK(17, 16)
> +#define   DPIO_DRIVER_CTL_MASK		REG_GENMASK(15, 12) /* always set to 0x8 */
> +#define   DPIO_CLK_BIAS_CTL_MASK	REG_GENMASK(11, 8) /* always set to 0x5 */
>  
>  #define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)
>  
> @@ -253,101 +259,110 @@
>  #define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
>  #define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
>  #define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
> -#define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
> -#define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
> -#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
> -#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
> +#define   DPIO_PCS_TX_LANE2_RESET	REG_BIT(16)
> +#define   DPIO_PCS_TX_LANE1_RESET	REG_BIT(7)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER2	REG_BIT(4)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	REG_BIT(3)
>  
> -#define VLV_PCS_DW1_GRP(ch)		_VLV_PCS_GRP((ch), 1)
> -#define VLV_PCS01_DW1(ch)		_VLV_PCS((ch), 0, 1)
> -#define VLV_PCS23_DW1(ch)		_VLV_PCS((ch), 1, 1)
> -#define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
> -#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
> -#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
> -#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
> -#define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
> +#define VLV_PCS_DW1_GRP(ch)		 _VLV_PCS_GRP((ch), 1)
> +#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
> +#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1)
> +#define   CHV_PCS_REQ_SOFTRESET_EN		REG_BIT(23)
> +#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN		REG_BIT(22)
> +#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN	REG_BIT(21)
> +#define   DPIO_PCS_CLK_DATAWIDTH_MASK		REG_GENMASK(7, 6)
> +#define   DPIO_PCS_CLK_DATAWIDTH_8_10		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)
> +#define   DPIO_PCS_CLK_DATAWIDTH_16_20		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
> +#define   DPIO_PCS_CLK_DATAWIDTH_32_40		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)
> +#define   DPIO_PCS_CLK_SOFT_RESET		REG_BIT(5)
>  
>  #define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
>  #define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
>  #define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
> -#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
> -#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
> +#define   DPIO_PCS_USEDCLKCHANNEL		REG_BIT(21)
> +#define   DPIO_PCS_USEDCLKCHANNEL_OVRRIDE	REG_BIT(20)
>  
> -#define VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
> +#define	VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)

Is the TAB intentional here, and in a number of similar places below?

BR,
Jani.

>  #define VLV_PCS01_DW9(ch)		_VLV_PCS((ch), 0, 9)
>  #define VLV_PCS23_DW9(ch)		_VLV_PCS((ch), 1, 9)
> -#define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
> -#define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
> -#define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
> -#define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
> -#define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
> -#define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
> +#define   DPIO_PCS_TX2MARGIN_MASK	REG_GENMASK(15, 13)
> +#define   DPIO_PCS_TX2MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0)
> +#define   DPIO_PCS_TX2MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1)
> +#define   DPIO_PCS_TX1MARGIN_MASK	REG_GENMASK(12, 10)
> +#define   DPIO_PCS_TX1MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0)
> +#define   DPIO_PCS_TX1MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1)
>  
> -#define VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
> +#define	VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
>  #define VLV_PCS01_DW10(ch)		_VLV_PCS((ch), 0, 10)
>  #define VLV_PCS23_DW10(ch)		_VLV_PCS((ch), 1, 10)
> -#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
> -#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
> -#define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
> -#define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
> -#define   DPIO_PCS_TX2DEEMP_6P0		(2 << 24)
> -#define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
> -#define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
> -#define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
> +#define   DPIO_PCS_SWING_CALC_TX1_TX3	REG_BIT(31)
> +#define   DPIO_PCS_SWING_CALC_TX0_TX2	REG_BIT(30)
> +#define   DPIO_PCS_TX2DEEMP_MASK	REG_GENMASK(27, 24)
> +#define   DPIO_PCS_TX2DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0)
> +#define   DPIO_PCS_TX2DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2)
> +#define   DPIO_PCS_TX1DEEMP_MASK	REG_GENMASK(19, 16)
> +#define   DPIO_PCS_TX1DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0)
> +#define   DPIO_PCS_TX1DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2)
>  
> -#define VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
> +#define	VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
>  #define VLV_PCS01_DW11(ch)		_VLV_PCS((ch), 0, 11)
>  #define VLV_PCS23_DW11(ch)		_VLV_PCS((ch), 1, 11)
> -#define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
> -#define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
> -#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
> -#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
> +#define   DPIO_TX2_STAGGER_MASK_MASK	REG_GENMASK(28, 24)
> +#define   DPIO_TX2_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x))
> +#define   DPIO_LANEDESKEW_STRAP_OVRD	REG_BIT(3)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER	REG_BIT(1)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER	REG_BIT(0)
>  
> -#define VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
> +#define	VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
>  #define VLV_PCS01_DW12(ch)		_VLV_PCS((ch), 0, 12)
>  #define VLV_PCS23_DW12(ch)		_VLV_PCS((ch), 1, 12)
> -#define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
> -#define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
> -#define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
> -#define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
> -#define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
> +#define   DPIO_TX2_STAGGER_MULT_MASK	REG_GENMASK(22, 20)
> +#define   DPIO_TX2_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x))
> +#define   DPIO_TX1_STAGGER_MULT_MASK	REG_GENMASK(20, 16)
> +#define   DPIO_TX1_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x))
> +#define   DPIO_TX1_STAGGER_MASK_MASK	REG_GENMASK(12, 8)
> +#define   DPIO_TX1_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x))
> +#define   DPIO_LANESTAGGER_STRAP_OVRD	REG_BIT(6)
> +#define   DPIO_LANESTAGGER_STRAP_MASK	REG_GENMASK(4, 0)
> +#define   DPIO_LANESTAGGER_STRAP(x)	REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x))
>  
> -#define VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
> +#define	VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
>  #define VLV_PCS01_DW14(ch)		_VLV_PCS((ch), 0, 14)
>  #define VLV_PCS23_DW14(ch)		_VLV_PCS((ch), 1, 14)
>  
> -#define VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
> -#define VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
> +#define	VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
> +#define	VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
>  #define VLV_PCS01_DW17(ch)		_VLV_PCS((ch), 0, 17)
>  #define VLV_PCS23_DW17(ch)		_VLV_PCS((ch), 1, 17)
>  
> -#define VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
> +#define	VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
>  #define VLV_PCS01_DW23(ch)		_VLV_PCS((ch), 0, 23)
>  #define VLV_PCS23_DW23(ch)		_VLV_PCS((ch), 1, 23)
>  
>  #define VLV_TX_DW2_GRP(ch)		_VLV_TX_GRP((ch), 2)
>  #define VLV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
> -#define   DPIO_SWING_MARGIN000_SHIFT	16
> -#define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
> -#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
> +#define   DPIO_SWING_MARGIN000_MASK	REG_GENMASK(23, 16)
> +#define   DPIO_SWING_MARGIN000(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x))
> +#define   DPIO_UNIQ_TRANS_SCALE_MASK	REG_GENMASK(15, 8)
> +#define   DPIO_UNIQ_TRANS_SCALE(x)	REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x))
>  
>  #define VLV_TX_DW3_GRP(ch)		_VLV_TX_GRP((ch), 3)
>  #define VLV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
>  /* The following bit for CHV phy */
> -#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
> -#define   DPIO_SWING_MARGIN101_SHIFT	16
> -#define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
> +#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	REG_BIT(27)
> +#define   DPIO_SWING_MARGIN101_MASK	REG_GENMASK(23, 16)
> +#define   DPIO_SWING_MARGIN101(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x))
>  
>  #define VLV_TX_DW4_GRP(ch)		_VLV_TX_GRP((ch), 4)
>  #define VLV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
> -#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
> -#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
> -#define   DPIO_SWING_DEEMPH6P0_SHIFT	16
> -#define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
> +#define   DPIO_SWING_DEEMPH9P5_MASK	REG_GENMASK(31, 24)
> +#define   DPIO_SWING_DEEMPH9P5(x)	REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x))
> +#define   DPIO_SWING_DEEMPH6P0_MASK	REG_GENMASK(23, 16)
> +#define   DPIO_SWING_DEEMPH6P0_SHIFT	REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x))
>  
>  #define VLV_TX_DW5_GRP(ch)		_VLV_TX_GRP((ch), 5)
>  #define VLV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
> -#define   DPIO_TX_OCALINIT_EN		(1 << 31)
> +#define   DPIO_TX_OCALINIT_EN		REG_BIT(31)
>  
>  #define VLV_TX_DW11_GRP(ch)		_VLV_TX_GRP((ch), 11)
>  #define VLV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
> @@ -357,93 +372,107 @@
>  
>  /* CHV dpPhy registers */
>  #define CHV_PLL_DW0(ch)			_CHV_PLL((ch), 0)
> +#define   DPIO_CHV_M2_DIV_MASK		REG_GENMASK(7, 0)
> +#define   DPIO_CHV_M2_DIV(m2)		REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2))
>  
>  #define CHV_PLL_DW1(ch)			_CHV_PLL((ch), 1)
> -#define   DPIO_CHV_N_DIV_SHIFT		8
> -#define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
> +#define   DPIO_CHV_N_DIV_MASK		REG_GENMASK(11, 8)
> +#define   DPIO_CHV_N_DIV(n)		REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n))
> +#define   DPIO_CHV_M1_DIV_MASK		REG_GENMASK(2, 0)
> +#define   DPIO_CHV_M1_DIV(m1)		REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1))
> +#define   DPIO_CHV_M1_DIV_BY_2		0
>  
>  #define CHV_PLL_DW2(ch)			_CHV_PLL((ch), 2)
> +#define   DPIO_CHV_M2_FRAC_DIV_MASK	REG_GENMASK(21, 0)
> +#define   DPIO_CHV_M2_FRAC_DIV(m2_frac)	REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac))
>  
>  #define CHV_PLL_DW3(ch)			_CHV_PLL((ch), 3)
> -#define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
> -#define  DPIO_CHV_FIRST_MOD		(0 << 8)
> -#define  DPIO_CHV_SECOND_MOD		(1 << 8)
> -#define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
> -#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
> +#define   DPIO_CHV_FRAC_DIV_EN		REG_BIT(16)
> +#define   DPIO_CHV_SECOND_MOD		REG_BIT(8)
> +#define   DPIO_CHV_FEEDFWD_GAIN_MASK	REG_GENMASK(3, 0)
> +#define   DPIO_CHV_FEEDFWD_GAIN(x)	REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x))
>  
>  #define CHV_PLL_DW6(ch)			_CHV_PLL((ch), 6)
> -#define   DPIO_CHV_GAIN_CTRL_SHIFT	16
> -#define	  DPIO_CHV_INT_COEFF_SHIFT	8
> -#define   DPIO_CHV_PROP_COEFF_SHIFT	0
> +#define   DPIO_CHV_GAIN_CTRL_MASK	REG_GENMASK(18, 16)
> +#define   DPIO_CHV_GAIN_CTRL(x)		REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x))
> +#define   DPIO_CHV_INT_COEFF_MASK	REG_GENMASK(12, 8)
> +#define   DPIO_CHV_INT_COEFF(x)		REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x))
> +#define   DPIO_CHV_PROP_COEFF_MASK	REG_GENMASK(3, 0)
> +#define   DPIO_CHV_PROP_COEFF(x)	REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x))
>  
>  #define CHV_PLL_DW8(ch)			_CHV_PLL((ch), 8)
> -#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> -#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
> +#define   DPIO_CHV_TDC_TARGET_CNT_MASK	REG_GENMASK(9, 0)
> +#define   DPIO_CHV_TDC_TARGET_CNT(x)	REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x))
>  
>  #define CHV_PLL_DW9(ch)			_CHV_PLL((ch), 9)
> -#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
> -#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
> -#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
> +#define   DPIO_CHV_INT_LOCK_THRESHOLD_MASK		REG_GENMASK(3, 1)
> +#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))
> +#define   DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	REG_BIT(0) /* 1: coarse & 0 : fine  */
>  
>  #define CHV_CMN_DW0_CH0			_CHV_CMN(0, 0)
> -#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
> -#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
> -#define   DPIO_ALLDL_POWERDOWN			(1 << 1)
> -#define   DPIO_ANYDL_POWERDOWN			(1 << 0)
> +#define   DPIO_ALLDL_POWERDOWN_CH0	REG_BIT(19)
> +#define   DPIO_ANYDL_POWERDOWN_CH0	REG_BIT(18)
> +#define   DPIO_ALLDL_POWERDOWN		BIT(1)
> +#define   DPIO_ANYDL_POWERDOWN		BIT(0)
>  
>  #define CHV_CMN_DW5_CH0			_CHV_CMN(0, 5)
> -#define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
> -#define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
> -#define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
> -#define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
> -#define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
> -#define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
> -#define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
> -#define   CHV_BUFLEFTENA1_MASK		(3 << 22)
> +#define   CHV_BUFRIGHTENA1_MASK		REG_GENMASK(21, 20)
> +#define   CHV_BUFRIGHTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0)
> +#define   CHV_BUFRIGHTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1)
> +#define   CHV_BUFRIGHTENA1_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3)
> +#define   CHV_BUFLEFTENA1_MASK		REG_GENMASK(23, 22)
> +#define   CHV_BUFLEFTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0)
> +#define   CHV_BUFLEFTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1)
> +#define   CHV_BUFLEFTENA1_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3)
>  
>  #define CHV_CMN_DW13_CH0		_CHV_CMN(0, 13)
>  #define CHV_CMN_DW0_CH1			_CHV_CMN(1, 0)
> -#define   DPIO_CHV_S1_DIV_SHIFT		21
> -#define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
> -#define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
> -#define   DPIO_CHV_K_DIV_SHIFT		4
> -#define   DPIO_PLL_FREQLOCK		(1 << 1)
> -#define   DPIO_PLL_LOCK			(1 << 0)
> +#define   DPIO_CHV_S1_DIV_MASK		REG_GENMASK(23, 21)
> +#define   DPIO_CHV_S1_DIV(s1)		REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1))
> +#define   DPIO_CHV_P1_DIV_MASK		REG_GENMASK(15, 13)
> +#define   DPIO_CHV_P1_DIV(p1)		REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1))
> +#define   DPIO_CHV_P2_DIV_MASK		REG_GENMASK(12, 8)
> +#define   DPIO_CHV_P2_DIV(p2)		REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2))
> +#define   DPIO_CHV_K_DIV_MASK		REG_GENMASK(7, 4)
> +#define   DPIO_CHV_K_DIV(k)		REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))
> +#define   DPIO_PLL_FREQLOCK		REG_BIT(1)
> +#define   DPIO_PLL_LOCK			REG_BIT(0)
>  #define CHV_CMN_DW13(ch)		_PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
>  
>  #define CHV_CMN_DW14_CH0		_CHV_CMN(0, 14)
>  #define CHV_CMN_DW1_CH1			_CHV_CMN(1, 1)
> -#define   DPIO_AFC_RECAL		(1 << 14)
> -#define   DPIO_DCLKP_EN			(1 << 13)
> -#define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
> -#define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
> -#define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
> -#define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
> -#define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
> -#define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
> -#define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
> -#define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
> +#define   DPIO_AFC_RECAL		REG_BIT(14)
> +#define   DPIO_DCLKP_EN			REG_BIT(13)
> +#define   CHV_BUFLEFTENA2_MASK		REG_GENMASK(18, 17) /* CL2 DW1 only */
> +#define   CHV_BUFLEFTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0)
> +#define   CHV_BUFLEFTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1)
> +#define   CHV_BUFLEFTENA2_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3)
> +#define   CHV_BUFRIGHTENA2_MASK		REG_GENMASK(20, 19) /* CL2 DW1 only */
> +#define   CHV_BUFRIGHTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0)
> +#define   CHV_BUFRIGHTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1)
> +#define   CHV_BUFRIGHTENA2_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3)
>  #define CHV_CMN_DW14(ch)		_PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
>  
>  #define CHV_CMN_DW19_CH0		_CHV_CMN(0, 19)
>  #define CHV_CMN_DW6_CH1			_CHV_CMN(1, 6)
> -#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
> -#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
> -#define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
> -#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
> +#define   DPIO_ALLDL_POWERDOWN_CH1	REG_BIT(30) /* CL2 DW6 only */
> +#define   DPIO_ANYDL_POWERDOWN_CH1	REG_BIT(29) /* CL2 DW6 only */
> +#define   DPIO_DYNPWRDOWNEN_CH1		REG_BIT(28) /* CL2 DW6 only */
> +#define   CHV_CMN_USEDCLKCHANNEL	REG_BIT(13)
>  #define CHV_CMN_DW19(ch)		_PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
>  
>  #define CHV_CMN_DW28			_CHV_CMN(0, 28)
> -#define   DPIO_CL1POWERDOWNEN		(1 << 23)
> -#define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
> -#define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
> -#define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
> -#define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
> -#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
> +#define   DPIO_CL1POWERDOWNEN			REG_BIT(23)
> +#define   DPIO_DYNPWRDOWNEN_CH0			REG_BIT(22)
> +#define   DPIO_SUS_CLK_CONFIG_MASK		REG_GENMASK(1, 0)
> +#define   DPIO_SUS_CLK_CONFIG_ON		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0)
> +#define   DPIO_SUS_CLK_CONFIG_CLKREQ		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1)
> +#define   DPIO_SUS_CLK_CONFIG_GATE		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2)
> +#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3)
>  
>  #define CHV_CMN_DW30			_CHV_CMN(0, 30)
> -#define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
> -#define   DPIO_LRC_BYPASS		(1 << 3)
> +#define   DPIO_CL2_LDOFUSE_PWRENB	REG_BIT(6)
> +#define   DPIO_LRC_BYPASS		REG_BIT(3)
>  
>  #define CHV_TX_DW0(ch, lane)		_VLV_TX((ch), (lane), 0)
>  #define CHV_TX_DW1(ch, lane)		_VLV_TX((ch), (lane), 1)
> @@ -458,10 +487,11 @@
>  #define CHV_TX_DW10(ch, lane)		_VLV_TX((ch), (lane), 10)
>  
>  #define CHV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
> -#define   DPIO_FRC_LATENCY_SHFIT	8
> +#define   DPIO_FRC_LATENCY_MASK		REG_GENMASK(10, 8)
> +#define   DPIO_FRC_LATENCY(x)		REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x))
>  
>  #define CHV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
> -#define   DPIO_UPAR_SHIFT		30
> +#define   DPIO_UPAR			REG_BIT(30)
>  
>  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
>  #define  MIPIO_RST_CTRL				(1 << 2)

-- 
Jani Nikula, Intel

Re: [PATCH 14/14] drm/i915/dpio: Extract vlv_dpio_phy_regs.h

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Pull the VLV/CHV DPIO PHY sideband registers to their own file.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

git show --color-moved tells me this is fine.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |   1 +
>  .../i915/display/intel_display_power_well.c   |   1 +
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c |   1 +
>  drivers/gpu/drm/i915/display/intel_dpll.c     |   1 +
>  .../gpu/drm/i915/display/vlv_dpio_phy_regs.h  | 309 ++++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h               | 298 -----------------
>  6 files changed, 313 insertions(+), 298 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 96ed1490fec7..59f989207c74 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -120,6 +120,7 @@
>  #include "skl_scaler.h"
>  #include "skl_universal_plane.h"
>  #include "skl_watermark.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_dsi.h"
>  #include "vlv_dsi_pll.h"
>  #include "vlv_dsi_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index e4ba6efc90e6..83f616097a29 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -27,6 +27,7 @@
>  #include "intel_tc.h"
>  #include "intel_vga.h"
>  #include "skl_watermark.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_sideband.h"
>  #include "vlv_sideband_reg.h"
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 11875d18a8fc..d20e4e9cf7f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -30,6 +30,7 @@
>  #include "intel_display_types.h"
>  #include "intel_dp.h"
>  #include "intel_dpio_phy.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_sideband.h"
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index c2ee95993a96..a981f45facb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -20,6 +20,7 @@
>  #include "intel_panel.h"
>  #include "intel_pps.h"
>  #include "intel_snps_phy.h"
> +#include "vlv_dpio_phy_regs.h"
>  #include "vlv_sideband.h"
>  
>  struct intel_dpll_funcs {
> diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
> new file mode 100644
> index 000000000000..477506f0b2cc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h
> @@ -0,0 +1,309 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef __VLV_DPIO_PHY_REGS_H__
> +#define __VLV_DPIO_PHY_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
> +#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
> +#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
> +#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
> +#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
> +#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4)
> +#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
> +#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4)
> +#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
> +
> +/*
> + * Per pipe/PLL DPIO regs
> + */
> +#define VLV_PLL_DW3(ch)			_VLV_PLL((ch), 3)
> +#define   DPIO_S1_DIV_MASK		REG_GENMASK(30, 28)
> +#define   DPIO_S1_DIV(s1)		REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
> +#define   DPIO_S1_DIV_DAC		0 /* 10, DAC 25-225M rate */
> +#define   DPIO_S1_DIV_HDMIDP		1 /* 5, DAC 225-400M rate */
> +#define   DPIO_S1_DIV_LVDS1		2 /* 14 */
> +#define   DPIO_S1_DIV_LVDS2		3 /* 7 */
> +#define   DPIO_K_DIV_MASK		REG_GENMASK(27, 24)
> +#define   DPIO_K_DIV(k)			REG_FIELD_PREP(DPIO_K_DIV_MASK, (k))
> +#define   DPIO_P1_DIV_MASK		REG_GENMASK(23, 21)
> +#define   DPIO_P1_DIV(p1)		REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
> +#define   DPIO_P2_DIV_MASK		REG_GENMASK(20, 16)
> +#define   DPIO_P2_DIV(p2)		REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
> +#define   DPIO_N_DIV_MASK		REG_GENMASK(15, 12)
> +#define   DPIO_N_DIV(n)			REG_FIELD_PREP(DPIO_N_DIV_MASK, (n))
> +#define   DPIO_ENABLE_CALIBRATION	REG_BIT(11)
> +#define   DPIO_M1_DIV_MASK		REG_GENMASK(10, 8)
> +#define   DPIO_M1_DIV(m1)		REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1))
> +#define   DPIO_M2_DIV_MASK		REG_GENMASK(7, 0)
> +#define   DPIO_M2_DIV(m2)		REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2))
> +
> +#define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
> +#define   DPIO_REFSEL_OVERRIDE		REG_BIT(27)
> +#define   DPIO_PLL_MODESEL_MASK		REG_GENMASK(26, 24)
> +#define   DPIO_BIAS_CURRENT_CTL_MASK	REG_GENMASK(22, 20) /* always 0x7 */
> +#define   DPIO_PLL_REFCLK_SEL_MASK	REG_GENMASK(17, 16)
> +#define   DPIO_DRIVER_CTL_MASK		REG_GENMASK(15, 12) /* always set to 0x8 */
> +#define   DPIO_CLK_BIAS_CTL_MASK	REG_GENMASK(11, 8) /* always set to 0x5 */
> +
> +#define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)
> +
> +#define VLV_PLL_DW16(ch)		_VLV_PLL((ch), 16)
> +
> +#define VLV_PLL_DW17(ch)		_VLV_PLL((ch), 17)
> +
> +#define VLV_PLL_DW18(ch)		_VLV_PLL((ch), 18)
> +
> +#define VLV_PLL_DW19(ch)		_VLV_PLL((ch), 19)
> +
> +#define VLV_REF_DW11			_VLV_REF(11)
> +
> +#define VLV_CMN_DW0			_VLV_CMN(0)
> +
> +/*
> + * Per DDI channel DPIO regs
> + */
> +#define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
> +#define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
> +#define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
> +#define   DPIO_PCS_TX_LANE2_RESET	REG_BIT(16)
> +#define   DPIO_PCS_TX_LANE1_RESET	REG_BIT(7)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER2	REG_BIT(4)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	REG_BIT(3)
> +
> +#define VLV_PCS_DW1_GRP(ch)		 _VLV_PCS_GRP((ch), 1)
> +#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
> +#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1)
> +#define   CHV_PCS_REQ_SOFTRESET_EN		REG_BIT(23)
> +#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN		REG_BIT(22)
> +#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN	REG_BIT(21)
> +#define   DPIO_PCS_CLK_DATAWIDTH_MASK		REG_GENMASK(7, 6)
> +#define   DPIO_PCS_CLK_DATAWIDTH_8_10		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)
> +#define   DPIO_PCS_CLK_DATAWIDTH_16_20		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
> +#define   DPIO_PCS_CLK_DATAWIDTH_32_40		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)
> +#define   DPIO_PCS_CLK_SOFT_RESET		REG_BIT(5)
> +
> +#define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
> +#define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
> +#define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
> +#define   DPIO_PCS_USEDCLKCHANNEL		REG_BIT(21)
> +#define   DPIO_PCS_USEDCLKCHANNEL_OVRRIDE	REG_BIT(20)
> +
> +#define	VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
> +#define VLV_PCS01_DW9(ch)		_VLV_PCS((ch), 0, 9)
> +#define VLV_PCS23_DW9(ch)		_VLV_PCS((ch), 1, 9)
> +#define   DPIO_PCS_TX2MARGIN_MASK	REG_GENMASK(15, 13)
> +#define   DPIO_PCS_TX2MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0)
> +#define   DPIO_PCS_TX2MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1)
> +#define   DPIO_PCS_TX1MARGIN_MASK	REG_GENMASK(12, 10)
> +#define   DPIO_PCS_TX1MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0)
> +#define   DPIO_PCS_TX1MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1)
> +
> +#define	VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
> +#define VLV_PCS01_DW10(ch)		_VLV_PCS((ch), 0, 10)
> +#define VLV_PCS23_DW10(ch)		_VLV_PCS((ch), 1, 10)
> +#define   DPIO_PCS_SWING_CALC_TX1_TX3	REG_BIT(31)
> +#define   DPIO_PCS_SWING_CALC_TX0_TX2	REG_BIT(30)
> +#define   DPIO_PCS_TX2DEEMP_MASK	REG_GENMASK(27, 24)
> +#define   DPIO_PCS_TX2DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0)
> +#define   DPIO_PCS_TX2DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2)
> +#define   DPIO_PCS_TX1DEEMP_MASK	REG_GENMASK(19, 16)
> +#define   DPIO_PCS_TX1DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0)
> +#define   DPIO_PCS_TX1DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2)
> +
> +#define	VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
> +#define VLV_PCS01_DW11(ch)		_VLV_PCS((ch), 0, 11)
> +#define VLV_PCS23_DW11(ch)		_VLV_PCS((ch), 1, 11)
> +#define   DPIO_TX2_STAGGER_MASK_MASK	REG_GENMASK(28, 24)
> +#define   DPIO_TX2_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x))
> +#define   DPIO_LANEDESKEW_STRAP_OVRD	REG_BIT(3)
> +#define   DPIO_LEFT_TXFIFO_RST_MASTER	REG_BIT(1)
> +#define   DPIO_RIGHT_TXFIFO_RST_MASTER	REG_BIT(0)
> +
> +#define	VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
> +#define VLV_PCS01_DW12(ch)		_VLV_PCS((ch), 0, 12)
> +#define VLV_PCS23_DW12(ch)		_VLV_PCS((ch), 1, 12)
> +#define   DPIO_TX2_STAGGER_MULT_MASK	REG_GENMASK(22, 20)
> +#define   DPIO_TX2_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x))
> +#define   DPIO_TX1_STAGGER_MULT_MASK	REG_GENMASK(20, 16)
> +#define   DPIO_TX1_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x))
> +#define   DPIO_TX1_STAGGER_MASK_MASK	REG_GENMASK(12, 8)
> +#define   DPIO_TX1_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x))
> +#define   DPIO_LANESTAGGER_STRAP_OVRD	REG_BIT(6)
> +#define   DPIO_LANESTAGGER_STRAP_MASK	REG_GENMASK(4, 0)
> +#define   DPIO_LANESTAGGER_STRAP(x)	REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x))
> +
> +#define	VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
> +#define VLV_PCS01_DW14(ch)		_VLV_PCS((ch), 0, 14)
> +#define VLV_PCS23_DW14(ch)		_VLV_PCS((ch), 1, 14)
> +
> +#define	VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
> +#define	VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
> +#define VLV_PCS01_DW17(ch)		_VLV_PCS((ch), 0, 17)
> +#define VLV_PCS23_DW17(ch)		_VLV_PCS((ch), 1, 17)
> +
> +#define	VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
> +#define VLV_PCS01_DW23(ch)		_VLV_PCS((ch), 0, 23)
> +#define VLV_PCS23_DW23(ch)		_VLV_PCS((ch), 1, 23)
> +
> +#define VLV_TX_DW2_GRP(ch)		_VLV_TX_GRP((ch), 2)
> +#define VLV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
> +#define   DPIO_SWING_MARGIN000_MASK	REG_GENMASK(23, 16)
> +#define   DPIO_SWING_MARGIN000(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x))
> +#define   DPIO_UNIQ_TRANS_SCALE_MASK	REG_GENMASK(15, 8)
> +#define   DPIO_UNIQ_TRANS_SCALE(x)	REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x))
> +
> +#define VLV_TX_DW3_GRP(ch)		_VLV_TX_GRP((ch), 3)
> +#define VLV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
> +/* The following bit for CHV phy */
> +#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	REG_BIT(27)
> +#define   DPIO_SWING_MARGIN101_MASK	REG_GENMASK(23, 16)
> +#define   DPIO_SWING_MARGIN101(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x))
> +
> +#define VLV_TX_DW4_GRP(ch)		_VLV_TX_GRP((ch), 4)
> +#define VLV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
> +#define   DPIO_SWING_DEEMPH9P5_MASK	REG_GENMASK(31, 24)
> +#define   DPIO_SWING_DEEMPH9P5(x)	REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x))
> +#define   DPIO_SWING_DEEMPH6P0_MASK	REG_GENMASK(23, 16)
> +#define   DPIO_SWING_DEEMPH6P0_SHIFT	REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x))
> +
> +#define VLV_TX_DW5_GRP(ch)		_VLV_TX_GRP((ch), 5)
> +#define VLV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
> +#define   DPIO_TX_OCALINIT_EN		REG_BIT(31)
> +
> +#define VLV_TX_DW11_GRP(ch)		_VLV_TX_GRP((ch), 11)
> +#define VLV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
> +
> +#define VLV_TX_DW14_GRP(ch)		_VLV_TX_GRP((ch), 14)
> +#define VLV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
> +
> +/* CHV dpPhy registers */
> +#define CHV_PLL_DW0(ch)			_CHV_PLL((ch), 0)
> +#define   DPIO_CHV_M2_DIV_MASK		REG_GENMASK(7, 0)
> +#define   DPIO_CHV_M2_DIV(m2)		REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2))
> +
> +#define CHV_PLL_DW1(ch)			_CHV_PLL((ch), 1)
> +#define   DPIO_CHV_N_DIV_MASK		REG_GENMASK(11, 8)
> +#define   DPIO_CHV_N_DIV(n)		REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n))
> +#define   DPIO_CHV_M1_DIV_MASK		REG_GENMASK(2, 0)
> +#define   DPIO_CHV_M1_DIV(m1)		REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1))
> +#define   DPIO_CHV_M1_DIV_BY_2		0
> +
> +#define CHV_PLL_DW2(ch)			_CHV_PLL((ch), 2)
> +#define   DPIO_CHV_M2_FRAC_DIV_MASK	REG_GENMASK(21, 0)
> +#define   DPIO_CHV_M2_FRAC_DIV(m2_frac)	REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac))
> +
> +#define CHV_PLL_DW3(ch)			_CHV_PLL((ch), 3)
> +#define   DPIO_CHV_FRAC_DIV_EN		REG_BIT(16)
> +#define   DPIO_CHV_SECOND_MOD		REG_BIT(8)
> +#define   DPIO_CHV_FEEDFWD_GAIN_MASK	REG_GENMASK(3, 0)
> +#define   DPIO_CHV_FEEDFWD_GAIN(x)	REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x))
> +
> +#define CHV_PLL_DW6(ch)			_CHV_PLL((ch), 6)
> +#define   DPIO_CHV_GAIN_CTRL_MASK	REG_GENMASK(18, 16)
> +#define   DPIO_CHV_GAIN_CTRL(x)		REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x))
> +#define   DPIO_CHV_INT_COEFF_MASK	REG_GENMASK(12, 8)
> +#define   DPIO_CHV_INT_COEFF(x)		REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x))
> +#define   DPIO_CHV_PROP_COEFF_MASK	REG_GENMASK(3, 0)
> +#define   DPIO_CHV_PROP_COEFF(x)	REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x))
> +
> +#define CHV_PLL_DW8(ch)			_CHV_PLL((ch), 8)
> +#define   DPIO_CHV_TDC_TARGET_CNT_MASK	REG_GENMASK(9, 0)
> +#define   DPIO_CHV_TDC_TARGET_CNT(x)	REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x))
> +
> +#define CHV_PLL_DW9(ch)			_CHV_PLL((ch), 9)
> +#define   DPIO_CHV_INT_LOCK_THRESHOLD_MASK		REG_GENMASK(3, 1)
> +#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))
> +#define   DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	REG_BIT(0) /* 1: coarse & 0 : fine  */
> +
> +#define CHV_CMN_DW0_CH0			_CHV_CMN(0, 0)
> +#define   DPIO_ALLDL_POWERDOWN_CH0	REG_BIT(19)
> +#define   DPIO_ANYDL_POWERDOWN_CH0	REG_BIT(18)
> +#define   DPIO_ALLDL_POWERDOWN		BIT(1)
> +#define   DPIO_ANYDL_POWERDOWN		BIT(0)
> +
> +#define CHV_CMN_DW5_CH0			_CHV_CMN(0, 5)
> +#define   CHV_BUFRIGHTENA1_MASK		REG_GENMASK(21, 20)
> +#define   CHV_BUFRIGHTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0)
> +#define   CHV_BUFRIGHTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1)
> +#define   CHV_BUFRIGHTENA1_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3)
> +#define   CHV_BUFLEFTENA1_MASK		REG_GENMASK(23, 22)
> +#define   CHV_BUFLEFTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0)
> +#define   CHV_BUFLEFTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1)
> +#define   CHV_BUFLEFTENA1_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3)
> +
> +#define CHV_CMN_DW13_CH0		_CHV_CMN(0, 13)
> +#define CHV_CMN_DW0_CH1			_CHV_CMN(1, 0)
> +#define   DPIO_CHV_S1_DIV_MASK		REG_GENMASK(23, 21)
> +#define   DPIO_CHV_S1_DIV(s1)		REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1))
> +#define   DPIO_CHV_P1_DIV_MASK		REG_GENMASK(15, 13)
> +#define   DPIO_CHV_P1_DIV(p1)		REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1))
> +#define   DPIO_CHV_P2_DIV_MASK		REG_GENMASK(12, 8)
> +#define   DPIO_CHV_P2_DIV(p2)		REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2))
> +#define   DPIO_CHV_K_DIV_MASK		REG_GENMASK(7, 4)
> +#define   DPIO_CHV_K_DIV(k)		REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))
> +#define   DPIO_PLL_FREQLOCK		REG_BIT(1)
> +#define   DPIO_PLL_LOCK			REG_BIT(0)
> +#define CHV_CMN_DW13(ch)		_PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
> +
> +#define CHV_CMN_DW14_CH0		_CHV_CMN(0, 14)
> +#define CHV_CMN_DW1_CH1			_CHV_CMN(1, 1)
> +#define   DPIO_AFC_RECAL		REG_BIT(14)
> +#define   DPIO_DCLKP_EN			REG_BIT(13)
> +#define   CHV_BUFLEFTENA2_MASK		REG_GENMASK(18, 17) /* CL2 DW1 only */
> +#define   CHV_BUFLEFTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0)
> +#define   CHV_BUFLEFTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1)
> +#define   CHV_BUFLEFTENA2_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3)
> +#define   CHV_BUFRIGHTENA2_MASK		REG_GENMASK(20, 19) /* CL2 DW1 only */
> +#define   CHV_BUFRIGHTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0)
> +#define   CHV_BUFRIGHTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1)
> +#define   CHV_BUFRIGHTENA2_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3)
> +#define CHV_CMN_DW14(ch)		_PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
> +
> +#define CHV_CMN_DW19_CH0		_CHV_CMN(0, 19)
> +#define CHV_CMN_DW6_CH1			_CHV_CMN(1, 6)
> +#define   DPIO_ALLDL_POWERDOWN_CH1	REG_BIT(30) /* CL2 DW6 only */
> +#define   DPIO_ANYDL_POWERDOWN_CH1	REG_BIT(29) /* CL2 DW6 only */
> +#define   DPIO_DYNPWRDOWNEN_CH1		REG_BIT(28) /* CL2 DW6 only */
> +#define   CHV_CMN_USEDCLKCHANNEL	REG_BIT(13)
> +#define CHV_CMN_DW19(ch)		_PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
> +
> +#define CHV_CMN_DW28			_CHV_CMN(0, 28)
> +#define   DPIO_CL1POWERDOWNEN			REG_BIT(23)
> +#define   DPIO_DYNPWRDOWNEN_CH0			REG_BIT(22)
> +#define   DPIO_SUS_CLK_CONFIG_MASK		REG_GENMASK(1, 0)
> +#define   DPIO_SUS_CLK_CONFIG_ON		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0)
> +#define   DPIO_SUS_CLK_CONFIG_CLKREQ		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1)
> +#define   DPIO_SUS_CLK_CONFIG_GATE		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2)
> +#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3)
> +
> +#define CHV_CMN_DW30			_CHV_CMN(0, 30)
> +#define   DPIO_CL2_LDOFUSE_PWRENB	REG_BIT(6)
> +#define   DPIO_LRC_BYPASS		REG_BIT(3)
> +
> +#define CHV_TX_DW0(ch, lane)		_VLV_TX((ch), (lane), 0)
> +#define CHV_TX_DW1(ch, lane)		_VLV_TX((ch), (lane), 1)
> +#define CHV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
> +#define CHV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
> +#define CHV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
> +#define CHV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
> +#define CHV_TX_DW6(ch, lane)		_VLV_TX((ch), (lane), 6)
> +#define CHV_TX_DW7(ch, lane)		_VLV_TX((ch), (lane), 7)
> +#define CHV_TX_DW8(ch, lane)		_VLV_TX((ch), (lane), 8)
> +#define CHV_TX_DW9(ch, lane)		_VLV_TX((ch), (lane), 9)
> +#define CHV_TX_DW10(ch, lane)		_VLV_TX((ch), (lane), 10)
> +
> +#define CHV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
> +#define   DPIO_FRC_LATENCY_MASK		REG_GENMASK(10, 8)
> +#define   DPIO_FRC_LATENCY(x)		REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x))
> +
> +#define CHV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
> +#define   DPIO_UPAR			REG_BIT(30)
> +
> +#endif /* __VLV_DPIO_PHY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a2313658ecae..481ae5529ba2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -195,304 +195,6 @@
>  #define  DPIO_SFR_BYPASS		(1 << 1)
>  #define  DPIO_CMNRST			(1 << 0)
>  
> -#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
> -#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
> -#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
> -#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
> -#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
> -#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4)
> -#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
> -#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
> -#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4)
> -#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
> -#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
> -
> -/*
> - * Per pipe/PLL DPIO regs
> - */
> -#define VLV_PLL_DW3(ch)			_VLV_PLL((ch), 3)
> -#define   DPIO_S1_DIV_MASK		REG_GENMASK(30, 28)
> -#define   DPIO_S1_DIV(s1)		REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1))
> -#define   DPIO_S1_DIV_DAC		0 /* 10, DAC 25-225M rate */
> -#define   DPIO_S1_DIV_HDMIDP		1 /* 5, DAC 225-400M rate */
> -#define   DPIO_S1_DIV_LVDS1		2 /* 14 */
> -#define   DPIO_S1_DIV_LVDS2		3 /* 7 */
> -#define   DPIO_K_DIV_MASK		REG_GENMASK(27, 24)
> -#define   DPIO_K_DIV(k)			REG_FIELD_PREP(DPIO_K_DIV_MASK, (k))
> -#define   DPIO_P1_DIV_MASK		REG_GENMASK(23, 21)
> -#define   DPIO_P1_DIV(p1)		REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1))
> -#define   DPIO_P2_DIV_MASK		REG_GENMASK(20, 16)
> -#define   DPIO_P2_DIV(p2)		REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2))
> -#define   DPIO_N_DIV_MASK		REG_GENMASK(15, 12)
> -#define   DPIO_N_DIV(n)			REG_FIELD_PREP(DPIO_N_DIV_MASK, (n))
> -#define   DPIO_ENABLE_CALIBRATION	REG_BIT(11)
> -#define   DPIO_M1_DIV_MASK		REG_GENMASK(10, 8)
> -#define   DPIO_M1_DIV(m1)		REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1))
> -#define   DPIO_M2_DIV_MASK		REG_GENMASK(7, 0)
> -#define   DPIO_M2_DIV(m2)		REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2))
> -
> -#define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
> -#define   DPIO_REFSEL_OVERRIDE		REG_BIT(27)
> -#define   DPIO_PLL_MODESEL_MASK		REG_GENMASK(26, 24)
> -#define   DPIO_BIAS_CURRENT_CTL_MASK	REG_GENMASK(22, 20) /* always 0x7 */
> -#define   DPIO_PLL_REFCLK_SEL_MASK	REG_GENMASK(17, 16)
> -#define   DPIO_DRIVER_CTL_MASK		REG_GENMASK(15, 12) /* always set to 0x8 */
> -#define   DPIO_CLK_BIAS_CTL_MASK	REG_GENMASK(11, 8) /* always set to 0x5 */
> -
> -#define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)
> -
> -#define VLV_PLL_DW16(ch)		_VLV_PLL((ch), 16)
> -
> -#define VLV_PLL_DW17(ch)		_VLV_PLL((ch), 17)
> -
> -#define VLV_PLL_DW18(ch)		_VLV_PLL((ch), 18)
> -
> -#define VLV_PLL_DW19(ch)		_VLV_PLL((ch), 19)
> -
> -#define VLV_REF_DW11			_VLV_REF(11)
> -
> -#define VLV_CMN_DW0			_VLV_CMN(0)
> -
> -/*
> - * Per DDI channel DPIO regs
> - */
> -#define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
> -#define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
> -#define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
> -#define   DPIO_PCS_TX_LANE2_RESET	REG_BIT(16)
> -#define   DPIO_PCS_TX_LANE1_RESET	REG_BIT(7)
> -#define   DPIO_LEFT_TXFIFO_RST_MASTER2	REG_BIT(4)
> -#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	REG_BIT(3)
> -
> -#define VLV_PCS_DW1_GRP(ch)		 _VLV_PCS_GRP((ch), 1)
> -#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
> -#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1)
> -#define   CHV_PCS_REQ_SOFTRESET_EN		REG_BIT(23)
> -#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN		REG_BIT(22)
> -#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN	REG_BIT(21)
> -#define   DPIO_PCS_CLK_DATAWIDTH_MASK		REG_GENMASK(7, 6)
> -#define   DPIO_PCS_CLK_DATAWIDTH_8_10		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)
> -#define   DPIO_PCS_CLK_DATAWIDTH_16_20		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
> -#define   DPIO_PCS_CLK_DATAWIDTH_32_40		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)
> -#define   DPIO_PCS_CLK_SOFT_RESET		REG_BIT(5)
> -
> -#define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
> -#define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
> -#define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
> -#define   DPIO_PCS_USEDCLKCHANNEL		REG_BIT(21)
> -#define   DPIO_PCS_USEDCLKCHANNEL_OVRRIDE	REG_BIT(20)
> -
> -#define	VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
> -#define VLV_PCS01_DW9(ch)		_VLV_PCS((ch), 0, 9)
> -#define VLV_PCS23_DW9(ch)		_VLV_PCS((ch), 1, 9)
> -#define   DPIO_PCS_TX2MARGIN_MASK	REG_GENMASK(15, 13)
> -#define   DPIO_PCS_TX2MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0)
> -#define   DPIO_PCS_TX2MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1)
> -#define   DPIO_PCS_TX1MARGIN_MASK	REG_GENMASK(12, 10)
> -#define   DPIO_PCS_TX1MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0)
> -#define   DPIO_PCS_TX1MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1)
> -
> -#define	VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
> -#define VLV_PCS01_DW10(ch)		_VLV_PCS((ch), 0, 10)
> -#define VLV_PCS23_DW10(ch)		_VLV_PCS((ch), 1, 10)
> -#define   DPIO_PCS_SWING_CALC_TX1_TX3	REG_BIT(31)
> -#define   DPIO_PCS_SWING_CALC_TX0_TX2	REG_BIT(30)
> -#define   DPIO_PCS_TX2DEEMP_MASK	REG_GENMASK(27, 24)
> -#define   DPIO_PCS_TX2DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0)
> -#define   DPIO_PCS_TX2DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2)
> -#define   DPIO_PCS_TX1DEEMP_MASK	REG_GENMASK(19, 16)
> -#define   DPIO_PCS_TX1DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0)
> -#define   DPIO_PCS_TX1DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2)
> -
> -#define	VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
> -#define VLV_PCS01_DW11(ch)		_VLV_PCS((ch), 0, 11)
> -#define VLV_PCS23_DW11(ch)		_VLV_PCS((ch), 1, 11)
> -#define   DPIO_TX2_STAGGER_MASK_MASK	REG_GENMASK(28, 24)
> -#define   DPIO_TX2_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x))
> -#define   DPIO_LANEDESKEW_STRAP_OVRD	REG_BIT(3)
> -#define   DPIO_LEFT_TXFIFO_RST_MASTER	REG_BIT(1)
> -#define   DPIO_RIGHT_TXFIFO_RST_MASTER	REG_BIT(0)
> -
> -#define	VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
> -#define VLV_PCS01_DW12(ch)		_VLV_PCS((ch), 0, 12)
> -#define VLV_PCS23_DW12(ch)		_VLV_PCS((ch), 1, 12)
> -#define   DPIO_TX2_STAGGER_MULT_MASK	REG_GENMASK(22, 20)
> -#define   DPIO_TX2_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x))
> -#define   DPIO_TX1_STAGGER_MULT_MASK	REG_GENMASK(20, 16)
> -#define   DPIO_TX1_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x))
> -#define   DPIO_TX1_STAGGER_MASK_MASK	REG_GENMASK(12, 8)
> -#define   DPIO_TX1_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x))
> -#define   DPIO_LANESTAGGER_STRAP_OVRD	REG_BIT(6)
> -#define   DPIO_LANESTAGGER_STRAP_MASK	REG_GENMASK(4, 0)
> -#define   DPIO_LANESTAGGER_STRAP(x)	REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x))
> -
> -#define	VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
> -#define VLV_PCS01_DW14(ch)		_VLV_PCS((ch), 0, 14)
> -#define VLV_PCS23_DW14(ch)		_VLV_PCS((ch), 1, 14)
> -
> -#define	VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
> -#define	VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
> -#define VLV_PCS01_DW17(ch)		_VLV_PCS((ch), 0, 17)
> -#define VLV_PCS23_DW17(ch)		_VLV_PCS((ch), 1, 17)
> -
> -#define	VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
> -#define VLV_PCS01_DW23(ch)		_VLV_PCS((ch), 0, 23)
> -#define VLV_PCS23_DW23(ch)		_VLV_PCS((ch), 1, 23)
> -
> -#define VLV_TX_DW2_GRP(ch)		_VLV_TX_GRP((ch), 2)
> -#define VLV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
> -#define   DPIO_SWING_MARGIN000_MASK	REG_GENMASK(23, 16)
> -#define   DPIO_SWING_MARGIN000(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x))
> -#define   DPIO_UNIQ_TRANS_SCALE_MASK	REG_GENMASK(15, 8)
> -#define   DPIO_UNIQ_TRANS_SCALE(x)	REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x))
> -
> -#define VLV_TX_DW3_GRP(ch)		_VLV_TX_GRP((ch), 3)
> -#define VLV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
> -/* The following bit for CHV phy */
> -#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	REG_BIT(27)
> -#define   DPIO_SWING_MARGIN101_MASK	REG_GENMASK(23, 16)
> -#define   DPIO_SWING_MARGIN101(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x))
> -
> -#define VLV_TX_DW4_GRP(ch)		_VLV_TX_GRP((ch), 4)
> -#define VLV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
> -#define   DPIO_SWING_DEEMPH9P5_MASK	REG_GENMASK(31, 24)
> -#define   DPIO_SWING_DEEMPH9P5(x)	REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x))
> -#define   DPIO_SWING_DEEMPH6P0_MASK	REG_GENMASK(23, 16)
> -#define   DPIO_SWING_DEEMPH6P0_SHIFT	REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x))
> -
> -#define VLV_TX_DW5_GRP(ch)		_VLV_TX_GRP((ch), 5)
> -#define VLV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
> -#define   DPIO_TX_OCALINIT_EN		REG_BIT(31)
> -
> -#define VLV_TX_DW11_GRP(ch)		_VLV_TX_GRP((ch), 11)
> -#define VLV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
> -
> -#define VLV_TX_DW14_GRP(ch)		_VLV_TX_GRP((ch), 14)
> -#define VLV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
> -
> -/* CHV dpPhy registers */
> -#define CHV_PLL_DW0(ch)			_CHV_PLL((ch), 0)
> -#define   DPIO_CHV_M2_DIV_MASK		REG_GENMASK(7, 0)
> -#define   DPIO_CHV_M2_DIV(m2)		REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2))
> -
> -#define CHV_PLL_DW1(ch)			_CHV_PLL((ch), 1)
> -#define   DPIO_CHV_N_DIV_MASK		REG_GENMASK(11, 8)
> -#define   DPIO_CHV_N_DIV(n)		REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n))
> -#define   DPIO_CHV_M1_DIV_MASK		REG_GENMASK(2, 0)
> -#define   DPIO_CHV_M1_DIV(m1)		REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1))
> -#define   DPIO_CHV_M1_DIV_BY_2		0
> -
> -#define CHV_PLL_DW2(ch)			_CHV_PLL((ch), 2)
> -#define   DPIO_CHV_M2_FRAC_DIV_MASK	REG_GENMASK(21, 0)
> -#define   DPIO_CHV_M2_FRAC_DIV(m2_frac)	REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac))
> -
> -#define CHV_PLL_DW3(ch)			_CHV_PLL((ch), 3)
> -#define   DPIO_CHV_FRAC_DIV_EN		REG_BIT(16)
> -#define   DPIO_CHV_SECOND_MOD		REG_BIT(8)
> -#define   DPIO_CHV_FEEDFWD_GAIN_MASK	REG_GENMASK(3, 0)
> -#define   DPIO_CHV_FEEDFWD_GAIN(x)	REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x))
> -
> -#define CHV_PLL_DW6(ch)			_CHV_PLL((ch), 6)
> -#define   DPIO_CHV_GAIN_CTRL_MASK	REG_GENMASK(18, 16)
> -#define   DPIO_CHV_GAIN_CTRL(x)		REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x))
> -#define   DPIO_CHV_INT_COEFF_MASK	REG_GENMASK(12, 8)
> -#define   DPIO_CHV_INT_COEFF(x)		REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x))
> -#define   DPIO_CHV_PROP_COEFF_MASK	REG_GENMASK(3, 0)
> -#define   DPIO_CHV_PROP_COEFF(x)	REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x))
> -
> -#define CHV_PLL_DW8(ch)			_CHV_PLL((ch), 8)
> -#define   DPIO_CHV_TDC_TARGET_CNT_MASK	REG_GENMASK(9, 0)
> -#define   DPIO_CHV_TDC_TARGET_CNT(x)	REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x))
> -
> -#define CHV_PLL_DW9(ch)			_CHV_PLL((ch), 9)
> -#define   DPIO_CHV_INT_LOCK_THRESHOLD_MASK		REG_GENMASK(3, 1)
> -#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))
> -#define   DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	REG_BIT(0) /* 1: coarse & 0 : fine  */
> -
> -#define CHV_CMN_DW0_CH0			_CHV_CMN(0, 0)
> -#define   DPIO_ALLDL_POWERDOWN_CH0	REG_BIT(19)
> -#define   DPIO_ANYDL_POWERDOWN_CH0	REG_BIT(18)
> -#define   DPIO_ALLDL_POWERDOWN		BIT(1)
> -#define   DPIO_ANYDL_POWERDOWN		BIT(0)
> -
> -#define CHV_CMN_DW5_CH0			_CHV_CMN(0, 5)
> -#define   CHV_BUFRIGHTENA1_MASK		REG_GENMASK(21, 20)
> -#define   CHV_BUFRIGHTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0)
> -#define   CHV_BUFRIGHTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1)
> -#define   CHV_BUFRIGHTENA1_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3)
> -#define   CHV_BUFLEFTENA1_MASK		REG_GENMASK(23, 22)
> -#define   CHV_BUFLEFTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0)
> -#define   CHV_BUFLEFTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1)
> -#define   CHV_BUFLEFTENA1_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3)
> -
> -#define CHV_CMN_DW13_CH0		_CHV_CMN(0, 13)
> -#define CHV_CMN_DW0_CH1			_CHV_CMN(1, 0)
> -#define   DPIO_CHV_S1_DIV_MASK		REG_GENMASK(23, 21)
> -#define   DPIO_CHV_S1_DIV(s1)		REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1))
> -#define   DPIO_CHV_P1_DIV_MASK		REG_GENMASK(15, 13)
> -#define   DPIO_CHV_P1_DIV(p1)		REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1))
> -#define   DPIO_CHV_P2_DIV_MASK		REG_GENMASK(12, 8)
> -#define   DPIO_CHV_P2_DIV(p2)		REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2))
> -#define   DPIO_CHV_K_DIV_MASK		REG_GENMASK(7, 4)
> -#define   DPIO_CHV_K_DIV(k)		REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))
> -#define   DPIO_PLL_FREQLOCK		REG_BIT(1)
> -#define   DPIO_PLL_LOCK			REG_BIT(0)
> -#define CHV_CMN_DW13(ch)		_PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
> -
> -#define CHV_CMN_DW14_CH0		_CHV_CMN(0, 14)
> -#define CHV_CMN_DW1_CH1			_CHV_CMN(1, 1)
> -#define   DPIO_AFC_RECAL		REG_BIT(14)
> -#define   DPIO_DCLKP_EN			REG_BIT(13)
> -#define   CHV_BUFLEFTENA2_MASK		REG_GENMASK(18, 17) /* CL2 DW1 only */
> -#define   CHV_BUFLEFTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0)
> -#define   CHV_BUFLEFTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1)
> -#define   CHV_BUFLEFTENA2_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3)
> -#define   CHV_BUFRIGHTENA2_MASK		REG_GENMASK(20, 19) /* CL2 DW1 only */
> -#define   CHV_BUFRIGHTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0)
> -#define   CHV_BUFRIGHTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1)
> -#define   CHV_BUFRIGHTENA2_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3)
> -#define CHV_CMN_DW14(ch)		_PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
> -
> -#define CHV_CMN_DW19_CH0		_CHV_CMN(0, 19)
> -#define CHV_CMN_DW6_CH1			_CHV_CMN(1, 6)
> -#define   DPIO_ALLDL_POWERDOWN_CH1	REG_BIT(30) /* CL2 DW6 only */
> -#define   DPIO_ANYDL_POWERDOWN_CH1	REG_BIT(29) /* CL2 DW6 only */
> -#define   DPIO_DYNPWRDOWNEN_CH1		REG_BIT(28) /* CL2 DW6 only */
> -#define   CHV_CMN_USEDCLKCHANNEL	REG_BIT(13)
> -#define CHV_CMN_DW19(ch)		_PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
> -
> -#define CHV_CMN_DW28			_CHV_CMN(0, 28)
> -#define   DPIO_CL1POWERDOWNEN			REG_BIT(23)
> -#define   DPIO_DYNPWRDOWNEN_CH0			REG_BIT(22)
> -#define   DPIO_SUS_CLK_CONFIG_MASK		REG_GENMASK(1, 0)
> -#define   DPIO_SUS_CLK_CONFIG_ON		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0)
> -#define   DPIO_SUS_CLK_CONFIG_CLKREQ		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1)
> -#define   DPIO_SUS_CLK_CONFIG_GATE		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2)
> -#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3)
> -
> -#define CHV_CMN_DW30			_CHV_CMN(0, 30)
> -#define   DPIO_CL2_LDOFUSE_PWRENB	REG_BIT(6)
> -#define   DPIO_LRC_BYPASS		REG_BIT(3)
> -
> -#define CHV_TX_DW0(ch, lane)		_VLV_TX((ch), (lane), 0)
> -#define CHV_TX_DW1(ch, lane)		_VLV_TX((ch), (lane), 1)
> -#define CHV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
> -#define CHV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
> -#define CHV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
> -#define CHV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
> -#define CHV_TX_DW6(ch, lane)		_VLV_TX((ch), (lane), 6)
> -#define CHV_TX_DW7(ch, lane)		_VLV_TX((ch), (lane), 7)
> -#define CHV_TX_DW8(ch, lane)		_VLV_TX((ch), (lane), 8)
> -#define CHV_TX_DW9(ch, lane)		_VLV_TX((ch), (lane), 9)
> -#define CHV_TX_DW10(ch, lane)		_VLV_TX((ch), (lane), 10)
> -
> -#define CHV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
> -#define   DPIO_FRC_LATENCY_MASK		REG_GENMASK(10, 8)
> -#define   DPIO_FRC_LATENCY(x)		REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x))
> -
> -#define CHV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
> -#define   DPIO_UPAR			REG_BIT(30)
> -
>  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
>  #define  MIPIO_RST_CTRL				(1 << 2)

-- 
Jani Nikula, Intel

Re: [PATCH 13/14] drm/i915/dpio: Clean up the vlv/chv PHY register bits

[Ville Syrjälä]

On Mon, Apr 22, 2024 at 03:46:01PM +0300, Jani Nikula wrote:
> On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Use REG_BIT() & co. for the vlv/chv DPIO PHY registers.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> What a PITA patch to review!

Aye. Sorry.

> 
> A couple of comments inline, overall
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> [snip]
> 
> >  #define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
> > -#define   DPIO_REFSEL_OVERRIDE		27
> > -#define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
> > -#define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
> 
> Here the shift is 21...
> 
> > -#define   DPIO_PLL_REFCLK_SEL_SHIFT	16 /* 2 bits */
> > -#define   DPIO_PLL_REFCLK_SEL_MASK	3
> > -#define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
> > -#define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
> > +#define   DPIO_REFSEL_OVERRIDE		REG_BIT(27)
> > +#define   DPIO_PLL_MODESEL_MASK		REG_GENMASK(26, 24)
> > +#define   DPIO_BIAS_CURRENT_CTL_MASK	REG_GENMASK(22, 20) /* always 0x7 */
> 
> ...and here it's 20. Is this is a fix to match spec or an accident?

20 looks to be the correct number. I guess I fixed it up when I
originally wrote this patch, which apparently happened a few
years ago. How time flies.

> 
> Code offers no help as it's unused afaict.
> 
> > +#define   DPIO_PLL_REFCLK_SEL_MASK	REG_GENMASK(17, 16)
> > +#define   DPIO_DRIVER_CTL_MASK		REG_GENMASK(15, 12) /* always set to 0x8 */
> > +#define   DPIO_CLK_BIAS_CTL_MASK	REG_GENMASK(11, 8) /* always set to 0x5 */
> >  
> >  #define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)
> >  
> > @@ -253,101 +259,110 @@
> >  #define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
> >  #define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
> >  #define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
> > -#define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
> > -#define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
> > -#define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
> > -#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
> > +#define   DPIO_PCS_TX_LANE2_RESET	REG_BIT(16)
> > +#define   DPIO_PCS_TX_LANE1_RESET	REG_BIT(7)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER2	REG_BIT(4)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER2	REG_BIT(3)
> >  
> > -#define VLV_PCS_DW1_GRP(ch)		_VLV_PCS_GRP((ch), 1)
> > -#define VLV_PCS01_DW1(ch)		_VLV_PCS((ch), 0, 1)
> > -#define VLV_PCS23_DW1(ch)		_VLV_PCS((ch), 1, 1)
> > -#define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
> > -#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
> > -#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
> > -#define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
> > -#define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
> > +#define VLV_PCS_DW1_GRP(ch)		 _VLV_PCS_GRP((ch), 1)
> > +#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1)
> > +#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1)
> > +#define   CHV_PCS_REQ_SOFTRESET_EN		REG_BIT(23)
> > +#define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN		REG_BIT(22)
> > +#define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN	REG_BIT(21)
> > +#define   DPIO_PCS_CLK_DATAWIDTH_MASK		REG_GENMASK(7, 6)
> > +#define   DPIO_PCS_CLK_DATAWIDTH_8_10		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1)
> > +#define   DPIO_PCS_CLK_DATAWIDTH_16_20		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2)
> > +#define   DPIO_PCS_CLK_DATAWIDTH_32_40		REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3)
> > +#define   DPIO_PCS_CLK_SOFT_RESET		REG_BIT(5)
> >  
> >  #define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
> >  #define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
> >  #define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
> > -#define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
> > -#define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
> > +#define   DPIO_PCS_USEDCLKCHANNEL		REG_BIT(21)
> > +#define   DPIO_PCS_USEDCLKCHANNEL_OVRRIDE	REG_BIT(20)
> >  
> > -#define VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
> > +#define	VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
> 
> Is the TAB intentional here, and in a number of similar places below?

No. I did spot some stray tabs before sending and thought I cleaned
then all up, but somehow they keep sneaking past my radar :/

> 
> BR,
> Jani.
> 
> >  #define VLV_PCS01_DW9(ch)		_VLV_PCS((ch), 0, 9)
> >  #define VLV_PCS23_DW9(ch)		_VLV_PCS((ch), 1, 9)
> > -#define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
> > -#define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
> > -#define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
> > -#define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
> > -#define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
> > -#define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
> > +#define   DPIO_PCS_TX2MARGIN_MASK	REG_GENMASK(15, 13)
> > +#define   DPIO_PCS_TX2MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0)
> > +#define   DPIO_PCS_TX2MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1)
> > +#define   DPIO_PCS_TX1MARGIN_MASK	REG_GENMASK(12, 10)
> > +#define   DPIO_PCS_TX1MARGIN_000	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0)
> > +#define   DPIO_PCS_TX1MARGIN_101	REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1)
> >  
> > -#define VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
> > +#define	VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
> >  #define VLV_PCS01_DW10(ch)		_VLV_PCS((ch), 0, 10)
> >  #define VLV_PCS23_DW10(ch)		_VLV_PCS((ch), 1, 10)
> > -#define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
> > -#define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
> > -#define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
> > -#define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
> > -#define   DPIO_PCS_TX2DEEMP_6P0		(2 << 24)
> > -#define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
> > -#define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
> > -#define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
> > +#define   DPIO_PCS_SWING_CALC_TX1_TX3	REG_BIT(31)
> > +#define   DPIO_PCS_SWING_CALC_TX0_TX2	REG_BIT(30)
> > +#define   DPIO_PCS_TX2DEEMP_MASK	REG_GENMASK(27, 24)
> > +#define   DPIO_PCS_TX2DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0)
> > +#define   DPIO_PCS_TX2DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2)
> > +#define   DPIO_PCS_TX1DEEMP_MASK	REG_GENMASK(19, 16)
> > +#define   DPIO_PCS_TX1DEEMP_9P5		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0)
> > +#define   DPIO_PCS_TX1DEEMP_6P0		REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2)
> >  
> > -#define VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
> > +#define	VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
> >  #define VLV_PCS01_DW11(ch)		_VLV_PCS((ch), 0, 11)
> >  #define VLV_PCS23_DW11(ch)		_VLV_PCS((ch), 1, 11)
> > -#define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
> > -#define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
> > -#define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
> > -#define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
> > +#define   DPIO_TX2_STAGGER_MASK_MASK	REG_GENMASK(28, 24)
> > +#define   DPIO_TX2_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x))
> > +#define   DPIO_LANEDESKEW_STRAP_OVRD	REG_BIT(3)
> > +#define   DPIO_LEFT_TXFIFO_RST_MASTER	REG_BIT(1)
> > +#define   DPIO_RIGHT_TXFIFO_RST_MASTER	REG_BIT(0)
> >  
> > -#define VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
> > +#define	VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
> >  #define VLV_PCS01_DW12(ch)		_VLV_PCS((ch), 0, 12)
> >  #define VLV_PCS23_DW12(ch)		_VLV_PCS((ch), 1, 12)
> > -#define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
> > -#define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
> > -#define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
> > -#define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
> > -#define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
> > +#define   DPIO_TX2_STAGGER_MULT_MASK	REG_GENMASK(22, 20)
> > +#define   DPIO_TX2_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x))
> > +#define   DPIO_TX1_STAGGER_MULT_MASK	REG_GENMASK(20, 16)
> > +#define   DPIO_TX1_STAGGER_MULT(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x))
> > +#define   DPIO_TX1_STAGGER_MASK_MASK	REG_GENMASK(12, 8)
> > +#define   DPIO_TX1_STAGGER_MASK(x)	REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x))
> > +#define   DPIO_LANESTAGGER_STRAP_OVRD	REG_BIT(6)
> > +#define   DPIO_LANESTAGGER_STRAP_MASK	REG_GENMASK(4, 0)
> > +#define   DPIO_LANESTAGGER_STRAP(x)	REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x))
> >  
> > -#define VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
> > +#define	VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
> >  #define VLV_PCS01_DW14(ch)		_VLV_PCS((ch), 0, 14)
> >  #define VLV_PCS23_DW14(ch)		_VLV_PCS((ch), 1, 14)
> >  
> > -#define VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
> > -#define VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
> > +#define	VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
> > +#define	VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
> >  #define VLV_PCS01_DW17(ch)		_VLV_PCS((ch), 0, 17)
> >  #define VLV_PCS23_DW17(ch)		_VLV_PCS((ch), 1, 17)
> >  
> > -#define VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
> > +#define	VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
> >  #define VLV_PCS01_DW23(ch)		_VLV_PCS((ch), 0, 23)
> >  #define VLV_PCS23_DW23(ch)		_VLV_PCS((ch), 1, 23)
> >  
> >  #define VLV_TX_DW2_GRP(ch)		_VLV_TX_GRP((ch), 2)
> >  #define VLV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
> > -#define   DPIO_SWING_MARGIN000_SHIFT	16
> > -#define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
> > -#define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
> > +#define   DPIO_SWING_MARGIN000_MASK	REG_GENMASK(23, 16)
> > +#define   DPIO_SWING_MARGIN000(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x))
> > +#define   DPIO_UNIQ_TRANS_SCALE_MASK	REG_GENMASK(15, 8)
> > +#define   DPIO_UNIQ_TRANS_SCALE(x)	REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x))
> >  
> >  #define VLV_TX_DW3_GRP(ch)		_VLV_TX_GRP((ch), 3)
> >  #define VLV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
> >  /* The following bit for CHV phy */
> > -#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
> > -#define   DPIO_SWING_MARGIN101_SHIFT	16
> > -#define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
> > +#define   DPIO_TX_UNIQ_TRANS_SCALE_EN	REG_BIT(27)
> > +#define   DPIO_SWING_MARGIN101_MASK	REG_GENMASK(23, 16)
> > +#define   DPIO_SWING_MARGIN101(x)	REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x))
> >  
> >  #define VLV_TX_DW4_GRP(ch)		_VLV_TX_GRP((ch), 4)
> >  #define VLV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
> > -#define   DPIO_SWING_DEEMPH9P5_SHIFT	24
> > -#define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
> > -#define   DPIO_SWING_DEEMPH6P0_SHIFT	16
> > -#define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
> > +#define   DPIO_SWING_DEEMPH9P5_MASK	REG_GENMASK(31, 24)
> > +#define   DPIO_SWING_DEEMPH9P5(x)	REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x))
> > +#define   DPIO_SWING_DEEMPH6P0_MASK	REG_GENMASK(23, 16)
> > +#define   DPIO_SWING_DEEMPH6P0_SHIFT	REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x))
> >  
> >  #define VLV_TX_DW5_GRP(ch)		_VLV_TX_GRP((ch), 5)
> >  #define VLV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
> > -#define   DPIO_TX_OCALINIT_EN		(1 << 31)
> > +#define   DPIO_TX_OCALINIT_EN		REG_BIT(31)
> >  
> >  #define VLV_TX_DW11_GRP(ch)		_VLV_TX_GRP((ch), 11)
> >  #define VLV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
> > @@ -357,93 +372,107 @@
> >  
> >  /* CHV dpPhy registers */
> >  #define CHV_PLL_DW0(ch)			_CHV_PLL((ch), 0)
> > +#define   DPIO_CHV_M2_DIV_MASK		REG_GENMASK(7, 0)
> > +#define   DPIO_CHV_M2_DIV(m2)		REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2))
> >  
> >  #define CHV_PLL_DW1(ch)			_CHV_PLL((ch), 1)
> > -#define   DPIO_CHV_N_DIV_SHIFT		8
> > -#define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
> > +#define   DPIO_CHV_N_DIV_MASK		REG_GENMASK(11, 8)
> > +#define   DPIO_CHV_N_DIV(n)		REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n))
> > +#define   DPIO_CHV_M1_DIV_MASK		REG_GENMASK(2, 0)
> > +#define   DPIO_CHV_M1_DIV(m1)		REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1))
> > +#define   DPIO_CHV_M1_DIV_BY_2		0
> >  
> >  #define CHV_PLL_DW2(ch)			_CHV_PLL((ch), 2)
> > +#define   DPIO_CHV_M2_FRAC_DIV_MASK	REG_GENMASK(21, 0)
> > +#define   DPIO_CHV_M2_FRAC_DIV(m2_frac)	REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac))
> >  
> >  #define CHV_PLL_DW3(ch)			_CHV_PLL((ch), 3)
> > -#define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
> > -#define  DPIO_CHV_FIRST_MOD		(0 << 8)
> > -#define  DPIO_CHV_SECOND_MOD		(1 << 8)
> > -#define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
> > -#define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
> > +#define   DPIO_CHV_FRAC_DIV_EN		REG_BIT(16)
> > +#define   DPIO_CHV_SECOND_MOD		REG_BIT(8)
> > +#define   DPIO_CHV_FEEDFWD_GAIN_MASK	REG_GENMASK(3, 0)
> > +#define   DPIO_CHV_FEEDFWD_GAIN(x)	REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x))
> >  
> >  #define CHV_PLL_DW6(ch)			_CHV_PLL((ch), 6)
> > -#define   DPIO_CHV_GAIN_CTRL_SHIFT	16
> > -#define	  DPIO_CHV_INT_COEFF_SHIFT	8
> > -#define   DPIO_CHV_PROP_COEFF_SHIFT	0
> > +#define   DPIO_CHV_GAIN_CTRL_MASK	REG_GENMASK(18, 16)
> > +#define   DPIO_CHV_GAIN_CTRL(x)		REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x))
> > +#define   DPIO_CHV_INT_COEFF_MASK	REG_GENMASK(12, 8)
> > +#define   DPIO_CHV_INT_COEFF(x)		REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x))
> > +#define   DPIO_CHV_PROP_COEFF_MASK	REG_GENMASK(3, 0)
> > +#define   DPIO_CHV_PROP_COEFF(x)	REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x))
> >  
> >  #define CHV_PLL_DW8(ch)			_CHV_PLL((ch), 8)
> > -#define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
> > -#define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
> > +#define   DPIO_CHV_TDC_TARGET_CNT_MASK	REG_GENMASK(9, 0)
> > +#define   DPIO_CHV_TDC_TARGET_CNT(x)	REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x))
> >  
> >  #define CHV_PLL_DW9(ch)			_CHV_PLL((ch), 9)
> > -#define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
> > -#define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
> > -#define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
> > +#define   DPIO_CHV_INT_LOCK_THRESHOLD_MASK		REG_GENMASK(3, 1)
> > +#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))
> > +#define   DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	REG_BIT(0) /* 1: coarse & 0 : fine  */
> >  
> >  #define CHV_CMN_DW0_CH0			_CHV_CMN(0, 0)
> > -#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
> > -#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
> > -#define   DPIO_ALLDL_POWERDOWN			(1 << 1)
> > -#define   DPIO_ANYDL_POWERDOWN			(1 << 0)
> > +#define   DPIO_ALLDL_POWERDOWN_CH0	REG_BIT(19)
> > +#define   DPIO_ANYDL_POWERDOWN_CH0	REG_BIT(18)
> > +#define   DPIO_ALLDL_POWERDOWN		BIT(1)
> > +#define   DPIO_ANYDL_POWERDOWN		BIT(0)
> >  
> >  #define CHV_CMN_DW5_CH0			_CHV_CMN(0, 5)
> > -#define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
> > -#define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
> > -#define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
> > -#define   CHV_BUFRIGHTENA1_MASK		(3 << 20)
> > -#define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
> > -#define   CHV_BUFLEFTENA1_NORMAL	(1 << 22)
> > -#define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
> > -#define   CHV_BUFLEFTENA1_MASK		(3 << 22)
> > +#define   CHV_BUFRIGHTENA1_MASK		REG_GENMASK(21, 20)
> > +#define   CHV_BUFRIGHTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0)
> > +#define   CHV_BUFRIGHTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1)
> > +#define   CHV_BUFRIGHTENA1_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3)
> > +#define   CHV_BUFLEFTENA1_MASK		REG_GENMASK(23, 22)
> > +#define   CHV_BUFLEFTENA1_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0)
> > +#define   CHV_BUFLEFTENA1_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1)
> > +#define   CHV_BUFLEFTENA1_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3)
> >  
> >  #define CHV_CMN_DW13_CH0		_CHV_CMN(0, 13)
> >  #define CHV_CMN_DW0_CH1			_CHV_CMN(1, 0)
> > -#define   DPIO_CHV_S1_DIV_SHIFT		21
> > -#define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
> > -#define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
> > -#define   DPIO_CHV_K_DIV_SHIFT		4
> > -#define   DPIO_PLL_FREQLOCK		(1 << 1)
> > -#define   DPIO_PLL_LOCK			(1 << 0)
> > +#define   DPIO_CHV_S1_DIV_MASK		REG_GENMASK(23, 21)
> > +#define   DPIO_CHV_S1_DIV(s1)		REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1))
> > +#define   DPIO_CHV_P1_DIV_MASK		REG_GENMASK(15, 13)
> > +#define   DPIO_CHV_P1_DIV(p1)		REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1))
> > +#define   DPIO_CHV_P2_DIV_MASK		REG_GENMASK(12, 8)
> > +#define   DPIO_CHV_P2_DIV(p2)		REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2))
> > +#define   DPIO_CHV_K_DIV_MASK		REG_GENMASK(7, 4)
> > +#define   DPIO_CHV_K_DIV(k)		REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k))
> > +#define   DPIO_PLL_FREQLOCK		REG_BIT(1)
> > +#define   DPIO_PLL_LOCK			REG_BIT(0)
> >  #define CHV_CMN_DW13(ch)		_PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
> >  
> >  #define CHV_CMN_DW14_CH0		_CHV_CMN(0, 14)
> >  #define CHV_CMN_DW1_CH1			_CHV_CMN(1, 1)
> > -#define   DPIO_AFC_RECAL		(1 << 14)
> > -#define   DPIO_DCLKP_EN			(1 << 13)
> > -#define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
> > -#define   CHV_BUFLEFTENA2_NORMAL	(1 << 17) /* CL2 DW1 only */
> > -#define   CHV_BUFLEFTENA2_FORCE		(3 << 17) /* CL2 DW1 only */
> > -#define   CHV_BUFLEFTENA2_MASK		(3 << 17) /* CL2 DW1 only */
> > -#define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
> > -#define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
> > -#define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
> > -#define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
> > +#define   DPIO_AFC_RECAL		REG_BIT(14)
> > +#define   DPIO_DCLKP_EN			REG_BIT(13)
> > +#define   CHV_BUFLEFTENA2_MASK		REG_GENMASK(18, 17) /* CL2 DW1 only */
> > +#define   CHV_BUFLEFTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0)
> > +#define   CHV_BUFLEFTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1)
> > +#define   CHV_BUFLEFTENA2_FORCE		REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3)
> > +#define   CHV_BUFRIGHTENA2_MASK		REG_GENMASK(20, 19) /* CL2 DW1 only */
> > +#define   CHV_BUFRIGHTENA2_DISABLE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0)
> > +#define   CHV_BUFRIGHTENA2_NORMAL	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1)
> > +#define   CHV_BUFRIGHTENA2_FORCE	REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3)
> >  #define CHV_CMN_DW14(ch)		_PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
> >  
> >  #define CHV_CMN_DW19_CH0		_CHV_CMN(0, 19)
> >  #define CHV_CMN_DW6_CH1			_CHV_CMN(1, 6)
> > -#define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
> > -#define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
> > -#define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
> > -#define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
> > +#define   DPIO_ALLDL_POWERDOWN_CH1	REG_BIT(30) /* CL2 DW6 only */
> > +#define   DPIO_ANYDL_POWERDOWN_CH1	REG_BIT(29) /* CL2 DW6 only */
> > +#define   DPIO_DYNPWRDOWNEN_CH1		REG_BIT(28) /* CL2 DW6 only */
> > +#define   CHV_CMN_USEDCLKCHANNEL	REG_BIT(13)
> >  #define CHV_CMN_DW19(ch)		_PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
> >  
> >  #define CHV_CMN_DW28			_CHV_CMN(0, 28)
> > -#define   DPIO_CL1POWERDOWNEN		(1 << 23)
> > -#define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
> > -#define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
> > -#define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
> > -#define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
> > -#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
> > +#define   DPIO_CL1POWERDOWNEN			REG_BIT(23)
> > +#define   DPIO_DYNPWRDOWNEN_CH0			REG_BIT(22)
> > +#define   DPIO_SUS_CLK_CONFIG_MASK		REG_GENMASK(1, 0)
> > +#define   DPIO_SUS_CLK_CONFIG_ON		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0)
> > +#define   DPIO_SUS_CLK_CONFIG_CLKREQ		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1)
> > +#define   DPIO_SUS_CLK_CONFIG_GATE		REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2)
> > +#define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3)
> >  
> >  #define CHV_CMN_DW30			_CHV_CMN(0, 30)
> > -#define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
> > -#define   DPIO_LRC_BYPASS		(1 << 3)
> > +#define   DPIO_CL2_LDOFUSE_PWRENB	REG_BIT(6)
> > +#define   DPIO_LRC_BYPASS		REG_BIT(3)
> >  
> >  #define CHV_TX_DW0(ch, lane)		_VLV_TX((ch), (lane), 0)
> >  #define CHV_TX_DW1(ch, lane)		_VLV_TX((ch), (lane), 1)
> > @@ -458,10 +487,11 @@
> >  #define CHV_TX_DW10(ch, lane)		_VLV_TX((ch), (lane), 10)
> >  
> >  #define CHV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
> > -#define   DPIO_FRC_LATENCY_SHFIT	8
> > +#define   DPIO_FRC_LATENCY_MASK		REG_GENMASK(10, 8)
> > +#define   DPIO_FRC_LATENCY(x)		REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x))
> >  
> >  #define CHV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
> > -#define   DPIO_UPAR_SHIFT		30
> > +#define   DPIO_UPAR			REG_BIT(30)
> >  
> >  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
> >  #define  MIPIO_RST_CTRL				(1 << 2)
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH 09/14] drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooks

[Ville Syrjälä]

On Mon, Apr 22, 2024 at 01:10:57PM +0300, Jani Nikula wrote:
> On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > diff --git a/drivers/gpu/drm/i915/vlv_sideband.c b/drivers/gpu/drm/i915/vlv_sideband.c
> > index ffa195560d0d..68291412f4cb 100644
> > --- a/drivers/gpu/drm/i915/vlv_sideband.c
> > +++ b/drivers/gpu/drm/i915/vlv_sideband.c
> > @@ -9,7 +9,6 @@
> >  #include "vlv_sideband.h"
> >  
> >  #include "display/intel_dpio_phy.h"
> > -#include "display/intel_display_types.h"
> 
> I guess this should be done in some other patch?

I think it should have been part of
commit f70a68bc1d18 ("drm/i915: convert vlv_dpio_read()/write() from
pipe to phy")

but got missed. This patch is basically what was left from a
similar change I had in my branch. I can split this hunk out
into a separate patch.

-- 
Ville Syrjälä
Intel

Re: [PATCH 12/14] drm/i915/dpio: Clean up VLV/CHV DPIO PHY register defines

[Jani Nikula]

On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The DPIO PHY registers follow clear numbering rules. Express
> those in a few macros to get rid of the hand calculated
> final offsets.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Okay, this one was even worse than patch 13. I admit I didn't go through
everything, but this is not just rubber stamping either, as I did set up
a spreadsheet to verify a lot of the changes here. Did a few spot checks
on some of the other stuff, and didn't find any mishaps.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_dpio_phy.c |   2 +-
>  drivers/gpu/drm/i915/i915_reg.h               | 271 +++++++-----------
>  2 files changed, 99 insertions(+), 174 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 89a51b420075..fa665d353df9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -1078,7 +1078,7 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
>  	vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040);
>  
>  	if (tx3_demph)
> -		vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(ch), tx3_demph);
> +		vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph);
>  
>  	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000);
>  	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b24ce3cff1a0..6d16f9944eff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -195,10 +195,22 @@
>  #define  DPIO_SFR_BYPASS		(1 << 1)
>  #define  DPIO_CMNRST			(1 << 0)
>  
> +#define _VLV_CMN(dw) (0x8100 + (dw) * 4)
> +#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4)
> +#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */
> +#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4)
> +#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */
> +#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4)
> +#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4)
> +#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4)
> +#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4)
> +#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4)
> +
>  /*
>   * Per pipe/PLL DPIO regs
>   */
> -#define _VLV_PLL_DW3_CH0		0x800c
> +#define VLV_PLL_DW3(ch)			_VLV_PLL((ch), 3)
>  #define   DPIO_POST_DIV_SHIFT		(28) /* 3 bits */
>  #define   DPIO_POST_DIV_DAC		0
>  #define   DPIO_POST_DIV_HDMIDP		1 /* DAC 225-400M rate */
> @@ -211,10 +223,8 @@
>  #define   DPIO_ENABLE_CALIBRATION	(1 << 11)
>  #define   DPIO_M1DIV_SHIFT		(8) /* 3 bits */
>  #define   DPIO_M2DIV_MASK		0xff
> -#define _VLV_PLL_DW3_CH1		0x802c
> -#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
>  
> -#define _VLV_PLL_DW5_CH0		0x8014
> +#define VLV_PLL_DW5(ch)			_VLV_PLL((ch), 5)
>  #define   DPIO_REFSEL_OVERRIDE		27
>  #define   DPIO_PLL_MODESEL_SHIFT	24 /* 3 bits */
>  #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
> @@ -222,101 +232,60 @@
>  #define   DPIO_PLL_REFCLK_SEL_MASK	3
>  #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
>  #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
> -#define _VLV_PLL_DW5_CH1		0x8034
> -#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
>  
> -#define _VLV_PLL_DW7_CH0		0x801c
> -#define _VLV_PLL_DW7_CH1		0x803c
> -#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
> +#define VLV_PLL_DW7(ch)			_VLV_PLL((ch), 7)
>  
> -#define _VLV_PLL_DW16_CH0		0x8040
> -#define _VLV_PLL_DW16_CH1		0x8060
> -#define VLV_PLL_DW16(ch) _PIPE(ch, _VLV_PLL_DW16_CH0, _VLV_PLL_DW16_CH1)
> +#define VLV_PLL_DW16(ch)		_VLV_PLL((ch), 16)
>  
> -#define _VLV_PLL_DW17_CH0		0x8044
> -#define _VLV_PLL_DW17_CH1		0x8064
> -#define VLV_PLL_DW17(ch) _PIPE(ch, _VLV_PLL_DW17_CH0, _VLV_PLL_DW17_CH1)
> +#define VLV_PLL_DW17(ch)		_VLV_PLL((ch), 17)
>  
> -#define _VLV_PLL_DW18_CH0		0x8048
> -#define _VLV_PLL_DW18_CH1		0x8068
> -#define VLV_PLL_DW18(ch) _PIPE(ch, _VLV_PLL_DW18_CH0, _VLV_PLL_DW18_CH1)
> +#define VLV_PLL_DW18(ch)		_VLV_PLL((ch), 18)
>  
> -#define _VLV_PLL_DW19_CH0		0x804c
> -#define _VLV_PLL_DW19_CH1		0x806c
> -#define VLV_PLL_DW19(ch) _PIPE(ch, _VLV_PLL_DW19_CH0, _VLV_PLL_DW19_CH1)
> +#define VLV_PLL_DW19(ch)		_VLV_PLL((ch), 19)
>  
> -/* Spec for ref block start counts at DW8 */
> -#define VLV_REF_DW11			0x80ac
> +#define VLV_REF_DW11			_VLV_REF(11)
>  
> -#define VLV_CMN_DW0			0x8100
> +#define VLV_CMN_DW0			_VLV_CMN(0)
>  
>  /*
>   * Per DDI channel DPIO regs
>   */
> -
> -#define _VLV_PCS_DW0_CH0_GRP		0x8200
> -#define _VLV_PCS_DW0_CH1_GRP		0x8400
> +#define VLV_PCS_DW0_GRP(ch)		_VLV_PCS_GRP((ch), 0)
> +#define VLV_PCS01_DW0(ch)		_VLV_PCS((ch), 0, 0)
> +#define VLV_PCS23_DW0(ch)		_VLV_PCS((ch), 1, 0)
>  #define   DPIO_PCS_TX_LANE2_RESET	(1 << 16)
>  #define   DPIO_PCS_TX_LANE1_RESET	(1 << 7)
>  #define   DPIO_LEFT_TXFIFO_RST_MASTER2	(1 << 4)
>  #define   DPIO_RIGHT_TXFIFO_RST_MASTER2	(1 << 3)
> -#define VLV_PCS_DW0_GRP(ch) _PORT(ch, _VLV_PCS_DW0_CH0_GRP, _VLV_PCS_DW0_CH1_GRP)
>  
> -#define _VLV_PCS01_DW0_CH0		0x200
> -#define _VLV_PCS23_DW0_CH0		0x400
> -#define _VLV_PCS01_DW0_CH1		0x2600
> -#define _VLV_PCS23_DW0_CH1		0x2800
> -#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
> -#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
> -
> -#define _VLV_PCS_DW1_CH0_GRP		0x8204
> -#define _VLV_PCS_DW1_CH1_GRP		0x8404
> +#define VLV_PCS_DW1_GRP(ch)		_VLV_PCS_GRP((ch), 1)
> +#define VLV_PCS01_DW1(ch)		_VLV_PCS((ch), 0, 1)
> +#define VLV_PCS23_DW1(ch)		_VLV_PCS((ch), 1, 1)
>  #define   CHV_PCS_REQ_SOFTRESET_EN	(1 << 23)
>  #define   DPIO_PCS_CLK_CRI_RXEB_EIOS_EN	(1 << 22)
>  #define   DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
>  #define   DPIO_PCS_CLK_DATAWIDTH_SHIFT	(6)
>  #define   DPIO_PCS_CLK_SOFT_RESET	(1 << 5)
> -#define VLV_PCS_DW1_GRP(ch) _PORT(ch, _VLV_PCS_DW1_CH0_GRP, _VLV_PCS_DW1_CH1_GRP)
>  
> -#define _VLV_PCS01_DW1_CH0		0x204
> -#define _VLV_PCS23_DW1_CH0		0x404
> -#define _VLV_PCS01_DW1_CH1		0x2604
> -#define _VLV_PCS23_DW1_CH1		0x2804
> -#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
> -#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
> -
> -#define _VLV_PCS_DW8_CH0_GRP		0x8220
> -#define _VLV_PCS_DW8_CH1_GRP		0x8420
> +#define VLV_PCS_DW8_GRP(ch)		_VLV_PCS_GRP((ch), 8)
> +#define VLV_PCS01_DW8(ch)		_VLV_PCS((ch), 0, 8)
> +#define VLV_PCS23_DW8(ch)		_VLV_PCS((ch), 1, 8)
>  #define   CHV_PCS_USEDCLKCHANNEL_OVRRIDE	(1 << 20)
>  #define   CHV_PCS_USEDCLKCHANNEL		(1 << 21)
> -#define VLV_PCS_DW8_GRP(ch) _PORT(ch, _VLV_PCS_DW8_CH0_GRP, _VLV_PCS_DW8_CH1_GRP)
>  
> -#define _VLV_PCS01_DW8_CH0		0x0220
> -#define _VLV_PCS23_DW8_CH0		0x0420
> -#define _VLV_PCS01_DW8_CH1		0x2620
> -#define _VLV_PCS23_DW8_CH1		0x2820
> -#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
> -#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
> -
> -#define _VLV_PCS_DW9_CH0_GRP		0x8224
> -#define _VLV_PCS_DW9_CH1_GRP		0x8424
> +#define VLV_PCS_DW9_GRP(ch)		_VLV_PCS_GRP((ch), 9)
> +#define VLV_PCS01_DW9(ch)		_VLV_PCS((ch), 0, 9)
> +#define VLV_PCS23_DW9(ch)		_VLV_PCS((ch), 1, 9)
>  #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
>  #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
>  #define   DPIO_PCS_TX2MARGIN_101	(1 << 13)
>  #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
>  #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
>  #define   DPIO_PCS_TX1MARGIN_101	(1 << 10)
> -#define VLV_PCS_DW9_GRP(ch) _PORT(ch, _VLV_PCS_DW9_CH0_GRP, _VLV_PCS_DW9_CH1_GRP)
>  
> -#define _VLV_PCS01_DW9_CH0		0x224
> -#define _VLV_PCS23_DW9_CH0		0x424
> -#define _VLV_PCS01_DW9_CH1		0x2624
> -#define _VLV_PCS23_DW9_CH1		0x2824
> -#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
> -#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
> -
> -#define _CHV_PCS_DW10_CH0_GRP		0x8228
> -#define _CHV_PCS_DW10_CH1_GRP		0x8428
> +#define VLV_PCS_DW10_GRP(ch)		_VLV_PCS_GRP((ch), 10)
> +#define VLV_PCS01_DW10(ch)		_VLV_PCS((ch), 0, 10)
> +#define VLV_PCS23_DW10(ch)		_VLV_PCS((ch), 1, 10)
>  #define   DPIO_PCS_SWING_CALC_TX0_TX2	(1 << 30)
>  #define   DPIO_PCS_SWING_CALC_TX1_TX3	(1 << 31)
>  #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
> @@ -325,147 +294,104 @@
>  #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
>  #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
>  #define   DPIO_PCS_TX1DEEMP_6P0		(2 << 16)
> -#define CHV_PCS_DW10_GRP(ch) _PORT(ch, _CHV_PCS_DW10_CH0_GRP, _CHV_PCS_DW10_CH1_GRP)
>  
> -#define _VLV_PCS01_DW10_CH0		0x0228
> -#define _VLV_PCS23_DW10_CH0		0x0428
> -#define _VLV_PCS01_DW10_CH1		0x2628
> -#define _VLV_PCS23_DW10_CH1		0x2828
> -#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
> -#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
> -
> -#define _VLV_PCS_DW11_CH0_GRP		0x822c
> -#define _VLV_PCS_DW11_CH1_GRP		0x842c
> +#define VLV_PCS_DW11_GRP(ch)		_VLV_PCS_GRP((ch), 11)
> +#define VLV_PCS01_DW11(ch)		_VLV_PCS((ch), 0, 11)
> +#define VLV_PCS23_DW11(ch)		_VLV_PCS((ch), 1, 11)
>  #define   DPIO_TX2_STAGGER_MASK(x)	((x) << 24)
>  #define   DPIO_LANEDESKEW_STRAP_OVRD	(1 << 3)
>  #define   DPIO_LEFT_TXFIFO_RST_MASTER	(1 << 1)
>  #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
> -#define VLV_PCS_DW11_GRP(ch) _PORT(ch, _VLV_PCS_DW11_CH0_GRP, _VLV_PCS_DW11_CH1_GRP)
>  
> -#define _VLV_PCS01_DW11_CH0		0x022c
> -#define _VLV_PCS23_DW11_CH0		0x042c
> -#define _VLV_PCS01_DW11_CH1		0x262c
> -#define _VLV_PCS23_DW11_CH1		0x282c
> -#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
> -#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
> -
> -#define _VLV_PCS01_DW12_CH0		0x0230
> -#define _VLV_PCS23_DW12_CH0		0x0430
> -#define _VLV_PCS01_DW12_CH1		0x2630
> -#define _VLV_PCS23_DW12_CH1		0x2830
> -#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
> -#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
> -
> -#define _VLV_PCS_DW12_CH0_GRP		0x8230
> -#define _VLV_PCS_DW12_CH1_GRP		0x8430
> +#define VLV_PCS_DW12_GRP(ch)		_VLV_PCS_GRP((ch), 12)
> +#define VLV_PCS01_DW12(ch)		_VLV_PCS((ch), 0, 12)
> +#define VLV_PCS23_DW12(ch)		_VLV_PCS((ch), 1, 12)
>  #define   DPIO_TX2_STAGGER_MULT(x)	((x) << 20)
>  #define   DPIO_TX1_STAGGER_MULT(x)	((x) << 16)
>  #define   DPIO_TX1_STAGGER_MASK(x)	((x) << 8)
>  #define   DPIO_LANESTAGGER_STRAP_OVRD	(1 << 6)
>  #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
> -#define VLV_PCS_DW12_GRP(ch) _PORT(ch, _VLV_PCS_DW12_CH0_GRP, _VLV_PCS_DW12_CH1_GRP)
>  
> -#define _VLV_PCS_DW14_CH0_GRP		0x8238
> -#define _VLV_PCS_DW14_CH1_GRP		0x8438
> -#define VLV_PCS_DW14_GRP(ch) _PORT(ch, _VLV_PCS_DW14_CH0_GRP, _VLV_PCS_DW14_CH1_GRP)
> +#define VLV_PCS_DW14_GRP(ch)		_VLV_PCS_GRP((ch), 14)
> +#define VLV_PCS01_DW14(ch)		_VLV_PCS((ch), 0, 14)
> +#define VLV_PCS23_DW14(ch)		_VLV_PCS((ch), 1, 14)
>  
> -#define VLV_PCS_DW17_BCAST		0xc044
> +#define VLV_PCS_DW17_BCAST		_VLV_PCS_BCAST(17)
> +#define VLV_PCS_DW17_GRP(ch)		_VLV_PCS_GRP((ch), 17)
> +#define VLV_PCS01_DW17(ch)		_VLV_PCS((ch), 0, 17)
> +#define VLV_PCS23_DW17(ch)		_VLV_PCS((ch), 1, 17)
>  
> -#define _VLV_PCS_DW23_CH0_GRP		0x825c
> -#define _VLV_PCS_DW23_CH1_GRP		0x845c
> -#define VLV_PCS_DW23_GRP(ch) _PORT(ch, _VLV_PCS_DW23_CH0_GRP, _VLV_PCS_DW23_CH1_GRP)
> +#define VLV_PCS_DW23_GRP(ch)		_VLV_PCS_GRP((ch), 23)
> +#define VLV_PCS01_DW23(ch)		_VLV_PCS((ch), 0, 23)
> +#define VLV_PCS23_DW23(ch)		_VLV_PCS((ch), 1, 23)
>  
> -#define _VLV_TX_DW2_CH0_GRP		0x8288
> -#define _VLV_TX_DW2_CH1_GRP		0x8488
> +#define VLV_TX_DW2_GRP(ch)		_VLV_TX_GRP((ch), 2)
> +#define VLV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
>  #define   DPIO_SWING_MARGIN000_SHIFT	16
>  #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
>  #define   DPIO_UNIQ_TRANS_SCALE_SHIFT	8
> -#define VLV_TX_DW2_GRP(ch) _PORT(ch, _VLV_TX_DW2_CH0_GRP, _VLV_TX_DW2_CH1_GRP)
>  
> -#define _VLV_TX_DW3_CH0_GRP		0x828c
> -#define _VLV_TX_DW3_CH1_GRP		0x848c
> +#define VLV_TX_DW3_GRP(ch)		_VLV_TX_GRP((ch), 3)
> +#define VLV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
>  /* The following bit for CHV phy */
>  #define   DPIO_TX_UNIQ_TRANS_SCALE_EN	(1 << 27)
>  #define   DPIO_SWING_MARGIN101_SHIFT	16
>  #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
> -#define VLV_TX_DW3_GRP(ch) _PORT(ch, _VLV_TX_DW3_CH0_GRP, _VLV_TX_DW3_CH1_GRP)
>  
> -#define _VLV_TX_DW4_CH0_GRP		0x8290
> -#define _VLV_TX_DW4_CH1_GRP		0x8490
> +#define VLV_TX_DW4_GRP(ch)		_VLV_TX_GRP((ch), 4)
> +#define VLV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
>  #define   DPIO_SWING_DEEMPH9P5_SHIFT	24
>  #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
>  #define   DPIO_SWING_DEEMPH6P0_SHIFT	16
>  #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
> -#define VLV_TX_DW4_GRP(ch) _PORT(ch, _VLV_TX_DW4_CH0_GRP, _VLV_TX_DW4_CH1_GRP)
>  
> -#define _VLV_TX3_DW4_CH0		0x690
> -#define _VLV_TX3_DW4_CH1		0x2a90
> -#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
> -
> -#define _VLV_TX_DW5_CH0_GRP		0x8294
> -#define _VLV_TX_DW5_CH1_GRP		0x8494
> +#define VLV_TX_DW5_GRP(ch)		_VLV_TX_GRP((ch), 5)
> +#define VLV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
>  #define   DPIO_TX_OCALINIT_EN		(1 << 31)
> -#define VLV_TX_DW5_GRP(ch) _PORT(ch, _VLV_TX_DW5_CH0_GRP, _VLV_TX_DW5_CH1_GRP)
>  
> -#define _VLV_TX_DW11_CH0_GRP		0x82ac
> -#define _VLV_TX_DW11_CH1_GRP		0x84ac
> -#define VLV_TX_DW11_GRP(ch) _PORT(ch, _VLV_TX_DW11_CH0_GRP, _VLV_TX_DW11_CH1_GRP)
> +#define VLV_TX_DW11_GRP(ch)		_VLV_TX_GRP((ch), 11)
> +#define VLV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
>  
> -#define _VLV_TX_DW14_CH0_GRP		0x82b8
> -#define _VLV_TX_DW14_CH1_GRP		0x84b8
> -#define VLV_TX_DW14_GRP(ch) _PORT(ch, _VLV_TX_DW14_CH0_GRP, _VLV_TX_DW14_CH1_GRP)
> +#define VLV_TX_DW14_GRP(ch)		_VLV_TX_GRP((ch), 14)
> +#define VLV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
>  
>  /* CHV dpPhy registers */
> -#define _CHV_PLL_DW0_CH0		0x8000
> -#define _CHV_PLL_DW0_CH1		0x8180
> -#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
> +#define CHV_PLL_DW0(ch)			_CHV_PLL((ch), 0)
>  
> -#define _CHV_PLL_DW1_CH0		0x8004
> -#define _CHV_PLL_DW1_CH1		0x8184
> +#define CHV_PLL_DW1(ch)			_CHV_PLL((ch), 1)
>  #define   DPIO_CHV_N_DIV_SHIFT		8
>  #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
> -#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
>  
> -#define _CHV_PLL_DW2_CH0		0x8008
> -#define _CHV_PLL_DW2_CH1		0x8188
> -#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
> +#define CHV_PLL_DW2(ch)			_CHV_PLL((ch), 2)
>  
> -#define _CHV_PLL_DW3_CH0		0x800c
> -#define _CHV_PLL_DW3_CH1		0x818c
> +#define CHV_PLL_DW3(ch)			_CHV_PLL((ch), 3)
>  #define  DPIO_CHV_FRAC_DIV_EN		(1 << 16)
>  #define  DPIO_CHV_FIRST_MOD		(0 << 8)
>  #define  DPIO_CHV_SECOND_MOD		(1 << 8)
>  #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
>  #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
> -#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
>  
> -#define _CHV_PLL_DW6_CH0		0x8018
> -#define _CHV_PLL_DW6_CH1		0x8198
> +#define CHV_PLL_DW6(ch)			_CHV_PLL((ch), 6)
>  #define   DPIO_CHV_GAIN_CTRL_SHIFT	16
>  #define	  DPIO_CHV_INT_COEFF_SHIFT	8
>  #define   DPIO_CHV_PROP_COEFF_SHIFT	0
> -#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
>  
> -#define _CHV_PLL_DW8_CH0		0x8020
> -#define _CHV_PLL_DW8_CH1		0x81A0
> +#define CHV_PLL_DW8(ch)			_CHV_PLL((ch), 8)
>  #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
>  #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
> -#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
>  
> -#define _CHV_PLL_DW9_CH0		0x8024
> -#define _CHV_PLL_DW9_CH1		0x81A4
> +#define CHV_PLL_DW9(ch)			_CHV_PLL((ch), 9)
>  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT		1 /* 3 bits */
>  #define  DPIO_CHV_INT_LOCK_THRESHOLD_MASK		(7 << 1)
>  #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
> -#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
>  
> -#define CHV_CMN_DW0_CH0			0x8100
> +#define CHV_CMN_DW0_CH0			_CHV_CMN(0, 0)
>  #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH0	19
>  #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH0	18
>  #define   DPIO_ALLDL_POWERDOWN			(1 << 1)
>  #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
>  
> -#define CHV_CMN_DW5_CH0			0x8114
> +#define CHV_CMN_DW5_CH0			_CHV_CMN(0, 5)
>  #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
>  #define   CHV_BUFRIGHTENA1_NORMAL	(1 << 20)
>  #define   CHV_BUFRIGHTENA1_FORCE	(3 << 20)
> @@ -475,18 +401,18 @@
>  #define   CHV_BUFLEFTENA1_FORCE		(3 << 22)
>  #define   CHV_BUFLEFTENA1_MASK		(3 << 22)
>  
> -#define CHV_CMN_DW13_CH0		0x8134
> -#define CHV_CMN_DW0_CH1			0x8080
> +#define CHV_CMN_DW13_CH0		_CHV_CMN(0, 13)
> +#define CHV_CMN_DW0_CH1			_CHV_CMN(1, 0)
>  #define   DPIO_CHV_S1_DIV_SHIFT		21
>  #define   DPIO_CHV_P1_DIV_SHIFT		13 /* 3 bits */
>  #define   DPIO_CHV_P2_DIV_SHIFT		8  /* 5 bits */
>  #define   DPIO_CHV_K_DIV_SHIFT		4
>  #define   DPIO_PLL_FREQLOCK		(1 << 1)
>  #define   DPIO_PLL_LOCK			(1 << 0)
> -#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
> +#define CHV_CMN_DW13(ch)		_PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1)
>  
> -#define CHV_CMN_DW14_CH0		0x8138
> -#define CHV_CMN_DW1_CH1			0x8084
> +#define CHV_CMN_DW14_CH0		_CHV_CMN(0, 14)
> +#define CHV_CMN_DW1_CH1			_CHV_CMN(1, 1)
>  #define   DPIO_AFC_RECAL		(1 << 14)
>  #define   DPIO_DCLKP_EN			(1 << 13)
>  #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
> @@ -497,17 +423,17 @@
>  #define   CHV_BUFRIGHTENA2_NORMAL	(1 << 19) /* CL2 DW1 only */
>  #define   CHV_BUFRIGHTENA2_FORCE	(3 << 19) /* CL2 DW1 only */
>  #define   CHV_BUFRIGHTENA2_MASK		(3 << 19) /* CL2 DW1 only */
> -#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
> +#define CHV_CMN_DW14(ch)		_PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1)
>  
> -#define CHV_CMN_DW19_CH0		0x814c
> -#define CHV_CMN_DW6_CH1		0x8098
> +#define CHV_CMN_DW19_CH0		_CHV_CMN(0, 19)
> +#define CHV_CMN_DW6_CH1			_CHV_CMN(1, 6)
>  #define   DPIO_ALLDL_POWERDOWN_SHIFT_CH1	30 /* CL2 DW6 only */
>  #define   DPIO_ANYDL_POWERDOWN_SHIFT_CH1	29 /* CL2 DW6 only */
>  #define   DPIO_DYNPWRDOWNEN_CH1		(1 << 28) /* CL2 DW6 only */
>  #define   CHV_CMN_USEDCLKCHANNEL	(1 << 13)
> -#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
> +#define CHV_CMN_DW19(ch)		_PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1)
>  
> -#define CHV_CMN_DW28			0x8170
> +#define CHV_CMN_DW28			_CHV_CMN(0, 28)
>  #define   DPIO_CL1POWERDOWNEN		(1 << 23)
>  #define   DPIO_DYNPWRDOWNEN_CH0		(1 << 22)
>  #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
> @@ -515,27 +441,26 @@
>  #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
>  #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
>  
> -#define CHV_CMN_DW30			0x8178
> +#define CHV_CMN_DW30			_CHV_CMN(0, 30)
>  #define   DPIO_CL2_LDOFUSE_PWRENB	(1 << 6)
>  #define   DPIO_LRC_BYPASS		(1 << 3)
>  
> -#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
> -					(lane) * 0x200 + (offset))
> +#define CHV_TX_DW0(ch, lane)		_VLV_TX((ch), (lane), 0)
> +#define CHV_TX_DW1(ch, lane)		_VLV_TX((ch), (lane), 1)
> +#define CHV_TX_DW2(ch, lane)		_VLV_TX((ch), (lane), 2)
> +#define CHV_TX_DW3(ch, lane)		_VLV_TX((ch), (lane), 3)
> +#define CHV_TX_DW4(ch, lane)		_VLV_TX((ch), (lane), 4)
> +#define CHV_TX_DW5(ch, lane)		_VLV_TX((ch), (lane), 5)
> +#define CHV_TX_DW6(ch, lane)		_VLV_TX((ch), (lane), 6)
> +#define CHV_TX_DW7(ch, lane)		_VLV_TX((ch), (lane), 7)
> +#define CHV_TX_DW8(ch, lane)		_VLV_TX((ch), (lane), 8)
> +#define CHV_TX_DW9(ch, lane)		_VLV_TX((ch), (lane), 9)
> +#define CHV_TX_DW10(ch, lane)		_VLV_TX((ch), (lane), 10)
>  
> -#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
> -#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
> -#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
> -#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
> -#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
> -#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
> -#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
> -#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
> -#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
> -#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
> -#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
> -#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
> +#define CHV_TX_DW11(ch, lane)		_VLV_TX((ch), (lane), 11)
>  #define   DPIO_FRC_LATENCY_SHFIT	8
> -#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
> +
> +#define CHV_TX_DW14(ch, lane)		_VLV_TX((ch), (lane), 14)
>  #define   DPIO_UPAR_SHIFT		30
>  
>  #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)

-- 
Jani Nikula, Intel

Re: [PATCH 09/14] drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooks

[Jani Nikula]

On Tue, 23 Apr 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, Apr 22, 2024 at 01:10:57PM +0300, Jani Nikula wrote:
>> On Mon, 22 Apr 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > diff --git a/drivers/gpu/drm/i915/vlv_sideband.c b/drivers/gpu/drm/i915/vlv_sideband.c
>> > index ffa195560d0d..68291412f4cb 100644
>> > --- a/drivers/gpu/drm/i915/vlv_sideband.c
>> > +++ b/drivers/gpu/drm/i915/vlv_sideband.c
>> > @@ -9,7 +9,6 @@
>> >  #include "vlv_sideband.h"
>> >  
>> >  #include "display/intel_dpio_phy.h"
>> > -#include "display/intel_display_types.h"
>> 
>> I guess this should be done in some other patch?
>
> I think it should have been part of
> commit f70a68bc1d18 ("drm/i915: convert vlv_dpio_read()/write() from
> pipe to phy")
>
> but got missed. This patch is basically what was left from a
> similar change I had in my branch. I can split this hunk out
> into a separate patch.

No big deal, really. I just want to get this stuff merged. :)

BR,
Jani.

-- 
Jani Nikula, Intel

Re: ✓ Fi.CI.BAT: success for drm/i915: VLV/CHV DPIO register cleanup

[Jani Nikula]

On Mon, 22 Apr 2024, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: drm/i915: VLV/CHV DPIO register cleanup
> URL   : https://patchwork.freedesktop.org/series/132691/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_14624 -> Patchwork_132691v1
> ====================================================
>
> Summary
> -------
>
>   **SUCCESS**
>
>   No regressions found.
>
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/index.html

BAT passed, where are the shard results?

BR,
Jani.



>
> Participating hosts (31 -> 30)
> ------------------------------
>
>   Missing    (1): fi-apl-guc 
>
> Known issues
> ------------
>
>   Here are the changes found in Patchwork_132691v1 that come from known issues:
>
> ### IGT changes ###
>
> #### Warnings ####
>
>   * igt@i915_module_load@reload:
>     - fi-kbl-7567u:       [DMESG-WARN][1] ([i915#10636] / [i915#180] / [i915#1982] / [i915#8585]) -> [DMESG-WARN][2] ([i915#10636] / [i915#180] / [i915#8585])
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14624/fi-kbl-7567u/igt@i915_module_load@reload.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/fi-kbl-7567u/igt@i915_module_load@reload.html
>
>   
>   [i915#10636]: https://gitlab.freedesktop.org/drm/intel/issues/10636
>   [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
>   [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
>   [i915#8585]: https://gitlab.freedesktop.org/drm/intel/issues/8585
>
>
> Build changes
> -------------
>
>   * Linux: CI_DRM_14624 -> Patchwork_132691v1
>
>   CI-20190529: 20190529
>   CI_DRM_14624: ff2f70f345aaee3cbcf93a3a06ff3a5ab88e1d7a @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_7814: 7814
>   Patchwork_132691v1: ff2f70f345aaee3cbcf93a3a06ff3a5ab88e1d7a @ git://anongit.freedesktop.org/gfx-ci/linux
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v1/index.html

-- 
Jani Nikula, Intel

✗ Fi.CI.CHECKPATCH: warning for drm/i915: VLV/CHV DPIO register cleanup (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: VLV/CHV DPIO register cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/132691/
State : warning

== Summary ==

Error: dim checkpatch failed
1e5364e2978e drm/i915/dpio: Remove pointless VLV_PCS01_DW8 read
6edc798fb246 drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/
9115ea6798d1 drm/i915/dpio: s/VLV_PLL_DW9_BCAST/VLV_PCS_DW17_BCAST/
c7246eff0964 drm/i915/dpio: Fix VLV DPIO PLL register dword numbering
-:73: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#73: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1955:
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 				 0x009f0003);

-:77: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#77: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1958:
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(pipe),
 				 0x00d0000f);

total: 0 errors, 0 warnings, 2 checks, 87 lines checked
8d1345a4fefa drm/i915/dpio: Remove pointless variables from vlv/chv DPLL code
bcf1bc12a1d3 drm/i915/dpio: Rename some variables
7f73ae2bf28b drm/i915/dpio: s/port/ch/
-:35: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#35: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1080:
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(ch),
 			 uniqtranscale_reg_value);

-:65: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#65: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1106:
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(ch),
 			 DPIO_PCS_TX_LANE2_RESET |

-:69: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#69: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1109:
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(ch),
 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |

total: 0 errors, 0 warnings, 3 checks, 241 lines checked
72e6f66899e4 drm/i915/dpio: s/pipe/ch/
-:116: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#116: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1952:
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
 				 0x009f0003);

-:120: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#120: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1955:
+		vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch),
 				 0x00d0000f);

-:127: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#127: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1961:
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df40000);

-:131: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#131: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1964:
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df70000);

-:137: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#137: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1969:
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df70000);

-:141: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#141: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:1972:
+			vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch),
 					 0x0df40000);

total: 0 errors, 0 warnings, 6 checks, 148 lines checked
e408f10f199c drm/i915/dpio: Derive the phy from the port rather than pipe in encoder hooks
b51aeefe07d8 drm/i915/dpio: Give VLV DPIO group register a clearer name
-:30: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#30: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1077:
+	vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch),
 			 uniqtranscale_reg_value);

-:52: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#52: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1102:
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch),
 			 DPIO_PCS_TX_LANE2_RESET |

-:56: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#56: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.c:1105:
+	vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch),
 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |

total: 0 errors, 0 warnings, 3 checks, 262 lines checked
74300d05fedc drm/i915/dpio: Rename a few CHV DPIO PHY registers
3ff5eac8b3de drm/i915/dpio: Clean up VLV/CHV DPIO PHY register defines
1376d31ec62c drm/i915/dpio: Clean up the vlv/chv PHY register bits
-:609: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#609: FILE: drivers/gpu/drm/i915/i915_reg.h:409:
+#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))

total: 0 errors, 1 warnings, 0 checks, 686 lines checked
97cb9ec79404 drm/i915/dpio: Extract vlv_dpio_phy_regs.h
-:63: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#63: 
new file mode 100644

-:289: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#289: FILE: drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h:222:
+#define   DPIO_CHV_INT_LOCK_THRESHOLD(x)		REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x))

total: 0 errors, 2 warnings, 0 checks, 641 lines checked

✗ Fi.CI.SPARSE: warning for drm/i915: VLV/CHV DPIO register cleanup (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: VLV/CHV DPIO register cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/132691/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2

✓ Fi.CI.BAT: success for drm/i915: VLV/CHV DPIO register cleanup (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 11357 bytes --]

== Series Details ==

Series: drm/i915: VLV/CHV DPIO register cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/132691/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14679 -> Patchwork_132691v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/index.html

Participating hosts (37 -> 35)
------------------------------

  Additional (4): bat-dg1-7 bat-atsm-1 fi-apl-guc fi-bsw-n3050 
  Missing    (6): fi-kbl-7567u bat-kbl-2 fi-snb-2520m bat-dg2-11 bat-arls-1 bat-arls-3 

Known issues
------------

  Here are the changes found in Patchwork_132691v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_huc_copy@huc-copy:
    - bat-atsm-1:         NOTRUN -> [FAIL][1] ([i915#10563])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-apl-guc:         NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/fi-apl-guc/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][3] +19 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_mmap@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@gem_mmap@basic.html
    - bat-dg1-7:          NOTRUN -> [SKIP][5] ([i915#4083])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@gem_mmap@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][6] ([i915#4077]) +2 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@gem_tiled_fence_blits@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][7] ([i915#4079]) +1 other test skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@gem_tiled_pread_basic.html
    - bat-dg1-7:          NOTRUN -> [SKIP][8] ([i915#4079]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg1-7:          NOTRUN -> [SKIP][9] ([i915#6621])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@i915_pm_rps@basic-api.html
    - bat-atsm-1:         NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [PASS][11] -> [ABORT][12] ([i915#10594])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][13] ([i915#4212]) +7 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][14] ([i915#4215])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@size-max:
    - bat-atsm-1:         NOTRUN -> [SKIP][15] ([i915#6077]) +37 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@kms_addfb_basic@size-max.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-dg1-7:          NOTRUN -> [SKIP][16] ([i915#4103] / [i915#4213]) +1 other test skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - bat-atsm-1:         NOTRUN -> [SKIP][17] ([i915#6078]) +22 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@kms_dsc@dsc-basic:
    - bat-dg1-7:          NOTRUN -> [SKIP][18] ([i915#3555] / [i915#3840])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg1-7:          NOTRUN -> [SKIP][19]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-atsm-1:         NOTRUN -> [SKIP][20] ([i915#6093]) +4 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-apl-guc:         NOTRUN -> [SKIP][21] +17 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/fi-apl-guc/igt@kms_hdmi_inject@inject-audio.html
    - bat-dg1-7:          NOTRUN -> [SKIP][22] ([i915#433])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
    - bat-atsm-1:         NOTRUN -> [SKIP][23] ([i915#1836]) +6 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-dg1-7:          NOTRUN -> [SKIP][24] ([i915#5354])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_prop_blob@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][25] ([i915#7357])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@kms_prop_blob@basic.html

  * igt@kms_psr@psr-primary-page-flip:
    - bat-dg1-7:          NOTRUN -> [SKIP][26] ([i915#1072] / [i915#9732]) +3 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@kms_psr@psr-primary-page-flip.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-atsm-1:         NOTRUN -> [SKIP][27] ([i915#6094])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html
    - bat-dg1-7:          NOTRUN -> [SKIP][28] ([i915#3555])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg1-7:          NOTRUN -> [SKIP][29] ([i915#3708]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-atsm-1:         NOTRUN -> [SKIP][30] ([i915#4077]) +4 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@prime_vgem@basic-fence-mmap.html
    - bat-dg1-7:          NOTRUN -> [SKIP][31] ([i915#3708] / [i915#4077]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-dg1-7/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-atsm-1:         NOTRUN -> [SKIP][32] +2 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-atsm-1/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@kms_flip@basic-flip-vs-modeset@a-dp6:
    - {bat-mtlp-9}:       [DMESG-WARN][33] ([i915#10435]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/bat-mtlp-9/igt@kms_flip@basic-flip-vs-modeset@a-dp6.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-mtlp-9/igt@kms_flip@basic-flip-vs-modeset@a-dp6.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-a-dp-6:
    - {bat-mtlp-9}:       [DMESG-WARN][35] ([i915#10435] / [i915#9157]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-a-dp-6.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24@pipe-a-dp-6.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10435
  [i915#10563]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10563
  [i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1836]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1836
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/433
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#6077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6077
  [i915#6078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6078
  [i915#6093]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6093
  [i915#6094]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6094
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#7357]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7357
  [i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732


Build changes
-------------

  * Linux: CI_DRM_14679 -> Patchwork_132691v2

  CI-20190529: 20190529
  CI_DRM_14679: 39bf0b9d268e460fe2b7e9f792c9d610655eb9b7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7826: ce6ce0f60dd1a6c0df93a01ad71a31964158a2cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_132691v2: 39bf0b9d268e460fe2b7e9f792c9d610655eb9b7 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/index.html

[-- Attachment #2: Type: text/html, Size: 13278 bytes --]

✗ Fi.CI.IGT: failure for drm/i915: VLV/CHV DPIO register cleanup (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 68983 bytes --]

== Series Details ==

Series: drm/i915: VLV/CHV DPIO register cleanup (rev2)
URL   : https://patchwork.freedesktop.org/series/132691/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14679_full -> Patchwork_132691v2_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_132691v2_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_132691v2_full, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_132691v2_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_big_fb@4-tiled-8bpp-rotate-0:
    - shard-dg2:          [PASS][1] -> [ABORT][2] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-2/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-3/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html

  
Known issues
------------

  Here are the changes found in Patchwork_132691v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-rkl:          NOTRUN -> [SKIP][3] ([i915#8411])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-dg1:          NOTRUN -> [SKIP][4] ([i915#8411])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@api_intel_bb@render-ccs:
    - shard-dg2:          NOTRUN -> [FAIL][5] ([i915#10380])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@api_intel_bb@render-ccs.html

  * igt@device_reset@cold-reset-bound:
    - shard-rkl:          NOTRUN -> [SKIP][6] ([i915#7701])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@device_reset@cold-reset-bound.html

  * igt@drm_fdinfo@busy-idle-check-all@vcs1:
    - shard-dg1:          NOTRUN -> [SKIP][7] ([i915#8414]) +10 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@drm_fdinfo@busy-idle-check-all@vcs1.html

  * igt@gem_busy@semaphore:
    - shard-dg1:          NOTRUN -> [SKIP][8] ([i915#3936])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@gem_busy@semaphore.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-dg1:          NOTRUN -> [SKIP][9] ([i915#3555] / [i915#9323])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#9323])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@gem_ccs@suspend-resume.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-tglu:         NOTRUN -> [SKIP][11] ([i915#6335])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_ctx_persistence@engines-hang:
    - shard-snb:          NOTRUN -> [SKIP][12] ([i915#1099])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-snb7/igt@gem_ctx_persistence@engines-hang.html

  * igt@gem_ctx_persistence@smoketest:
    - shard-rkl:          NOTRUN -> [FAIL][13] ([i915#10251])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@gem_ctx_persistence@smoketest.html

  * igt@gem_ctx_sseu@engines:
    - shard-dg1:          NOTRUN -> [SKIP][14] ([i915#280]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-rkl:          NOTRUN -> [SKIP][15] ([i915#280])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_eio@kms:
    - shard-dg2:          [PASS][16] -> [INCOMPLETE][17] ([i915#10513] / [i915#1982])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-11/igt@gem_eio@kms.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-7/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@bonded-semaphore:
    - shard-dg2:          NOTRUN -> [SKIP][18] ([i915#4812])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gem_exec_balancer@bonded-semaphore.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-rkl:          NOTRUN -> [SKIP][19] ([i915#4525])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_capture@capture-invisible@lmem0:
    - shard-dg1:          NOTRUN -> [SKIP][20] ([i915#6334]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@gem_exec_capture@capture-invisible@lmem0.html

  * igt@gem_exec_capture@capture@vecs0-lmem0:
    - shard-dg1:          NOTRUN -> [FAIL][21] ([i915#10386]) +1 other test fail
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@gem_exec_capture@capture@vecs0-lmem0.html

  * igt@gem_exec_fair@basic-none-share:
    - shard-dg1:          NOTRUN -> [SKIP][22] ([i915#3539] / [i915#4852]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@gem_exec_fair@basic-none-share.html

  * igt@gem_exec_fair@basic-none@bcs0:
    - shard-rkl:          NOTRUN -> [FAIL][23] ([i915#2842]) +4 other tests fail
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@gem_exec_fair@basic-none@bcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-rkl:          [PASS][24] -> [FAIL][25] ([i915#2842])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
    - shard-glk:          NOTRUN -> [FAIL][26] ([i915#2842])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fence@submit:
    - shard-dg1:          NOTRUN -> [SKIP][27] ([i915#4812]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@gem_exec_fence@submit.html

  * igt@gem_exec_flush@basic-wb-pro-default:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#3539] / [i915#4852])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gem_exec_flush@basic-wb-pro-default.html

  * igt@gem_exec_reloc@basic-gtt-read-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][29] ([i915#3281]) +12 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@gem_exec_reloc@basic-gtt-read-noreloc.html

  * igt@gem_exec_reloc@basic-wc-cpu-noreloc:
    - shard-dg1:          NOTRUN -> [SKIP][30] ([i915#3281]) +4 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@gem_exec_reloc@basic-wc-cpu-noreloc.html

  * igt@gem_exec_reloc@basic-write-gtt-noreloc:
    - shard-dg2:          NOTRUN -> [SKIP][31] ([i915#3281]) +4 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gem_exec_reloc@basic-write-gtt-noreloc.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#4860])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          NOTRUN -> [SKIP][33] ([i915#4613] / [i915#7582])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
    - shard-dg1:          [PASS][34] -> [FAIL][35] ([i915#10378]) +1 other test fail
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-13/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-17/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][36] ([i915#4613]) +2 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@random:
    - shard-glk:          NOTRUN -> [SKIP][37] ([i915#4613]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-glk3/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [PASS][38] -> [TIMEOUT][39] ([i915#5493])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-18/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_media_vme:
    - shard-dg1:          NOTRUN -> [SKIP][40] ([i915#284])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@gem_media_vme.html

  * igt@gem_mmap_gtt@medium-copy-odd:
    - shard-dg1:          NOTRUN -> [SKIP][41] ([i915#4077]) +9 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@gem_mmap_gtt@medium-copy-odd.html

  * igt@gem_mmap_wc@bad-size:
    - shard-dg2:          NOTRUN -> [SKIP][42] ([i915#4083])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gem_mmap_wc@bad-size.html

  * igt@gem_mmap_wc@copy:
    - shard-dg1:          NOTRUN -> [SKIP][43] ([i915#4083]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@gem_mmap_wc@copy.html

  * igt@gem_partial_pwrite_pread@reads-snoop:
    - shard-dg1:          NOTRUN -> [SKIP][44] ([i915#3282]) +3 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@gem_partial_pwrite_pread@reads-snoop.html

  * igt@gem_pread@snoop:
    - shard-dg2:          NOTRUN -> [SKIP][45] ([i915#3282])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gem_pread@snoop.html

  * igt@gem_pwrite_snooped:
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#3282]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@gem_pwrite_snooped.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-rkl:          NOTRUN -> [SKIP][47] ([i915#4270]) +2 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - shard-dg1:          NOTRUN -> [SKIP][48] ([i915#4270]) +3 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html

  * igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#5190] / [i915#8428]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-dg1:          NOTRUN -> [SKIP][50] ([i915#4079]) +1 other test skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#4079])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_userptr_blits@access-control:
    - shard-dg1:          NOTRUN -> [SKIP][52] ([i915#3297])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@gem_userptr_blits@access-control.html
    - shard-tglu:         NOTRUN -> [SKIP][53] ([i915#3297])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#3297])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-rkl:          NOTRUN -> [SKIP][55] ([i915#3297])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#2856])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-rkl:          NOTRUN -> [SKIP][57] ([i915#2527]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-dg1:          NOTRUN -> [SKIP][58] ([i915#2527]) +2 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@gen9_exec_parse@bb-start-cmd.html
    - shard-tglu:         NOTRUN -> [SKIP][59] ([i915#2527] / [i915#2856])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [PASS][60] -> [INCOMPLETE][61] ([i915#9697] / [i915#9849])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
    - shard-snb:          [PASS][62] -> [INCOMPLETE][63] ([i915#9849])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb4/igt@i915_module_load@reload-with-fault-injection.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-snb6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][64] ([i915#8399])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_sseu@full-enable:
    - shard-dg1:          NOTRUN -> [SKIP][65] ([i915#4387])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@i915_pm_sseu@full-enable.html
    - shard-tglu:         NOTRUN -> [SKIP][66] ([i915#4387])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@i915_pm_sseu@full-enable.html

  * igt@i915_query@hwconfig_table:
    - shard-dg1:          NOTRUN -> [SKIP][67] ([i915#6245])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@i915_query@hwconfig_table.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-tglu:         NOTRUN -> [INCOMPLETE][68] ([i915#7443])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-8/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
    - shard-dg1:          NOTRUN -> [SKIP][69] ([i915#4212]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][70] ([i915#8709]) +11 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-d-hdmi-a-2-4-mc-ccs.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#5286]) +4 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@kms_big_fb@4-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg1:          NOTRUN -> [SKIP][72] ([i915#4538] / [i915#5286]) +4 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][73] ([i915#3638]) +3 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][74] ([i915#3638])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-tglu:         [PASS][75] -> [FAIL][76] ([i915#3743]) +3 other tests fail
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-9/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-glk:          NOTRUN -> [SKIP][77] +177 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-glk5/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-dg2:          NOTRUN -> [SKIP][78] ([i915#4538] / [i915#5190]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][79] ([i915#4538]) +3 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_joiner@basic:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([i915#10656])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_big_joiner@basic.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][81] ([i915#6095]) +131 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#10307] / [i915#6095]) +153 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-5/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][83] ([i915#6095]) +11 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][84] ([i915#10278])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-xe2-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-4/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][86] ([i915#6095]) +61 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-rkl:          NOTRUN -> [SKIP][87] ([i915#3742])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([i915#7213]) +3 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#4087]) +3 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-6/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-dg1:          NOTRUN -> [SKIP][90] ([i915#7828]) +7 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-tglu:         NOTRUN -> [SKIP][91] ([i915#7828]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#7828])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_frames@hdmi-crc-single:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#7828]) +5 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@kms_chamelium_frames@hdmi-crc-single.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#7118] / [i915#9424])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@content-type-change:
    - shard-tglu:         NOTRUN -> [SKIP][95] ([i915#6944] / [i915#9424])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-8/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-dg1:          NOTRUN -> [SKIP][96] ([i915#3299])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][97] ([i915#9424])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-7/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@uevent:
    - shard-dg1:          NOTRUN -> [SKIP][98] ([i915#7116] / [i915#9424])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][99] ([i915#3555]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-dg1:          NOTRUN -> [SKIP][100] ([i915#3555]) +4 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][101] ([i915#3359]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][102] ([i915#3359])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg1:          NOTRUN -> [SKIP][103] ([i915#4103] / [i915#4213])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
    - shard-tglu:         NOTRUN -> [SKIP][104] ([i915#4103])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-dg1:          NOTRUN -> [SKIP][105] ([i915#9067])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-rkl:          NOTRUN -> [SKIP][106] ([i915#4103])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][107] ([i915#9227])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-8/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html
    - shard-rkl:          NOTRUN -> [SKIP][108] ([i915#9723])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][109] ([i915#9723])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-tglu:         NOTRUN -> [SKIP][110] ([i915#3555])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][111] ([i915#3804])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_aux_dev:
    - shard-dg2:          [PASS][112] -> [SKIP][113] ([i915#1257])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-11/igt@kms_dp_aux_dev.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-5/igt@kms_dp_aux_dev.html
    - shard-dg1:          NOTRUN -> [SKIP][114] ([i915#1257])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_dp_aux_dev.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][115] ([i915#3840])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-dg1:          NOTRUN -> [SKIP][116] ([i915#3555] / [i915#3840])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#3555] / [i915#3840])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#3840] / [i915#9053])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-dg1:          NOTRUN -> [SKIP][119] ([i915#3469])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
    - shard-dg2:          NOTRUN -> [SKIP][120] +5 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][121] +30 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][122] ([i915#3637]) +1 other test skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][123] ([i915#9934]) +5 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][124] ([i915#8381])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][125] ([i915#2587] / [i915#2672]) +2 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#2672])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][127] ([i915#2672]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
    - shard-snb:          [PASS][128] -> [SKIP][129]
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][130] ([i915#8708]) +3 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
    - shard-dg1:          NOTRUN -> [SKIP][131] +42 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][132] ([i915#3458]) +17 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move:
    - shard-tglu:         NOTRUN -> [SKIP][133] +21 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-dg2:          NOTRUN -> [SKIP][134] ([i915#3458]) +3 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#5439])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#3023]) +16 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][137] ([i915#1825]) +22 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#5354]) +8 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][139] ([i915#8708]) +16 other tests skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-snb:          NOTRUN -> [SKIP][140] +5 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-snb7/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#3555] / [i915#8228])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-7/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][142] ([i915#3555] / [i915#8228])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-swap:
    - shard-dg1:          NOTRUN -> [SKIP][143] ([i915#3555] / [i915#8228]) +1 other test skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_hdr@static-swap.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-tglu:         NOTRUN -> [SKIP][144] ([i915#6301])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_panel_fitting@atomic-fastset.html
    - shard-dg1:          NOTRUN -> [SKIP][145] ([i915#6301])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [FAIL][146] ([i915#8292])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-13/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][147] ([i915#9423]) +7 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-b-hdmi-a-4.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][148] ([i915#9423]) +7 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][149] ([i915#9423]) +3 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-8/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-a-hdmi-a-1.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][150] ([i915#9423]) +5 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][151] ([i915#5176] / [i915#9423]) +1 other test skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][152] ([i915#5235]) +11 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][153] ([i915#5235] / [i915#9423]) +15 other tests skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-5/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-d-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#5235] / [i915#9423] / [i915#9728]) +3 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][155] ([i915#5235]) +5 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-dg1:          NOTRUN -> [SKIP][156] ([i915#9685]) +1 other test skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#3361])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         [PASS][158] -> [SKIP][159] ([i915#4281])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-7/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#9340])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-dg1:          NOTRUN -> [SKIP][161] ([i915#8430])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@kms_pm_lpsp@screens-disabled.html
    - shard-tglu:         NOTRUN -> [SKIP][162] ([i915#8430])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg2:          [PASS][163] -> [SKIP][164] ([i915#9519]) +2 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-8/igt@kms_pm_rpm@dpms-lpsp.html
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [PASS][165] -> [SKIP][166] ([i915#9519]) +2 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-6/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@fences-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][167] ([i915#4077]) +3 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_pm_rpm@fences-dpms.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglu:         NOTRUN -> [SKIP][168] ([i915#9519])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_prime@d3hot:
    - shard-dg1:          NOTRUN -> [SKIP][169] ([i915#6524])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-15/igt@kms_prime@d3hot.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([i915#9683])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#1072] / [i915#9732]) +15 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@psr-cursor-plane-onoff:
    - shard-tglu:         NOTRUN -> [SKIP][172] ([i915#9732]) +6 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_psr@psr-cursor-plane-onoff.html

  * igt@kms_psr@psr-primary-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][173] ([i915#1072] / [i915#9732]) +4 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_psr@psr-primary-mmap-cpu.html

  * igt@kms_psr@psr2-sprite-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][174] ([i915#1072] / [i915#9732]) +19 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_psr@psr2-sprite-mmap-gtt.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-dg1:          [PASS][175] -> [DMESG-WARN][176] ([i915#4423])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-17/igt@kms_rotation_crc@primary-rotation-90.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-13/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#5190])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-rkl:          NOTRUN -> [SKIP][178] ([i915#5289])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg1:          NOTRUN -> [SKIP][179] ([i915#5289]) +2 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][180] ([i915#3555]) +2 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg1:          NOTRUN -> [SKIP][181] ([i915#8623])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-tglu:         NOTRUN -> [SKIP][182] ([i915#8623])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][183] -> [FAIL][184] ([i915#9196])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][185] ([i915#9196])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-2.html

  * igt@kms_vrr@max-min:
    - shard-rkl:          NOTRUN -> [SKIP][186] ([i915#9906])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-2/igt@kms_vrr@max-min.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg1:          NOTRUN -> [SKIP][187] ([i915#2437])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#2437] / [i915#9412])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf_pmu@module-unload:
    - shard-dg2:          NOTRUN -> [FAIL][189] ([i915#10537] / [i915#5793])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-dg1:          NOTRUN -> [SKIP][190] ([i915#8516])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_vgem@fence-write-hang:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([i915#3708])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@prime_vgem@fence-write-hang.html

  * igt@runner@aborted:
    - shard-glk:          NOTRUN -> [FAIL][192] ([i915#10291])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-glk5/igt@runner@aborted.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-dg2:          NOTRUN -> [SKIP][193] ([i915#9917])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@sriov_basic@bind-unbind-vf.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each:
    - shard-tglu:         NOTRUN -> [SKIP][194] ([i915#9917])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-8/igt@sriov_basic@enable-vfs-bind-unbind-each.html

  * igt@syncobj_timeline@invalid-wait-zero-handles:
    - shard-dg1:          NOTRUN -> [FAIL][195] ([i915#9781])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@syncobj_timeline@invalid-wait-zero-handles.html
    - shard-tglu:         NOTRUN -> [FAIL][196] ([i915#9781])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@syncobj_timeline@invalid-wait-zero-handles.html

  * igt@v3d/v3d_perfmon@destroy-invalid-perfmon:
    - shard-dg2:          NOTRUN -> [SKIP][197] ([i915#2575]) +2 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@v3d/v3d_perfmon@destroy-invalid-perfmon.html

  * igt@v3d/v3d_submit_cl@job-perfmon:
    - shard-dg1:          NOTRUN -> [SKIP][198] ([i915#2575]) +10 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@v3d/v3d_submit_cl@job-perfmon.html

  * igt@vc4/vc4_create_bo@create-bo-zeroed:
    - shard-rkl:          NOTRUN -> [SKIP][199] ([i915#7711]) +7 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-3/igt@vc4/vc4_create_bo@create-bo-zeroed.html

  * igt@vc4/vc4_label_bo@set-bad-name:
    - shard-dg1:          NOTRUN -> [SKIP][200] ([i915#7711]) +6 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-14/igt@vc4/vc4_label_bo@set-bad-name.html
    - shard-tglu:         NOTRUN -> [SKIP][201] ([i915#2575]) +3 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@vc4/vc4_label_bo@set-bad-name.html

  * igt@vc4/vc4_wait_seqno@bad-seqno-0ns:
    - shard-dg2:          NOTRUN -> [SKIP][202] ([i915#7711]) +1 other test skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-2/igt@vc4/vc4_wait_seqno@bad-seqno-0ns.html

  
#### Possible fixes ####

  * igt@drm_fdinfo@idle@rcs0:
    - shard-rkl:          [FAIL][203] ([i915#7742]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-3/igt@drm_fdinfo@idle@rcs0.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-5/igt@drm_fdinfo@idle@rcs0.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglu:         [FAIL][205] ([i915#6268]) -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-3/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_exec_fair@basic-pace@rcs0:
    - shard-tglu:         [FAIL][207] ([i915#2876]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-6/igt@gem_exec_fair@basic-pace@rcs0.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-7/igt@gem_exec_fair@basic-pace@rcs0.html

  * igt@gem_lmem_swapping@heavy-random@lmem0:
    - shard-dg1:          [FAIL][209] ([i915#10378]) -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-18/igt@gem_lmem_swapping@heavy-random@lmem0.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-16/igt@gem_lmem_swapping@heavy-random@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-random@lmem0:
    - shard-dg2:          [FAIL][211] ([i915#10378]) -> [PASS][212] +1 other test pass
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-10/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-10/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-tglu:         [INCOMPLETE][213] ([i915#10047] / [i915#9820]) -> [PASS][214]
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-4/igt@i915_module_load@reload-with-fault-injection.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [FAIL][215] ([i915#10031]) -> [PASS][216]
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-4/igt@i915_suspend@basic-s3-without-i915.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-1/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1:
    - shard-tglu:         [FAIL][217] ([i915#2521]) -> [PASS][218]
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-8/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-mtlp:         [DMESG-FAIL][219] ([i915#2017]) -> [PASS][220]
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1:
    - shard-snb:          [INCOMPLETE][221] ([i915#4839]) -> [PASS][222]
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-rkl:          [SKIP][223] ([i915#9519]) -> [PASS][224]
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-dg2:          [SKIP][225] ([i915#9519]) -> [PASS][226]
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
    - shard-snb:          [FAIL][227] ([i915#9196]) -> [PASS][228]
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-snb7/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
    - shard-tglu:         [FAIL][229] ([i915#9196]) -> [PASS][230] +2 other tests pass
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-2/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html

  
#### Warnings ####

  * igt@gem_eio@kms:
    - shard-dg1:          [INCOMPLETE][231] ([i915#10513] / [i915#1982]) -> [INCOMPLETE][232] ([i915#10513])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg1-18/igt@gem_eio@kms.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg1-18/igt@gem_eio@kms.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
    - shard-tglu:         [FAIL][233] ([i915#3591]) -> [WARN][234] ([i915#2681])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-tglu-9/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-tglu-3/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-dg2:          [SKIP][235] ([i915#3458]) -> [SKIP][236] ([i915#10433] / [i915#3458]) +2 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][237] ([i915#4816]) -> [SKIP][238] ([i915#4070] / [i915#4816])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-rkl-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_psr@fbc-pr-primary-blt:
    - shard-dg2:          [SKIP][239] ([i915#1072] / [i915#9732]) -> [SKIP][240] ([i915#1072] / [i915#9673] / [i915#9732]) +10 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-8/igt@kms_psr@fbc-pr-primary-blt.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-11/igt@kms_psr@fbc-pr-primary-blt.html

  * igt@kms_psr@fbc-psr2-sprite-mmap-cpu:
    - shard-dg2:          [SKIP][241] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][242] ([i915#1072] / [i915#9732]) +7 other tests skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-dg2-11/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-dg2-7/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-glk:          [SKIP][243] -> [FAIL][244] ([i915#10959])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14679/shard-glk8/igt@kms_tiled_display@basic-test-pattern.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/shard-glk7/igt@kms_tiled_display@basic-test-pattern.html

  
  [i915#10031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10031
  [i915#10047]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10047
  [i915#10251]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10251
  [i915#10278]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10278
  [i915#10291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10291
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
  [i915#10380]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10380
  [i915#10386]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10386
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513
  [i915#10537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10537
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2017]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2017
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#2876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2876
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3743]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3743
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
  [i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5793]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5793
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6268]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6268
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
  [i915#7443]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7443
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7701]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
  [i915#9227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9227
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9697
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9728]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9728
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9781
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_14679 -> Patchwork_132691v2

  CI-20190529: 20190529
  CI_DRM_14679: 39bf0b9d268e460fe2b7e9f792c9d610655eb9b7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7826: ce6ce0f60dd1a6c0df93a01ad71a31964158a2cf @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_132691v2: 39bf0b9d268e460fe2b7e9f792c9d610655eb9b7 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132691v2/index.html

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