Re: [PATCH 18/19] drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Tue, Apr 30, 2024 at 01:10:12PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the PORT_ALPM_CTL register macro.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr.c      | 6 ++++--
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
>  2 files changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index fad24b1e5ae2..e88f326b78d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1790,7 +1790,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp)
>  			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
>  			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
>  
> -		intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
> +		intel_de_write(dev_priv,
> +			       PORT_ALPM_CTL(dev_priv, cpu_transcoder),
>  			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
>  			       PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
>  			       PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> @@ -2116,7 +2117,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  			     ALPM_CTL_ALPM_ENABLE |
>  			     ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
>  
> -		intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder),
> +		intel_de_rmw(dev_priv,
> +			     PORT_ALPM_CTL(dev_priv, cpu_transcoder),
>  			     PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0);
>  	}
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 05dc1c1d4ac2..5e52dddacf91 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -335,7 +335,7 @@
>  #define  ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val)	REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val)
>  
>  #define _PORT_ALPM_CTL_A			0x16fa2c
> -#define PORT_ALPM_CTL(tran)			_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)
> +#define PORT_ALPM_CTL(dev_priv, tran)			_MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A)
>  #define  PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE	REG_BIT(31)
>  #define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK	REG_GENMASK(23, 20)
>  #define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val)	REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)
> -- 
> 2.39.2
>