[PATCH v6 00/18] Enable DP2.1 alpm

[PATCH v6 00/18] Enable DP2.1 alpm

[Animesh Manna]

ALPM support added on DP2.1 and xe3p will support DP2.1 alpm.
This patch series extending alpm supoort for DP2.1.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (18):
  drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability
  drm/i915/alpm: Move alpm sink capability readout into a separate
    function
  drm/i915/alpm: alpm_init() for DP2.1
  drm/i915/alpm: Enable debugfs for DP2.1
  drm/i915/alpm: Refactor Auxless wake time calculation
  drm/i915/alpm: Auxless wake time calculation for Xe3p
  drm/i915/alpm: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd
  drm/i915/alpm: table based establishment period
  drm/i915/alpm: Half LFPS cycle calculation
  drm/i915/alpm: Modify LFPS cycle count for DP ALPM
  drm/i915/alpm: Modify LFPS_CYCLE_COUNT bitfield for xe3lpd
  drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM
  drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY
  drm/i915/alpm: Replace is_edp() with alpm_is_possible()
  drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf
  drm/i915/alpm: Compute and program switch to active latency
  drm/i915/alpm: Program zero-based LFPS half cycle duration
  drm/i915/alpm: Disallow ALPM for UHBR link rate

 drivers/gpu/drm/i915/display/intel_alpm.c     | 359 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_alpm.h     |   7 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |   5 +-
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  15 +-
 .../drm/i915/display/intel_dp_link_training.c |  21 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  27 ++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |   2 +
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  48 ++-
 drivers/gpu/drm/i915/display/intel_psr.h      |   1 -
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  16 +-
 include/drm/display/drm_dp.h                  |   4 +-
 14 files changed, 433 insertions(+), 83 deletions(-)

-- 
2.29.0

[PATCH v6 01/18] drm/i915/alpm: Add DPCD definition for DP2.1 ALPM capability

[Animesh Manna]

Add required DPCD address which will be needed to enable DP2.1 ALPM.

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 include/drm/display/drm_dp.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h
index e63c7f075f54..9f1e9ef5cdb6 100644
--- a/include/drm/display/drm_dp.h
+++ b/include/drm/display/drm_dp.h
@@ -1541,6 +1541,8 @@
 /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
 #define DP_PHY_REPEATER_128B132B_RATES			    0xf0007 /* 2.0 */
 #define DP_PHY_REPEATER_EQ_DONE                             0xf0008 /* 2.0 E11 */
+#define DP_LTTPR_ALPM_CAPABILITIES                          0xf0009 /* 2.1 */
+#define DP_TOTAL_LTTPR_CNT                                  0xf000a /* 2.1 */
 
 enum drm_dp_phy {
 	DP_PHY_DPRX,
@@ -1720,7 +1722,7 @@ enum drm_dp_phy {
 #define DP_DSC_BRANCH_CAP_SIZE		3
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
 #define EDP_DISPLAY_CTL_CAP_SIZE	5
-#define DP_LTTPR_COMMON_CAP_SIZE	8
+#define DP_LTTPR_COMMON_CAP_SIZE	10
 #define DP_LTTPR_PHY_CAP_SIZE		3
 
 #define DP_SDP_AUDIO_TIMESTAMP		0x01
-- 
2.29.0

[PATCH v6 02/18] drm/i915/alpm: Move alpm sink capability readout into a separate function

[Animesh Manna]

Abstract ALPM DPCD initialization into its own function.

v2:
- Improve commit description. [Suraj, Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 11 +++++++++++
 drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c   |  6 +-----
 3 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 10943539bc7c..a6743fe62d48 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -43,6 +43,17 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
 }
 
+bool intel_alpm_init_dpcd(struct intel_dp *intel_dp)
+{
+	u8 dpcd;
+
+	if (drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
+		return false;
+
+	intel_dp->alpm_dpcd = dpcd;
+	return true;
+}
+
 void intel_alpm_init(struct intel_dp *intel_dp)
 {
 	mutex_init(&intel_dp->alpm.lock);
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index f8f605d94f96..56c3e1482e37 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -15,6 +15,7 @@ struct intel_connector;
 struct intel_atomic_state;
 struct intel_crtc;
 
+bool intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0cd5e6b5034c..650c8b39270b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4783,7 +4783,6 @@ static bool
 intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
-	int ret;
 	u8 dprx;
 
 	/* this function is meant to be called only once */
@@ -4829,10 +4828,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
 	 */
 	intel_dp_init_source_oui(intel_dp);
 
-	/* Read the ALPM DPCD caps */
-	ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
-				    &intel_dp->alpm_dpcd);
-	if (ret < 0)
+	if (!intel_alpm_init_dpcd(intel_dp))
 		return false;
 
 	/*
-- 
2.29.0

[PATCH v6 03/18] drm/i915/alpm: alpm_init() for DP2.1

[Animesh Manna]

Initialize ALPM for DP2.1 and separate out ALPM mutex-init
from alpm-init.

v2: Separate out mutex-init. [Jani]
v3: Refactor further to avoid DISPLAY_VER check in multiple places. [Jani]
v4: Cosmetic changes. [Suraj]
v5: Reset alpm_dpcd and simplify source-supported check.
v6: Drop display-version check for eDP for backward compatible.

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 9 +++++++++
 drivers/gpu/drm/i915/display/intel_alpm.h | 1 +
 drivers/gpu/drm/i915/display/intel_dp.c   | 9 +++++++--
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index a6743fe62d48..4801fc6bade2 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -43,6 +43,15 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
 		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
 }
 
+bool intel_alpm_source_supported(struct intel_connector *connector)
+{
+	struct intel_display *display = to_intel_display(connector);
+
+	return (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort &&
+		DISPLAY_VER(display) >= 35) ||
+	        connector->base.connector_type == DRM_MODE_CONNECTOR_eDP;
+}
+
 bool intel_alpm_init_dpcd(struct intel_dp *intel_dp)
 {
 	u8 dpcd;
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 56c3e1482e37..9a02fa386ee3 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -15,6 +15,7 @@ struct intel_connector;
 struct intel_atomic_state;
 struct intel_crtc;
 
+bool intel_alpm_source_supported(struct intel_connector *connector);
 bool intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 650c8b39270b..b4742bd33cb4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6354,6 +6354,7 @@ intel_dp_detect(struct drm_connector *_connector,
 		connector->dp.panel_replay_caps.su_support = false;
 		connector->dp.panel_replay_caps.dsc_support =
 			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
+		intel_dp->alpm_dpcd = 0;
 
 		intel_dp_mst_disconnect(intel_dp);
 
@@ -6376,6 +6377,9 @@ intel_dp_detect(struct drm_connector *_connector,
 	if (ret == 1)
 		connector->base.epoch_counter++;
 
+	if (intel_alpm_source_supported(connector))
+		intel_alpm_init_dpcd(intel_dp);
+
 	if (!intel_dp_is_edp(intel_dp))
 		intel_psr_init_dpcd(intel_dp, connector);
 
@@ -7019,8 +7023,6 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	 */
 	intel_hpd_enable_detection(encoder);
 
-	intel_alpm_init(intel_dp);
-
 	/* Cache DPCD and EDID for edp. */
 	has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
 
@@ -7235,6 +7237,9 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 
 	intel_psr_init(intel_dp);
 
+	if (intel_alpm_source_supported(connector))
+		intel_alpm_init(intel_dp);
+
 	return true;
 
 fail:
-- 
2.29.0

[PATCH v6 04/18] drm/i915/alpm: Enable debugfs for DP2.1

[Animesh Manna]

Enable ALPM debug info through lobf debug info.

v2: cosmetic change. [Suraj]
v3: Use common api instead of DISPLAY_VER check in multiple places. [Jani]
v4: Add display-version check as it dropped for EDP.

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 4801fc6bade2..901493bb1448 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -739,8 +739,10 @@ void intel_alpm_lobf_debugfs_add(struct intel_connector *connector)
 	struct intel_display *display = to_intel_display(connector);
 	struct dentry *root = connector->base.debugfs_entry;
 
-	if (DISPLAY_VER(display) < 20 ||
-	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
+	if (DISPLAY_VER(display) < 20)
+		return;
+
+	if (!intel_alpm_source_supported(connector))
 		return;
 
 	debugfs_create_file("i915_edp_lobf_debug", 0644, root,
-- 
2.29.0

[PATCH v6 05/18] drm/i915/alpm: Refactor Auxless wake time calculation

[Animesh Manna]

Divide the auxless wake time calculation in parts which will
help later to add Xe3p related modification.

v2: Refactor first existing calculation. [Jani]
v3: Cosmetic changes. [Jani, Suraj]

Bspec: 71477
Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 31 ++++++++++++++++-------
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 901493bb1448..d5823174576a 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -102,6 +102,25 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
+static int get_tphy2_p2_to_p0(const struct intel_crtc_state *crtc_state)
+{
+	return 12 * 1000;
+}
+
+static int get_establishment_period(const struct intel_crtc_state *crtc_state)
+{
+	int t1 = 50 * 1000;
+	int tps4 = 252;
+	/* port_clock is link rate in 10kbit/s units */
+	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
+	int tcds, establishment_period;
+
+	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
+	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+
+	return establishment_period;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -123,17 +142,11 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
  */
 static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
 {
-	int tphy2_p2_to_p0 = 12 * 1000;
-	int t1 = 50 * 1000;
-	int tps4 = 252;
-	/* port_clock is link rate in 10kbit/s units */
-	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
-	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
-	int t2 = num_ml_phy_lock * tml_phy_lock;
-	int tcds = 1 * t2;
+	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
+	int establishment_period = get_establishment_period(crtc_state);
 
 	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
-			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
+			    establishment_period, 1000);
 }
 
 static int
-- 
2.29.0

[PATCH v6 06/18] drm/i915/alpm: Auxless wake time calculation for Xe3p

[Animesh Manna]

Add support for auxless waketime calculation for DP2.1 ALPM
as dependent parameter got changed.

v1: Initial version.
v2: Use intel_dp_is_uhbr(). [Jani]
v3:
- Separate out switch to active latency calculation.
- Use macro definition for ML_PHY_LOCK length. [Suraj]
v4:
- Fix 32-bit signed integer overflow. [sashiko]
- Fix negative return of drm_dp_lttpr_count(). [sashiko]
- Introduce get_ml_phy_lock_len() and get_dp_link_symbol_size(). [Jouni]
- Align variable naming with bpec formula of establishment_period. [Jouni]

Bspec: 71477
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 69 +++++++++++++++++++----
 1 file changed, 58 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index d5823174576a..924fa8dd4638 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -102,21 +102,64 @@ static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 		1000 / (2 * LFPS_CYCLE_COUNT);
 }
 
+#define ML_PHY_LOCK_LEN		252
+#define ML_PHY_LOCK_LEN_UHBR	396
+
 static int get_tphy2_p2_to_p0(const struct intel_crtc_state *crtc_state)
 {
-	return 12 * 1000;
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	return DISPLAY_VER(display) >= 35 ? (20 * 1000) : (12 * 1000);
+}
+
+static int get_ml_phy_lock_len(const struct intel_crtc_state *crtc_state)
+{
+	return intel_dp_is_uhbr(crtc_state) ? ML_PHY_LOCK_LEN_UHBR : ML_PHY_LOCK_LEN;
+}
+
+static int get_dp_link_symbol_size(const struct intel_crtc_state *crtc_state)
+{
+	return intel_dp_is_uhbr(crtc_state) ? 32 : 10;
 }
 
-static int get_establishment_period(const struct intel_crtc_state *crtc_state)
+static int get_establishment_period(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state)
 {
 	int t1 = 50 * 1000;
-	int tps4 = 252;
-	/* port_clock is link rate in 10kbit/s units */
-	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state->port_clock;
+	int tps4 = get_ml_phy_lock_len(crtc_state) * get_dp_link_symbol_size(crtc_state);
+	/*
+	 * port_clock is link rate in 10kbit/s units, so multiplying by
+	 * (1000 * 1000)/10 = 100000
+	 */
+	int tml_phy_lock = 100000 * tps4 / crtc_state->port_clock;
+	int lttpr_count = 0;
 	int tcds, establishment_period;
 
-	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
-	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
+	} else {
+		tcds = 7 * tml_phy_lock;
+		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+	}
+
+	if (lttpr_count > 0) {
+		/* tlw and tcs values are taken from DP2.1 spec */
+		int tlw = 13000;
+		int tcs = 10000;
+		int tlfps_period = get_lfps_cycle_time(crtc_state);
+		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
+			    (lttpr_count - 1) * (tlw + tlfps_period));
+		int tacds = 70000;
+		int tds = 7 * tml_phy_lock;
+
+		/* tdrl is same as tcds*/
+		establishment_period = tlw + tlfps_period + tdcs + tacds +
+				       (lttpr_count - 1) * tds + tcds;
+	} else {
+		/* TODO: Add a check for data realign by DPCD 0x116[3] */
+
+		establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
+	}
 
 	return establishment_period;
 }
@@ -138,12 +181,16 @@ static int get_establishment_period(const struct intel_crtc_state *crtc_state)
  * within the CDS period complete within the CDS period regardless of
  * entry into the period
  * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
- * TPS4 Length = 252 Symbols
+ * ML_PHY_LOCK Length (8b/10b): 252
+ * ML_PHY_LOCK Length (128b/132b): 396
+ * TPS4 Length = ML_PHY_LOCK * Rate Div
+ * Rate Div = 32 for 128b/132b and 10 for 8b/10b.
  */
-static int _lnl_compute_aux_less_wake_time(const struct intel_crtc_state *crtc_state)
+static int _lnl_compute_aux_less_wake_time(struct intel_dp *intel_dp,
+					   const struct intel_crtc_state *crtc_state)
 {
 	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
-	int establishment_period = get_establishment_period(crtc_state);
+	int establishment_period = get_establishment_period(intel_dp, crtc_state);
 
 	return DIV_ROUND_UP(tphy2_p2_to_p0 + get_lfps_cycle_time(crtc_state) +
 			    establishment_period, 1000);
@@ -158,7 +205,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 		lfps_half_cycle;
 
 	aux_less_wake_time =
-		_lnl_compute_aux_less_wake_time(crtc_state);
+		_lnl_compute_aux_less_wake_time(intel_dp, crtc_state);
 	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
 						       aux_less_wake_time);
 	silence_period = get_silence_period_symbols(crtc_state);
-- 
2.29.0

[PATCH v6 07/18] drm/i915/alpm: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd

[Animesh Manna]

The AUX_LESS_WAKE_TIME bitfield in ALPM_CTL is widened from 6 bits to
8 bits starting from xe3lpd (display version 35). Add the register mask
and field macro for the wider bitfield and program the wake time using
the appropriate macro based on the display version.

v2: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd. [Suraj]
v3: Separate out AUX_LESS_WAKE_TIME bitfield change into its own
patch. [Jouni]

Bspec: 71477
Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 8 ++++++--
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 ++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 924fa8dd4638..dc025058a626 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -610,8 +610,12 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
 		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
 			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
-			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
-			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
+			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
+
+		if (DISPLAY_VER(display) < 35)
+			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
+		else
+			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(crtc_state->alpm_state.aux_less_wake_lines);
 
 		if (intel_dp->as_sdp_supported)
 			intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index bb577e7e3bbd..016ce24944dc 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -301,7 +301,9 @@
 #define  ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES		5
 #define  ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines)	REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES)
 #define  ALPM_CTL_AUX_LESS_WAKE_TIME_MASK		REG_GENMASK(5, 0)
+#define  ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD	REG_GENMASK(7, 0)
 #define  ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val)
+#define  ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(val)	REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD, val)
 
 #define _ALPM_CTL2_A	0x60954
 #define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A)
-- 
2.29.0

[PATCH v6 08/18] drm/i915/alpm: table based establishment period

[Animesh Manna]

Only use the table when the link rate is listed (idx valid)
and the LTTPR count is within the table bounds. A zero entry
means the rate has no tabulated value, so fall back to the
computed establishment period below.

Note: The table and its values are taken from DP2.1 vesa spec.

v2: Add check for negative error codes from drm_dp_lttpr_count(). [sashiko]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 95 +++++++++++++++++++++++
 1 file changed, 95 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index dc025058a626..cb24bba801a1 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -122,6 +122,92 @@ static int get_dp_link_symbol_size(const struct intel_crtc_state *crtc_state)
 	return intel_dp_is_uhbr(crtc_state) ? 32 : 10;
 }
 
+#define DEFAULT_MAX_LTTPR_COUNT 7
+#define MAX_SUPPORTED_DP_LINK_RATES 12
+
+static const u32 establishment_periods[DEFAULT_MAX_LTTPR_COUNT][MAX_SUPPORTED_DP_LINK_RATES] = {
+	/* 1620, 2160, 2430, 2700, 3240, 4320, 5400, 6750, 8100, 10000, 13500, 20000 */
+	/* No Retimers */
+	{ 61070, 0, 0, 56710, 0, 0, 53450, 0, 52360, 59050, 56750, 54620 },
+	/*  1 Retimer  */
+	{ 155670, 0, 0, 151310, 0, 0, 148050, 0, 146960, 153650, 151350, 149220 },
+	/*  2 Retimers */
+	{ 181160, 0, 0, 172450, 0, 0, 165910, 0, 163740, 177120, 172520, 168220 },
+	/*  3 Retimers */
+	{ 206650, 0, 0, 193580, 0, 0, 183780, 0, 180510, 200590, 193690, 187290 },
+	/*  4 Retimers */
+	{ 232140, 0, 0, 214710, 0, 0, 201650, 0, 197290, 224060, 214860, 206320 },
+	/*  5 Retimers */
+	{ 257620, 0, 0, 235850, 0, 0, 219510, 0, 214070, 247530, 236030, 225360 },
+	/*  6 Retimers */
+	{ 283110, 0, 0, 256980, 0, 0, 237380, 0, 230850, 271000, 257200, 244390 },
+};
+
+enum link_rate_idx {
+	LINK_RATE_INVALID = -1,
+	LINK_RATE_1,
+	LINK_RATE_2,
+	LINK_RATE_3,
+	LINK_RATE_4,
+	LINK_RATE_5,
+	LINK_RATE_6,
+	LINK_RATE_7,
+	LINK_RATE_8,
+	LINK_RATE_9,
+	LINK_RATE_10,
+	LINK_RATE_11,
+	LINK_RATE_12
+};
+
+static int get_link_rate_index(int port_clock)
+{
+	int link_rate_index;
+
+	switch (port_clock) {
+	case 162000:
+		link_rate_index = LINK_RATE_1;	// Rate_1 (RBR) - 1.62 Gbps/Lane
+		break;
+	case 216000:
+		link_rate_index = LINK_RATE_2;	// Rate_2       - 2.16 Gbps/Lane
+		break;
+	case 243000:
+		link_rate_index = LINK_RATE_3;	// Rate_3       - 2.43 Gbps/Lane
+		break;
+	case 270000:
+		link_rate_index = LINK_RATE_4;	// Rate_4 (HBR) - 2.70 Gbps/Lane
+		break;
+	case 324000:
+		link_rate_index = LINK_RATE_5;	// Rate_5 (RBR2)- 3.24 Gbps/Lane
+		break;
+	case 432000:
+		link_rate_index = LINK_RATE_6;	// Rate_6       - 4.32 Gbps/Lane
+		break;
+	case 540000:
+		link_rate_index = LINK_RATE_7;	// Rate_7 (HBR2)- 5.40 Gbps/Lane
+		break;
+	case 675000:
+		link_rate_index = LINK_RATE_8;	// Rate_8       - 6.75 Gbps/Lane
+		break;
+	case 810000:
+		link_rate_index = LINK_RATE_9;	// Rate_9 (HBR3)- 8.10 Gbps/Lane
+		break;
+	case 1000000:
+		link_rate_index = LINK_RATE_10;	// Rate_10 (UHBR10) - 10.0 Gbps/Lane
+		break;
+	case 1350000:
+		link_rate_index = LINK_RATE_11;	// Rate_11 (UHBR13.5) - 13.5 Gbps/Lane
+		break;
+	case 2000000:
+		link_rate_index = LINK_RATE_12;	// Rate_12 (UHBR20) - 20.0 Gbps/Lane
+		break;
+	default:
+		link_rate_index = LINK_RATE_INVALID;
+		break;
+	}
+
+	return link_rate_index;
+}
+
 static int get_establishment_period(struct intel_dp *intel_dp,
 				    const struct intel_crtc_state *crtc_state)
 {
@@ -138,8 +224,17 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) * tml_phy_lock;
 	} else {
+		int idx = get_link_rate_index(crtc_state->port_clock);
+
 		tcds = 7 * tml_phy_lock;
 		lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+
+		if (idx != LINK_RATE_INVALID && lttpr_count >= 0 &&
+		    lttpr_count < DEFAULT_MAX_LTTPR_COUNT &&
+		    establishment_periods[lttpr_count][idx]) {
+			establishment_period = establishment_periods[lttpr_count][idx];
+			return establishment_period;
+		}
 	}
 
 	if (lttpr_count > 0) {
-- 
2.29.0

[PATCH v6 09/18] drm/i915/alpm: Half LFPS cycle calculation

[Animesh Manna]

Add support for half LFPS cycle calculation for DP2.1 ALPM as dependent
parameters got changed.

v1: Initial version.
v2: Avoid returning early. [Jani]
v3: Use intel_crtc_has_type(). [Suraj]
v4: Split in separate function based on HAS_LT_PHY() check. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 41 ++++++++++++++++++-----
 1 file changed, 33 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index cb24bba801a1..14ecb27095b2 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -74,24 +74,49 @@ static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
 		1000 / 1000;
 }
 
-static void get_lfps_cycle_min_max_time(const struct intel_crtc_state *crtc_state,
-					int *min, int *max)
+static void lnl_get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
+					     int *min, int *max)
 {
-	if (crtc_state->port_clock < 540000) {
-		*min = 65 * LFPS_CYCLE_COUNT;
-		*max = 75 * LFPS_CYCLE_COUNT;
-	} else {
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
+		if (crtc_state->port_clock < 540000) {
+			*min = 65 * LFPS_CYCLE_COUNT;
+			*max = 75 * LFPS_CYCLE_COUNT;
+		} else {
+			*min = 140;
+			*max = 800;
+		}
+	}
+}
+
+static void xe3plpd_get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
+						 int *min, int *max)
+{
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
 		*min = 140;
 		*max = 800;
+	} else {
+		*min = 320;
+		*max = 1600;
 	}
 }
 
+static void get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
+					int *min, int *max)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (HAS_LT_PHY(display))
+		xe3plpd_get_lfps_period_min_max_time(crtc_state, min, max);
+	else
+		lnl_get_lfps_period_min_max_time(crtc_state, min, max);
+}
+
 static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
 {
 	int tlfps_cycle_min, tlfps_cycle_max;
 
-	get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
-				    &tlfps_cycle_max);
+	get_lfps_period_min_max_time(crtc_state, &tlfps_cycle_min,
+				     &tlfps_cycle_max);
 
 	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
 }
-- 
2.29.0

[PATCH v6 10/18] drm/i915/alpm: Modify LFPS cycle count for DP ALPM

[Animesh Manna]

For DP minimum LFPS count is set to minimum 16.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 14ecb27095b2..22ed341763fa 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -24,7 +24,8 @@
 				(SILENCE_PERIOD_MAX_TIME -	\
 				 SILENCE_PERIOD_MIN_TIME) / 2)
 
-#define LFPS_CYCLE_COUNT 10
+#define LFPS_CYCLE_COUNT	10
+#define LFPS_CYCLE_COUNT_DP	16
 
 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
 {
@@ -121,10 +122,19 @@ static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
 	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
 }
 
+static int get_lfps_cycle_count(const struct intel_crtc_state *crtc_state)
+{
+	/* External DP uses a minimum of 16 LFPS cycles. */
+	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
+		return LFPS_CYCLE_COUNT_DP;
+
+	return LFPS_CYCLE_COUNT;
+}
+
 static int get_lfps_half_cycle_clocks(const struct intel_crtc_state *crtc_state)
 {
 	return get_lfps_cycle_time(crtc_state) * crtc_state->port_clock / 1000 /
-		1000 / (2 * LFPS_CYCLE_COUNT);
+		1000 / (2 * get_lfps_cycle_count(crtc_state));
 }
 
 #define ML_PHY_LOCK_LEN		252
@@ -779,7 +789,7 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
 			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
 			PORT_ALPM_CTL_SILENCE_PERIOD(
 				crtc_state->alpm_state.silence_period_sym_clocks);
-		lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
+		lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(get_lfps_cycle_count(crtc_state)) |
 			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
 				crtc_state->alpm_state.lfps_half_cycle_num_of_syms) |
 			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
-- 
2.29.0

[PATCH v6 11/18] drm/i915/alpm: Modify LFPS_CYCLE_COUNT bitfield for xe3lpd

[Animesh Manna]

The LFPS_CYCLE_COUNT bitfield in PORT_ALPM_LFPS_CTL is widened from
4 bits (27:24) to 7 bits (30:24) starting from xe3lpd. Add the wider
register mask and field macro, and program the cycle count using the
appropriate macro based on the display version.

v2: Split in a separate patch. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 11 ++++++++++-
 drivers/gpu/drm/i915/display/intel_psr_regs.h |  2 ++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 22ed341763fa..da653a407e97 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -784,12 +784,21 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
 		return;
 
 	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+		int lfps_cycle = get_lfps_cycle_count(crtc_state);
+		u32 lfps_cycle_val;
+
+		if (DISPLAY_VER(display) >= 35)
+			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(lfps_cycle);
+		else
+			lfps_cycle_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(lfps_cycle);
+
 		alpm_ctl_val = PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |
 			PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) |
 			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
 			PORT_ALPM_CTL_SILENCE_PERIOD(
 				crtc_state->alpm_state.silence_period_sym_clocks);
-		lfps_ctl_val = PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(get_lfps_cycle_count(crtc_state)) |
+
+		lfps_ctl_val = lfps_cycle_val |
 			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
 				crtc_state->alpm_state.lfps_half_cycle_num_of_syms) |
 			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 016ce24944dc..8f60b671755a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -335,8 +335,10 @@
 #define PORT_ALPM_LFPS_CTL(port)				_MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B)
 #define  PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY			REG_BIT(31)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK		REG_GENMASK(27, 24)
+#define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD	REG_GENMASK(30, 24)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)		REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
+#define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
 #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(20, 16)
 #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
 #define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(12, 8)
-- 
2.29.0

[PATCH v6 12/18] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM

[Animesh Manna]

Issue a AUX write transaction to DPCD DP_TOTAL_LTTPR_CNT (0xf000a)
with total number of LTTPR before link training.

v2: Cosmetic changes. [Suraj]
v3:
- Use same encoding format for lttpr_count. [Jouni]
- Avoid reading alpm_ctl2 register. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     |  7 ++++++-
 .../drm/i915/display/intel_dp_link_training.c | 21 +++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index da653a407e97..06c1a59aa2c5 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -726,7 +726,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	u32 alpm_ctl;
+	u32 alpm_ctl, alpm_ctl2, lttpr_count;
 
 	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
 					  !crtc_state->has_lobf))
@@ -762,6 +762,11 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 
 	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines);
 
+	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
+
+	alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
+
+	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2);
 	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
 	mutex_unlock(&intel_dp->alpm.lock);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index cb92cff90614..37c8306a1fa0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -2265,6 +2265,25 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
 	return passed;
 }
 
+static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp,
+					int lttpr_count)
+{
+	u8 val;
+
+	/*
+	 * Program only for DP2.1 and return if LTTPR revison is less than 0x20
+	 * where 0:3 represents minor rev and 4:7 represent major rev
+	 */
+	if (!intel_dp_is_edp(intel_dp) ||
+	    lttpr_count < 0 ||
+	    intel_dp->lttpr_common_caps[0] <= 0x20)
+		return;
+
+	val = intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
+					  DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, val);
+}
+
 /**
  * intel_dp_start_link_train - start link training
  * @state: Atomic state
@@ -2304,6 +2323,8 @@ void intel_dp_start_link_train(struct intel_atomic_state *state,
 
 	intel_dp_prepare_link_train(intel_dp, crtc_state);
 
+	intel_dp_update_lttpr_count(intel_dp, lttpr_count);
+
 	if (intel_dp_is_uhbr(crtc_state))
 		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
 	else
-- 
2.29.0

[PATCH v6 13/18] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY

[Animesh Manna]

Enable MAC to transmit LFPS via LT PHY during aux-less alpm.

v2:
- Correct commit description. [Suraj]
- Remove loop as no dependency on the transmitter LT_PHY_CMN_CTL0. [Suraj]
v3: Cosmetic changes. [Suraj]

Cc: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  5 +++-
 drivers/gpu/drm/i915/display/intel_lt_phy.c   | 27 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 ++
 .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  3 +++
 4 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 9b3b526e5e55..5244218132aa 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3796,7 +3796,10 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
 	 *     ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
 	 *         register
 	 */
-	intel_lnl_mac_transmit_lfps(encoder, crtc_state);
+	if (HAS_LT_PHY(display))
+		intel_xe3plpd_mac_transmit_lfps(encoder, crtc_state);
+	else
+		intel_lnl_mac_transmit_lfps(encoder, crtc_state);
 }
 
 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 86492651b01d..4fe010df20be 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -5,6 +5,7 @@
 
 #include <drm/drm_print.h>
 
+#include "intel_alpm.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
@@ -2357,3 +2358,29 @@ void intel_lt_phy_verify_plls(struct intel_display *display)
 	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables);
 	intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables);
 }
+
+/*
+ * According to HAS we need to enable MAC Transmitting LFPS in the "PHY Common
+ * Control 0" PIPE register in case of AUX Less ALPM is going to be used. This
+ * function is doing that and is called by link retrain sequence.
+ */
+void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *crtc_state)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+	struct ref_tracker *wakeref;
+	u8 owned_lane_mask;
+
+	if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+		return;
+
+	wakeref = intel_lt_phy_transaction_begin(encoder);
+
+	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+
+	intel_lt_phy_rmw(encoder, owned_lane_mask, LT_PHY_CMN_CTL_0,
+			 LT_PHY_CMN_LFPS_ENABLE,
+			 LT_PHY_CMN_LFPS_ENABLE, MB_WRITE_COMMITTED);
+
+	intel_lt_phy_transaction_end(encoder, wakeref);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index 16de39484779..c76c97b90946 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -49,5 +49,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
 			      const struct intel_dpll_hw_state *dpll_hw_state);
 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
 void intel_lt_phy_verify_plls(struct intel_display *display);
+void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_LT_PHY_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index ff6d7829dbb9..b64ff57e0c09 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -35,6 +35,9 @@
 #define LT_PHY_TXY_CTL10_MAC(idx)	_MMIO(LT_PHY_TXY_CTL10(idx))
 #define  LT_PHY_TX_LANE_ENABLE		REG_BIT8(0)
 
+#define LT_PHY_CMN_CTL_0		(0x800)
+#define  LT_PHY_CMN_LFPS_ENABLE		REG_BIT8(1)
+
 /* LT Phy Vendor Register */
 #define LT_PHY_VDR_0_CONFIG	0xC02
 #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)
-- 
2.29.0

[PATCH v6 14/18] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[Animesh Manna]

Add a separate alpm_is_possible() which will check for alpm
capability from dpcd info.

v2: Drop DISPLAY_VER() check as intel_alpm_source_supported
already checking and populating dpcd info. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 13 ++++++++++---
 drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 06c1a59aa2c5..29a93a252fe9 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -69,6 +69,13 @@ void intel_alpm_init(struct intel_dp *intel_dp)
 	mutex_init(&intel_dp->alpm.lock);
 }
 
+bool intel_alpm_is_possible(struct intel_dp *intel_dp)
+{
+	return (intel_dp->alpm_dpcd ||
+		intel_dp->lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
+					    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]);
+}
+
 static int get_silence_period_symbols(const struct intel_crtc_state *crtc_state)
 {
 	return SILENCE_PERIOD_TIME * intel_dp_link_symbol_clock(crtc_state->port_clock) /
@@ -546,7 +553,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
 	if (intel_dp->alpm.sink_alpm_error)
 		return;
 
-	if (!intel_dp_is_edp(intel_dp))
+	if (!intel_alpm_is_possible(intel_dp))
 		return;
 
 	if (DISPLAY_VER(display) < 20)
@@ -832,7 +839,7 @@ void intel_alpm_lobf_disable(const struct intel_crtc_state *new_crtc_state)
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (!intel_dp_is_edp(intel_dp))
+		if (!intel_alpm_is_possible(intel_dp))
 			continue;
 
 		mutex_lock(&intel_dp->alpm.lock);
@@ -873,7 +880,7 @@ void intel_alpm_lobf_enable(const struct intel_crtc_state *new_crtc_state)
 
 		intel_dp = enc_to_intel_dp(encoder);
 
-		if (intel_dp_is_edp(intel_dp)) {
+		if (intel_alpm_is_possible(intel_dp)) {
 			intel_alpm_enable_sink(intel_dp, new_crtc_state);
 			intel_alpm_configure(intel_dp, new_crtc_state);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index 9a02fa386ee3..ea90eba76ca7 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -18,6 +18,7 @@ struct intel_crtc;
 bool intel_alpm_source_supported(struct intel_connector *connector);
 bool intel_alpm_init_dpcd(struct intel_dp *intel_dp);
 void intel_alpm_init(struct intel_dp *intel_dp);
+bool intel_alpm_is_possible(struct intel_dp *intel_dp);
 bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 			       struct intel_crtc_state *crtc_state);
 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
-- 
2.29.0

[PATCH v6 15/18] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[Animesh Manna]

For DP2.1, ALPM (Advanced Link Power Management) is optional: Panel
Replay can be supported without ALPM. Until now ALPM enablement was
derived implicitly from other features - eDP Panel Replay and PSR2
always implied ALPM (intel_psr_needs_alpm()), while LOBF was tracked
separately via has_lobf - so this scattered, feature-coupled logic
cannot express "Panel Replay without ALPM".

Introduce a single crtc_state->has_alpm flag as the source of truth for
whether ALPM is enabled for a pipe configuration, computed during config
validation:

 - Panel Replay: from alpm_config_valid() when ALPM is possible; eDP
   Panel Replay additionally requires has_alpm.
 - PSR2 / Selective Update: from intel_alpm_is_possible().
 - LOBF: from has_lobf.

The Panel Replay path sets has_alpm speculatively, so clear it when
Panel Replay is not the finally selected feature, ensuring a PSR1
fallback never enables ALPM.

Use has_alpm in place of the feature-specific checks in the ALPM
configure, port configure, sink enable and MAC-transmit-LFPS paths, and
key the late wake-line selection off has_alpm / has_panel_replay.

Also rename intel_alpm_is_alpm_aux_less() to intel_alpm_is_aux_less()
and base the aux-less decision on has_panel_replay, keeping the source
programming consistent with the sink's DP_ALPM_MODE_AUX_LESS. The now
unused intel_psr_needs_alpm() is removed.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 25 +++++-----
 drivers/gpu/drm/i915/display/intel_alpm.h     |  4 +-
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  6 ++-
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_lt_phy.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 48 +++++++++++--------
 drivers/gpu/drm/i915/display/intel_psr.h      |  1 -
 7 files changed, 47 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 29a93a252fe9..236341aa3c8d 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -37,11 +37,11 @@ bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp)
 	return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
 }
 
-bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
-				 const struct intel_crtc_state *crtc_state)
+bool intel_alpm_is_aux_less(struct intel_dp *intel_dp,
+			    const struct intel_crtc_state *crtc_state)
 {
-	return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) ||
-		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
+	return crtc_state->has_panel_replay ||
+	       (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
 }
 
 bool intel_alpm_source_supported(struct intel_connector *connector)
@@ -537,6 +537,7 @@ void intel_alpm_lobf_compute_config_late(struct intel_dp *intel_dp,
 
 	crtc_state->has_lobf = (crtc_state->set_context_latency + crtc_state->vrr.guardband) >
 			       (first_sdp_position + waketime_in_lines);
+	crtc_state->has_alpm = crtc_state->has_lobf;
 }
 
 void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
@@ -719,7 +720,7 @@ void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state)
 		intel_dp = enc_to_intel_dp(encoder);
 
 		if (!intel_dp->as_sdp_supported ||
-		    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+		    !intel_alpm_is_aux_less(intel_dp, crtc_state))
 			continue;
 
 		mutex_lock(&intel_dp->alpm.lock);
@@ -735,8 +736,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 alpm_ctl, alpm_ctl2, lttpr_count;
 
-	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
-					  !crtc_state->has_lobf))
+	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
 		return;
 
 	mutex_lock(&intel_dp->alpm.lock);
@@ -744,7 +744,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	 * Panel Replay on eDP is always using ALPM aux less. I.e. no need to
 	 * check panel support at this point.
 	 */
-	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+	if (intel_alpm_is_aux_less(intel_dp, crtc_state)) {
 		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
 			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
 			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
@@ -792,10 +792,10 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
 	enum port port = dp_to_dig_port(intel_dp)->base.port;
 	u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
 
-	if (DISPLAY_VER(display) < 20)
+	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
 		return;
 
-	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
+	if (intel_alpm_is_aux_less(intel_dp, crtc_state)) {
 		int lfps_cycle = get_lfps_cycle_count(crtc_state);
 		u32 lfps_cycle_val;
 
@@ -854,13 +854,12 @@ void intel_alpm_enable_sink(struct intel_dp *intel_dp,
 {
 	u8 val;
 
-	if (!intel_psr_needs_alpm(intel_dp, crtc_state) && !crtc_state->has_lobf)
+	if (!crtc_state->has_alpm)
 		return;
 
 	val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
 
-	if (crtc_state->has_panel_replay || (crtc_state->has_lobf &&
-					     intel_alpm_aux_less_wake_supported(intel_dp)))
+	if (intel_alpm_is_aux_less(intel_dp, crtc_state))
 		val |= DP_ALPM_MODE_AUX_LESS;
 
 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);
diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
index ea90eba76ca7..5d404e7b07de 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.h
+++ b/drivers/gpu/drm/i915/display/intel_alpm.h
@@ -35,8 +35,8 @@ void intel_alpm_lobf_enable(const struct intel_crtc_state *new_crtc_state);
 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
 bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
 bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
-bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
-				 const struct intel_crtc_state *crtc_state);
+bool intel_alpm_is_aux_less(struct intel_dp *intel_dp,
+			    const struct intel_crtc_state *crtc_state);
 bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp *intel_dp,
 					      const struct intel_crtc_state *crtc_state);
 void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dbebd7210848..26a5d40289ac 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3449,8 +3449,10 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 	int i;
 	u8 owned_lane_mask;
 
-	if (DISPLAY_VER(display) < 20 ||
-	    !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
+	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
+		return;
+
+	if (!intel_alpm_is_aux_less(enc_to_intel_dp(encoder), crtc_state))
 		return;
 
 	owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a5f18ac8a7d0..e2cc73c98479 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1448,6 +1448,7 @@ struct intel_crtc_state {
 		u8 silence_period_sym_clocks;
 		u8 lfps_half_cycle_num_of_syms;
 	} alpm_state;
+	bool has_alpm;
 
 	/* to track changes in plane color blocks */
 	bool plane_color_changed;
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 4fe010df20be..8ebbdc3c0184 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -2371,7 +2371,7 @@ void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
 	struct ref_tracker *wakeref;
 	u8 owned_lane_mask;
 
-	if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
+	if (!crtc_state->has_alpm || !intel_alpm_is_aux_less(intel_dp, crtc_state))
 		return;
 
 	wakeref = intel_lt_phy_transaction_begin(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 872e253db178..1f14dbe57512 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1648,6 +1648,8 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
 	crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector,
 								       crtc_state->has_panel_replay);
 
+	crtc_state->has_alpm = intel_alpm_is_possible(intel_dp);
+
 	return true;
 
 unsupported:
@@ -1735,11 +1737,17 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
 	crtc_state->link_off_after_as_sdp_when_pr_active = compute_link_off_after_as_sdp_when_pr_active(connector);
 	crtc_state->disable_as_sdp_when_pr_active = compute_disable_as_sdp_when_pr_active(connector);
 
+	if (intel_alpm_is_possible(intel_dp))
+		crtc_state->has_alpm = alpm_config_valid(intel_dp, crtc_state, true, true, false);
+
 	if (!intel_dp_is_edp(intel_dp))
 		return true;
 
 	/* Remaining checks are for eDP only */
 
+	if (!crtc_state->has_alpm)
+		return false;
+
 	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
 	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
 		return false;
@@ -1762,9 +1770,6 @@ static bool _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
 		return false;
 	}
 
-	if (!alpm_config_valid(intel_dp, crtc_state, true, true, false))
-		return false;
-
 	return true;
 }
 
@@ -1888,6 +1893,15 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
 	crtc_state->panel_replay_dsc_support = connector->dp.panel_replay_caps.dsc_support;
 	crtc_state->has_panel_replay = _panel_replay_compute_config(crtc_state, conn_state);
 
+	/*
+	 * has_alpm may have been set speculatively while evaluating Panel
+	 * Replay. It is only valid if Panel Replay was actually selected;
+	 * otherwise the finally chosen feature (PSR2/SU or LOBF) decides it and
+	 * a PSR1 fallback must not enable ALPM.
+	 */
+	if (!crtc_state->has_panel_replay)
+		crtc_state->has_alpm = false;
+
 	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
 		_psr_compute_config(intel_dp, crtc_state, conn_state);
 
@@ -4555,16 +4569,6 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)
 				    connector, &i915_psr_status_fops);
 }
 
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)
-{
-	/*
-	 * eDP Panel Replay uses always ALPM
-	 * PSR2 uses ALPM but PSR1 doesn't
-	 */
-	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
-					     crtc_state->has_panel_replay);
-}
-
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state)
 {
@@ -4578,15 +4582,17 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
 	int vblank = intel_crtc_vblank_length(crtc_state);
 	int wake_lines;
 
-	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
-		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
-	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
-		wake_lines = DISPLAY_VER(display) < 20 ?
-			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
-						    crtc_state->alpm_state.fast_wake_lines) :
-			     crtc_state->alpm_state.io_wake_lines;
-	else
+	if (crtc_state->has_alpm) {
+		if (crtc_state->has_panel_replay)
+			wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+		else
+			wake_lines = DISPLAY_VER(display) < 20 ?
+				     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
+							    crtc_state->alpm_state.fast_wake_lines) :
+				     crtc_state->alpm_state.io_wake_lines;
+	} else {
 		wake_lines = 0;
+	}
 
 	/*
 	 * Disable the PSR features if wake lines exceed the available vblank.
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index d545fdaa0de7..4905ba4da4b8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -79,7 +79,6 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
 int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state);
 void intel_psr_connector_debugfs_add(struct intel_connector *connector);
 void intel_psr_debugfs_register(struct intel_display *display);
-bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
 bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
 				   const struct intel_crtc_state *crtc_state);
 void intel_psr_compute_config_late(struct intel_dp *intel_dp,
-- 
2.29.0

[PATCH v6 16/18] drm/i915/alpm: Compute and program switch to active latency

[Animesh Manna]

Program the ALPM switch to active latency into ALPM_CTL2. For UHBR link
rates the latency is derived from the link symbol clock and converted to
scanlines, for non-UHBR rates it is zero.

v2: Use macro instead of magic number wherever possible. [Jouni]

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 29 ++++++++++++++++++-
 .../drm/i915/display/intel_display_types.h    |  1 +
 2 files changed, 29 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 236341aa3c8d..84777c8d31bb 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -301,6 +301,31 @@ static int get_establishment_period(struct intel_dp *intel_dp,
 	return establishment_period;
 }
 
+static int get_switch_to_active(const struct intel_crtc_state *crtc_state)
+{
+	int port_clock = crtc_state->port_clock;
+	int switch_to_active;
+
+	if (intel_dp_is_uhbr(crtc_state)) {
+		/* symbol_clock (fLink) in MHz */
+		int symbol_clock = port_clock / intel_dp_link_symbol_size(port_clock) / 100;
+
+		/*
+		 * tSwitch to Active = 32 * (ML_PHY_LOCK Length + 3 + 64) / fLink
+		 *
+		 * The "+ 3" term is the trailing zero padding after the
+		 * POST_LT_SCRAMBLER_RESET, the "+ 64" term represents the MTP
+		 * time slots. The result is in microseconds.
+		 */
+		switch_to_active = get_dp_link_symbol_size(crtc_state) *
+				   (ML_PHY_LOCK_LEN_UHBR + 3 + 64) / symbol_clock;
+	} else {
+		switch_to_active = 0;
+	}
+
+	return switch_to_active;
+}
+
 /*
  * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+
  * tSilence, Max+ tPHY Establishment + tCDS) / tline)
@@ -360,7 +385,8 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
 	crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines;
 	crtc_state->alpm_state.silence_period_sym_clocks = silence_period;
 	crtc_state->alpm_state.lfps_half_cycle_num_of_syms = lfps_half_cycle;
-
+	crtc_state->alpm_state.switch_to_active = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
+									   get_switch_to_active(crtc_state));
 	return true;
 }
 
@@ -772,6 +798,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
 
 	alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
+	alpm_ctl2 |= ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(crtc_state->alpm_state.switch_to_active);
 
 	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2);
 	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e2cc73c98479..6387258cd633 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1447,6 +1447,7 @@ struct intel_crtc_state {
 		u8 aux_less_wake_lines;
 		u8 silence_period_sym_clocks;
 		u8 lfps_half_cycle_num_of_syms;
+		int switch_to_active;
 	} alpm_state;
 	bool has_alpm;
 
-- 
2.29.0

[PATCH v6 17/18] drm/i915/alpm: Program zero-based LFPS half cycle duration

[Animesh Manna]

The LFPS Half Cycle Duration field, as well as the First and Last LFPS
Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per
Bspec the value programmed must be N_Symbol - 1. The number of symbols
was programmed directly, making each half cycle one symbol clock too
long.

Subtract one in the PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION,
PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and
PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION field macros so the
programmed value matches the zero-based field encoding.

Bspec: 71632
Cc: Jouni Högander <jouni.hogander@intel.com>
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 8f60b671755a..387edf8df6e9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -339,11 +339,17 @@
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)		REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
 #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD, (val) - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
+/*
+ * The LFPS half cycle duration fields (including the first and last half
+ * cycle) are zero-based, i.e. the value programmed is N_Symbol - 1.
+ *
+ * Bspec: 71632
+ */
 #define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(20, 16)
-#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, val)
+#define  PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
 #define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(12, 8)
-#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)
+#define  PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
 #define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(4, 0)
-#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)
+#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
 
 #endif /* __INTEL_PSR_REGS_H__ */
-- 
2.29.0

[PATCH v6 18/18] drm/i915/alpm: Disallow ALPM for UHBR link rate

[Animesh Manna]

DP2.1 ALPM is not supported on UHBR (128b/132b) link rates on the NVL
platform. Reject the ALPM parameter computation for external DP running
at a UHBR rate on display version 35, so that ALPM (and the Panel Replay
and LOBF features that rely on it) is not enabled in that case. eDP is
excluded so eDP ALPM keeps working at any link rate.

Cc: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index 84777c8d31bb..51805a6bca86 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -453,6 +453,12 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
 	int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;
 	u8 max_wake_lines;
 
+	/* DP2.1 ALPM is not supported on UHBR (128b/132b) link rates on NVL. */
+	if (DISPLAY_VER(display) == 35 &&
+	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
+	    intel_dp_is_uhbr(crtc_state))
+		return false;
+
 	io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) +
 		preamble + phy_wake + tfw_exit_latency;
 	fast_wake_time = precharge + preamble + phy_wake +
-- 
2.29.0

Re: [PATCH v6 07/18] drm/i915/alpm: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/alpm: ALPM AUX-less wake time incorrectly restricted to legacy 6-bit maximum on xe3lpd
--

commit fefc7fdf839fcf4154d50e19eac0f82242cca5ad
Author: Animesh Manna <animesh.manna@intel.com>
Subject: drm/i915/alpm: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd

This commit widens the ALPM_CTL_AUX_LESS_WAKE_TIME bitfield from 6 bits
to 8 bits for xe3lpd (display version 35) and later. It introduces new
register macros and updates lnl_alpm_configure() to program the wake time
using the appropriate macro based on the display version.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 924fa8dd4638f..dc025058a6266 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -610,8 +610,12 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
>  		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
>  			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
> -			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |
> -			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
> +			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS;
> +
> +		if (DISPLAY_VER(display) < 35)
> +			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state->alpm_state.aux_less_wake_lines);
> +		else
> +			alpm_ctl |= ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(crtc_state->alpm_state.aux_less_wake_lines);

[Severity: Medium]
While this successfully programs the wider 8-bit wake time on xe3lpd hardware,
does _lnl_compute_aux_less_alpm_params() in the same file also need to be
updated to use this new mask?

Looking at _lnl_compute_aux_less_alpm_params(), the bounds check is still
hardcoded to the 6-bit legacy mask ALPM_CTL_AUX_LESS_WAKE_TIME_MASK on all
platforms:

	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
		return false;

Will this restrict aux_less_wake_lines to a maximum of 63, causing validation
to fail and aborting ALPM if the computed wake time is larger on xe3lpd?

Additionally, the safest params fallback is also restricted to the legacy mask:

	if (display->params.psr_safest_params)
		aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK;

Will this cap the safest params to 63 instead of 255 on xe3lpd?

>  
>  		if (intel_dp->as_sdp_supported)
>  			intel_alpm_configure_pr_as_sdp(intel_dp, crtc_state);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915180449.277933-1-animesh.manna@intel.com?part=7

Re: [PATCH v6 09/18] drm/i915/alpm: Half LFPS cycle calculation

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] display/alpm: uninitialized stack variables used for ALPM hardware programming
--

commit b718ea1f4bfa5d8848c313251d36c92815933b23
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Half LFPS cycle calculation

This commit adds support for half LFPS cycle calculation for DP2.1 ALPM
as dependent parameters got changed.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index cb24bba801a19..14ecb27095b29 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
[ ... ]
> +static void lnl_get_lfps_period_min_max_time(const struct intel_crtc_state *crtc_state,
> +					     int *min, int *max)
> +{
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +		if (crtc_state->port_clock < 540000) {
> +			*min = 65 * LFPS_CYCLE_COUNT;
> +			*max = 75 * LFPS_CYCLE_COUNT;
> +		} else {
> +			*min = 140;
> +			*max = 800;
> +		}
> +	}
> +}

[Severity: High]
Does this function leave min and max completely uninitialized for
non-eDP configurations?

For instance, when connecting an external DisplayPort sink on LunarLake
with ALPM capabilities, intel_crtc_has_type(..., INTEL_OUTPUT_EDP) would
be false, and the function returns without setting these parameters.

[ ... ]
>  static int get_lfps_cycle_time(const struct intel_crtc_state *crtc_state)
>  {
>  	int tlfps_cycle_min, tlfps_cycle_max;
>  
> -	get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
> -				    &tlfps_cycle_max);
> +	get_lfps_period_min_max_time(crtc_state, &tlfps_cycle_min,
> +				     &tlfps_cycle_max);
>  
>  	return tlfps_cycle_min +  (tlfps_cycle_max - tlfps_cycle_min) / 2;
>  }

[Severity: High]
Can these stack variables be consumed while still uninitialized?

Because lnl_get_lfps_period_min_max_time() lacks a non-eDP fallback, it
appears tlfps_cycle_min and tlfps_cycle_max could retain their uninitialized
stack values here when called for a standard DisplayPort setup.

These garbage values would then be used in the arithmetic calculation and
subsequently programmed into hardware ALPM registers. Could this potentially
cause display link corruption, link training failures, or hardware timeouts?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915180449.277933-1-animesh.manna@intel.com?part=9

Re: [PATCH v6 16/18] drm/i915/alpm: Compute and program switch to active latency

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/i915/alpm: ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY bounds check missing
- [High] drm/i915/alpm: switch_to_active math error inflates latency 32x
--

commit 6e4638c7fe4ea7d79d2000aac2b17f2fc3edc381
Author: Animesh Manna <animesh.manna@intel.com>
Subject: drm/i915/alpm: Compute and program switch to active latency

This commit programs the ALPM switch to active latency into ALPM_CTL2. For
UHBR link rates, the latency is derived from the link symbol clock and
converted to scanlines, while for non-UHBR rates it is set to zero.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 236341aa3c8d8..84777c8d31bb4 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
[ ... ]
> @@ -301,6 +301,31 @@ static int get_establishment_period(struct intel_dp *intel_dp,
>  	return establishment_period;
>  }
>  
> +static int get_switch_to_active(const struct intel_crtc_state *crtc_state)
> +{
> +	int port_clock = crtc_state->port_clock;
> +	int switch_to_active;
> +
> +	if (intel_dp_is_uhbr(crtc_state)) {
> +		/* symbol_clock (fLink) in MHz */
> +		int symbol_clock = port_clock / intel_dp_link_symbol_size(port_clock) / 100;
> +
> +		/*
> +		 * tSwitch to Active = 32 * (ML_PHY_LOCK Length + 3 + 64) / fLink
> +		 *
> +		 * The "+ 3" term is the trailing zero padding after the
> +		 * POST_LT_SCRAMBLER_RESET, the "+ 64" term represents the MTP
> +		 * time slots. The result is in microseconds.
> +		 */
> +		switch_to_active = get_dp_link_symbol_size(crtc_state) *
> +				   (ML_PHY_LOCK_LEN_UHBR + 3 + 64) / symbol_clock;

[Severity: High]
Does this logic incorrectly substitute the symbol rate for the bit rate,
inflating the latency by 32x?

In the DP spec formula, fLink is the link rate in Mbps, and multiplying the
symbol count by 32 correctly calculates bits divided by bit-rate. However,
symbol_clock is calculated here as port_clock / 32, meaning the denominator is
32x smaller than intended.

This math error calculates a latency of ~47.4us instead of 1.48us, causing
excessively long ALPM wake sequences. Additionally, standard integer division
here drops fractional microseconds, so if corrected, the wait time might be
shorter than the physical hardware minimum on high-clock displays.

> +	} else {
> +		switch_to_active = 0;
> +	}
> +
> +	return switch_to_active;
> +}
> +
[ ... ]
> @@ -360,7 +385,8 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp,
>  	crtc_state->alpm_state.aux_less_wake_lines = aux_less_wake_lines;
>  	crtc_state->alpm_state.silence_period_sym_clocks = silence_period;
>  	crtc_state->alpm_state.lfps_half_cycle_num_of_syms = lfps_half_cycle;
> -
> +	crtc_state->alpm_state.switch_to_active = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
> +									   get_switch_to_active(crtc_state));

[Severity: High]
Can the computed scanline count overflow the 5-bit register field it is
later written to?

Unlike the other parameters configured in _lnl_compute_aux_less_alpm_params(),
there is no bounds check here against the maximum allowed value before
assigning it to switch_to_active.

With the 32x inflation bug above, on high-refresh-rate displays (like 4K @
360Hz), ~47us translates to > 31 scanlines.

>  	return true;
>  }
>  
[ ... ]
> @@ -772,6 +798,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
>  
>  	alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
> +	alpm_ctl2 |= ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(crtc_state->alpm_state.switch_to_active);

[Severity: High]
Does this silently mask and truncate the unbounded scanline count?

ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY uses REG_FIELD_PREP with a 5-bit mask.
Any value > 31 is silently truncated. For example, 32 scanlines truncates
to 0, completely removing the required wake latency. This causes the hardware
to exit ALPM before the PHY has locked, leading to link training failures or
display corruption.

>  
>  	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2);
>  	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915180449.277933-1-animesh.manna@intel.com?part=16

Re: [PATCH v6 12/18] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] drm/i915/alpm: DP 2.1 ALPM LTTPR logic is unreachable dead code
- [Medium] drm/i915/alpm: Unchecked negative return from drm_dp_lttpr_count() causes register corruption
- [Low] drm/i915/alpm: Dead code in lttpr_count error check
- [Low] drm/i915/alpm: Comment contradicts LTTPR revision code check
--

commit a317ca0f7af6803f7b3932311f82447dfda1b648
Author: Animesh Manna <animesh.manna@intel.com>
drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM

This commit programs the total number of LTTPRs for DP 2.1 ALPM before
link training by issuing an AUX write transaction to DP_TOTAL_LTTPR_CNT.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index da653a407e97e..06c1a59aa2c51 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -726,7 +726,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -	u32 alpm_ctl;
> +	u32 alpm_ctl, alpm_ctl2, lttpr_count;
>  
[ ... ]
> @@ -762,6 +762,11 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  
>  	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines);
>  
> +	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> +
> +	alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);

[Severity: Medium]
Does this assignment to a u32 variable cause error codes to go unhandled?

The function drm_dp_lttpr_count() can return negative error codes like
-ERANGE or -EINVAL on failure. If this happens, assigning it to the unsigned
lttpr_count variable strips the negative sign and results in a large value
being passed into ALPM_CTL2_NUMBER_OF_LTTPR(). This could corrupt the
register programming by injecting invalid bits via REG_FIELD_PREP.

> +
> +	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2);
>  	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
>  	mutex_unlock(&intel_dp->alpm.lock);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index cb92cff906146..37c8306a1fa0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -2265,6 +2265,25 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
>  	return passed;
>  }
>  
> +static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp,
> +					int lttpr_count)
> +{
> +	u8 val;
> +
> +	/*
> +	 * Program only for DP2.1 and return if LTTPR revison is less than 0x20
> +	 * where 0:3 represents minor rev and 4:7 represent major rev
> +	 */

[Severity: Low]
This isn't a bug, but the comment specifies "less than 0x20", while the
code below implements a less than or equal to 0x20 (<= 0x20) check.

> +	if (!intel_dp_is_edp(intel_dp) ||
> +	    lttpr_count < 0 ||

[Severity: Low]
Is this lttpr_count < 0 check reachable?

In intel_dp_start_link_train(), the lttpr_count is clamped to 0 on error
before being passed to this function:

	if (lttpr_count < 0)
		/* Still continue with enabling the port and link training. */
		lttpr_count = 0;

	intel_dp_prepare_link_train(intel_dp, crtc_state);
	intel_dp_update_lttpr_count(intel_dp, lttpr_count);

> +	    intel_dp->lttpr_common_caps[0] <= 0x20)

[Severity: High]
Can this LTTPR programming ever be reached for either DP or eDP configurations?

For standard DP connections, the function returns immediately because of the
!intel_dp_is_edp(intel_dp) check above.

For eDP connections, intel_dp_init_lttpr_and_dprx_caps() explicitly skips
LTTPR capabilities initialization, leaving intel_dp->lttpr_common_caps[0]
as 0. That causes the function to also return immediately due to this
<= 0x20 check, rendering the feature unreachable.

> +		return;
> +
> +	val = intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
> +					  DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, val);
> +}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915180449.277933-1-animesh.manna@intel.com?part=12

Re: [PATCH v6 14/18] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] drm/i915/alpm: invalid DPCD capability checks in intel_alpm_is_possible()
- [High] drm/i915/alpm: ALPM_CTL left enabled on hot-unplug due to dynamic capability checks
--

commit f95070b21da14e9f299aa7eaa97682597723ecc9
Author: Animesh Manna <animesh.manna@intel.com>
Subject: drm/i915/alpm: Replace is_edp() with alpm_is_possible()

This commit introduces a separate intel_alpm_is_possible() function to
check for ALPM capability from DPCD information, replacing earlier checks
that relied solely on the panel being eDP.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 06c1a59aa2c51..29a93a252fe9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c

[ ... ]

> @@ -69,6 +69,13 @@ void intel_alpm_init(struct intel_dp *intel_dp)
>  	mutex_init(&intel_dp->alpm.lock);
>  }
>  
> +bool intel_alpm_is_possible(struct intel_dp *intel_dp)
> +{
> +	return (intel_dp->alpm_dpcd ||
> +		intel_dp->lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
> +					    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]);
> +}

[Severity: High]
Does this logic correctly enforce DP requirements for ALPM?

It looks like this uses a logical OR instead of requiring both the sink and
LTTPR to support ALPM. Additionally, this seems to access the raw capability
byte without masking the specific ALPM capability bit, which could mean
reserved bits will be evaluated as true. 

Can this break standard DP link training invariants when connecting a display
with LTTPRs that support ALPM while the sink does not, or when a sink has
reserved bits set but no ALPM support?

[ ... ]

> @@ -832,7 +839,7 @@ void intel_alpm_lobf_disable(const struct intel_crtc_state *new_crtc_state)
>  
>  		intel_dp = enc_to_intel_dp(encoder);
>  
> -		if (!intel_dp_is_edp(intel_dp))
> +		if (!intel_alpm_is_possible(intel_dp))
>  			continue;
>  
>  		mutex_lock(&intel_dp->alpm.lock);

[Severity: High]
Could this dynamic capability check cause ALPM_CTL to be left enabled during
a hot-unplug event?

During a hot-unplug event, the cached DPCD capabilities like alpm_dpcd can
be cleared before the teardown hooks execute. Because this teardown function
checks these dynamic capabilities via intel_alpm_is_possible() instead of
the old hardware state, it might return early and fail to clear the ALPM_CTL
hardware register.

Would this leave the transcoder with ALPM enabled when it is supposed to be
disabled, potentially causing state mismatches on subsequent modesets?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915180449.277933-1-animesh.manna@intel.com?part=14

Re: [PATCH v6 03/18] drm/i915/alpm: alpm_init() for DP2.1

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/alpm: hardware state leak on hot-unplug due to premature capability reset
--

commit b6800420511819216ede410fb998491c8d931411
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: alpm_init() for DP2.1

This commit initializes ALPM for DP2.1 and separates out ALPM mutex-init
from alpm-init.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 650c8b39270be..b4742bd33cb42 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6354,6 +6354,7 @@ intel_dp_detect(struct drm_connector *_connector,
>  		connector->dp.panel_replay_caps.su_support = false;
>  		connector->dp.panel_replay_caps.dsc_support =
>  			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
> +		intel_dp->alpm_dpcd = 0;

[Severity: Medium]
Does clearing this capability flag during the detect callback cause a 
hardware state leak on hot-unplug?

When an active display is hot-unplugged, intel_dp_detect() runs and zeroes 
intel_dp->alpm_dpcd here. However, userspace will subsequently issue an 
atomic commit to disable the CRTC. 

During that disable sequence, intel_alpm_disable() in intel_alpm.c checks 
intel_dp->alpm_dpcd to see if it should proceed. Since the capability was 
already cleared, the check evaluates to false and the function exits early. 
This skips the register cleanup, leaving the transcoder's ALPM_CTL hardware 
registers enabled.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915180449.277933-1-animesh.manna@intel.com?part=3

Re: [PATCH v6 18/18] drm/i915/alpm: Disallow ALPM for UHBR link rate

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915: ALPM and Panel Replay stay enabled with zeroed params on external DP UHBR
--

commit 735fad731be8c8f544adf68949ae9f43b62606f2
Author: Animesh Manna <animesh.manna@intel.com>

drm/i915/alpm: Disallow ALPM for UHBR link rate

This commit attempts to reject ALPM parameter computation for external DP
running at a UHBR rate on NVL platforms. eDP is explicitly excluded from this
check to keep eDP ALPM working at all link rates.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 84777c8d31bb4..51805a6bca867 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -453,6 +453,12 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp,
>  	int precharge = intel_dp_aux_fw_sync_len(intel_dp) - preamble;
>  	u8 max_wake_lines;
>  
> +	/* DP2.1 ALPM is not supported on UHBR (128b/132b) link rates on NVL. */
> +	if (DISPLAY_VER(display) == 35 &&
> +	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
> +	    intel_dp_is_uhbr(crtc_state))
> +		return false;
> +

[Severity: High]
Does returning false here successfully prevent ALPM and Panel Replay from being
enabled on external DP?

Looking at _panel_replay_compute_config() in
drivers/gpu/drm/i915/display/intel_psr.c, there is an early return for non-eDP
displays:

    if (!intel_dp_is_edp(intel_dp))
        return true;

    /* Remaining checks are for eDP only */

    if (!crtc_state->has_alpm)
        return false;

Because of this early return, the failed ALPM parameter computation is bypassed
for external DP. Later in intel_sel_update_config_valid(), has_alpm is
unconditionally overwritten:

    crtc_state->has_alpm = intel_alpm_is_possible(intel_dp);
    return true;

Could this sequence leave ALPM and Panel Replay enabled with uninitialized
(zeroed) wake lines and times, potentially violating DP specifications and
preventing the external display from waking up correctly?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915180449.277933-1-animesh.manna@intel.com?part=18

Re: [PATCH v6 15/18] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] drm/i915/alpm: Unconditional overwrite of has_alpm breaks Panel Replay without ALPM
- [High] drm/i915/alpm: Retained eDP check in intel_psr_needs_alpm_aux_less prevents AS SDP for external DP
- [High] drm/i915/alpm: has_alpm state leak when PSR/PR features are downgraded late
- [Medium] drm/i915/alpm: Early return in intel_alpm_port_configure prevents clearing stale ALPM state
- [Medium] drm/i915/alpm: Missing has_alpm check causes incorrect PR_ALPM_CTL programming
--

commit 4dcfef3fd89e0ed18372dabec785892c009d57eb
Author: Animesh Manna <animesh.manna@intel.com>
Subject: drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

This commit introduces a single crtc_state->has_alpm flag to track ALPM
enablement, decoupling it from implicit feature tracking like eDP Panel
Replay, PSR2, or LOBF. It updates various ALPM configuration and port
paths to use this new flag as the single source of truth.

> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 29a93a252fe9b..236341aa3c8d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c

[ ... ]

> @@ -719,7 +720,7 @@ void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state *crtc_state)
>  		intel_dp = enc_to_intel_dp(encoder);
>  
>  		if (!intel_dp->as_sdp_supported ||
> -		    !intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
> +		    !intel_alpm_is_aux_less(intel_dp, crtc_state))
>  			continue;
>  
>  		mutex_lock(&intel_dp->alpm.lock);

[Severity: Medium]
Does this missing check for crtc_state->has_alpm cause incorrect
PR_ALPM_CTL programming?

The intel_alpm_is_aux_less() function evaluates to true for Panel Replay
regardless of the actual has_alpm state. Without an explicit check verifying
that ALPM is actually active, if Panel Replay is explicitly falling back to
a "without ALPM" configuration, this loop will incorrectly write AS SDP
parameters to the ALPM controller, which contradicts the fallback state.

[ ... ]

> @@ -792,10 +792,10 @@ void intel_alpm_port_configure(struct intel_dp *intel_dp,
>  	enum port port = dp_to_dig_port(intel_dp)->base.port;
>  	u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
>  
> -	if (DISPLAY_VER(display) < 20)
> +	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
>  		return;

[Severity: Medium]
Will this early return prevent clearing stale ALPM state in the hardware?

Previously, this function would proceed and write the zeroed alpm_ctl_val
and lfps_ctl_val to the hardware when ALPM was disabled. By returning
early when crtc_state->has_alpm is false, any transition from an
ALPM-enabled mode to an ALPM-disabled mode will skip the clearing writes.
This leaves the hardware with an active ALPM configuration while the driver
state considers it disabled.

> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 872e253db1786..1f14dbe57512f 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1648,6 +1648,8 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
>  	crtc_state->enable_psr2_su_region_et = psr2_su_region_et_valid(connector,
>  								       crtc_state->has_panel_replay);
>  
> +	crtc_state->has_alpm = intel_alpm_is_possible(intel_dp);
> +

[Severity: High]
Does this unconditional assignment overwrite the validated has_alpm state?

The Panel Replay configuration path sets has_alpm based on whether ALPM
timing actually fits into the vblank period. When Panel Replay is validated
but ALPM timing fails, has_alpm is correctly set to false to allow Panel
Replay without ALPM.

This line in intel_sel_update_config_valid() unconditionally overwrites
that calculated state with a simple capability check, forcing it back to
true. This destroys the fallback state, causing the late compute config
to evaluate ALPM wake lines again, fail, and fully disable Panel Replay
on external DP.

[ ... ]

> @@ -4555,16 +4569,6 @@ void intel_psr_connector_debugfs_add(struct intel_connector *connector)
>  				    connector, &i915_psr_status_fops);
>  }
>  
> -bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state)
> -{
> -	/*
> -	 * eDP Panel Replay uses always ALPM
> -	 * PSR2 uses ALPM but PSR1 doesn't
> -	 */
> -	return intel_dp_is_edp(intel_dp) && (crtc_state->has_sel_update ||
> -					     crtc_state->has_panel_replay);
> -}
> -
>  bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>  				   const struct intel_crtc_state *crtc_state)
>  {

[Severity: High]
Does retaining the eDP-only check in intel_psr_needs_alpm_aux_less()
prevent AS SDP configuration for external DP Panel Replay?

While intel_alpm_is_aux_less() was updated to support external DP,
intel_psr_needs_alpm_aux_less() still restricts true return values to
eDP only. Any external DP configuration enabling Panel Replay will fail
this check when evaluated by intel_dp_pr_with_as_sdp_enabled() in the
link training paths.

This leads to silently missing the DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE
configuration during link training, causing a mismatch between source
programming and the sink DPCD configuration.

> @@ -4578,15 +4582,17 @@ void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>  	int vblank = intel_crtc_vblank_length(crtc_state);
>  	int wake_lines;
>  
> -	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
> -		wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
> -	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
> -		wake_lines = DISPLAY_VER(display) < 20 ?
> -			     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
> -						    crtc_state->alpm_state.fast_wake_lines) :
> -			     crtc_state->alpm_state.io_wake_lines;
> -	else
> +	if (crtc_state->has_alpm) {
> +		if (crtc_state->has_panel_replay)
> +			wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
> +		else
> +			wake_lines = DISPLAY_VER(display) < 20 ?
> +				     psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
> +							    crtc_state->alpm_state.fast_wake_lines) :
> +				     crtc_state->alpm_state.io_wake_lines;
> +	} else {
>  		wake_lines = 0;
> +	}
>  
>  	/*
>  	 * Disable the PSR features if wake lines exceed the available vblank.

[Severity: High]
Can has_alpm leak as true if PSR or Panel Replay features are disabled
late in this function?

When falling back to PSR1 or fully disabling PSR due to vblank timing limits
or hardware workarounds later in intel_psr_compute_config_late():

    if (crtc_state->has_panel_replay) {
            crtc_state->has_panel_replay = false;
            crtc_state->has_psr = false;
    }
    crtc_state->has_sel_update = false;

The corresponding feature flags are cleared, but has_alpm is left as true.
Since ALPM programming paths (like intel_alpm_port_configure) now rely
directly on has_alpm, this leaked state can cause unintended ALPM hardware
programming on unsupported modes.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915180449.277933-1-animesh.manna@intel.com?part=15

Re: [PATCH v6 17/18] drm/i915/alpm: Program zero-based LFPS half cycle duration

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/i915/alpm: bounds check rejects max valid LFPS half cycle duration
--

commit df710743c62bb2cde8d5cec635597f5355e70e89
Author: Animesh Manna <animesh.manna@intel.com>
Subject: drm/i915/alpm: Program zero-based LFPS half cycle duration

The LFPS Half Cycle Duration field, as well as the First and Last LFPS
Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per
Bspec the value programmed must be N_Symbol - 1. The number of symbols
was programmed directly, making each half cycle one symbol clock too
long.

> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 8f60b671755aa..387edf8df6e98 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -339,11 +339,17 @@

[ ... ]

>  #define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(4, 0)
> -#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, val)
> +#define  PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)

[Severity: Medium]
Since this macro now subtracts 1 for zero-based encoding, does the bounds
check in _lnl_compute_aux_less_alpm_params() also need to be updated?

drivers/gpu/drm/i915/display/intel_alpm.c:_lnl_compute_aux_less_alpm_params() {
	...
	if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK ||
	    silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK ||
	    lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK)
		return false;
	...
}

It looks like this check restricts the maximum allowed symbols to 31 (the
mask value). With the new zero-based encoding, shouldn't a value of 32 be
permitted? If lfps_half_cycle is 32, this bounds check will return false,
which could artificially restrict the limit and reject valid hardware
display configurations.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260915180449.277933-1-animesh.manna@intel.com?part=17

✓ i915.CI.BAT: success for Enable DP2.1 alpm (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 970 bytes --]

== Series Details ==

Series: Enable DP2.1 alpm (rev6)
URL   : https://patchwork.freedesktop.org/series/156417/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_19152 -> Patchwork_156417v6
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/index.html

Participating hosts (39 -> 38)
------------------------------

  Missing    (1): bat-dg2-13 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: CI_DRM_19152 -> Patchwork_156417v6

  CI-20190529: 20190529
  CI_DRM_19152: 0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9098: 9098
  Patchwork_156417v6: 0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/index.html

[-- Attachment #2: Type: text/html, Size: 1535 bytes --]

✗ i915.CI.Full: failure for Enable DP2.1 alpm (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 144960 bytes --]

== Series Details ==

Series: Enable DP2.1 alpm (rev6)
URL   : https://patchwork.freedesktop.org/series/156417/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_19152_full -> Patchwork_156417v6_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_156417v6_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_156417v6_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_156417v6_full:

### IGT changes ###

#### Possible regressions ####

  * igt@perf@gen12-oa-tlb-invalidate@1-vcs1:
    - shard-mtlp:         [PASS][1] -> [FAIL][2] +1 other test fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-6/igt@perf@gen12-oa-tlb-invalidate@1-vcs1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-2/igt@perf@gen12-oa-tlb-invalidate@1-vcs1.html

  
Known issues
------------

  Here are the changes found in Patchwork_156417v6_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_setmaster@master-drop-set-user:
    - shard-mtlp:         [PASS][3] -> [FAIL][4] ([i915#17048])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@core_setmaster@master-drop-set-user.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@core_setmaster@master-drop-set-user.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu-1:       NOTRUN -> [SKIP][5] ([i915#11078])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_bad_reloc@negative-reloc-bltcopy:
    - shard-mtlp:         NOTRUN -> [SKIP][6] ([i915#3281]) +1 other test skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@gem_bad_reloc@negative-reloc-bltcopy.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-mtlp:         NOTRUN -> [SKIP][7] ([i915#9323])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-tglu:         NOTRUN -> [SKIP][8] ([i915#13008])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][9] ([i915#9323])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          [PASS][10] -> [INCOMPLETE][11] ([i915#13356] / [i915#16348])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg2-3/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-5/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-tglu:         NOTRUN -> [SKIP][12] ([i915#7697])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@gem_close_race@multigpu-basic-process.html
    - shard-dg1:          NOTRUN -> [SKIP][13] ([i915#7697])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-tglu-1:       NOTRUN -> [SKIP][14] ([i915#7697])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-dg1:          NOTRUN -> [SKIP][15] +30 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_sseu@engines:
    - shard-tglu:         NOTRUN -> [SKIP][16] ([i915#280])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@gem_ctx_sseu@engines.html

  * igt@gem_eio@in-flight-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][17] ([i915#13390])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk9/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-dg1:          NOTRUN -> [SKIP][18] ([i915#4036])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_balancer@parallel:
    - shard-tglu:         NOTRUN -> [SKIP][19] ([i915#4525]) +2 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-tglu-1:       NOTRUN -> [SKIP][20] ([i915#4525]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-rkl:          NOTRUN -> [SKIP][21] ([i915#4525])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_big@single:
    - shard-rkl:          NOTRUN -> [FAIL][22] ([i915#16604])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-2/igt@gem_exec_big@single.html

  * igt@gem_exec_capture@capture-invisible:
    - shard-glk11:        NOTRUN -> [SKIP][23] ([i915#6334]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk11/igt@gem_exec_capture@capture-invisible.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-tglu:         NOTRUN -> [SKIP][24] ([i915#6344])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_capture@capture@vecs0-lmem0:
    - shard-dg1:          NOTRUN -> [FAIL][25] ([i915#16904]) +2 other tests fail
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@gem_exec_capture@capture@vecs0-lmem0.html

  * igt@gem_exec_fence@syncobj-backward-timeline-chain-engines:
    - shard-snb:          NOTRUN -> [SKIP][26] +93 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-snb1/igt@gem_exec_fence@syncobj-backward-timeline-chain-engines.html

  * igt@gem_exec_flush@basic-batch-kernel-default-wb:
    - shard-dg1:          NOTRUN -> [SKIP][27] ([i915#3539] / [i915#4852]) +2 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@gem_exec_flush@basic-batch-kernel-default-wb.html

  * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][28] ([i915#3281]) +7 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html

  * igt@gem_exec_reloc@basic-write-read:
    - shard-dg1:          NOTRUN -> [SKIP][29] ([i915#3281]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@gem_exec_reloc@basic-write-read.html

  * igt@gem_exec_schedule@preempt-queue:
    - shard-dg1:          NOTRUN -> [SKIP][30] ([i915#4812]) +1 other test skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@gem_exec_schedule@preempt-queue.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][31] ([i915#13196] / [i915#13356]) +1 other test incomplete
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk11/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][32] ([i915#4860])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@gem_fenced_exec_thrash@no-spare-fences-interruptible.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-tglu:         NOTRUN -> [SKIP][33] ([i915#4613] / [i915#7582])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-mtlp:         NOTRUN -> [SKIP][34] ([i915#4613])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - shard-tglu-1:       NOTRUN -> [SKIP][35] ([i915#4613]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-rkl:          NOTRUN -> [SKIP][36] ([i915#4613]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][37] ([i915#14544] / [i915#4613])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-glk:          NOTRUN -> [SKIP][38] ([i915#4613]) +3 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk9/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@verify-random-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][39] ([i915#4613]) +5 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@gem_lmem_swapping@verify-random-ccs.html

  * igt@gem_madvise@dontneed-before-pwrite:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#3282])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@gem_madvise@dontneed-before-pwrite.html

  * igt@gem_mmap_wc@close:
    - shard-dg1:          NOTRUN -> [SKIP][41] ([i915#4083]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@gem_mmap_wc@close.html

  * igt@gem_mmap_wc@write-read:
    - shard-mtlp:         NOTRUN -> [SKIP][42] ([i915#4083])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@gem_mmap_wc@write-read.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#3282])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-6/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-dg1:          NOTRUN -> [SKIP][44] ([i915#3282]) +5 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_pread@exhaustion:
    - shard-glk:          NOTRUN -> [WARN][45] ([i915#2658])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk9/igt@gem_pread@exhaustion.html
    - shard-tglu:         NOTRUN -> [WARN][46] ([i915#2658]) +1 other test warn
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-random:
    - shard-rkl:          NOTRUN -> [SKIP][47] ([i915#3282]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-2/igt@gem_pwrite@basic-random.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-tglu:         NOTRUN -> [SKIP][48] ([i915#13398])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_render_copy@yf-tiled-ccs-to-linear:
    - shard-mtlp:         NOTRUN -> [SKIP][49] ([i915#8428]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@gem_render_copy@yf-tiled-ccs-to-linear.html

  * igt@gem_tiled_wb:
    - shard-dg1:          NOTRUN -> [SKIP][50] ([i915#4077]) +5 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@gem_tiled_wb.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][51] ([i915#3297]) +1 other test skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][52] ([i915#3297]) +2 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][53] ([i915#3297]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][54] ([i915#13356] / [i915#14586])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk10/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-tglu:         NOTRUN -> [SKIP][55] ([i915#2527] / [i915#2856]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-dg1:          NOTRUN -> [SKIP][56] ([i915#2527]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-mtlp:         NOTRUN -> [SKIP][57] ([i915#2856])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-tglu-1:       NOTRUN -> [SKIP][58] ([i915#2527] / [i915#2856]) +2 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#2527]) +2 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@gen9_exec_parse@secure-batches.html

  * igt@gpu_buddy@gpu_buddy:
    - shard-dg1:          NOTRUN -> [SKIP][60] ([i915#15678])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@gpu_buddy@gpu_buddy.html

  * igt@i915_drm_fdinfo@all-busy-idle-check-all:
    - shard-dg1:          NOTRUN -> [SKIP][61] ([i915#14123])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@i915_drm_fdinfo@all-busy-idle-check-all.html

  * igt@i915_drm_fdinfo@virtual-busy-hang-all:
    - shard-dg1:          NOTRUN -> [SKIP][62] ([i915#14118])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@i915_drm_fdinfo@virtual-busy-hang-all.html

  * igt@i915_module_load@resize-bar:
    - shard-rkl:          NOTRUN -> [SKIP][63] ([i915#6412])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-dg1:          NOTRUN -> [SKIP][64] ([i915#6590]) +1 other test skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@i915_pm_freq_mult@media-freq@gt0.html
    - shard-tglu:         NOTRUN -> [SKIP][65] ([i915#6590]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglu-1:       NOTRUN -> [WARN][66] ([i915#13790] / [i915#2681]) +1 other test warn
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_sseu@full-enable:
    - shard-mtlp:         NOTRUN -> [SKIP][67] ([i915#8437])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@i915_pm_sseu@full-enable.html

  * igt@i915_query@query-topology-known-pci-ids:
    - shard-tglu:         NOTRUN -> [SKIP][68] ([i915#16109])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@i915_query@query-topology-known-pci-ids.html

  * igt@i915_query@query-topology-unsupported:
    - shard-tglu:         NOTRUN -> [SKIP][69] ([i915#16079])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@i915_query@query-topology-unsupported.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#5723])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-rkl:          [PASS][71] -> [INCOMPLETE][72] ([i915#4817])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@i915_suspend@fence-restore-tiled2untiled.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - shard-dg1:          NOTRUN -> [SKIP][73] ([i915#4215])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-tglu:         NOTRUN -> [SKIP][74] ([i915#12454] / [i915#12712])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-2:
    - shard-glk:          [PASS][75] -> [FAIL][76] ([i915#14888]) +1 other test fail
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-2.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk1/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-2.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-tglu-1:       NOTRUN -> [SKIP][77] ([i915#1769] / [i915#3555])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#5286]) +2 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][79] ([i915#5286]) +4 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-dg1:          NOTRUN -> [SKIP][80] ([i915#5286])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-dg1:          NOTRUN -> [SKIP][81] ([i915#4538] / [i915#5286]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
    - shard-tglu:         NOTRUN -> [SKIP][82] ([i915#5286]) +4 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-tglu:         NOTRUN -> [SKIP][83] ([i915#3828])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html
    - shard-dg1:          NOTRUN -> [SKIP][84] ([i915#3828])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][85] ([i915#3638])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][86] ([i915#3638])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][87] ([i915#14544] / [i915#3638])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][88] ([i915#4423])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][89] +2 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-dg1:          NOTRUN -> [SKIP][90] ([i915#4538]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-c-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][91] ([i915#6095]) +17 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-c-edp-1.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][92] ([i915#14098] / [i915#6095]) +19 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-2/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#14544] / [i915#6095]) +7 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#14098] / [i915#14544] / [i915#6095]) +6 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][95] ([i915#12313])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-glk10:        NOTRUN -> [SKIP][96] +109 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk10/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
    - shard-glk:          NOTRUN -> [SKIP][97] +372 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#12805])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc:
    - shard-glk11:        NOTRUN -> [SKIP][99] +137 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk11/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([i915#6095]) +11 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-6/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          [PASS][101] -> [INCOMPLETE][102] ([i915#15582])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk2/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-1.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk8/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][103] ([i915#6095]) +69 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
    - shard-rkl:          [PASS][104] -> [INCOMPLETE][105] ([i915#14694] / [i915#15582]) +1 other test incomplete
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-2/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][106] ([i915#14694] / [i915#15582]) +1 other test incomplete
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][107] ([i915#6095]) +29 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][108] ([i915#6095]) +186 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-17/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-tglu-1:       NOTRUN -> [SKIP][109] ([i915#6095]) +54 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#10307] / [i915#6095]) +89 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-6/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#10307] / [i915#10434] / [i915#6095]) +5 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-4/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition:
    - shard-tglu:         NOTRUN -> [SKIP][112] ([i915#3742])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-rkl:          NOTRUN -> [SKIP][113] ([i915#3742])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#17016]) +3 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-4/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_audio@hdmi-audio-after-suspend:
    - shard-mtlp:         NOTRUN -> [SKIP][115] ([i915#11151])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_chamelium_audio@hdmi-audio-after-suspend.html

  * igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d:
    - shard-dg1:          NOTRUN -> [SKIP][116] ([i915#16471])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d.html
    - shard-tglu:         NOTRUN -> [SKIP][117] ([i915#16471]) +1 other test skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_chamelium_color_pipeline@plane-ctm3x4-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d:
    - shard-rkl:          NOTRUN -> [SKIP][118] ([i915#16471])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_chamelium_color_pipeline@plane-lut1d.html

  * igt@kms_chamelium_edid@dp-edid-change-during-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#11151] / [i915#7828]) +3 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-tglu-1:       NOTRUN -> [SKIP][120] ([i915#11151] / [i915#7828]) +7 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_frames@hdmi-aspect-ratio:
    - shard-tglu:         NOTRUN -> [SKIP][121] ([i915#11151] / [i915#7828]) +6 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_chamelium_frames@hdmi-aspect-ratio.html

  * igt@kms_chamelium_hpd@dp-hpd-fast:
    - shard-mtlp:         NOTRUN -> [SKIP][122] ([i915#11151] / [i915#7828])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_chamelium_hpd@dp-hpd-fast.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-dg1:          NOTRUN -> [SKIP][123] ([i915#11151] / [i915#7828]) +5 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_color_pipeline@plane-ctm3x4-lut1d@pipe-b-plane-4:
    - shard-mtlp:         NOTRUN -> [SKIP][124] ([i915#16990]) +7 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_color_pipeline@plane-ctm3x4-lut1d@pipe-b-plane-4.html

  * igt@kms_color_pipeline@plane-ctm3x4@pipe-b-plane-3:
    - shard-tglu:         NOTRUN -> [SKIP][125] ([i915#16990]) +31 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_color_pipeline@plane-ctm3x4@pipe-b-plane-3.html

  * igt@kms_color_pipeline@plane-lut1d-ctm3x4-lut1d@pipe-a-plane-4:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([i915#16990]) +5 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_color_pipeline@plane-lut1d-ctm3x4-lut1d@pipe-a-plane-4.html

  * igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-d-plane-3:
    - shard-tglu-1:       NOTRUN -> [SKIP][127] ([i915#16990]) +31 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_color_pipeline@plane-lut1d-ctm3x4@pipe-d-plane-3.html

  * igt@kms_color_pipeline@plane-lut1d-lut1d@pipe-b-plane-4:
    - shard-dg1:          NOTRUN -> [SKIP][128] ([i915#16990]) +31 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_color_pipeline@plane-lut1d-lut1d@pipe-b-plane-4.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][129] ([i915#14544] / [i915#15865])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0-hdcp14:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#15330]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][131] ([i915#15330] / [i915#3116] / [i915#3299]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([i915#15865]) +2 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][133] ([i915#15865]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-2/igt@kms_content_protection@suspend-resume.html

  * igt@kms_content_protection@type1:
    - shard-dg1:          NOTRUN -> [SKIP][134] ([i915#15865])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#14544] / [i915#3555])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#13049]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-rkl:          NOTRUN -> [SKIP][137] ([i915#3555]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [FAIL][138] ([i915#13566]) +1 other test fail
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-mtlp:         NOTRUN -> [SKIP][139] ([i915#13049])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-tglu:         NOTRUN -> [SKIP][140] ([i915#3555]) +3 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-rapid-movement-max-size:
    - shard-dg1:          NOTRUN -> [SKIP][141] ([i915#3555])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-rkl:          [PASS][142] -> [FAIL][143] ([i915#13566]) +3 other tests fail
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-1/igt@kms_cursor_crc@cursor-sliding-256x85.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-tglu-1:       NOTRUN -> [SKIP][144] ([i915#3555]) +1 other test skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][145] ([i915#13049])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [FAIL][146] ([i915#13566]) +1 other test fail
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-sliding-64x64:
    - shard-glk:          NOTRUN -> [DMESG-FAIL][147] ([i915#118]) +2 other tests dmesg-fail
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk3/igt@kms_cursor_crc@cursor-sliding-64x64.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][148] +54 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          NOTRUN -> [FAIL][149] ([i915#15804])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-rkl:          NOTRUN -> [SKIP][150] ([i915#9067])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
    - shard-tglu-1:       NOTRUN -> [SKIP][151] ([i915#9067])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-tglu-1:       NOTRUN -> [SKIP][152] ([i915#9723])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-rkl:          NOTRUN -> [SKIP][153] ([i915#13691])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][154] ([i915#14544] / [i915#3804])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_aux_dev@basic:
    - shard-dg1:          NOTRUN -> [SKIP][155] ([i915#1257])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_dp_aux_dev@basic.html
    - shard-tglu:         NOTRUN -> [SKIP][156] ([i915#1257])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_dp_aux_dev@basic.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-tglu:         NOTRUN -> [SKIP][157] ([i915#13749])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-mtlp:         NOTRUN -> [SKIP][158] ([i915#16867])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#16867])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback.html
    - shard-tglu-1:       NOTRUN -> [SKIP][160] ([i915#16870])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-bigjoiner:
    - shard-mtlp:         NOTRUN -> [SKIP][161] ([i915#16361])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_dsc@dsc-fractional-bpp-bigjoiner.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][162] ([i915#14544] / [i915#16361])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc-bigjoiner:
    - shard-tglu:         NOTRUN -> [SKIP][163] ([i915#16361]) +1 other test skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_dsc@dsc-with-bpc-bigjoiner.html

  * igt@kms_dsc@dsc-with-formats-ultrajoiner:
    - shard-rkl:          NOTRUN -> [SKIP][164] ([i915#16361]) +1 other test skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_dsc@dsc-with-formats-ultrajoiner.html

  * igt@kms_dsc@dsc-with-output-formats-ultrajoiner:
    - shard-dg1:          NOTRUN -> [SKIP][165] ([i915#16361])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_dsc@dsc-with-output-formats-ultrajoiner.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][166] ([i915#16361]) +2 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#16680])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_fbcon_fbt@psr.html
    - shard-tglu-1:       NOTRUN -> [SKIP][168] ([i915#16680])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_fbcon_fbt@psr.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-mtlp:         [PASS][169] -> [ABORT][170] ([i915#17026])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-4/igt@kms_fbcon_fbt@psr-suspend.html
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-5/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-tglu:         NOTRUN -> [SKIP][171] ([i915#16081]) +1 other test skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-tglu-1:       NOTRUN -> [SKIP][172] ([i915#16599])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@hdr:
    - shard-rkl:          [PASS][173] -> [SKIP][174] ([i915#16600])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_feature_discovery@hdr.html
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_feature_discovery@hdr.html
    - shard-mtlp:         NOTRUN -> [SKIP][175] ([i915#16600])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_feature_discovery@hdr.html

  * igt@kms_flip@2x-blocking-absolute-wf_vblank:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#14544] / [i915#9934])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_flip@2x-blocking-absolute-wf_vblank.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-tglu-1:       NOTRUN -> [SKIP][177] ([i915#3637] / [i915#9934]) +4 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-mtlp:         NOTRUN -> [SKIP][178] ([i915#3637] / [i915#9934]) +1 other test skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][179] ([i915#9934]) +2 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop:
    - shard-tglu:         NOTRUN -> [SKIP][180] ([i915#9934])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@kms_flip@2x-flip-vs-dpms-on-nop.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][181] -> [FAIL][182] ([i915#13027])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-rkl:          NOTRUN -> [SKIP][183] ([i915#9934]) +2 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-glk:          NOTRUN -> [INCOMPLETE][184] ([i915#12745] / [i915#4839])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk9/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][185] ([i915#12745])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk9/igt@kms_flip@2x-flip-vs-suspend-interruptible@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-plain-flip:
    - shard-tglu:         NOTRUN -> [SKIP][186] ([i915#3637] / [i915#9934]) +4 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][187] ([i915#12745] / [i915#4839])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk10/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][188] ([i915#12745])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk10/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-dg1:          NOTRUN -> [SKIP][189] ([i915#15643])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][190] ([i915#15643]) +3 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html
    - shard-tglu-1:       NOTRUN -> [SKIP][191] ([i915#15643]) +4 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][192] ([i915#15643]) +1 other test skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][193] +69 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][194] ([i915#14544] / [i915#1825]) +1 other test skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-rkl:          [PASS][195] -> [INCOMPLETE][196] ([i915#10056])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-suspend.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][197] ([i915#10056] / [i915#16593])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk3/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff:
    - shard-rkl:          [PASS][198] -> [SKIP][199] ([i915#15989]) +10 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][200] ([i915#15989]) +18 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][201] ([i915#15989]) +6 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][202] ([i915#15989]) +11 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff.html
    - shard-tglu-1:       NOTRUN -> [SKIP][203] ([i915#15989]) +17 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][204] ([i915#14544]) +11 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][205] +102 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][206] ([i915#1825]) +1 other test skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][207] ([i915#15990] / [i915#8708])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-move:
    - shard-tglu-1:       NOTRUN -> [SKIP][208] ([i915#15102]) +31 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][209] ([i915#14544] / [i915#15102]) +9 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][210] ([i915#15102]) +25 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte:
    - shard-dg1:          NOTRUN -> [SKIP][211] ([i915#15102]) +18 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-spr-indfb-onoff:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#15991])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-indfb-plflip-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][213] ([i915#15991]) +6 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-shrfb-scaledprimary:
    - shard-tglu:         NOTRUN -> [SKIP][214] ([i915#15102]) +43 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][215] ([i915#15990]) +2 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-fullscreen:
    - shard-glk:          [PASS][216] -> [SKIP][217] +10 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk8/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-fullscreen.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk2/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][218] ([i915#15990] / [i915#8708]) +10 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][219] ([i915#15991] / [i915#1825]) +3 other tests skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][220] ([i915#15990] / [i915#8708]) +1 other test skip
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][221] ([i915#15990]) +9 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-pgflip-blt:
    - shard-mtlp:         NOTRUN -> [SKIP][222] ([i915#15989]) +6 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-mtlp:         [PASS][223] -> [SKIP][224] ([i915#15725])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-4/igt@kms_hdmi_inject@inject-audio.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-1/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-rkl:          NOTRUN -> [SKIP][225] ([i915#16644] / [i915#3555] / [i915#8228])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@static-swap:
    - shard-tglu-1:       NOTRUN -> [SKIP][226] ([i915#3555] / [i915#8228])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle:
    - shard-tglu:         NOTRUN -> [SKIP][227] ([i915#3555] / [i915#8228]) +1 other test skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-dg1:          NOTRUN -> [SKIP][228] ([i915#3555] / [i915#8228])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][229] ([i915#15460]) +1 other test skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-2/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][230] ([i915#15459])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][231] ([i915#15458])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_joiner@basic-force-ultra-joiner.html
    - shard-tglu-1:       NOTRUN -> [SKIP][232] ([i915#15458])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-mtlp:         NOTRUN -> [SKIP][233] ([i915#13688])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-mtlp:         NOTRUN -> [SKIP][234] ([i915#15458])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_mst@mst-suspend-read-crc:
    - shard-tglu:         NOTRUN -> [SKIP][235] ([i915#16451])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_mst@mst-suspend-read-crc.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-mtlp:         NOTRUN -> [SKIP][236] ([i915#15815])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
    - shard-dg1:          NOTRUN -> [SKIP][237] ([i915#15709]) +1 other test skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping:
    - shard-rkl:          NOTRUN -> [SKIP][238] ([i915#15709]) +1 other test skip
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-tglu:         NOTRUN -> [SKIP][239] ([i915#15709]) +2 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier:
    - shard-mtlp:         NOTRUN -> [SKIP][240] ([i915#15709]) +1 other test skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
    - shard-tglu-1:       NOTRUN -> [SKIP][241] ([i915#15709]) +4 other tests skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html

  * igt@kms_plane_alpha_blend@alpha-basic:
    - shard-glk:          NOTRUN -> [FAIL][242] ([i915#12178])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk3/igt@kms_plane_alpha_blend@alpha-basic.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][243] ([i915#7862]) +1 other test fail
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk3/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk11:        NOTRUN -> [FAIL][244] ([i915#10647] / [i915#12169])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk11/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk11:        NOTRUN -> [FAIL][245] ([i915#10647]) +1 other test fail
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk11/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-tglu:         NOTRUN -> [SKIP][246] ([i915#13958])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][247] ([i915#13958])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-tglu-1:       NOTRUN -> [SKIP][248] ([i915#13958])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d:
    - shard-dg1:          NOTRUN -> [SKIP][249] ([i915#15329]) +9 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d.html
    - shard-tglu:         NOTRUN -> [SKIP][250] ([i915#15329]) +9 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a:
    - shard-mtlp:         NOTRUN -> [SKIP][251] ([i915#15329]) +3 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-75@pipe-a.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-tglu:         NOTRUN -> [SKIP][252] ([i915#12343] / [i915#9812])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-10/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][253] ([i915#12343] / [i915#5354])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          NOTRUN -> [SKIP][254] ([i915#3828])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_pm_dc@dc5-retention-flops.html
    - shard-tglu-1:       NOTRUN -> [SKIP][255] ([i915#3828]) +1 other test skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_rpm@cursor-dpms:
    - shard-mtlp:         NOTRUN -> [SKIP][256] ([i915#4077]) +2 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_pm_rpm@cursor-dpms.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][257] ([i915#15073])
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          [PASS][258] -> [SKIP][259] ([i915#15073]) +1 other test skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-6/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [PASS][260] -> [SKIP][261] ([i915#15073]) +1 other test skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-tglu-1:       NOTRUN -> [SKIP][262] ([i915#15073])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
    - shard-dg1:          [PASS][263] -> [SKIP][264] ([i915#15073]) +2 other tests skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg1-12/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_pm_rpm@package-g7:
    - shard-dg1:          NOTRUN -> [SKIP][265] ([i915#15403])
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_pm_rpm@package-g7.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-dg1:          NOTRUN -> [SKIP][266] ([i915#6524])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_prime@basic-crc-hybrid.html
    - shard-tglu:         NOTRUN -> [SKIP][267] ([i915#6524])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf:
    - shard-glk10:        NOTRUN -> [SKIP][268] ([i915#11520]) +3 other tests skip
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk10/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-tglu:         NOTRUN -> [SKIP][269] ([i915#11520]) +7 other tests skip
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-snb:          NOTRUN -> [SKIP][270] ([i915#11520]) +1 other test skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-snb1/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-glk11:        NOTRUN -> [SKIP][271] ([i915#11520]) +3 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk11/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          NOTRUN -> [SKIP][272] ([i915#11520]) +2 other tests skip
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][273] ([i915#9808]) +2 other tests skip
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][274] ([i915#12316]) +1 other test skip
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf:
    - shard-glk:          NOTRUN -> [SKIP][275] ([i915#11520]) +7 other tests skip
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk3/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-dg1:          NOTRUN -> [SKIP][276] ([i915#11520]) +3 other tests skip
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][277] ([i915#11520] / [i915#14544]) +2 other tests skip
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-tglu-1:       NOTRUN -> [SKIP][278] ([i915#11520]) +4 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr@fbc-pr-sprite-plane-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][279] ([i915#1072] / [i915#9732]) +9 other tests skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
    - shard-tglu-1:       NOTRUN -> [SKIP][280] ([i915#9732]) +16 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_psr@fbc-pr-sprite-plane-onoff.html

  * igt@kms_psr@fbc-psr-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][281] ([i915#1072] / [i915#14544] / [i915#9732]) +2 other tests skip
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_psr@fbc-psr-dpms.html

  * igt@kms_psr@fbc-psr2-dpms:
    - shard-mtlp:         NOTRUN -> [SKIP][282] ([i915#9688]) +4 other tests skip
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_psr@fbc-psr2-dpms.html

  * igt@kms_psr@pr-primary-page-flip:
    - shard-tglu:         NOTRUN -> [SKIP][283] ([i915#9732]) +17 other tests skip
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-8/igt@kms_psr@pr-primary-page-flip.html

  * igt@kms_psr@psr-cursor-render:
    - shard-dg1:          NOTRUN -> [SKIP][284] ([i915#1072] / [i915#9732]) +9 other tests skip
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@kms_psr@psr-cursor-render.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglu:         NOTRUN -> [SKIP][285] ([i915#15949])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][286] ([i915#15492] / [i915#16184])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk11/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-rkl:          NOTRUN -> [SKIP][287] ([i915#5289])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
    - shard-tglu-1:       NOTRUN -> [SKIP][288] ([i915#5289])
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-mtlp:         NOTRUN -> [SKIP][289] ([i915#12755] / [i915#15867])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-dg2:          NOTRUN -> [SKIP][290] ([i915#3555])
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-6/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-mtlp:         NOTRUN -> [SKIP][291] ([i915#3555] / [i915#8809])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][292] ([i915#12276]) +3 other tests incomplete
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk5/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_vblank@ts-continuation-modeset-hang:
    - shard-mtlp:         [PASS][293] -> [SKIP][294] ([i915#17031]) +28 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_vblank@ts-continuation-modeset-hang.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_vblank@ts-continuation-modeset-hang.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][295] ([i915#12276]) +1 other test incomplete
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_vrr@flip-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][296] ([i915#14544] / [i915#15243] / [i915#3555])
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@max-min:
    - shard-tglu-1:       NOTRUN -> [SKIP][297] ([i915#9906])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-1/igt@kms_vrr@max-min.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-tglu:         NOTRUN -> [SKIP][298] ([i915#9906])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-9/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-dg1:          NOTRUN -> [SKIP][299] ([i915#9906])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-dg1:          NOTRUN -> [SKIP][300] ([i915#2433])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@perf@per-context-mode-unprivileged.html

  * igt@perf_pmu@module-unload:
    - shard-tglu:         NOTRUN -> [ABORT][301] ([i915#15778])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-5/igt@perf_pmu@module-unload.html
    - shard-glk11:        NOTRUN -> [ABORT][302] ([i915#15778])
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk11/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@semaphore-wait-idle@vcs1:
    - shard-mtlp:         [PASS][303] -> [FAIL][304] ([i915#16855]) +6 other tests fail
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-4/igt@perf_pmu@semaphore-wait-idle@vcs1.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-1/igt@perf_pmu@semaphore-wait-idle@vcs1.html

  * igt@prime_udl@share-import-addfb:
    - shard-dg1:          NOTRUN -> [SKIP][305] ([i915#16420])
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@prime_udl@share-import-addfb.html

  * igt@prime_vgem@basic-write:
    - shard-dg1:          NOTRUN -> [SKIP][306] ([i915#3708])
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@coherency-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][307] ([i915#3708] / [i915#4077])
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-18/igt@prime_vgem@coherency-gtt.html

  * igt@prime_vgem@fence-read-hang:
    - shard-rkl:          NOTRUN -> [SKIP][308] ([i915#3708])
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@prime_vgem@fence-read-hang.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3:
    - shard-rkl:          [INCOMPLETE][309] ([i915#13356]) -> [PASS][310] +1 other test pass
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-4/igt@gem_ctx_isolation@preservation-s3.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-2/igt@gem_ctx_isolation@preservation-s3.html

  * igt@gem_mmap_offset@clear-via-pagefault:
    - shard-mtlp:         [INCOMPLETE][311] ([i915#16021] / [i915#16108] / [i915#16202]) -> [PASS][312] +1 other test pass
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@gem_mmap_offset@clear-via-pagefault.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@gem_mmap_offset@clear-via-pagefault.html

  * igt@gem_pxp@display-protected-crc:
    - shard-mtlp:         [FAIL][313] ([i915#17052]) -> [PASS][314]
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@gem_pxp@display-protected-crc.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@gem_pxp@display-protected-crc.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          [ABORT][315] ([i915#5566]) -> [PASS][316]
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk5/igt@gen9_exec_parse@allowed-single.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk3/igt@gen9_exec_parse@allowed-single.html

  * igt@i915_pm_rps@engine-order:
    - shard-glk:          [FAIL][317] ([i915#14896]) -> [PASS][318]
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk5/igt@i915_pm_rps@engine-order.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk5/igt@i915_pm_rps@engine-order.html

  * igt@i915_suspend@forcewake:
    - shard-rkl:          [INCOMPLETE][319] ([i915#4817]) -> [PASS][320]
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-3/igt@i915_suspend@forcewake.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-5/igt@i915_suspend@forcewake.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-hdmi-a-1:
    - shard-glk:          [FAIL][321] ([i915#14888]) -> [PASS][322]
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-hdmi-a-1.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk1/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         [FAIL][323] ([i915#15733] / [i915#5138]) -> [PASS][324]
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][325] ([i915#13027]) -> [PASS][326]
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-dg1:          [DMESG-WARN][327] ([i915#4423]) -> [PASS][328] +1 other test pass
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg1-16/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-17/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-blt:
    - shard-rkl:          [SKIP][329] ([i915#15989]) -> [PASS][330] +2 other tests pass
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-blt.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-indfb-msflip-blt:
    - shard-glk:          [SKIP][331] -> [PASS][332] +1 other test pass
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk2/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-indfb-msflip-blt.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk8/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_getfb@getfb2-into-addfb2:
    - shard-mtlp:         [SKIP][333] ([i915#17031]) -> [PASS][334] +39 other tests pass
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_getfb@getfb2-into-addfb2.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_getfb@getfb2-into-addfb2.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2:          [SKIP][335] ([i915#15073]) -> [PASS][336]
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg2-1/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@perf_pmu@gt-awake:
    - shard-mtlp:         [FAIL][337] -> [PASS][338]
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-5/igt@perf_pmu@gt-awake.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@perf_pmu@gt-awake.html

  
#### Warnings ####

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-rkl:          [SKIP][339] ([i915#14544] / [i915#9323]) -> [SKIP][340] ([i915#9323])
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@gem_ccs@block-multicopy-compressed.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_create@create-ext-set-pat:
    - shard-rkl:          [SKIP][341] ([i915#14544] / [i915#8562]) -> [SKIP][342] ([i915#8562])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@gem_create@create-ext-set-pat.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@gem_create@create-ext-set-pat.html

  * igt@gem_eio@kms:
    - shard-tglu:         [DMESG-WARN][343] ([i915#13363]) -> [ABORT][344] ([i915#13363])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-tglu-7/igt@gem_eio@kms.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-tglu-3/igt@gem_eio@kms.html

  * igt@gem_exec_reloc@basic-cpu-active:
    - shard-mtlp:         [SKIP][345] ([i915#3281]) -> [SKIP][346] ([i915#17031]) +1 other test skip
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@gem_exec_reloc@basic-cpu-active.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@gem_exec_reloc@basic-cpu-active.html

  * igt@gem_exec_reloc@basic-cpu-read:
    - shard-rkl:          [SKIP][347] ([i915#14544] / [i915#3281]) -> [SKIP][348] ([i915#3281]) +1 other test skip
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-read.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@gem_exec_reloc@basic-cpu-read.html

  * igt@gem_exec_reloc@basic-gtt-cpu-active:
    - shard-rkl:          [SKIP][349] ([i915#3281]) -> [SKIP][350] ([i915#14544] / [i915#3281])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@gem_exec_reloc@basic-gtt-cpu-active.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-cpu-active.html

  * igt@gem_exec_reloc@basic-wc-noreloc:
    - shard-mtlp:         [SKIP][351] ([i915#17031]) -> [SKIP][352] ([i915#3281]) +2 other tests skip
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@gem_exec_reloc@basic-wc-noreloc.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@gem_exec_reloc@basic-wc-noreloc.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-rkl:          [SKIP][353] ([i915#4613]) -> [SKIP][354] ([i915#14544] / [i915#4613])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@gem_lmem_swapping@heavy-verify-random.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@random:
    - shard-rkl:          [SKIP][355] ([i915#14544] / [i915#4613]) -> [SKIP][356] ([i915#4613]) +1 other test skip
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@gem_lmem_swapping@random.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@gem_lmem_swapping@random.html

  * igt@gem_madvise@dontneed-before-pwrite:
    - shard-rkl:          [SKIP][357] ([i915#14544] / [i915#3282]) -> [SKIP][358] ([i915#3282]) +2 other tests skip
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@gem_madvise@dontneed-before-pwrite.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@gem_madvise@dontneed-before-pwrite.html

  * igt@gem_softpin@evict-snoop:
    - shard-mtlp:         [SKIP][359] ([i915#17031]) -> [SKIP][360] ([i915#4885])
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@gem_softpin@evict-snoop.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@gem_softpin@evict-snoop.html

  * igt@gem_tiled_partial_pwrite_pread@reads:
    - shard-rkl:          [SKIP][361] ([i915#3282]) -> [SKIP][362] ([i915#14544] / [i915#3282])
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@gem_tiled_partial_pwrite_pread@reads.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@gem_tiled_partial_pwrite_pread@reads.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-rkl:          [SKIP][363] ([i915#2527]) -> [SKIP][364] ([i915#14544] / [i915#2527])
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@gen9_exec_parse@allowed-single.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-rkl:          [SKIP][365] ([i915#14544] / [i915#2527]) -> [SKIP][366] ([i915#2527]) +1 other test skip
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@gen9_exec_parse@bb-chained.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@gen9_exec_parse@bb-chained.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          [SKIP][367] ([i915#8399]) -> [SKIP][368] ([i915#14544] / [i915#8399])
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@i915_pm_freq_api@freq-suspend.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_sseu@full-enable:
    - shard-rkl:          [SKIP][369] ([i915#14544] / [i915#4387]) -> [SKIP][370] ([i915#4387])
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@i915_pm_sseu@full-enable.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@i915_pm_sseu@full-enable.html

  * igt@i915_suspend@sysfs-reader:
    - shard-rkl:          [INCOMPLETE][371] ([i915#4817]) -> [ABORT][372] ([i915#15140])
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@i915_suspend@sysfs-reader.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@i915_suspend@sysfs-reader.html

  * igt@intel_hwmon@hwmon-read:
    - shard-mtlp:         [SKIP][373] ([i915#17031]) -> [SKIP][374] ([i915#7707])
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@intel_hwmon@hwmon-read.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - shard-mtlp:         [SKIP][375] ([i915#4212]) -> [SKIP][376] ([i915#17031])
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_addfb_basic@tile-pitch-mismatch.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-mtlp:         [SKIP][377] ([i915#17031]) -> [SKIP][378] ([i915#3555])
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-rkl:          [SKIP][379] ([i915#14544] / [i915#5286]) -> [SKIP][380] ([i915#5286]) +1 other test skip
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_big_fb@4-tiled-addfb-size-overflow.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][381] ([i915#3638]) -> [SKIP][382] ([i915#14544] / [i915#3638])
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-mtlp:         [SKIP][383] ([i915#17031]) -> [SKIP][384] +4 other tests skip
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         [SKIP][385] -> [SKIP][386] ([i915#17031]) +2 other tests skip
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][387] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][388] ([i915#14098] / [i915#6095]) +9 other tests skip
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-2.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
    - shard-mtlp:         [SKIP][389] ([i915#6095]) -> [SKIP][390] ([i915#17031]) +2 other tests skip
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][391] ([i915#12313] / [i915#14544]) -> [SKIP][392] ([i915#12313])
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs:
    - shard-rkl:          [SKIP][393] ([i915#14098] / [i915#6095]) -> [SKIP][394] ([i915#14098] / [i915#14544] / [i915#6095])
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-mtlp:         [SKIP][395] ([i915#17031]) -> [SKIP][396] ([i915#6095]) +1 other test skip
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-mtlp:         [SKIP][397] ([i915#17031]) -> [SKIP][398] ([i915#12313])
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][399] ([i915#14544] / [i915#6095]) -> [SKIP][400] ([i915#6095]) +8 other tests skip
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_chamelium_audio@hdmi-audio-after-suspend:
    - shard-rkl:          [SKIP][401] ([i915#11151] / [i915#14544]) -> [SKIP][402] ([i915#11151])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_chamelium_audio@hdmi-audio-after-suspend.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_chamelium_audio@hdmi-audio-after-suspend.html

  * igt@kms_chamelium_audio@hdmi-audio-edid:
    - shard-mtlp:         [SKIP][403] ([i915#17031]) -> [SKIP][404] ([i915#11151] / [i915#7828]) +1 other test skip
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_chamelium_audio@hdmi-audio-edid.html
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_chamelium_audio@hdmi-audio-edid.html

  * igt@kms_chamelium_color_pipeline@plane-lut3d-green-only:
    - shard-mtlp:         [SKIP][405] ([i915#17031]) -> [SKIP][406] ([i915#16464] / [i915#16471])
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_chamelium_color_pipeline@plane-lut3d-green-only.html
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_chamelium_color_pipeline@plane-lut3d-green-only.html

  * igt@kms_chamelium_edid@vga-edid-read:
    - shard-rkl:          [SKIP][407] ([i915#11151] / [i915#7828]) -> [SKIP][408] ([i915#11151] / [i915#14544] / [i915#7828])
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_chamelium_edid@vga-edid-read.html
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_chamelium_edid@vga-edid-read.html

  * igt@kms_chamelium_hpd@dp-hpd-fast:
    - shard-rkl:          [SKIP][409] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][410] ([i915#11151] / [i915#7828]) +1 other test skip
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-fast.html
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_chamelium_hpd@dp-hpd-fast.html

  * igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode:
    - shard-mtlp:         [SKIP][411] ([i915#11151] / [i915#7828]) -> [SKIP][412] ([i915#17031]) +2 other tests skip
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_chamelium_hpd@hdmi-hpd-enable-disable-mode.html

  * igt@kms_content_protection@content-type-change:
    - shard-rkl:          [SKIP][413] ([i915#14544] / [i915#15865]) -> [SKIP][414] ([i915#15865])
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_content_protection@content-type-change.html
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@lic-type-0:
    - shard-mtlp:         [SKIP][415] ([i915#17031]) -> [SKIP][416] ([i915#15865])
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_content_protection@lic-type-0.html
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@lic-type-0-hdcp14:
    - shard-mtlp:         [SKIP][417] ([i915#15865]) -> [SKIP][418] ([i915#17031])
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_content_protection@lic-type-0-hdcp14.html
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_content_protection@lic-type-0-hdcp14.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-mtlp:         [SKIP][419] ([i915#13049]) -> [SKIP][420] ([i915#17031]) +1 other test skip
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_cursor_crc@cursor-onscreen-512x512.html
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-rkl:          [SKIP][421] ([i915#13049] / [i915#14544]) -> [SKIP][422] ([i915#13049])
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_cursor_crc@cursor-random-512x512.html
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x32:
    - shard-rkl:          [SKIP][423] ([i915#14544] / [i915#3555]) -> [SKIP][424] ([i915#3555]) +3 other tests skip
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-mtlp:         [SKIP][425] ([i915#17031]) -> [SKIP][426] ([i915#13049])
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-rkl:          [SKIP][427] ([i915#4103]) -> [SKIP][428] ([i915#14544] / [i915#4103])
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-mtlp:         [SKIP][429] ([i915#9809]) -> [SKIP][430] ([i915#17031]) +2 other tests skip
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-rkl:          [SKIP][431] ([i915#14544] / [i915#4103]) -> [SKIP][432] ([i915#4103])
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-mtlp:         [SKIP][433] ([i915#17031]) -> [SKIP][434] ([i915#16119] / [i915#4213])
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          [SKIP][435] ([i915#3555] / [i915#3804]) -> [SKIP][436] ([i915#14544] / [i915#3555] / [i915#3804])
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-rkl:          [SKIP][437] ([i915#14544] / [i915#16867]) -> [SKIP][438] ([i915#16867])
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-mtlp:         [SKIP][439] ([i915#13707]) -> [SKIP][440] ([i915#17031])
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-basic-ultrajoiner:
    - shard-mtlp:         [SKIP][441] ([i915#17031]) -> [SKIP][442] ([i915#16361]) +1 other test skip
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_dsc@dsc-basic-ultrajoiner.html
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_dsc@dsc-basic-ultrajoiner.html

  * igt@kms_dsc@dsc-with-output-formats-bigjoiner:
    - shard-mtlp:         [SKIP][443] ([i915#16361]) -> [SKIP][444] ([i915#17031])
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner:
    - shard-rkl:          [SKIP][445] ([i915#14544] / [i915#16361]) -> [SKIP][446] ([i915#16361]) +1 other test skip
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner.html
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner.html

  * igt@kms_feature_discovery@psr2:
    - shard-rkl:          [SKIP][447] ([i915#658]) -> [SKIP][448] ([i915#14544] / [i915#658])
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_feature_discovery@psr2.html
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
    - shard-mtlp:         [SKIP][449] ([i915#3637] / [i915#9934]) -> [SKIP][450] ([i915#17031]) +2 other tests skip
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-rkl:          [SKIP][451] ([i915#14544] / [i915#9934]) -> [SKIP][452] ([i915#9934]) +1 other test skip
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_flip@2x-flip-vs-dpms.html
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-rmfb:
    - shard-mtlp:         [SKIP][453] ([i915#17031]) -> [SKIP][454] ([i915#3637] / [i915#9934]) +1 other test skip
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_flip@2x-flip-vs-rmfb.html
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_flip@2x-flip-vs-rmfb.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-dg1:          [SKIP][455] ([i915#9934]) -> [SKIP][456] ([i915#4423] / [i915#9934])
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg1-15/igt@kms_flip@2x-flip-vs-suspend.html
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-19/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@flip-vs-fences-interruptible:
    - shard-mtlp:         [SKIP][457] ([i915#17031]) -> [SKIP][458] ([i915#8381])
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_flip@flip-vs-fences-interruptible.html
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_flip@flip-vs-fences-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-mtlp:         [SKIP][459] ([i915#15643]) -> [SKIP][460] ([i915#17031])
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-rkl:          [SKIP][461] ([i915#14544] / [i915#15643]) -> [SKIP][462] ([i915#15643])
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-rkl:          [SKIP][463] ([i915#15643]) -> [SKIP][464] ([i915#14544] / [i915#15643])
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-mtlp:         [SKIP][465] ([i915#17031]) -> [SKIP][466] ([i915#15643])
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-mtlp:         [SKIP][467] ([i915#15990] / [i915#8708]) -> [SKIP][468] ([i915#17031])
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-mtlp:         [SKIP][469] ([i915#17031]) -> [SKIP][470] ([i915#15990] / [i915#8708]) +4 other tests skip
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu:
    - shard-mtlp:         [SKIP][471] ([i915#17031]) -> [SKIP][472] ([i915#15991] / [i915#1825]) +5 other tests skip
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu.html
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         [SKIP][473] ([i915#15990]) -> [SKIP][474] ([i915#17031]) +4 other tests skip
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-shrfb-pgflip-blt:
    - shard-rkl:          [SKIP][475] ([i915#14544]) -> [SKIP][476] +30 other tests skip
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-shrfb-pgflip-blt.html
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
    - shard-rkl:          [SKIP][477] -> [SKIP][478] ([i915#14544]) +10 other tests skip
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-rkl:          [SKIP][479] ([i915#14544] / [i915#5439]) -> [SKIP][480] ([i915#5439])
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-rkl:          [SKIP][481] ([i915#15102]) -> [SKIP][482] ([i915#14544] / [i915#15102]) +5 other tests skip
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-pri-indfb-draw-pwrite.html
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-shrfb-draw-blt:
    - shard-mtlp:         [SKIP][483] ([i915#17031]) -> [SKIP][484] ([i915#15991]) +12 other tests skip
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-shrfb-draw-blt.html
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-mmap-gtt:
    - shard-mtlp:         [SKIP][485] ([i915#17031]) -> [SKIP][486] ([i915#15990]) +3 other tests skip
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-mmap-gtt.html
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-suspend:
    - shard-mtlp:         [SKIP][487] ([i915#17031]) -> [SKIP][488] ([i915#15989]) +9 other tests skip
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_frontbuffer_tracking@hdr-suspend.html
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_frontbuffer_tracking@hdr-suspend.html
    - shard-glk:          [SKIP][489] -> [INCOMPLETE][490] ([i915#16056] / [i915#16593])
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk3/igt@kms_frontbuffer_tracking@hdr-suspend.html
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk8/igt@kms_frontbuffer_tracking@hdr-suspend.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][491] ([i915#14544] / [i915#15102]) -> [SKIP][492] ([i915#15102]) +16 other tests skip
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-mtlp:         [SKIP][493] ([i915#15991] / [i915#1825]) -> [SKIP][494] ([i915#17031]) +6 other tests skip
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
    - shard-dg1:          [SKIP][495] ([i915#15990] / [i915#4423] / [i915#8708]) -> [SKIP][496] ([i915#15990] / [i915#8708])
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-draw-blt:
    - shard-mtlp:         [SKIP][497] ([i915#15989]) -> [SKIP][498] ([i915#17031]) +9 other tests skip
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-draw-blt.html
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-dg1:          [SKIP][499] ([i915#15990]) -> [SKIP][500] ([i915#15990] / [i915#4423])
   [499]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg1-15/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
   [500]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-17/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-pri-indfb-draw-mmap-cpu:
    - shard-mtlp:         [SKIP][501] ([i915#15991]) -> [SKIP][502] ([i915#17031]) +5 other tests skip
   [501]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-pri-indfb-draw-mmap-cpu.html
   [502]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-mtlp:         [SKIP][503] ([i915#12713] / [i915#16490]) -> [SKIP][504] ([i915#17031])
   [503]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_hdr@brightness-with-hdr.html
   [504]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-rkl:          [SKIP][505] ([i915#13688] / [i915#14544]) -> [SKIP][506] ([i915#13688])
   [505]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_joiner@basic-max-non-joiner.html
   [506]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-mtlp:         [SKIP][507] ([i915#15458]) -> [SKIP][508] ([i915#17031])
   [507]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_joiner@basic-ultra-joiner.html
   [508]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-rkl:          [SKIP][509] ([i915#14544] / [i915#15458]) -> [SKIP][510] ([i915#15458])
   [509]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
   [510]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][511] ([i915#14544] / [i915#15815]) -> [SKIP][512] ([i915#15815])
   [511]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [512]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-glk:          [DMESG-FAIL][513] ([i915#118]) -> [DMESG-WARN][514] ([i915#118])
   [513]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-glk5/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
   [514]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-glk5/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping:
    - shard-dg1:          [SKIP][515] ([i915#15709] / [i915#4423]) -> [SKIP][516] ([i915#15709])
   [515]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg1-18/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping.html
   [516]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-12/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier:
    - shard-rkl:          [SKIP][517] ([i915#14544] / [i915#15709]) -> [SKIP][518] ([i915#15709])
   [517]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html
   [518]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping:
    - shard-mtlp:         [SKIP][519] ([i915#15709]) -> [SKIP][520] ([i915#17031]) +1 other test skip
   [519]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html
   [520]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-mtlp:         [SKIP][521] ([i915#17031]) -> [SKIP][522] ([i915#15709])
   [521]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
   [522]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping:
    - shard-rkl:          [SKIP][523] ([i915#15709]) -> [SKIP][524] ([i915#14544] / [i915#15709])
   [523]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html
   [524]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping.html

  * igt@kms_plane_lowres@tiling-none:
    - shard-mtlp:         [SKIP][525] ([i915#11614] / [i915#3582]) -> [SKIP][526] ([i915#17031])
   [525]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_plane_lowres@tiling-none.html
   [526]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_plane_lowres@tiling-none.html

  * igt@kms_plane_multiple@2x-tiling-y:
    - shard-rkl:          [SKIP][527] ([i915#13958] / [i915#14544]) -> [SKIP][528] ([i915#13958])
   [527]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-y.html
   [528]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_plane_multiple@2x-tiling-y.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75:
    - shard-mtlp:         [SKIP][529] ([i915#17031]) -> [SKIP][530] ([i915#15329] / [i915#3555] / [i915#6953])
   [529]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_plane_scaling@planes-downscale-factor-0-75.html
   [530]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_plane_scaling@planes-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
    - shard-mtlp:         [SKIP][531] ([i915#15329] / [i915#3555] / [i915#6953]) -> [SKIP][532] ([i915#17031])
   [531]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html
   [532]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg1:          [SKIP][533] ([i915#9340]) -> [SKIP][534] ([i915#3828])
   [533]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg1-12/igt@kms_pm_lpsp@kms-lpsp.html
   [534]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-14/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-mtlp:         [SKIP][535] ([i915#17031]) -> [SKIP][536] ([i915#9808])
   [535]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html
   [536]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-mtlp:         [SKIP][537] ([i915#12316]) -> [SKIP][538] ([i915#17031])
   [537]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html
   [538]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-rkl:          [SKIP][539] ([i915#11520] / [i915#14544]) -> [SKIP][540] ([i915#11520]) +2 other tests skip
   [539]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
   [540]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf:
    - shard-dg1:          [SKIP][541] ([i915#11520]) -> [SKIP][542] ([i915#11520] / [i915#4423])
   [541]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-dg1-15/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html
   [542]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-dg1-17/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-psr-no-drrs:
    - shard-mtlp:         [SKIP][543] ([i915#9688]) -> [SKIP][544] ([i915#17031]) +1 other test skip
   [543]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_psr@fbc-psr-no-drrs.html
   [544]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_psr@fbc-psr-no-drrs.html

  * igt@kms_psr@fbc-psr2-primary-mmap-cpu:
    - shard-mtlp:         [SKIP][545] ([i915#17031]) -> [SKIP][546] ([i915#9688]) +2 other tests skip
   [545]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_psr@fbc-psr2-primary-mmap-cpu.html
   [546]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-8/igt@kms_psr@fbc-psr2-primary-mmap-cpu.html

  * igt@kms_psr@psr2-cursor-mmap-gtt:
    - shard-rkl:          [SKIP][547] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][548] ([i915#1072] / [i915#9732]) +7 other tests skip
   [547]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_psr@psr2-cursor-mmap-gtt.html
   [548]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-1/igt@kms_psr@psr2-cursor-mmap-gtt.html

  * igt@kms_psr@psr2-sprite-mmap-cpu:
    - shard-rkl:          [SKIP][549] ([i915#1072] / [i915#9732]) -> [SKIP][550] ([i915#1072] / [i915#14544] / [i915#9732]) +2 other tests skip
   [549]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_psr@psr2-sprite-mmap-cpu.html
   [550]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_psr@psr2-sprite-mmap-cpu.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-rkl:          [SKIP][551] ([i915#14544] / [i915#5289]) -> [SKIP][552] ([i915#5289]) +2 other tests skip
   [551]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [552]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-4/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-mtlp:         [SKIP][553] ([i915#17031]) -> [SKIP][554] ([i915#8623])
   [553]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-7/igt@kms_tiled_display@basic-test-pattern.html
   [554]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-6/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-mtlp:         [SKIP][555] ([i915#8808] / [i915#9906]) -> [SKIP][556] ([i915#17031])
   [555]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-mtlp-8/igt@kms_vrr@flip-basic-fastset.html
   [556]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-mtlp-7/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@flipline:
    - shard-rkl:          [SKIP][557] ([i915#15243] / [i915#3555]) -> [SKIP][558] ([i915#14544] / [i915#15243] / [i915#3555])
   [557]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19152/shard-rkl-8/igt@kms_vrr@flipline.html
   [558]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/shard-rkl-6/igt@kms_vrr@flipline.html

  
  [i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11614]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11614
  [i915#118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/118
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12178]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12178
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13196
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13363]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13363
  [i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
  [i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#14123]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14123
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
  [i915#14694]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14694
  [i915#14888]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14888
  [i915#14896]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14896
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15140]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15140
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15403]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15403
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15492]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15492
  [i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15678]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15678
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15725]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15725
  [i915#15733]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15733
  [i915#15778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15778
  [i915#15804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15804
  [i915#15815]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15815
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15867
  [i915#15949]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15949
  [i915#15989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15989
  [i915#15990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15990
  [i915#15991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15991
  [i915#16021]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16021
  [i915#16056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16056
  [i915#16079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16079
  [i915#16081]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16081
  [i915#16108]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16108
  [i915#16109]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16109
  [i915#16119]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16119
  [i915#16184]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16184
  [i915#16202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16202
  [i915#16348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16348
  [i915#16361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16361
  [i915#16420]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16420
  [i915#16451]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16451
  [i915#16464]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16464
  [i915#16471]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16471
  [i915#16490]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16490
  [i915#16593]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16593
  [i915#16599]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16599
  [i915#16600]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16600
  [i915#16604]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16604
  [i915#16644]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16644
  [i915#16680]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16680
  [i915#16855]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16855
  [i915#16867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16867
  [i915#16870]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16870
  [i915#16904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16904
  [i915#16990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16990
  [i915#17016]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17016
  [i915#17026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17026
  [i915#17031]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17031
  [i915#17048]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17048
  [i915#17052]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/17052
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3582
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#4036]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4036
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7862]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7862
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8437
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8808
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_19152 -> Patchwork_156417v6

  CI-20190529: 20190529
  CI_DRM_19152: 0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9098: 9098
  Patchwork_156417v6: 0fb8d1900f1a6b9d21aadbfa5f784979b950bcf8 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_156417v6/index.html

[-- Attachment #2: Type: text/html, Size: 190277 bytes --]

Re: [PATCH v6 02/18] drm/i915/alpm: Move alpm sink capability readout into a separate function

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Abstract ALPM DPCD initialization into its own function.
> 
> v2:
> - Improve commit description. [Suraj, Jouni]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c   |  6 +-----
>  3 files changed, 13 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 10943539bc7c..a6743fe62d48 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -43,6 +43,17 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp
> *intel_dp,
>  		(crtc_state->has_lobf &&
> intel_alpm_aux_less_wake_supported(intel_dp));
>  }
>  
> +bool intel_alpm_init_dpcd(struct intel_dp *intel_dp)
> +{
> +	u8 dpcd;
> +
> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
> +		return false;
> +
> +	intel_dp->alpm_dpcd = dpcd;
> +	return true;
> +}
> +
>  void intel_alpm_init(struct intel_dp *intel_dp)
>  {
>  	mutex_init(&intel_dp->alpm.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index f8f605d94f96..56c3e1482e37 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -15,6 +15,7 @@ struct intel_connector;
>  struct intel_atomic_state;
>  struct intel_crtc;
>  
> +bool intel_alpm_init_dpcd(struct intel_dp *intel_dp);
>  void intel_alpm_init(struct intel_dp *intel_dp);
>  bool intel_alpm_compute_params(struct intel_dp *intel_dp,
>  			       struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0cd5e6b5034c..650c8b39270b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4783,7 +4783,6 @@ static bool
>  intel_edp_init_dpcd(struct intel_dp *intel_dp, struct
> intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> -	int ret;
>  	u8 dprx;
>  
>  	/* this function is meant to be called only once */
> @@ -4829,10 +4828,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp,
> struct intel_connector *connector
>  	 */
>  	intel_dp_init_source_oui(intel_dp);
>  
> -	/* Read the ALPM DPCD caps */
> -	ret = drm_dp_dpcd_read_byte(&intel_dp->aux,
> DP_RECEIVER_ALPM_CAP,
> -				    &intel_dp->alpm_dpcd);
> -	if (ret < 0)
> +	if (!intel_alpm_init_dpcd(intel_dp))
>  		return false;
>  
>  	/*

Re: [PATCH v6 02/18] drm/i915/alpm: Move alpm sink capability readout into a separate function

[Hogander, Jouni]

On Mon, 2026-09-28 at 12:58 +0300, Hogander, Jouni wrote:
> On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> > Abstract ALPM DPCD initialization into its own function.
> > 
> > v2:
> > - Improve commit description. [Suraj, Jouni]

Small note here. It is not just commit description that changed. Also
error value of intel_alpm_init_dpcd is handled and there is early exit
in intel_edp_init_dpcd.

BR,
Jouni Högander
> > 
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> 
> Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c | 11 +++++++++++
> >  drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
> >  drivers/gpu/drm/i915/display/intel_dp.c   |  6 +-----
> >  3 files changed, 13 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 10943539bc7c..a6743fe62d48 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -43,6 +43,17 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp
> > *intel_dp,
> >  		(crtc_state->has_lobf &&
> > intel_alpm_aux_less_wake_supported(intel_dp));
> >  }
> >  
> > +bool intel_alpm_init_dpcd(struct intel_dp *intel_dp)
> > +{
> > +	u8 dpcd;
> > +
> > +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
> > +		return false;
> > +
> > +	intel_dp->alpm_dpcd = dpcd;
> > +	return true;
> > +}
> > +
> >  void intel_alpm_init(struct intel_dp *intel_dp)
> >  {
> >  	mutex_init(&intel_dp->alpm.lock);
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index f8f605d94f96..56c3e1482e37 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -15,6 +15,7 @@ struct intel_connector;
> >  struct intel_atomic_state;
> >  struct intel_crtc;
> >  
> > +bool intel_alpm_init_dpcd(struct intel_dp *intel_dp);
> >  void intel_alpm_init(struct intel_dp *intel_dp);
> >  bool intel_alpm_compute_params(struct intel_dp *intel_dp,
> >  			       struct intel_crtc_state
> > *crtc_state);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0cd5e6b5034c..650c8b39270b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4783,7 +4783,6 @@ static bool
> >  intel_edp_init_dpcd(struct intel_dp *intel_dp, struct
> > intel_connector *connector)
> >  {
> >  	struct intel_display *display =
> > to_intel_display(intel_dp);
> > -	int ret;
> >  	u8 dprx;
> >  
> >  	/* this function is meant to be called only once */
> > @@ -4829,10 +4828,7 @@ intel_edp_init_dpcd(struct intel_dp
> > *intel_dp,
> > struct intel_connector *connector
> >  	 */
> >  	intel_dp_init_source_oui(intel_dp);
> >  
> > -	/* Read the ALPM DPCD caps */
> > -	ret = drm_dp_dpcd_read_byte(&intel_dp->aux,
> > DP_RECEIVER_ALPM_CAP,
> > -				    &intel_dp->alpm_dpcd);
> > -	if (ret < 0)
> > +	if (!intel_alpm_init_dpcd(intel_dp))
> >  		return false;
> >  
> >  	/*
> 

Re: [PATCH v6 03/18] drm/i915/alpm: alpm_init() for DP2.1

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Initialize ALPM for DP2.1 and separate out ALPM mutex-init
> from alpm-init.
> 
> v2: Separate out mutex-init. [Jani]
> v3: Refactor further to avoid DISPLAY_VER check in multiple places.
> [Jani]
> v4: Cosmetic changes. [Suraj]
> v5: Reset alpm_dpcd and simplify source-supported check.
> v6: Drop display-version check for eDP for backward compatible.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 9 +++++++++
>  drivers/gpu/drm/i915/display/intel_alpm.h | 1 +
>  drivers/gpu/drm/i915/display/intel_dp.c   | 9 +++++++--
>  3 files changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index a6743fe62d48..4801fc6bade2 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -43,6 +43,15 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp
> *intel_dp,
>  		(crtc_state->has_lobf &&
> intel_alpm_aux_less_wake_supported(intel_dp));
>  }
>  
> +bool intel_alpm_source_supported(struct intel_connector *connector)
> +{
> +	struct intel_display *display = to_intel_display(connector);
> +
> +	return (connector->base.connector_type ==
> DRM_MODE_CONNECTOR_DisplayPort &&
> +		DISPLAY_VER(display) >= 35) ||
> +	        connector->base.connector_type ==
> DRM_MODE_CONNECTOR_eDP;
> +}
> +
>  bool intel_alpm_init_dpcd(struct intel_dp *intel_dp)
>  {
>  	u8 dpcd;
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 56c3e1482e37..9a02fa386ee3 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -15,6 +15,7 @@ struct intel_connector;
>  struct intel_atomic_state;
>  struct intel_crtc;
>  
> +bool intel_alpm_source_supported(struct intel_connector *connector);
>  bool intel_alpm_init_dpcd(struct intel_dp *intel_dp);
>  void intel_alpm_init(struct intel_dp *intel_dp);
>  bool intel_alpm_compute_params(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 650c8b39270b..b4742bd33cb4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6354,6 +6354,7 @@ intel_dp_detect(struct drm_connector
> *_connector,
>  		connector->dp.panel_replay_caps.su_support = false;
>  		connector->dp.panel_replay_caps.dsc_support =
>  			INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
> +		intel_dp->alpm_dpcd = 0;
>  
>  		intel_dp_mst_disconnect(intel_dp);
>  
> @@ -6376,6 +6377,9 @@ intel_dp_detect(struct drm_connector
> *_connector,
>  	if (ret == 1)
>  		connector->base.epoch_counter++;
>  
> +	if (intel_alpm_source_supported(connector))
> +		intel_alpm_init_dpcd(intel_dp);

This is done already for eDP. You could make it conditional to
!intel_dp_is edp.

I also found it a bit confusing why alpm_init_dpcd is conditional to
intel_alpm_source_supported in case of DP but not in case of eDP. How
about moving intel_alpm_source_supported in intel_alpm_init/_dpcd?

BR,
Jouni Högander

> +
>  	if (!intel_dp_is_edp(intel_dp))
>  		intel_psr_init_dpcd(intel_dp, connector);
>  
> @@ -7019,8 +7023,6 @@ static bool intel_edp_init_connector(struct
> intel_dp *intel_dp,
>  	 */
>  	intel_hpd_enable_detection(encoder);
>  
> -	intel_alpm_init(intel_dp);
> -
>  	/* Cache DPCD and EDID for edp. */
>  	has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
>  
> @@ -7235,6 +7237,9 @@ intel_dp_init_connector(struct
> intel_digital_port *dig_port,
>  
>  	intel_psr_init(intel_dp);
>  
> +	if (intel_alpm_source_supported(connector))
> +		intel_alpm_init(intel_dp);
> +
>  	return true;
>  
>  fail:

Re: [PATCH v6 04/18] drm/i915/alpm: Enable debugfs for DP2.1

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Enable ALPM debug info through lobf debug info.
> 
> v2: cosmetic change. [Suraj]
> v3: Use common api instead of DISPLAY_VER check in multiple places.
> [Jani]
> v4: Add display-version check as it dropped for EDP.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 4801fc6bade2..901493bb1448 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -739,8 +739,10 @@ void intel_alpm_lobf_debugfs_add(struct
> intel_connector *connector)
>  	struct intel_display *display = to_intel_display(connector);
>  	struct dentry *root = connector->base.debugfs_entry;
>  
> -	if (DISPLAY_VER(display) < 20 ||
> -	    connector->base.connector_type !=
> DRM_MODE_CONNECTOR_eDP)
> +	if (DISPLAY_VER(display) < 20)
> +		return;
> +
> +	if (!intel_alpm_source_supported(connector))
>  		return;
>  
>  	debugfs_create_file("i915_edp_lobf_debug", 0644, root,

These are named as i915_edp_lobf_debug even if they are created on DP
connector.

BR,
Jouni Högander

Re: [PATCH v6 05/18] drm/i915/alpm: Refactor Auxless wake time calculation

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Divide the auxless wake time calculation in parts which will
> help later to add Xe3p related modification.
> 
> v2: Refactor first existing calculation. [Jani]
> v3: Cosmetic changes. [Jani, Suraj]
> 
> Bspec: 71477
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 31 ++++++++++++++++-----
> --
>  1 file changed, 22 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 901493bb1448..d5823174576a 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -102,6 +102,25 @@ static int get_lfps_half_cycle_clocks(const
> struct intel_crtc_state *crtc_state)
>  		1000 / (2 * LFPS_CYCLE_COUNT);
>  }
>  
> +static int get_tphy2_p2_to_p0(const struct intel_crtc_state
> *crtc_state)
> +{
> +	return 12 * 1000;
> +}
> +
> +static int get_establishment_period(const struct intel_crtc_state
> *crtc_state)
> +{
> +	int t1 = 50 * 1000;
> +	int tps4 = 252;
> +	/* port_clock is link rate in 10kbit/s units */
> +	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state-
> >port_clock;
> +	int tcds, establishment_period;
> +
> +	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) *
> tml_phy_lock;
> +	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);

Here you could return SILENCE_PERIOD_TIME + t1 + tcds.

> +
> +	return establishment_period;
> +}
> +
>  /*
>   * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period,
> Max+
>   * tSilence, Max+ tPHY Establishment + tCDS) / tline)
> @@ -123,17 +142,11 @@ static int get_lfps_half_cycle_clocks(const
> struct intel_crtc_state *crtc_state)
>   */
>  static int _lnl_compute_aux_less_wake_time(const struct
> intel_crtc_state *crtc_state)
>  {
> -	int tphy2_p2_to_p0 = 12 * 1000;
> -	int t1 = 50 * 1000;
> -	int tps4 = 252;
> -	/* port_clock is link rate in 10kbit/s units */
> -	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state-
> >port_clock;
> -	int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) +
> 1;

I think you should keep num_ml_phy_lock also in your helper. Just to
keep readability. Also in patch 6 you will have then:

if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
	num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1;
} else {
...
	num_ml_phy_lock = 7;
...

tcds = num_ml_phy_lock * tml_phy_lock;

BR,
Jouni Högander

> -	int t2 = num_ml_phy_lock * tml_phy_lock;
> -	int tcds = 1 * t2;
> +	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
> +	int establishment_period =
> get_establishment_period(crtc_state);
>  
>  	return DIV_ROUND_UP(tphy2_p2_to_p0 +
> get_lfps_cycle_time(crtc_state) +
> -			    SILENCE_PERIOD_TIME + t1 + tcds, 1000);
> +			    establishment_period, 1000);
>  }
>  
>  static int

Re: [PATCH v6 06/18] drm/i915/alpm: Auxless wake time calculation for Xe3p

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Add support for auxless waketime calculation for DP2.1 ALPM
> as dependent parameter got changed.
> 
> v1: Initial version.
> v2: Use intel_dp_is_uhbr(). [Jani]
> v3:
> - Separate out switch to active latency calculation.
> - Use macro definition for ML_PHY_LOCK length. [Suraj]
> v4:
> - Fix 32-bit signed integer overflow. [sashiko]
> - Fix negative return of drm_dp_lttpr_count(). [sashiko]
> - Introduce get_ml_phy_lock_len() and get_dp_link_symbol_size().
> [Jouni]

My comment was referring existing intel_dp.c:intel_dp_link_symbol_size

> - Align variable naming with bpec formula of establishment_period.
> [Jouni]
> 
> Bspec: 71477
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 69 +++++++++++++++++++--
> --
>  1 file changed, 58 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index d5823174576a..924fa8dd4638 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -102,21 +102,64 @@ static int get_lfps_half_cycle_clocks(const
> struct intel_crtc_state *crtc_state)
>  		1000 / (2 * LFPS_CYCLE_COUNT);
>  }
>  
> +#define ML_PHY_LOCK_LEN		252
> +#define ML_PHY_LOCK_LEN_UHBR	396
> +
>  static int get_tphy2_p2_to_p0(const struct intel_crtc_state
> *crtc_state)
>  {
> -	return 12 * 1000;
> +	struct intel_display *display =
> to_intel_display(crtc_state);
> +
> +	return DISPLAY_VER(display) >= 35 ? (20 * 1000) : (12 *
> 1000);

This should actually use HAS_LT_PHY().

> +}
> +
> +static int get_ml_phy_lock_len(const struct intel_crtc_state
> *crtc_state)
> +{
> +	return intel_dp_is_uhbr(crtc_state) ? ML_PHY_LOCK_LEN_UHBR :
> ML_PHY_LOCK_LEN;
> +}
> +
> +static int get_dp_link_symbol_size(const struct intel_crtc_state
> *crtc_state)
> +{
> +	return intel_dp_is_uhbr(crtc_state) ? 32 : 10;
>  }

This is duplicate of intel_dp_link_symbol_size.

>  
> -static int get_establishment_period(const struct intel_crtc_state
> *crtc_state)
> +static int get_establishment_period(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state
> *crtc_state)
>  {
>  	int t1 = 50 * 1000;
> -	int tps4 = 252;
> -	/* port_clock is link rate in 10kbit/s units */
> -	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state-
> >port_clock;
> +	int tps4 = get_ml_phy_lock_len(crtc_state) *
> get_dp_link_symbol_size(crtc_state);
> +	/*
> +	 * port_clock is link rate in 10kbit/s units, so multiplying
> by
> +	 * (1000 * 1000)/10 = 100000
> +	 */
> +	int tml_phy_lock = 100000 * tps4 / crtc_state->port_clock;

tml_phy_lock:

For 8b/10b: 
252 Symbol clocks * ( 10 / (Link Rate in Mbps) )

For 128b/132b:
396 Super Symbol clocks * ( 32/ (Link Rate in Mbps) )

In comment you should have:
* (10000 * 10000)/intel_dp_link_symbol_size()

> +	int lttpr_count = 0;
>  	int tcds, establishment_period;
>  
> -	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) *
> tml_phy_lock;
> -	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) *
> tml_phy_lock;
> +	} else {
> +		tcds = 7 * tml_phy_lock;
> +		lttpr_count = drm_dp_lttpr_count(intel_dp-
> >lttpr_common_caps);
> +	}
> +
> +	if (lttpr_count > 0) {
> +		/* tlw and tcs values are taken from DP2.1 spec */
> +		int tlw = 13000;
> +		int tcs = 10000;
> +		int tlfps_period = get_lfps_cycle_time(crtc_state);
> +		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
> +			    (lttpr_count - 1) * (tlw +
> tlfps_period));
> +		int tacds = 70000;
> +		int tds = 7 * tml_phy_lock;
> +
> +		/* tdrl is same as tcds*/
> +		establishment_period = tlw + tlfps_period + tdcs +
> tacds +
> +				       (lttpr_count - 1) * tds +
> tcds;
> +	} else {
> +		/* TODO: Add a check for data realign by DPCD
> 0x116[3] */
> +
> +		establishment_period = (SILENCE_PERIOD_TIME + t1 +
> tcds);
> +	}
>  
>  	return establishment_period;
>  }
> @@ -138,12 +181,16 @@ static int get_establishment_period(const
> struct intel_crtc_state *crtc_state)
>   * within the CDS period complete within the CDS period regardless
> of
>   * entry into the period
>   * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )

Here also switch 10 as Rate Div.

BR,
Jouni Högander

> - * TPS4 Length = 252 Symbols
> + * ML_PHY_LOCK Length (8b/10b): 252
> + * ML_PHY_LOCK Length (128b/132b): 396
> + * TPS4 Length = ML_PHY_LOCK * Rate Div
> + * Rate Div = 32 for 128b/132b and 10 for 8b/10b.
>   */
> -static int _lnl_compute_aux_less_wake_time(const struct
> intel_crtc_state *crtc_state)
> +static int _lnl_compute_aux_less_wake_time(struct intel_dp
> *intel_dp,
> +					   const struct
> intel_crtc_state *crtc_state)
>  {
>  	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
> -	int establishment_period =
> get_establishment_period(crtc_state);
> +	int establishment_period =
> get_establishment_period(intel_dp, crtc_state);
>  
>  	return DIV_ROUND_UP(tphy2_p2_to_p0 +
> get_lfps_cycle_time(crtc_state) +
>  			    establishment_period, 1000);
> @@ -158,7 +205,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp
> *intel_dp,
>  		lfps_half_cycle;
>  
>  	aux_less_wake_time =
> -		_lnl_compute_aux_less_wake_time(crtc_state);
> +		_lnl_compute_aux_less_wake_time(intel_dp,
> crtc_state);
>  	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state-
> >hw.adjusted_mode,
>  						      
> aux_less_wake_time);
>  	silence_period = get_silence_period_symbols(crtc_state);

Re: [PATCH v6 06/18] drm/i915/alpm: Auxless wake time calculation for Xe3p

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Add support for auxless waketime calculation for DP2.1 ALPM
> as dependent parameter got changed.
> 
> v1: Initial version.
> v2: Use intel_dp_is_uhbr(). [Jani]
> v3:
> - Separate out switch to active latency calculation.
> - Use macro definition for ML_PHY_LOCK length. [Suraj]
> v4:
> - Fix 32-bit signed integer overflow. [sashiko]
> - Fix negative return of drm_dp_lttpr_count(). [sashiko]
> - Introduce get_ml_phy_lock_len() and get_dp_link_symbol_size().
> [Jouni]
> - Align variable naming with bpec formula of establishment_period.
> [Jouni]
> 
> Bspec: 71477
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 69 +++++++++++++++++++--
> --
>  1 file changed, 58 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index d5823174576a..924fa8dd4638 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -102,21 +102,64 @@ static int get_lfps_half_cycle_clocks(const
> struct intel_crtc_state *crtc_state)
>  		1000 / (2 * LFPS_CYCLE_COUNT);
>  }
>  
> +#define ML_PHY_LOCK_LEN		252
> +#define ML_PHY_LOCK_LEN_UHBR	396
> +
>  static int get_tphy2_p2_to_p0(const struct intel_crtc_state
> *crtc_state)
>  {
> -	return 12 * 1000;
> +	struct intel_display *display =
> to_intel_display(crtc_state);
> +
> +	return DISPLAY_VER(display) >= 35 ? (20 * 1000) : (12 *
> 1000);
> +}
> +
> +static int get_ml_phy_lock_len(const struct intel_crtc_state
> *crtc_state)
> +{
> +	return intel_dp_is_uhbr(crtc_state) ? ML_PHY_LOCK_LEN_UHBR :
> ML_PHY_LOCK_LEN;
> +}
> +
> +static int get_dp_link_symbol_size(const struct intel_crtc_state
> *crtc_state)
> +{
> +	return intel_dp_is_uhbr(crtc_state) ? 32 : 10;
>  }
>  
> -static int get_establishment_period(const struct intel_crtc_state
> *crtc_state)
> +static int get_establishment_period(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state
> *crtc_state)
>  {
>  	int t1 = 50 * 1000;
> -	int tps4 = 252;
> -	/* port_clock is link rate in 10kbit/s units */
> -	int tml_phy_lock = 1000 * 1000 * tps4 / crtc_state-
> >port_clock;
> +	int tps4 = get_ml_phy_lock_len(crtc_state) *
> get_dp_link_symbol_size(crtc_state);
> +	/*
> +	 * port_clock is link rate in 10kbit/s units, so multiplying
> by
> +	 * (1000 * 1000)/10 = 100000
> +	 */
> +	int tml_phy_lock = 100000 * tps4 / crtc_state->port_clock;
> +	int lttpr_count = 0;
>  	int tcds, establishment_period;
>  
> -	tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) *
> tml_phy_lock;
> -	establishment_period = (SILENCE_PERIOD_TIME + t1 + tcds);
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) *
> tml_phy_lock;
> +	} else {
> +		tcds = 7 * tml_phy_lock;
> +		lttpr_count = drm_dp_lttpr_count(intel_dp-
> >lttpr_common_caps);

You should check drm_dp_lttpr_count return value.

BR,
Jouni Högander

> +	}
> +
> +	if (lttpr_count > 0) {
> +		/* tlw and tcs values are taken from DP2.1 spec */
> +		int tlw = 13000;
> +		int tcs = 10000;
> +		int tlfps_period = get_lfps_cycle_time(crtc_state);
> +		int tdcs = (SILENCE_PERIOD_TIME + t1 + tcs +
> +			    (lttpr_count - 1) * (tlw +
> tlfps_period));
> +		int tacds = 70000;
> +		int tds = 7 * tml_phy_lock;
> +
> +		/* tdrl is same as tcds*/
> +		establishment_period = tlw + tlfps_period + tdcs +
> tacds +
> +				       (lttpr_count - 1) * tds +
> tcds;
> +	} else {
> +		/* TODO: Add a check for data realign by DPCD
> 0x116[3] */
> +
> +		establishment_period = (SILENCE_PERIOD_TIME + t1 +
> tcds);
> +	}
>  
>  	return establishment_period;
>  }
> @@ -138,12 +181,16 @@ static int get_establishment_period(const
> struct intel_crtc_state *crtc_state)
>   * within the CDS period complete within the CDS period regardless
> of
>   * entry into the period
>   * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
> - * TPS4 Length = 252 Symbols
> + * ML_PHY_LOCK Length (8b/10b): 252
> + * ML_PHY_LOCK Length (128b/132b): 396
> + * TPS4 Length = ML_PHY_LOCK * Rate Div
> + * Rate Div = 32 for 128b/132b and 10 for 8b/10b.
>   */
> -static int _lnl_compute_aux_less_wake_time(const struct
> intel_crtc_state *crtc_state)
> +static int _lnl_compute_aux_less_wake_time(struct intel_dp
> *intel_dp,
> +					   const struct
> intel_crtc_state *crtc_state)
>  {
>  	int tphy2_p2_to_p0 = get_tphy2_p2_to_p0(crtc_state);
> -	int establishment_period =
> get_establishment_period(crtc_state);
> +	int establishment_period =
> get_establishment_period(intel_dp, crtc_state);
>  
>  	return DIV_ROUND_UP(tphy2_p2_to_p0 +
> get_lfps_cycle_time(crtc_state) +
>  			    establishment_period, 1000);
> @@ -158,7 +205,7 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp
> *intel_dp,
>  		lfps_half_cycle;
>  
>  	aux_less_wake_time =
> -		_lnl_compute_aux_less_wake_time(crtc_state);
> +		_lnl_compute_aux_less_wake_time(intel_dp,
> crtc_state);
>  	aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state-
> >hw.adjusted_mode,
>  						      
> aux_less_wake_time);
>  	silence_period = get_silence_period_symbols(crtc_state);

Re: [PATCH v6 07/18] drm/i915/alpm: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> The AUX_LESS_WAKE_TIME bitfield in ALPM_CTL is widened from 6 bits to
> 8 bits starting from xe3lpd (display version 35). Add the register
> mask
> and field macro for the wider bitfield and program the wake time
> using
> the appropriate macro based on the display version.
> 
> v2: Modify AUX_LESS_WAKE_TIME bitfield for xe3lpd. [Suraj]
> v3: Separate out AUX_LESS_WAKE_TIME bitfield change into its own
> patch. [Jouni]
> 
> Bspec: 71477
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     | 8 ++++++--
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 ++
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 924fa8dd4638..dc025058a626 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -610,8 +610,12 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp,
>  	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
>  		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
>  			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
> -			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS
> |
> -			ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state-
> >alpm_state.aux_less_wake_lines);
> +			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS
> ;
> +
> +		if (DISPLAY_VER(display) < 35)
> +			alpm_ctl |=
> ALPM_CTL_AUX_LESS_WAKE_TIME(crtc_state-
> >alpm_state.aux_less_wake_lines);
> +		else
> +			alpm_ctl |=
> ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(crtc_state-
> >alpm_state.aux_less_wake_lines);

You should modify _lnl_compute_aux_less_wake_time to take this change
into account.

BR,
Jouni Högander

>  
>  		if (intel_dp->as_sdp_supported)
>  			intel_alpm_configure_pr_as_sdp(intel_dp,
> crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index bb577e7e3bbd..016ce24944dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -301,7 +301,9 @@
>  #define  ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES		5
>  #define 
> ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines)	REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK,(lines)-ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES)
>  #define 
> ALPM_CTL_AUX_LESS_WAKE_TIME_MASK		REG_GENMASK(5, 0)
> +#define 
> ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD	REG_GENMASK(7, 0)
>  #define 
> ALPM_CTL_AUX_LESS_WAKE_TIME(val)		REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK,val)
> +#define 
> ALPM_CTL_AUX_LESS_WAKE_TIME_XE3LPD(val)	REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK_XE3LPD,val)

>  
>  #define _ALPM_CTL2_A	0x60954
>  #define ALPM_CTL2(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran,
> _ALPM_CTL2_A)

Re: [PATCH v6 08/18] drm/i915/alpm: table based establishment period

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Only use the table when the link rate is listed (idx valid)
> and the LTTPR count is within the table bounds. A zero entry
> means the rate has no tabulated value, so fall back to the
> computed establishment period below.
> 
> Note: The table and its values are taken from DP2.1 vesa spec.
> 
> v2: Add check for negative error codes from drm_dp_lttpr_count().
> [sashiko]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 95
> +++++++++++++++++++++++
>  1 file changed, 95 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index dc025058a626..cb24bba801a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -122,6 +122,92 @@ static int get_dp_link_symbol_size(const struct
> intel_crtc_state *crtc_state)
>  	return intel_dp_is_uhbr(crtc_state) ? 32 : 10;
>  }
>  
> +#define DEFAULT_MAX_LTTPR_COUNT 7
> +#define MAX_SUPPORTED_DP_LINK_RATES 12
> +
> +static const u32
> establishment_periods[DEFAULT_MAX_LTTPR_COUNT][MAX_SUPPORTED_DP_LINK_
> RATES] = {
> +	/* 1620, 2160, 2430, 2700, 3240, 4320, 5400, 6750, 8100,
> 10000, 13500, 20000 */
> +	/* No Retimers */
> +	{ 61070, 0, 0, 56710, 0, 0, 53450, 0, 52360, 59050, 56750,
> 54620 },
> +	/*  1 Retimer  */
> +	{ 155670, 0, 0, 151310, 0, 0, 148050, 0, 146960, 153650,
> 151350, 149220 },
> +	/*  2 Retimers */
> +	{ 181160, 0, 0, 172450, 0, 0, 165910, 0, 163740, 177120,
> 172520, 168220 },
> +	/*  3 Retimers */
> +	{ 206650, 0, 0, 193580, 0, 0, 183780, 0, 180510, 200590,
> 193690, 187290 },
> +	/*  4 Retimers */
> +	{ 232140, 0, 0, 214710, 0, 0, 201650, 0, 197290, 224060,
> 214860, 206320 },
> +	/*  5 Retimers */
> +	{ 257620, 0, 0, 235850, 0, 0, 219510, 0, 214070, 247530,
> 236030, 225360 },
> +	/*  6 Retimers */
> +	{ 283110, 0, 0, 256980, 0, 0, 237380, 0, 230850, 271000,
> 257200, 244390 },
> +};
> +
> +enum link_rate_idx {
> +	LINK_RATE_INVALID = -1,
> +	LINK_RATE_1,
> +	LINK_RATE_2,
> +	LINK_RATE_3,
> +	LINK_RATE_4,
> +	LINK_RATE_5,
> +	LINK_RATE_6,
> +	LINK_RATE_7,
> +	LINK_RATE_8,
> +	LINK_RATE_9,
> +	LINK_RATE_10,
> +	LINK_RATE_11,
> +	LINK_RATE_12
> +};
> +
> +static int get_link_rate_index(int port_clock)
> +{
> +	int link_rate_index;
> +
> +	switch (port_clock) {
> +	case 162000:
> +		link_rate_index = LINK_RATE_1;	// Rate_1 (RBR) -
> 1.62 Gbps/Lane
> +		break;
> +	case 216000:
> +		link_rate_index = LINK_RATE_2;	// Rate_2       -
> 2.16 Gbps/Lane
> +		break;
> +	case 243000:
> +		link_rate_index = LINK_RATE_3;	// Rate_3       -
> 2.43 Gbps/Lane
> +		break;
> +	case 270000:
> +		link_rate_index = LINK_RATE_4;	// Rate_4 (HBR) -
> 2.70 Gbps/Lane
> +		break;
> +	case 324000:
> +		link_rate_index = LINK_RATE_5;	// Rate_5 (RBR2)-
> 3.24 Gbps/Lane
> +		break;
> +	case 432000:
> +		link_rate_index = LINK_RATE_6;	// Rate_6       -
> 4.32 Gbps/Lane
> +		break;
> +	case 540000:
> +		link_rate_index = LINK_RATE_7;	// Rate_7 (HBR2)-
> 5.40 Gbps/Lane
> +		break;
> +	case 675000:
> +		link_rate_index = LINK_RATE_8;	// Rate_8       -
> 6.75 Gbps/Lane
> +		break;
> +	case 810000:
> +		link_rate_index = LINK_RATE_9;	// Rate_9 (HBR3)-
> 8.10 Gbps/Lane
> +		break;
> +	case 1000000:
> +		link_rate_index = LINK_RATE_10;	// Rate_10
> (UHBR10) - 10.0 Gbps/Lane
> +		break;
> +	case 1350000:
> +		link_rate_index = LINK_RATE_11;	// Rate_11
> (UHBR13.5) - 13.5 Gbps/Lane
> +		break;
> +	case 2000000:
> +		link_rate_index = LINK_RATE_12;	// Rate_12
> (UHBR20) - 20.0 Gbps/Lane
> +		break;
> +	default:
> +		link_rate_index = LINK_RATE_INVALID;
> +		break;
> +	}
> +
> +	return link_rate_index;
> +}

Difference between what this table is giving us and what we are getting
from the formula is coming from SILENCE_PERIOD_TIME and tlfps_period.
In DP spec they are using max values while our calculation is using
midpoint.

I think we could just switch to max values on these and drop adding
tables completely.

BR,
Jouni Högander

> +
>  static int get_establishment_period(struct intel_dp *intel_dp,
>  				    const struct intel_crtc_state
> *crtc_state)
>  {
> @@ -138,8 +224,17 @@ static int get_establishment_period(struct
> intel_dp *intel_dp,
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
>  		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) *
> tml_phy_lock;
>  	} else {
> +		int idx = get_link_rate_index(crtc_state-
> >port_clock);
> +
>  		tcds = 7 * tml_phy_lock;
>  		lttpr_count = drm_dp_lttpr_count(intel_dp-
> >lttpr_common_caps);
> +
> +		if (idx != LINK_RATE_INVALID && lttpr_count >= 0 &&
> +		    lttpr_count < DEFAULT_MAX_LTTPR_COUNT &&
> +		    establishment_periods[lttpr_count][idx]) {
> +			establishment_period =
> establishment_periods[lttpr_count][idx];
> +			return establishment_period;
> +		}
>  	}
>  
>  	if (lttpr_count > 0) {

Re: [PATCH v6 08/18] drm/i915/alpm: table based establishment period

[Hogander, Jouni]

On Tue, 2026-09-29 at 10:00 +0300, Hogander, Jouni wrote:
> On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> > Only use the table when the link rate is listed (idx valid)
> > and the LTTPR count is within the table bounds. A zero entry
> > means the rate has no tabulated value, so fall back to the
> > computed establishment period below.
> > 
> > Note: The table and its values are taken from DP2.1 vesa spec.
> > 
> > v2: Add check for negative error codes from drm_dp_lttpr_count().
> > [sashiko]
> > 
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c | 95
> > +++++++++++++++++++++++
> >  1 file changed, 95 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index dc025058a626..cb24bba801a1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -122,6 +122,92 @@ static int get_dp_link_symbol_size(const
> > struct
> > intel_crtc_state *crtc_state)
> >  	return intel_dp_is_uhbr(crtc_state) ? 32 : 10;
> >  }
> >  
> > +#define DEFAULT_MAX_LTTPR_COUNT 7
> > +#define MAX_SUPPORTED_DP_LINK_RATES 12
> > +
> > +static const u32
> > establishment_periods[DEFAULT_MAX_LTTPR_COUNT][MAX_SUPPORTED_DP_LIN
> > K_
> > RATES] = {
> > +	/* 1620, 2160, 2430, 2700, 3240, 4320, 5400, 6750, 8100,
> > 10000, 13500, 20000 */
> > +	/* No Retimers */
> > +	{ 61070, 0, 0, 56710, 0, 0, 53450, 0, 52360, 59050, 56750,
> > 54620 },
> > +	/*  1 Retimer  */
> > +	{ 155670, 0, 0, 151310, 0, 0, 148050, 0, 146960, 153650,
> > 151350, 149220 },
> > +	/*  2 Retimers */
> > +	{ 181160, 0, 0, 172450, 0, 0, 165910, 0, 163740, 177120,
> > 172520, 168220 },
> > +	/*  3 Retimers */
> > +	{ 206650, 0, 0, 193580, 0, 0, 183780, 0, 180510, 200590,
> > 193690, 187290 },
> > +	/*  4 Retimers */
> > +	{ 232140, 0, 0, 214710, 0, 0, 201650, 0, 197290, 224060,
> > 214860, 206320 },
> > +	/*  5 Retimers */
> > +	{ 257620, 0, 0, 235850, 0, 0, 219510, 0, 214070, 247530,
> > 236030, 225360 },
> > +	/*  6 Retimers */
> > +	{ 283110, 0, 0, 256980, 0, 0, 237380, 0, 230850, 271000,
> > 257200, 244390 },
> > +};
> > +
> > +enum link_rate_idx {
> > +	LINK_RATE_INVALID = -1,
> > +	LINK_RATE_1,
> > +	LINK_RATE_2,
> > +	LINK_RATE_3,
> > +	LINK_RATE_4,
> > +	LINK_RATE_5,
> > +	LINK_RATE_6,
> > +	LINK_RATE_7,
> > +	LINK_RATE_8,
> > +	LINK_RATE_9,
> > +	LINK_RATE_10,
> > +	LINK_RATE_11,
> > +	LINK_RATE_12
> > +};
> > +
> > +static int get_link_rate_index(int port_clock)
> > +{
> > +	int link_rate_index;
> > +
> > +	switch (port_clock) {
> > +	case 162000:
> > +		link_rate_index = LINK_RATE_1;	// Rate_1 (RBR) -
> > 1.62 Gbps/Lane
> > +		break;
> > +	case 216000:
> > +		link_rate_index = LINK_RATE_2;	// Rate_2       -
> > 2.16 Gbps/Lane
> > +		break;
> > +	case 243000:
> > +		link_rate_index = LINK_RATE_3;	// Rate_3       -
> > 2.43 Gbps/Lane
> > +		break;
> > +	case 270000:
> > +		link_rate_index = LINK_RATE_4;	// Rate_4 (HBR) -
> > 2.70 Gbps/Lane
> > +		break;
> > +	case 324000:
> > +		link_rate_index = LINK_RATE_5;	// Rate_5 (RBR2)-
> > 3.24 Gbps/Lane
> > +		break;
> > +	case 432000:
> > +		link_rate_index = LINK_RATE_6;	// Rate_6       -
> > 4.32 Gbps/Lane
> > +		break;
> > +	case 540000:
> > +		link_rate_index = LINK_RATE_7;	// Rate_7 (HBR2)-
> > 5.40 Gbps/Lane
> > +		break;
> > +	case 675000:
> > +		link_rate_index = LINK_RATE_8;	// Rate_8       -
> > 6.75 Gbps/Lane
> > +		break;
> > +	case 810000:
> > +		link_rate_index = LINK_RATE_9;	// Rate_9 (HBR3)-
> > 8.10 Gbps/Lane
> > +		break;
> > +	case 1000000:
> > +		link_rate_index = LINK_RATE_10;	// Rate_10
> > (UHBR10) - 10.0 Gbps/Lane
> > +		break;
> > +	case 1350000:
> > +		link_rate_index = LINK_RATE_11;	// Rate_11
> > (UHBR13.5) - 13.5 Gbps/Lane
> > +		break;
> > +	case 2000000:
> > +		link_rate_index = LINK_RATE_12;	// Rate_12
> > (UHBR20) - 20.0 Gbps/Lane
> > +		break;
> > +	default:
> > +		link_rate_index = LINK_RATE_INVALID;
> > +		break;
> > +	}
> > +
> > +	return link_rate_index;
> > +}
> 
> Difference between what this table is giving us and what we are
> getting
> from the formula is coming from SILENCE_PERIOD_TIME and tlfps_period.
> In DP spec they are using max values while our calculation is using
> midpoint.
> 
> I think we could just switch to max values on these and drop adding
> tables completely.

This would unnecessarily increase our wake-time. Maybe we could just
accept the difference between calculated and pre-calculated values as
we understand where it comes from? We are using mid point in the
configuration and that is what we use in wake time calculation as well.
Values table from VESA spec are calculated using max values.

BR,
Jouni Högander
> 
> BR,
> Jouni Högander
> 
> > +
> >  static int get_establishment_period(struct intel_dp *intel_dp,
> >  				    const struct intel_crtc_state
> > *crtc_state)
> >  {
> > @@ -138,8 +224,17 @@ static int get_establishment_period(struct
> > intel_dp *intel_dp,
> >  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> >  		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1)
> > *
> > tml_phy_lock;
> >  	} else {
> > +		int idx = get_link_rate_index(crtc_state-
> > > port_clock);
> > +
> >  		tcds = 7 * tml_phy_lock;
> >  		lttpr_count = drm_dp_lttpr_count(intel_dp-
> > > lttpr_common_caps);
> > +
> > +		if (idx != LINK_RATE_INVALID && lttpr_count >= 0
> > &&
> > +		    lttpr_count < DEFAULT_MAX_LTTPR_COUNT &&
> > +		    establishment_periods[lttpr_count][idx]) {
> > +			establishment_period =
> > establishment_periods[lttpr_count][idx];
> > +			return establishment_period;
> > +		}
> >  	}
> >  
> >  	if (lttpr_count > 0) {
> 

Re: [PATCH v6 09/18] drm/i915/alpm: Half LFPS cycle calculation

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Add support for half LFPS cycle calculation for DP2.1 ALPM as
> dependent
> parameters got changed.
> 
> v1: Initial version.
> v2: Avoid returning early. [Jani]
> v3: Use intel_crtc_has_type(). [Suraj]
> v4: Split in separate function based on HAS_LT_PHY() check. [Jouni]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 41 ++++++++++++++++++---
> --
>  1 file changed, 33 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index cb24bba801a1..14ecb27095b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -74,24 +74,49 @@ static int get_silence_period_symbols(const
> struct intel_crtc_state *crtc_state)
>  		1000 / 1000;
>  }
>  
> -static void get_lfps_cycle_min_max_time(const struct
> intel_crtc_state *crtc_state,
> -					int *min, int *max)
> +static void lnl_get_lfps_period_min_max_time(const struct
> intel_crtc_state *crtc_state,
> +					     int *min, int *max)
>  {
> -	if (crtc_state->port_clock < 540000) {
> -		*min = 65 * LFPS_CYCLE_COUNT;
> -		*max = 75 * LFPS_CYCLE_COUNT;
> -	} else {
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> +		if (crtc_state->port_clock < 540000) {
> +			*min = 65 * LFPS_CYCLE_COUNT;
> +			*max = 75 * LFPS_CYCLE_COUNT;
> +		} else {
> +			*min = 140;
> +			*max = 800;
> +		}
> +	}
> +}
> +
> +static void xe3plpd_get_lfps_period_min_max_time(const struct
> intel_crtc_state *crtc_state,
> +						 int *min, int *max)
> +{
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
>  		*min = 140;
>  		*max = 800;
> +	} else {
> +		*min = 320;
> +		*max = 1600;
>  	}
>  }
>  
> +static void get_lfps_period_min_max_time(const struct
> intel_crtc_state *crtc_state,
> +					int *min, int *max)
> +{
> +	struct intel_display *display =
> to_intel_display(crtc_state);
> +
> +	if (HAS_LT_PHY(display))
> +		xe3plpd_get_lfps_period_min_max_time(crtc_state,
> min, max);

As you are checking HAS_LT_PHY better prefix would be lt_.

BR,
Jouni Högander

> +	else
> +		lnl_get_lfps_period_min_max_time(crtc_state, min,
> max);
> +}
> +
>  static int get_lfps_cycle_time(const struct intel_crtc_state
> *crtc_state)
>  {
>  	int tlfps_cycle_min, tlfps_cycle_max;
>  
> -	get_lfps_cycle_min_max_time(crtc_state, &tlfps_cycle_min,
> -				    &tlfps_cycle_max);
> +	get_lfps_period_min_max_time(crtc_state, &tlfps_cycle_min,
> +				     &tlfps_cycle_max);
>  
>  	return tlfps_cycle_min +  (tlfps_cycle_max -
> tlfps_cycle_min) / 2;
>  }

Re: [PATCH v6 02/18] drm/i915/alpm: Move alpm sink capability readout into a separate function

[Jani Nikula]

On Tue, 15 Sep 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> Abstract ALPM DPCD initialization into its own function.
>
> v2:
> - Improve commit description. [Suraj, Jouni]
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 11 +++++++++++
>  drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c   |  6 +-----
>  3 files changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 10943539bc7c..a6743fe62d48 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -43,6 +43,17 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
>  		(crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp));
>  }
>  
> +bool intel_alpm_init_dpcd(struct intel_dp *intel_dp)
> +{
> +	u8 dpcd;
> +
> +	if (drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
> +		return false;
> +
> +	intel_dp->alpm_dpcd = dpcd;
> +	return true;
> +}

Why not propagate the original error instead of flattening to a boolean?
What does boolean true/false mean for a function that's not a predicate
function but "init"?

From a maintenance perspective, the mixing of bool vs. int return values
is a problem because you never know what is being checked for in the
caller side:

	if (!intel_alpm_init_dpcd())

Does that return bool and false means failure? Or does that return int
and false means success?!


BR,
Jani.


> +
>  void intel_alpm_init(struct intel_dp *intel_dp)
>  {
>  	mutex_init(&intel_dp->alpm.lock);
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h
> index f8f605d94f96..56c3e1482e37 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -15,6 +15,7 @@ struct intel_connector;
>  struct intel_atomic_state;
>  struct intel_crtc;
>  
> +bool intel_alpm_init_dpcd(struct intel_dp *intel_dp);
>  void intel_alpm_init(struct intel_dp *intel_dp);
>  bool intel_alpm_compute_params(struct intel_dp *intel_dp,
>  			       struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0cd5e6b5034c..650c8b39270b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4783,7 +4783,6 @@ static bool
>  intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
> -	int ret;
>  	u8 dprx;
>  
>  	/* this function is meant to be called only once */
> @@ -4829,10 +4828,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector
>  	 */
>  	intel_dp_init_source_oui(intel_dp);
>  
> -	/* Read the ALPM DPCD caps */
> -	ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
> -				    &intel_dp->alpm_dpcd);
> -	if (ret < 0)
> +	if (!intel_alpm_init_dpcd(intel_dp))
>  		return false;
>  
>  	/*

-- 
Jani Nikula, Intel

Re: [PATCH v6 12/18] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM

[Jani Nikula]

On Tue, 15 Sep 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> Issue a AUX write transaction to DPCD DP_TOTAL_LTTPR_CNT (0xf000a)
> with total number of LTTPR before link training.
>
> v2: Cosmetic changes. [Suraj]
> v3:
> - Use same encoding format for lttpr_count. [Jouni]
> - Avoid reading alpm_ctl2 register. [Jouni]
>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     |  7 ++++++-
>  .../drm/i915/display/intel_dp_link_training.c | 21 +++++++++++++++++++
>  2 files changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
> index da653a407e97..06c1a59aa2c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -726,7 +726,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -	u32 alpm_ctl;
> +	u32 alpm_ctl, alpm_ctl2, lttpr_count;
>  
>  	if (DISPLAY_VER(display) < 20 || (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
>  					  !crtc_state->has_lobf))
> @@ -762,6 +762,11 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
>  
>  	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state->alpm_state.check_entry_lines);
>  
> +	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
> +
> +	alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
> +
> +	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder), alpm_ctl2);
>  	intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl);
>  	mutex_unlock(&intel_dp->alpm.lock);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index cb92cff90614..37c8306a1fa0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -2265,6 +2265,25 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
>  	return passed;
>  }
>  
> +static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp,
> +					int lttpr_count)
> +{
> +	u8 val;
> +
> +	/*
> +	 * Program only for DP2.1 and return if LTTPR revison is less than 0x20
> +	 * where 0:3 represents minor rev and 4:7 represent major rev
> +	 */
> +	if (!intel_dp_is_edp(intel_dp) ||
> +	    lttpr_count < 0 ||
> +	    intel_dp->lttpr_common_caps[0] <= 0x20)
> +		return;
> +
> +	val = intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
> +					  DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, val);

Please use the modern DPCD accessors throughout the series. See [1].

BR,
Jani.


[1] https://lore.kernel.org/r/cover.1789547331.git.jani.nikula@intel.com

> +}
> +
>  /**
>   * intel_dp_start_link_train - start link training
>   * @state: Atomic state
> @@ -2304,6 +2323,8 @@ void intel_dp_start_link_train(struct intel_atomic_state *state,
>  
>  	intel_dp_prepare_link_train(intel_dp, crtc_state);
>  
> +	intel_dp_update_lttpr_count(intel_dp, lttpr_count);
> +
>  	if (intel_dp_is_uhbr(crtc_state))
>  		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
>  	else

-- 
Jani Nikula, Intel

Re: [PATCH v6 10/18] drm/i915/alpm: Modify LFPS cycle count for DP ALPM

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> For DP minimum LFPS count is set to minimum 16.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++++++++++++---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 14ecb27095b2..22ed341763fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -24,7 +24,8 @@
>  				(SILENCE_PERIOD_MAX_TIME -	\
>  				 SILENCE_PERIOD_MIN_TIME) / 2)
>  
> -#define LFPS_CYCLE_COUNT 10
> +#define LFPS_CYCLE_COUNT	10
> +#define LFPS_CYCLE_COUNT_DP	16
>  
>  bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
>  {
> @@ -121,10 +122,19 @@ static int get_lfps_cycle_time(const struct
> intel_crtc_state *crtc_state)
>  	return tlfps_cycle_min +  (tlfps_cycle_max -
> tlfps_cycle_min) / 2;
>  }
>  
> +static int get_lfps_cycle_count(const struct intel_crtc_state
> *crtc_state)
> +{
> +	/* External DP uses a minimum of 16 LFPS cycles. */

I think this comment is useless. Anyways:

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> +	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> +		return LFPS_CYCLE_COUNT_DP;
> +
> +	return LFPS_CYCLE_COUNT;
> +}
> +
>  static int get_lfps_half_cycle_clocks(const struct intel_crtc_state
> *crtc_state)
>  {
>  	return get_lfps_cycle_time(crtc_state) * crtc_state-
> >port_clock / 1000 /
> -		1000 / (2 * LFPS_CYCLE_COUNT);
> +		1000 / (2 * get_lfps_cycle_count(crtc_state));
>  }
>  
>  #define ML_PHY_LOCK_LEN		252
> @@ -779,7 +789,7 @@ void intel_alpm_port_configure(struct intel_dp
> *intel_dp,
>  			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
>  			PORT_ALPM_CTL_SILENCE_PERIOD(
>  				crtc_state-
> >alpm_state.silence_period_sym_clocks);
> -		lfps_ctl_val =
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
> +		lfps_ctl_val =
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(get_lfps_cycle_count(crtc_state))
> |
>  			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(
>  				crtc_state-
> >alpm_state.lfps_half_cycle_num_of_syms) |
>  			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DUR
> ATION(

RE: [PATCH v6 02/18] drm/i915/alpm: Move alpm sink capability readout into a separate function

[Manna, Animesh]

> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Wednesday, September 30, 2026 1:35 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; dri-
> devel@lists.freedesktop.org
> Cc: Hogander, Jouni <jouni.hogander@intel.com>; Kandpal, Suraj
> <suraj.kandpal@intel.com>; Manna, Animesh <animesh.manna@intel.com>
> Subject: Re: [PATCH v6 02/18] drm/i915/alpm: Move alpm sink capability
> readout into a separate function
> 
> On Tue, 15 Sep 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > Abstract ALPM DPCD initialization into its own function.
> >
> > v2:
> > - Improve commit description. [Suraj, Jouni]
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c | 11 +++++++++++
> > drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
> >  drivers/gpu/drm/i915/display/intel_dp.c   |  6 +-----
> >  3 files changed, 13 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 10943539bc7c..a6743fe62d48 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -43,6 +43,17 @@ bool intel_alpm_is_alpm_aux_less(struct intel_dp
> *intel_dp,
> >  		(crtc_state->has_lobf &&
> > intel_alpm_aux_less_wake_supported(intel_dp));
> >  }
> >
> > +bool intel_alpm_init_dpcd(struct intel_dp *intel_dp) {
> > +	u8 dpcd;
> > +
> > +	if (drm_dp_dpcd_read_byte(&intel_dp->aux,
> DP_RECEIVER_ALPM_CAP, &dpcd) < 0)
> > +		return false;
> > +
> > +	intel_dp->alpm_dpcd = dpcd;
> > +	return true;
> > +}
> 
> Why not propagate the original error instead of flattening to a boolean?
> What does boolean true/false mean for a function that's not a predicate
> function but "init"?
> 
> From a maintenance perspective, the mixing of bool vs. int return values is a
> problem because you never know what is being checked for in the caller side:
> 
> 	if (!intel_alpm_init_dpcd())
> 
> Does that return bool and false means failure? Or does that return int and
> false means success?!

false indicates that it is not correctly initialized.
Got your concern, will try to keep return value as int.

Regards,
Animesh
> 
> 
> BR,
> Jani.
> 
> 
> > +
> >  void intel_alpm_init(struct intel_dp *intel_dp)  {
> >  	mutex_init(&intel_dp->alpm.lock);
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> > b/drivers/gpu/drm/i915/display/intel_alpm.h
> > index f8f605d94f96..56c3e1482e37 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> > @@ -15,6 +15,7 @@ struct intel_connector;  struct intel_atomic_state;
> > struct intel_crtc;
> >
> > +bool intel_alpm_init_dpcd(struct intel_dp *intel_dp);
> >  void intel_alpm_init(struct intel_dp *intel_dp);  bool
> > intel_alpm_compute_params(struct intel_dp *intel_dp,
> >  			       struct intel_crtc_state *crtc_state); diff --git
> > a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 0cd5e6b5034c..650c8b39270b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -4783,7 +4783,6 @@ static bool
> >  intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector
> > *connector)  {
> >  	struct intel_display *display = to_intel_display(intel_dp);
> > -	int ret;
> >  	u8 dprx;
> >
> >  	/* this function is meant to be called only once */ @@ -4829,10
> > +4828,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct
> intel_connector *connector
> >  	 */
> >  	intel_dp_init_source_oui(intel_dp);
> >
> > -	/* Read the ALPM DPCD caps */
> > -	ret = drm_dp_dpcd_read_byte(&intel_dp->aux,
> DP_RECEIVER_ALPM_CAP,
> > -				    &intel_dp->alpm_dpcd);
> > -	if (ret < 0)
> > +	if (!intel_alpm_init_dpcd(intel_dp))
> >  		return false;
> >
> >  	/*
> 
> --
> Jani Nikula, Intel

RE: [PATCH v6 04/18] drm/i915/alpm: Enable debugfs for DP2.1

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Monday, September 28, 2026 4:53 PM
> To: intel-xe@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Manna,
> Animesh <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Kandpal, Suraj <suraj.kandpal@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [PATCH v6 04/18] drm/i915/alpm: Enable debugfs for DP2.1
> 
> On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> > Enable ALPM debug info through lobf debug info.
> >
> > v2: cosmetic change. [Suraj]
> > v3: Use common api instead of DISPLAY_VER check in multiple places.
> > [Jani]
> > v4: Add display-version check as it dropped for EDP.
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 4801fc6bade2..901493bb1448 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -739,8 +739,10 @@ void intel_alpm_lobf_debugfs_add(struct
> > intel_connector *connector)
> >  	struct intel_display *display = to_intel_display(connector);
> >  	struct dentry *root = connector->base.debugfs_entry;
> >
> > -	if (DISPLAY_VER(display) < 20 ||
> > -	    connector->base.connector_type !=
> > DRM_MODE_CONNECTOR_eDP)
> > +	if (DISPLAY_VER(display) < 20)
> > +		return;
> > +
> > +	if (!intel_alpm_source_supported(connector))
> >  		return;
> >
> >  	debugfs_create_file("i915_edp_lobf_debug", 0644, root,
> 
> These are named as i915_edp_lobf_debug even if they are created on DP
> connector.

We have couple of options,
i) rename to i915_lobf_debug, but backward compatibility will be broken.
ii) create a new debugfs for dp - i915_dp_lobf_debug. Code duplication will be there.
ii) as LOBF introduced first on edp to so DP will use existing edp-interface. 

Good to know your opinion, I see all these options have pros and cons.

Regards,
Animesh 
> 
> BR,
> Jouni Högander

RE: [PATCH v6 08/18] drm/i915/alpm: table based establishment period

[Manna, Animesh]

> -----Original Message-----
> From: Hogander, Jouni <jouni.hogander@intel.com>
> Sent: Tuesday, September 29, 2026 12:30 PM
> To: intel-xe@lists.freedesktop.org; dri-devel@lists.freedesktop.org; Manna,
> Animesh <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Kandpal, Suraj <suraj.kandpal@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [PATCH v6 08/18] drm/i915/alpm: table based establishment
> period
> 
> On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> > Only use the table when the link rate is listed (idx valid) and the
> > LTTPR count is within the table bounds. A zero entry means the rate
> > has no tabulated value, so fall back to the computed establishment
> > period below.
> >
> > Note: The table and its values are taken from DP2.1 vesa spec.
> >
> > v2: Add check for negative error codes from drm_dp_lttpr_count().
> > [sashiko]
> >
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c | 95
> > +++++++++++++++++++++++
> >  1 file changed, 95 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index dc025058a626..cb24bba801a1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -122,6 +122,92 @@ static int get_dp_link_symbol_size(const struct
> > intel_crtc_state *crtc_state)
> >  	return intel_dp_is_uhbr(crtc_state) ? 32 : 10;
> >  }
> >
> > +#define DEFAULT_MAX_LTTPR_COUNT 7
> > +#define MAX_SUPPORTED_DP_LINK_RATES 12
> > +
> > +static const u32
> >
> establishment_periods[DEFAULT_MAX_LTTPR_COUNT][MAX_SUPPORTED_D
> P_LINK_
> > RATES] = {
> > +	/* 1620, 2160, 2430, 2700, 3240, 4320, 5400, 6750, 8100,
> > 10000, 13500, 20000 */
> > +	/* No Retimers */
> > +	{ 61070, 0, 0, 56710, 0, 0, 53450, 0, 52360, 59050, 56750,
> > 54620 },
> > +	/*  1 Retimer  */
> > +	{ 155670, 0, 0, 151310, 0, 0, 148050, 0, 146960, 153650,
> > 151350, 149220 },
> > +	/*  2 Retimers */
> > +	{ 181160, 0, 0, 172450, 0, 0, 165910, 0, 163740, 177120,
> > 172520, 168220 },
> > +	/*  3 Retimers */
> > +	{ 206650, 0, 0, 193580, 0, 0, 183780, 0, 180510, 200590,
> > 193690, 187290 },
> > +	/*  4 Retimers */
> > +	{ 232140, 0, 0, 214710, 0, 0, 201650, 0, 197290, 224060,
> > 214860, 206320 },
> > +	/*  5 Retimers */
> > +	{ 257620, 0, 0, 235850, 0, 0, 219510, 0, 214070, 247530,
> > 236030, 225360 },
> > +	/*  6 Retimers */
> > +	{ 283110, 0, 0, 256980, 0, 0, 237380, 0, 230850, 271000,
> > 257200, 244390 },
> > +};
> > +
> > +enum link_rate_idx {
> > +	LINK_RATE_INVALID = -1,
> > +	LINK_RATE_1,
> > +	LINK_RATE_2,
> > +	LINK_RATE_3,
> > +	LINK_RATE_4,
> > +	LINK_RATE_5,
> > +	LINK_RATE_6,
> > +	LINK_RATE_7,
> > +	LINK_RATE_8,
> > +	LINK_RATE_9,
> > +	LINK_RATE_10,
> > +	LINK_RATE_11,
> > +	LINK_RATE_12
> > +};
> > +
> > +static int get_link_rate_index(int port_clock) {
> > +	int link_rate_index;
> > +
> > +	switch (port_clock) {
> > +	case 162000:
> > +		link_rate_index = LINK_RATE_1;	// Rate_1 (RBR) -
> > 1.62 Gbps/Lane
> > +		break;
> > +	case 216000:
> > +		link_rate_index = LINK_RATE_2;	// Rate_2       -
> > 2.16 Gbps/Lane
> > +		break;
> > +	case 243000:
> > +		link_rate_index = LINK_RATE_3;	// Rate_3       -
> > 2.43 Gbps/Lane
> > +		break;
> > +	case 270000:
> > +		link_rate_index = LINK_RATE_4;	// Rate_4 (HBR) -
> > 2.70 Gbps/Lane
> > +		break;
> > +	case 324000:
> > +		link_rate_index = LINK_RATE_5;	// Rate_5 (RBR2)-
> > 3.24 Gbps/Lane
> > +		break;
> > +	case 432000:
> > +		link_rate_index = LINK_RATE_6;	// Rate_6       -
> > 4.32 Gbps/Lane
> > +		break;
> > +	case 540000:
> > +		link_rate_index = LINK_RATE_7;	// Rate_7 (HBR2)-
> > 5.40 Gbps/Lane
> > +		break;
> > +	case 675000:
> > +		link_rate_index = LINK_RATE_8;	// Rate_8       -
> > 6.75 Gbps/Lane
> > +		break;
> > +	case 810000:
> > +		link_rate_index = LINK_RATE_9;	// Rate_9 (HBR3)-
> > 8.10 Gbps/Lane
> > +		break;
> > +	case 1000000:
> > +		link_rate_index = LINK_RATE_10;	// Rate_10
> > (UHBR10) - 10.0 Gbps/Lane
> > +		break;
> > +	case 1350000:
> > +		link_rate_index = LINK_RATE_11;	// Rate_11
> > (UHBR13.5) - 13.5 Gbps/Lane
> > +		break;
> > +	case 2000000:
> > +		link_rate_index = LINK_RATE_12;	// Rate_12
> > (UHBR20) - 20.0 Gbps/Lane
> > +		break;
> > +	default:
> > +		link_rate_index = LINK_RATE_INVALID;
> > +		break;
> > +	}
> > +
> > +	return link_rate_index;
> > +}
> 
> Difference between what this table is giving us and what we are getting from
> the formula is coming from SILENCE_PERIOD_TIME and tlfps_period.
> In DP spec they are using max values while our calculation is using midpoint.
> 
> I think we could just switch to max values on these and drop adding tables
> completely.

As per I know the formula-based approach with max values also little short from the values coming from Vesa spec. This is found little sensitive during ALPM testing on specific test setup and resulting flip-done timeout. To overcome the issue currently prefer to direct values from vesa spec. And if not present will fallback to formula based approach.

Regards,
Animesh



> 
> BR,
> Jouni Högander
> 
> > +
> >  static int get_establishment_period(struct intel_dp *intel_dp,
> >  				    const struct intel_crtc_state
> > *crtc_state)
> >  {
> > @@ -138,8 +224,17 @@ static int get_establishment_period(struct
> > intel_dp *intel_dp,
> >  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
> >  		tcds = (7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1) *
> tml_phy_lock;
> >  	} else {
> > +		int idx = get_link_rate_index(crtc_state-
> > >port_clock);
> > +
> >  		tcds = 7 * tml_phy_lock;
> >  		lttpr_count = drm_dp_lttpr_count(intel_dp-
> > >lttpr_common_caps);
> > +
> > +		if (idx != LINK_RATE_INVALID && lttpr_count >= 0 &&
> > +		    lttpr_count < DEFAULT_MAX_LTTPR_COUNT &&
> > +		    establishment_periods[lttpr_count][idx]) {
> > +			establishment_period =
> > establishment_periods[lttpr_count][idx];
> > +			return establishment_period;
> > +		}
> >  	}
> >
> >  	if (lttpr_count > 0) {

Re: [PATCH v6 10/18] drm/i915/alpm: Modify LFPS cycle count for DP ALPM

[Hogander, Jouni]

On Thu, 2026-10-01 at 09:22 +0300, Hogander, Jouni wrote:
> On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> > For DP minimum LFPS count is set to minimum 16.
> > 
> > Cc: Jouni Högander <jouni.hogander@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++++++++++++---
> >  1 file changed, 13 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > index 14ecb27095b2..22ed341763fa 100644
> > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > @@ -24,7 +24,8 @@
> >  				(SILENCE_PERIOD_MAX_TIME -	\
> >  				 SILENCE_PERIOD_MIN_TIME) / 2)
> >  
> > -#define LFPS_CYCLE_COUNT 10
> > +#define LFPS_CYCLE_COUNT	10
> > +#define LFPS_CYCLE_COUNT_DP	16
> >  
> >  bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
> >  {
> > @@ -121,10 +122,19 @@ static int get_lfps_cycle_time(const struct
> > intel_crtc_state *crtc_state)
> >  	return tlfps_cycle_min +  (tlfps_cycle_max -
> > tlfps_cycle_min) / 2;
> >  }
> >  
> > +static int get_lfps_cycle_count(const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +	/* External DP uses a minimum of 16 LFPS cycles. */
> 
> I think this comment is useless. Anyways:
> 
> Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> 
> > +	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > +		return LFPS_CYCLE_COUNT_DP;
> > +
> > +	return LFPS_CYCLE_COUNT;
> > +}
> > +
> >  static int get_lfps_half_cycle_clocks(const struct
> > intel_crtc_state
> > *crtc_state)
> >  {
> >  	return get_lfps_cycle_time(crtc_state) * crtc_state-
> > > port_clock / 1000 /

Just realized that this has to be
intel_dp_link_symbol_clock(crtc_state>port_clock). For eDP it have been
working as crtc_state->port_clock ==
intel_dp_link_symbol_clock(crtc_state>port_clock) always.

BR,
Jouni Högander

> > -		1000 / (2 * LFPS_CYCLE_COUNT);
> > +		1000 / (2 * get_lfps_cycle_count(crtc_state));
> >  }
> >  
> >  #define ML_PHY_LOCK_LEN		252
> > @@ -779,7 +789,7 @@ void intel_alpm_port_configure(struct intel_dp
> > *intel_dp,
> >  			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> >  			PORT_ALPM_CTL_SILENCE_PERIOD(
> >  				crtc_state-
> > > alpm_state.silence_period_sym_clocks);
> > -		lfps_ctl_val =
> > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
> > +		lfps_ctl_val =
> > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(get_lfps_cycle_count(crtc_state
> > ))
> > > 
> >  			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATIO
> > N(
> >  				crtc_state-
> > > alpm_state.lfps_half_cycle_num_of_syms) |
> >  			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_D
> > UR
> > ATION(
> 

Re: [PATCH v6 10/18] drm/i915/alpm: Modify LFPS cycle count for DP ALPM

[Hogander, Jouni]

On Thu, 2026-10-01 at 15:10 +0300, Hogander, Jouni wrote:
> On Thu, 2026-10-01 at 09:22 +0300, Hogander, Jouni wrote:
> > On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> > > For DP minimum LFPS count is set to minimum 16.
> > > 
> > > Cc: Jouni Högander <jouni.hogander@intel.com>
> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++++++++++++---
> > >  1 file changed, 13 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > > index 14ecb27095b2..22ed341763fa 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > > @@ -24,7 +24,8 @@
> > >  				(SILENCE_PERIOD_MAX_TIME -
> > > 	\
> > >  				 SILENCE_PERIOD_MIN_TIME) / 2)
> > >  
> > > -#define LFPS_CYCLE_COUNT 10
> > > +#define LFPS_CYCLE_COUNT	10
> > > +#define LFPS_CYCLE_COUNT_DP	16
> > >  
> > >  bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp)
> > >  {
> > > @@ -121,10 +122,19 @@ static int get_lfps_cycle_time(const struct
> > > intel_crtc_state *crtc_state)
> > >  	return tlfps_cycle_min +  (tlfps_cycle_max -
> > > tlfps_cycle_min) / 2;
> > >  }
> > >  
> > > +static int get_lfps_cycle_count(const struct intel_crtc_state
> > > *crtc_state)
> > > +{
> > > +	/* External DP uses a minimum of 16 LFPS cycles. */
> > 
> > I think this comment is useless. Anyways:
> > 
> > Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> > 
> > > +	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> > > +		return LFPS_CYCLE_COUNT_DP;
> > > +
> > > +	return LFPS_CYCLE_COUNT;
> > > +}
> > > +
> > >  static int get_lfps_half_cycle_clocks(const struct
> > > intel_crtc_state
> > > *crtc_state)
> > >  {
> > >  	return get_lfps_cycle_time(crtc_state) * crtc_state-
> > > > port_clock / 1000 /
> 
> Just realized that this has to be
> intel_dp_link_symbol_clock(crtc_state>port_clock). For eDP it have
> been
> working as crtc_state->port_clock ==
> intel_dp_link_symbol_clock(crtc_state>port_clock) always.

Maybe also good to rename this as get_lfps_half_cycle_symbols.

BR,
Jouni Högander

> 
> BR,
> Jouni Högander
> 
> > > -		1000 / (2 * LFPS_CYCLE_COUNT);
> > > +		1000 / (2 * get_lfps_cycle_count(crtc_state));
> > >  }
> > >  
> > >  #define ML_PHY_LOCK_LEN		252
> > > @@ -779,7 +789,7 @@ void intel_alpm_port_configure(struct
> > > intel_dp
> > > *intel_dp,
> > >  			PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) |
> > >  			PORT_ALPM_CTL_SILENCE_PERIOD(
> > >  				crtc_state-
> > > > alpm_state.silence_period_sym_clocks);
> > > -		lfps_ctl_val =
> > > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(LFPS_CYCLE_COUNT) |
> > > +		lfps_ctl_val =
> > > PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(get_lfps_cycle_count(crtc_sta
> > > te
> > > ))
> > > > 
> > >  			PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURAT
> > > IO
> > > N(
> > >  				crtc_state-
> > > > alpm_state.lfps_half_cycle_num_of_syms) |
> > >  			PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE
> > > _D
> > > UR
> > > ATION(
> > 
> 

Re: [PATCH v6 12/18] drm/i915/alpm: Program LTTPR count for DP 2.1 ALPM

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Issue a AUX write transaction to DPCD DP_TOTAL_LTTPR_CNT (0xf000a)
> with total number of LTTPR before link training.
> 
> v2: Cosmetic changes. [Suraj]
> v3:
> - Use same encoding format for lttpr_count. [Jouni]
> - Avoid reading alpm_ctl2 register. [Jouni]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     |  7 ++++++-
>  .../drm/i915/display/intel_dp_link_training.c | 21
> +++++++++++++++++++
>  2 files changed, 27 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index da653a407e97..06c1a59aa2c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -726,7 +726,7 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp,
>  {
>  	struct intel_display *display = to_intel_display(intel_dp);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -	u32 alpm_ctl;
> +	u32 alpm_ctl, alpm_ctl2, lttpr_count;
>  
>  	if (DISPLAY_VER(display) < 20 ||
> (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
>  					  !crtc_state->has_lobf))
> @@ -762,6 +762,11 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp,
>  
>  	alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(crtc_state-
> >alpm_state.check_entry_lines);
>  
> +	lttpr_count = drm_dp_lttpr_count(intel_dp-
> >lttpr_common_caps);

You should check the return value here.

> +
> +	alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
> +
> +	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder),
> alpm_ctl2);
>  	intel_de_write(display, ALPM_CTL(display, cpu_transcoder),
> alpm_ctl);
>  	mutex_unlock(&intel_dp->alpm.lock);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index cb92cff90614..37c8306a1fa0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -2265,6 +2265,25 @@ intel_dp_128b132b_link_train(struct intel_dp
> *intel_dp,
>  	return passed;
>  }
>  
> +static void intel_dp_update_lttpr_count(struct intel_dp *intel_dp,
> +					int lttpr_count)
> +{
> +	u8 val;
> +
> +	/*
> +	 * Program only for DP2.1 and return if LTTPR revison is
> less than 0x20
> +	 * where 0:3 represents minor rev and 4:7 represent major
> rev
> +	 */
> +	if (!intel_dp_is_edp(intel_dp) ||

This is wrong. You probably meant
intel_dp_is_edp(intel_dp)intel_dp_is_edp(intel_dp).

> +	    lttpr_count < 0 ||

No need to check this. It's already set as 0 in start_link_train if <
0.

BR,
Jouni Högander

> +	    intel_dp->lttpr_common_caps[0] <= 0x20)
> +		return;
> +
> +	val = intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
> +					 
> DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> +	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TOTAL_LTTPR_CNT, val);
> +}
> +
>  /**
>   * intel_dp_start_link_train - start link training
>   * @state: Atomic state
> @@ -2304,6 +2323,8 @@ void intel_dp_start_link_train(struct
> intel_atomic_state *state,
>  
>  	intel_dp_prepare_link_train(intel_dp, crtc_state);
>  
> +	intel_dp_update_lttpr_count(intel_dp, lttpr_count);
> +
>  	if (intel_dp_is_uhbr(crtc_state))
>  		passed = intel_dp_128b132b_link_train(intel_dp,
> crtc_state, lttpr_count);
>  	else

Re: [PATCH v6 13/18] drm/i915/alpm: Enable MAC Transmitting LFPS for LT PHY

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Enable MAC to transmit LFPS via LT PHY during aux-less alpm.
> 
> v2:
> - Correct commit description. [Suraj]
> - Remove loop as no dependency on the transmitter LT_PHY_CMN_CTL0.
> [Suraj]
> v3: Cosmetic changes. [Suraj]
> 
Bspec reference.

> Cc: Jouni Högander <jouni.hogander@intel.com>
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  5 +++-
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   | 27
> +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_lt_phy.h   |  2 ++
>  .../gpu/drm/i915/display/intel_lt_phy_regs.h  |  3 +++
>  4 files changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 9b3b526e5e55..5244218132aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3796,7 +3796,10 @@ static void
> mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>  	 *     ii. Enable MAC Transmits LFPS in the "PHY Common
> Control 0" PIPE
>  	 *         register
>  	 */
> -	intel_lnl_mac_transmit_lfps(encoder, crtc_state);
> +	if (HAS_LT_PHY(display))
> +		intel_xe3plpd_mac_transmit_lfps(encoder,
> crtc_state);

Maybe better prefix for this would be intel_lt_mac_*

> +	else
> +		intel_lnl_mac_transmit_lfps(encoder, crtc_state);
>  }
>  
>  static void intel_ddi_prepare_link_retrain(struct intel_dp
> *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 86492651b01d..4fe010df20be 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -5,6 +5,7 @@
>  
>  #include <drm/drm_print.h>
>  
> +#include "intel_alpm.h"
>  #include "intel_cx0_phy.h"
>  #include "intel_cx0_phy_regs.h"
>  #include "intel_ddi.h"
> @@ -2357,3 +2358,29 @@ void intel_lt_phy_verify_plls(struct
> intel_display *display)
>  	intel_lt_phy_pll_verify_tables(display,
> xe3plpd_lt_edp_tables);
>  	intel_lt_phy_pll_verify_tables(display,
> xe3plpd_lt_hdmi_tables);
>  }
> +
> +/*
> + * According to HAS we need to enable MAC Transmitting LFPS in the
> "PHY Common
> + * Control 0" PIPE register in case of AUX Less ALPM is going to be
> used. This
> + * function is doing that and is called by link retrain sequence.
> + */
> +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
> +				     const struct intel_crtc_state
> *crtc_state)
> +{
> +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +	struct ref_tracker *wakeref;
> +	u8 owned_lane_mask;
> +
> +	if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
> +		return;

You should also check alpm or modify intel_alpm_is_alpm_aux_less.

> +
> +	wakeref = intel_lt_phy_transaction_begin(encoder);
> +
> +	owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
> +
> +	intel_lt_phy_rmw(encoder, owned_lane_mask, LT_PHY_CMN_CTL_0,
> +			 LT_PHY_CMN_LFPS_ENABLE,
> +			 LT_PHY_CMN_LFPS_ENABLE,
> MB_WRITE_COMMITTED);
> +
> +	intel_lt_phy_transaction_end(encoder, wakeref);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> index 16de39484779..c76c97b90946 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
> @@ -49,5 +49,7 @@ void intel_xe3plpd_pll_enable(struct intel_encoder
> *encoder,
>  			      const struct intel_dpll_hw_state
> *dpll_hw_state);
>  void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
>  void intel_lt_phy_verify_plls(struct intel_display *display);
> +void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
> +				     const struct intel_crtc_state
> *crtc_state);
>  
>  #endif /* __INTEL_LT_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index ff6d7829dbb9..b64ff57e0c09 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -35,6 +35,9 @@
>  #define LT_PHY_TXY_CTL10_MAC(idx)	_MMIO(LT_PHY_TXY_CTL10(idx))
>  #define  LT_PHY_TX_LANE_ENABLE		REG_BIT8(0)
>  
> +#define LT_PHY_CMN_CTL_0		(0x800)
> +#define  LT_PHY_CMN_LFPS_ENABLE		REG_BIT8(1)

LT_PHY_CMN_MAC_TRANSMIT_LFPS would better follow what is in Bspec.

BR,
Jouni Högander

> +
>  /* LT Phy Vendor Register */
>  #define LT_PHY_VDR_0_CONFIG	0xC02
>  #define  LT_PHY_VDR_DP_PLL_ENABLE	REG_BIT(7)

Re: [PATCH v6 14/18] drm/i915/alpm: Replace is_edp() with alpm_is_possible()

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Add a separate alpm_is_possible() which will check for alpm
> capability from dpcd info.
> 
> v2: Drop DISPLAY_VER() check as intel_alpm_source_supported
> already checking and populating dpcd info. [Jouni]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 13 ++++++++++---
>  drivers/gpu/drm/i915/display/intel_alpm.h |  1 +
>  2 files changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 06c1a59aa2c5..29a93a252fe9 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -69,6 +69,13 @@ void intel_alpm_init(struct intel_dp *intel_dp)
>  	mutex_init(&intel_dp->alpm.lock);
>  }
>  
> +bool intel_alpm_is_possible(struct intel_dp *intel_dp)
> +{
> +	return (intel_dp->alpm_dpcd ||
> +		intel_dp-
> >lttpr_common_caps[DP_LTTPR_ALPM_CAPABILITIES -
> +					   
> DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]);
> +}
> +
>  static int get_silence_period_symbols(const struct intel_crtc_state
> *crtc_state)
>  {
>  	return SILENCE_PERIOD_TIME *
> intel_dp_link_symbol_clock(crtc_state->port_clock) /
> @@ -546,7 +553,7 @@ void intel_alpm_lobf_compute_config(struct
> intel_dp *intel_dp,
>  	if (intel_dp->alpm.sink_alpm_error)
>  		return;
>  
> -	if (!intel_dp_is_edp(intel_dp))
> +	if (!intel_alpm_is_possible(intel_dp))
>  		return;
>  
>  	if (DISPLAY_VER(display) < 20)
> @@ -832,7 +839,7 @@ void intel_alpm_lobf_disable(const struct
> intel_crtc_state *new_crtc_state)
>  
>  		intel_dp = enc_to_intel_dp(encoder);
>  
> -		if (!intel_dp_is_edp(intel_dp))
> +		if (!intel_alpm_is_possible(intel_dp))

I think rather than converting these you should remove these checks
from enable and disable. LOBF is not supposed to be enabled in
new_crtc_state if "!intel_alpm_is_possible()"

BR,
Jouni Högander
 
>  			continue;
>  
>  		mutex_lock(&intel_dp->alpm.lock);
> @@ -873,7 +880,7 @@ void intel_alpm_lobf_enable(const struct
> intel_crtc_state *new_crtc_state)
>  
>  		intel_dp = enc_to_intel_dp(encoder);
>  
> -		if (intel_dp_is_edp(intel_dp)) {
> +		if (intel_alpm_is_possible(intel_dp)) {
>  			intel_alpm_enable_sink(intel_dp,
> new_crtc_state);
>  			intel_alpm_configure(intel_dp,
> new_crtc_state);
>  		}
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index 9a02fa386ee3..ea90eba76ca7 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -18,6 +18,7 @@ struct intel_crtc;
>  bool intel_alpm_source_supported(struct intel_connector *connector);
>  bool intel_alpm_init_dpcd(struct intel_dp *intel_dp);
>  void intel_alpm_init(struct intel_dp *intel_dp);
> +bool intel_alpm_is_possible(struct intel_dp *intel_dp);
>  bool intel_alpm_compute_params(struct intel_dp *intel_dp,
>  			       struct intel_crtc_state *crtc_state);
>  void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,

Re: [PATCH v6 15/18] drm/i915/alpm: Introduce has_alpm to decouple from pr/psr2/lobf

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> For DP2.1, ALPM (Advanced Link Power Management) is optional: Panel
> Replay can be supported without ALPM. Until now ALPM enablement was
> derived implicitly from other features - eDP Panel Replay and PSR2
> always implied ALPM (intel_psr_needs_alpm()), while LOBF was tracked
> separately via has_lobf - so this scattered, feature-coupled logic
> cannot express "Panel Replay without ALPM".
> 
> Introduce a single crtc_state->has_alpm flag as the source of truth
> for
> whether ALPM is enabled for a pipe configuration, computed during
> config
> validation:
> 
>  - Panel Replay: from alpm_config_valid() when ALPM is possible; eDP
>    Panel Replay additionally requires has_alpm.
>  - PSR2 / Selective Update: from intel_alpm_is_possible().
>  - LOBF: from has_lobf.
> 
> The Panel Replay path sets has_alpm speculatively, so clear it when
> Panel Replay is not the finally selected feature, ensuring a PSR1
> fallback never enables ALPM.
> 
> Use has_alpm in place of the feature-specific checks in the ALPM
> configure, port configure, sink enable and MAC-transmit-LFPS paths,
> and
> key the late wake-line selection off has_alpm / has_panel_replay.
> 
> Also rename intel_alpm_is_alpm_aux_less() to intel_alpm_is_aux_less()
> and base the aux-less decision on has_panel_replay, keeping the
> source
> programming consistent with the sink's DP_ALPM_MODE_AUX_LESS. The now
> unused intel_psr_needs_alpm() is removed.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     | 25 +++++-----
>  drivers/gpu/drm/i915/display/intel_alpm.h     |  4 +-
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  6 ++-
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_lt_phy.c   |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 48 +++++++++++------
> --
>  drivers/gpu/drm/i915/display/intel_psr.h      |  1 -
>  7 files changed, 47 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 29a93a252fe9..236341aa3c8d 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -37,11 +37,11 @@ bool intel_alpm_aux_less_wake_supported(struct
> intel_dp *intel_dp)
>  	return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP;
>  }
>  
> -bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
> -				 const struct intel_crtc_state
> *crtc_state)
> +bool intel_alpm_is_aux_less(struct intel_dp *intel_dp,
> +			    const struct intel_crtc_state
> *crtc_state)
>  {
> -	return intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)
> ||
> -		(crtc_state->has_lobf &&
> intel_alpm_aux_less_wake_supported(intel_dp));
> +	return crtc_state->has_panel_replay ||
> +	       (crtc_state->has_lobf &&
> intel_alpm_aux_less_wake_supported(intel_dp));
>  }
>  
>  bool intel_alpm_source_supported(struct intel_connector *connector)
> @@ -537,6 +537,7 @@ void intel_alpm_lobf_compute_config_late(struct
> intel_dp *intel_dp,
>  
>  	crtc_state->has_lobf = (crtc_state->set_context_latency +
> crtc_state->vrr.guardband) >
>  			       (first_sdp_position +
> waketime_in_lines);
> +	crtc_state->has_alpm = crtc_state->has_lobf;
>  }
>  
>  void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp,
> @@ -719,7 +720,7 @@ void intel_alpm_pr_as_sdp_update(const struct
> intel_crtc_state *crtc_state)
>  		intel_dp = enc_to_intel_dp(encoder);
>  
>  		if (!intel_dp->as_sdp_supported ||
> -		    !intel_alpm_is_alpm_aux_less(intel_dp,
> crtc_state))
> +		    !intel_alpm_is_aux_less(intel_dp, crtc_state))
>  			continue;
>  
>  		mutex_lock(&intel_dp->alpm.lock);
> @@ -735,8 +736,7 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp,
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 alpm_ctl, alpm_ctl2, lttpr_count;
>  
> -	if (DISPLAY_VER(display) < 20 ||
> (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
> -					  !crtc_state->has_lobf))
> +	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
>  		return;
>  
>  	mutex_lock(&intel_dp->alpm.lock);
> @@ -744,7 +744,7 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp,
>  	 * Panel Replay on eDP is always using ALPM aux less. I.e.
> no need to
>  	 * check panel support at this point.
>  	 */
> -	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> +	if (intel_alpm_is_aux_less(intel_dp, crtc_state)) {
>  		alpm_ctl = ALPM_CTL_ALPM_ENABLE |
>  			ALPM_CTL_ALPM_AUX_LESS_ENABLE |
>  			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS
> ;
> @@ -792,10 +792,10 @@ void intel_alpm_port_configure(struct intel_dp
> *intel_dp,
>  	enum port port = dp_to_dig_port(intel_dp)->base.port;
>  	u32 alpm_ctl_val = 0, lfps_ctl_val = 0;
>  
> -	if (DISPLAY_VER(display) < 20)
> +	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
>  		return;
>  
> -	if (intel_alpm_is_alpm_aux_less(intel_dp, crtc_state)) {
> +	if (intel_alpm_is_aux_less(intel_dp, crtc_state)) {
>  		int lfps_cycle = get_lfps_cycle_count(crtc_state);
>  		u32 lfps_cycle_val;
>  
> @@ -854,13 +854,12 @@ void intel_alpm_enable_sink(struct intel_dp
> *intel_dp,
>  {
>  	u8 val;
>  
> -	if (!intel_psr_needs_alpm(intel_dp, crtc_state) &&
> !crtc_state->has_lobf)
> +	if (!crtc_state->has_alpm)
>  		return;
>  
>  	val = DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE;
>  
> -	if (crtc_state->has_panel_replay || (crtc_state->has_lobf &&
> -					    
> intel_alpm_aux_less_wake_supported(intel_dp)))
> +	if (intel_alpm_is_aux_less(intel_dp, crtc_state))
>  		val |= DP_ALPM_MODE_AUX_LESS;
>  
>  	drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
> val);
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h
> b/drivers/gpu/drm/i915/display/intel_alpm.h
> index ea90eba76ca7..5d404e7b07de 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.h
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.h
> @@ -35,8 +35,8 @@ void intel_alpm_lobf_enable(const struct
> intel_crtc_state *new_crtc_state);
>  void intel_alpm_lobf_debugfs_add(struct intel_connector *connector);
>  bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp);
>  bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp);
> -bool intel_alpm_is_alpm_aux_less(struct intel_dp *intel_dp,
> -				 const struct intel_crtc_state
> *crtc_state);
> +bool intel_alpm_is_aux_less(struct intel_dp *intel_dp,
> +			    const struct intel_crtc_state
> *crtc_state);
>  bool intel_alpm_pr_as_sdp_skip_frames_enabled(struct intel_dp
> *intel_dp,
>  					      const struct
> intel_crtc_state *crtc_state);
>  void intel_alpm_pr_as_sdp_update(const struct intel_crtc_state
> *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index dbebd7210848..26a5d40289ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3449,8 +3449,10 @@ void intel_lnl_mac_transmit_lfps(struct
> intel_encoder *encoder,
>  	int i;
>  	u8 owned_lane_mask;
>  
> -	if (DISPLAY_VER(display) < 20 ||
> -	    !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder),
> crtc_state))
> +	if (DISPLAY_VER(display) < 20 || !crtc_state->has_alpm)
> +		return;
> +
> +	if (!intel_alpm_is_aux_less(enc_to_intel_dp(encoder),
> crtc_state))
>  		return;
>  
>  	owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index a5f18ac8a7d0..e2cc73c98479 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1448,6 +1448,7 @@ struct intel_crtc_state {
>  		u8 silence_period_sym_clocks;
>  		u8 lfps_half_cycle_num_of_syms;
>  	} alpm_state;
> +	bool has_alpm;
>  
>  	/* to track changes in plane color blocks */
>  	bool plane_color_changed;
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 4fe010df20be..8ebbdc3c0184 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2371,7 +2371,7 @@ void intel_xe3plpd_mac_transmit_lfps(struct
> intel_encoder *encoder,
>  	struct ref_tracker *wakeref;
>  	u8 owned_lane_mask;
>  
> -	if (!intel_alpm_is_alpm_aux_less(intel_dp, crtc_state))
> +	if (!crtc_state->has_alpm ||
> !intel_alpm_is_aux_less(intel_dp, crtc_state))
>  		return;
>  
>  	wakeref = intel_lt_phy_transaction_begin(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 872e253db178..1f14dbe57512 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1648,6 +1648,8 @@ static bool
> intel_sel_update_config_valid(struct intel_crtc_state *crtc_state,
>  	crtc_state->enable_psr2_su_region_et =
> psr2_su_region_et_valid(connector,
>  								    
>    crtc_state->has_panel_replay);
>  
> +	crtc_state->has_alpm = intel_alpm_is_possible(intel_dp);

For PSR2 right place for this is in intel_psr2_config_valid. There is
already alpm_config_valid call.

I would rather set it in one place. At the end of
intel_psr_compute_config_late if doing it this way.

I would rather target to have :

1. alpm_compute_config ()
   doing intel_alpm_compute_params. Setting two new flags in
alpm_state->aux_less_possible and alpm_state->aux_wake_possible. Also
doing what lobf_compute_config is doing now.

2. psr_compute_config
   using values/flags computed by alpm_compute_config and choosing  
psr/psr2/pr based on those.
...

3. psr_compute_config_late
   no changes.

4. alpm_compute_config_late
   set has_lobf and has_alpm based on calculation by
alpm_compute_config, psr_compute_config and psr_compute_config_late.

Next logical move after this would be to have the configuration of ALPM
happening in one place. Not needed in this patch set though.

BR,
Jouni Högander

> +
>  	return true;
>  
>  unsupported:
> @@ -1735,11 +1737,17 @@ static bool
> _panel_replay_compute_config(struct intel_crtc_state *crtc_state,
>  	crtc_state->link_off_after_as_sdp_when_pr_active =
> compute_link_off_after_as_sdp_when_pr_active(connector);
>  	crtc_state->disable_as_sdp_when_pr_active =
> compute_disable_as_sdp_when_pr_active(connector);
>  
> +	if (intel_alpm_is_possible(intel_dp))
> +		crtc_state->has_alpm = alpm_config_valid(intel_dp,
> crtc_state, true, true, false);
> +
>  	if (!intel_dp_is_edp(intel_dp))
>  		return true;
>  
>  	/* Remaining checks are for eDP only */
>  
> +	if (!crtc_state->has_alpm)
> +		return false;
> +
>  	if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A &&
>  	    to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_B)
>  		return false;
> @@ -1762,9 +1770,6 @@ static bool _panel_replay_compute_config(struct
> intel_crtc_state *crtc_state,
>  		return false;
>  	}
>  
> -	if (!alpm_config_valid(intel_dp, crtc_state, true, true,
> false))
> -		return false;
> -
>  	return true;
>  }
>  
> @@ -1888,6 +1893,15 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
>  	crtc_state->panel_replay_dsc_support = connector-
> >dp.panel_replay_caps.dsc_support;
>  	crtc_state->has_panel_replay =
> _panel_replay_compute_config(crtc_state, conn_state);
>  
> +	/*
> +	 * has_alpm may have been set speculatively while evaluating
> Panel
> +	 * Replay. It is only valid if Panel Replay was actually
> selected;
> +	 * otherwise the finally chosen feature (PSR2/SU or LOBF)
> decides it and
> +	 * a PSR1 fallback must not enable ALPM.
> +	 */
> +	if (!crtc_state->has_panel_replay)
> +		crtc_state->has_alpm = false;
> +
>  	crtc_state->has_psr = crtc_state->has_panel_replay ? true :
>  		_psr_compute_config(intel_dp, crtc_state,
> conn_state);
>  
> @@ -4555,16 +4569,6 @@ void intel_psr_connector_debugfs_add(struct
> intel_connector *connector)
>  				    connector,
> &i915_psr_status_fops);
>  }
>  
> -bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct
> intel_crtc_state *crtc_state)
> -{
> -	/*
> -	 * eDP Panel Replay uses always ALPM
> -	 * PSR2 uses ALPM but PSR1 doesn't
> -	 */
> -	return intel_dp_is_edp(intel_dp) && (crtc_state-
> >has_sel_update ||
> -					     crtc_state-
> >has_panel_replay);
> -}
> -
>  bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>  				   const struct intel_crtc_state
> *crtc_state)
>  {
> @@ -4578,15 +4582,17 @@ void intel_psr_compute_config_late(struct
> intel_dp *intel_dp,
>  	int vblank = intel_crtc_vblank_length(crtc_state);
>  	int wake_lines;
>  
> -	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state))
> -		wake_lines = crtc_state-
> >alpm_state.aux_less_wake_lines;
> -	else if (intel_psr_needs_alpm(intel_dp, crtc_state))
> -		wake_lines = DISPLAY_VER(display) < 20 ?
> -			     psr2_block_count_lines(crtc_state-
> >alpm_state.io_wake_lines,
> -						    crtc_state-
> >alpm_state.fast_wake_lines) :
> -			     crtc_state->alpm_state.io_wake_lines;
> -	else
> +	if (crtc_state->has_alpm) {
> +		if (crtc_state->has_panel_replay)
> +			wake_lines = crtc_state-
> >alpm_state.aux_less_wake_lines;
> +		else
> +			wake_lines = DISPLAY_VER(display) < 20 ?
> +				    
> psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
> +							   
> crtc_state->alpm_state.fast_wake_lines) :
> +				     crtc_state-
> >alpm_state.io_wake_lines;
> +	} else {
>  		wake_lines = 0;
> +	}
>  
>  	/*
>  	 * Disable the PSR features if wake lines exceed the
> available vblank.
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index d545fdaa0de7..4905ba4da4b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -79,7 +79,6 @@ void intel_psr_trigger_frame_change_event(struct
> intel_dsb *dsb,
>  int intel_psr_min_set_context_latency(const struct intel_crtc_state
> *crtc_state);
>  void intel_psr_connector_debugfs_add(struct intel_connector
> *connector);
>  void intel_psr_debugfs_register(struct intel_display *display);
> -bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct
> intel_crtc_state *crtc_state);
>  bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>  				   const struct intel_crtc_state
> *crtc_state);
>  void intel_psr_compute_config_late(struct intel_dp *intel_dp,

Re: [PATCH v6 16/18] drm/i915/alpm: Compute and program switch to active latency

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> Program the ALPM switch to active latency into ALPM_CTL2. For UHBR
> link
> rates the latency is derived from the link symbol clock and converted
> to
> scanlines, for non-UHBR rates it is zero.
> 
> v2: Use macro instead of magic number wherever possible. [Jouni]
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c     | 29
> ++++++++++++++++++-
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  2 files changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 236341aa3c8d..84777c8d31bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -301,6 +301,31 @@ static int get_establishment_period(struct
> intel_dp *intel_dp,
>  	return establishment_period;
>  }
>  
> +static int get_switch_to_active(const struct intel_crtc_state
> *crtc_state)
> +{
> +	int port_clock = crtc_state->port_clock;
> +	int switch_to_active;
> +
> +	if (intel_dp_is_uhbr(crtc_state)) {
> +		/* symbol_clock (fLink) in MHz */
> +		int symbol_clock = port_clock /
> intel_dp_link_symbol_size(port_clock) / 100;

Use intel_dp_link_symbol_clock.

BR,
Jouni Högander

> +
> +		/*
> +		 * tSwitch to Active = 32 * (ML_PHY_LOCK Length + 3
> + 64) / fLink
> +		 *
> +		 * The "+ 3" term is the trailing zero padding after
> the
> +		 * POST_LT_SCRAMBLER_RESET, the "+ 64" term
> represents the MTP
> +		 * time slots. The result is in microseconds.
> +		 */
> +		switch_to_active =
> get_dp_link_symbol_size(crtc_state) *
> +				   (ML_PHY_LOCK_LEN_UHBR + 3 + 64) /
> symbol_clock;
> +	} else {
> +		switch_to_active = 0;
> +	}
> +
> +	return switch_to_active;
> +}
> +
>  /*
>   * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period,
> Max+
>   * tSilence, Max+ tPHY Establishment + tCDS) / tline)
> @@ -360,7 +385,8 @@ _lnl_compute_aux_less_alpm_params(struct intel_dp
> *intel_dp,
>  	crtc_state->alpm_state.aux_less_wake_lines =
> aux_less_wake_lines;
>  	crtc_state->alpm_state.silence_period_sym_clocks =
> silence_period;
>  	crtc_state->alpm_state.lfps_half_cycle_num_of_syms =
> lfps_half_cycle;
> -
> +	crtc_state->alpm_state.switch_to_active =
> intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode,
> +								
> 	   get_switch_to_active(crtc_state));
>  	return true;
>  }
>  
> @@ -772,6 +798,7 @@ static void lnl_alpm_configure(struct intel_dp
> *intel_dp,
>  	lttpr_count = drm_dp_lttpr_count(intel_dp-
> >lttpr_common_caps);
>  
>  	alpm_ctl2 = ALPM_CTL2_NUMBER_OF_LTTPR(lttpr_count);
> +	alpm_ctl2 |= ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(crtc_state-
> >alpm_state.switch_to_active);
>  
>  	intel_de_write(display, ALPM_CTL2(display, cpu_transcoder),
> alpm_ctl2);
>  	intel_de_write(display, ALPM_CTL(display, cpu_transcoder),
> alpm_ctl);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e2cc73c98479..6387258cd633 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1447,6 +1447,7 @@ struct intel_crtc_state {
>  		u8 aux_less_wake_lines;
>  		u8 silence_period_sym_clocks;
>  		u8 lfps_half_cycle_num_of_syms;
> +		int switch_to_active;
>  	} alpm_state;
>  	bool has_alpm;
>  

Re: [PATCH v6 17/18] drm/i915/alpm: Program zero-based LFPS half cycle duration

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> The LFPS Half Cycle Duration field, as well as the First and Last
> LFPS
> Half Cycle Duration fields, in PORT_ALPM_LFPS_CTL are zero-based: per
> Bspec the value programmed must be N_Symbol - 1. The number of
> symbols
> was programmed directly, making each half cycle one symbol clock too
> long.
> 
> Subtract one in the PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION,
> PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION and
> PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION field macros so the
> programmed value matches the zero-based field encoding.
> 
> Bspec: 71632
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Assisted-by: Claude:claude-opus-4-8
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 8f60b671755a..387edf8df6e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -339,11 +339,17 @@
>  #define  PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN		7
>  #define 
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(val)		REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK,(val)-PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
>  #define 
> PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_XE3LPD(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK_XE3LPD,(val)-PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN)
> +/*
> + * The LFPS half cycle duration fields (including the first and last
> half
> + * cycle) are zero-based, i.e. the value programmed is N_Symbol - 1.
> + *
> + * Bspec: 71632
> + */
>  #define 
> PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(20, 16)
> -#define 
> PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK,val)
> +#define 
> PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION_MASK,(val)-1)
>  #define 
> PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(12
> , 8)
> -#define 
> PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP
> (PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, val)
> +#define 
> PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP
> (PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION_MASK, (val) - 1)
>  #define 
> PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK	REG_GENMASK(4, 0)
> -#define 
> PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK,val)
> +#define 
> PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION(val)	REG_FIELD_PREP(PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK,(val)-1)
>  
>  #endif /* __INTEL_PSR_REGS_H__ */

Re: [PATCH v6 18/18] drm/i915/alpm: Disallow ALPM for UHBR link rate

[Hogander, Jouni]

On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> DP2.1 ALPM is not supported on UHBR (128b/132b) link rates on the NVL
> platform. Reject the ALPM parameter computation for external DP
> running
> at a UHBR rate on display version 35, so that ALPM (and the Panel
> Replay
> and LOBF features that rely on it) is not enabled in that case. eDP
> is
> excluded so eDP ALPM keeps working at any link rate.
> 
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_alpm.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> b/drivers/gpu/drm/i915/display/intel_alpm.c
> index 84777c8d31bb..51805a6bca86 100644
> --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> @@ -453,6 +453,12 @@ bool intel_alpm_compute_params(struct intel_dp
> *intel_dp,
>  	int precharge = intel_dp_aux_fw_sync_len(intel_dp) -
> preamble;
>  	u8 max_wake_lines;
>  
> +	/* DP2.1 ALPM is not supported on UHBR (128b/132b) link
> rates on NVL. */
> +	if (DISPLAY_VER(display) == 35 &&
> +	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
> +	    intel_dp_is_uhbr(crtc_state))
> +		return false;
> +
>  	io_wake_time = max(precharge,
> io_buffer_wake_time(crtc_state)) +
>  		preamble + phy_wake + tfw_exit_latency;
>  	fast_wake_time = precharge + preamble + phy_wake +

I think more logical place for this would be in intel_alpm_is_possible.

BR,
Jouni Högander

Re: [PATCH v6 04/18] drm/i915/alpm: Enable debugfs for DP2.1

[Hogander, Jouni]

On Thu, 2026-10-01 at 11:32 +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Hogander, Jouni <jouni.hogander@intel.com>
> > Sent: Monday, September 28, 2026 4:53 PM
> > To: intel-xe@lists.freedesktop.org;
> > dri-devel@lists.freedesktop.org; Manna,
> > Animesh <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: Kandpal, Suraj <suraj.kandpal@intel.com>; Nikula, Jani
> > <jani.nikula@intel.com>
> > Subject: Re: [PATCH v6 04/18] drm/i915/alpm: Enable debugfs for
> > DP2.1
> > 
> > On Tue, 2026-09-15 at 23:34 +0530, Animesh Manna wrote:
> > > Enable ALPM debug info through lobf debug info.
> > > 
> > > v2: cosmetic change. [Suraj]
> > > v3: Use common api instead of DISPLAY_VER check in multiple
> > > places.
> > > [Jani]
> > > v4: Add display-version check as it dropped for EDP.
> > > 
> > > Cc: Jouni Högander <jouni.hogander@intel.com>
> > > Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_alpm.c | 6 ++++--
> > >  1 file changed, 4 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c
> > > b/drivers/gpu/drm/i915/display/intel_alpm.c
> > > index 4801fc6bade2..901493bb1448 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_alpm.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_alpm.c
> > > @@ -739,8 +739,10 @@ void intel_alpm_lobf_debugfs_add(struct
> > > intel_connector *connector)
> > >  	struct intel_display *display =
> > > to_intel_display(connector);
> > >  	struct dentry *root = connector->base.debugfs_entry;
> > > 
> > > -	if (DISPLAY_VER(display) < 20 ||
> > > -	    connector->base.connector_type !=
> > > DRM_MODE_CONNECTOR_eDP)
> > > +	if (DISPLAY_VER(display) < 20)
> > > +		return;
> > > +
> > > +	if (!intel_alpm_source_supported(connector))
> > >  		return;
> > > 
> > >  	debugfs_create_file("i915_edp_lobf_debug", 0644, root,
> > 
> > These are named as i915_edp_lobf_debug even if they are created on
> > DP
> > connector.
> 
> We have couple of options,
> i) rename to i915_lobf_debug, but backward compatibility will be
> broken.
> ii) create a new debugfs for dp - i915_dp_lobf_debug. Code
> duplication will be there.
> ii) as LOBF introduced first on edp to so DP will use existing edp-
> interface. 
> 
> Good to know your opinion, I see all these options have pros and
> cons.

I would vote for naming both as i915_lobf_debug. DP/eDP is already in
connector path. Code (IGT in practice) could first try new interface
and then if not found try old naming.

BR,
Jouni Högander

> 
> Regards,
> Animesh 
> > 
> > BR,
> > Jouni Högander
>