[PATCH 1/1] drm/i915: Do RPM Wake during GuC/HuC status read

[PATCH 1/1] drm/i915: Do RPM Wake during GuC/HuC status read

[Sagar Arun Kamble]

HUC_STATUS, GUC_STATUS, SOFT_SCRATCH  registers are read in debugfs.
This patch covers those accesses by RPM get/put.

Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3ae0656..639ed12 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2374,7 +2374,9 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data)
 	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
 		huc_fw->rsa_offset, huc_fw->rsa_size);
 
+	intel_runtime_pm_get(dev_priv);
 	seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
+	intel_runtime_pm_put(dev_priv);
 
 	return 0;
 }
@@ -2406,6 +2408,8 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
 	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
 		guc_fw->rsa_offset, guc_fw->rsa_size);
 
+	intel_runtime_pm_get(dev_priv);
+
 	tmp = I915_READ(GUC_STATUS);
 
 	seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
@@ -2419,6 +2423,8 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
 	for (i = 0; i < 16; i++)
 		seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
 
+	intel_runtime_pm_put(dev_priv);
+
 	return 0;
 }
 
-- 
1.9.1

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Re: [PATCH 1/1] drm/i915: Do RPM Wake during GuC/HuC status read

[Chris Wilson]

On Fri, Feb 03, 2017 at 01:00:18PM +0530, Sagar Arun Kamble wrote:
> HUC_STATUS, GUC_STATUS, SOFT_SCRATCH  registers are read in debugfs.
> This patch covers those accesses by RPM get/put.

See also I915_PARAM_HUC_STATUS.

> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Testcase? There's definitely at least one that should be covering this.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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✗ Fi.CI.BAT: failure for series starting with [1/1] drm/i915: Do RPM Wake during GuC/HuC status read

[Patchwork]

== Series Details ==

Series: series starting with [1/1] drm/i915: Do RPM Wake during GuC/HuC status read
URL   : https://patchwork.freedesktop.org/series/19034/
State : failure

== Summary ==

Series 19034v1 Series without cover letter
https://patchwork.freedesktop.org/api/1.0/series/19034/revisions/1/mbox/

Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> FAIL       (fi-skl-6770hq)

fi-bdw-5557u     total:247  pass:233  dwarn:0   dfail:0   fail:0   skip:14 
fi-bsw-n3050     total:247  pass:208  dwarn:0   dfail:0   fail:0   skip:39 
fi-bxt-j4205     total:247  pass:225  dwarn:0   dfail:0   fail:0   skip:22 
fi-bxt-t5700     total:78   pass:65   dwarn:0   dfail:0   fail:0   skip:12 
fi-byt-j1900     total:247  pass:220  dwarn:0   dfail:0   fail:0   skip:27 
fi-byt-n2820     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-hsw-4770      total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-hsw-4770r     total:247  pass:228  dwarn:0   dfail:0   fail:0   skip:19 
fi-ivb-3520m     total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-ivb-3770      total:247  pass:226  dwarn:0   dfail:0   fail:0   skip:21 
fi-kbl-7500u     total:247  pass:224  dwarn:0   dfail:0   fail:2   skip:21 
fi-skl-6260u     total:247  pass:234  dwarn:0   dfail:0   fail:0   skip:13 
fi-skl-6700hq    total:247  pass:227  dwarn:0   dfail:0   fail:0   skip:20 
fi-skl-6700k     total:247  pass:222  dwarn:4   dfail:0   fail:0   skip:21 
fi-skl-6770hq    total:247  pass:233  dwarn:0   dfail:0   fail:1   skip:13 
fi-snb-2520m     total:247  pass:216  dwarn:0   dfail:0   fail:0   skip:31 
fi-snb-2600      total:247  pass:215  dwarn:0   dfail:0   fail:0   skip:32 

0f01216949002d20b9dc6d300c82df5ffa59e9a7 drm-tip: 2017y-02m-02d-19h-49m-15s UTC integration manifest
d0d917c drm/i915: Do RPM Wake during GuC/HuC status read

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3686/
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Re: [PATCH 1/1] drm/i915: Do RPM Wake during GuC/HuC status read

[Kamble, Sagar A]

On 2/3/2017 1:07 PM, Chris Wilson wrote:
> On Fri, Feb 03, 2017 at 01:00:18PM +0530, Sagar Arun Kamble wrote:
>> HUC_STATUS, GUC_STATUS, SOFT_SCRATCH  registers are read in debugfs.
>> This patch covers those accesses by RPM get/put.
> See also I915_PARAM_HUC_STATUS.
Yes. Will update this. Daniel had commented that this was broken. Will 
float rev2
>
>> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Testcase? There's definitely at least one that should be covering this.
Did you mean testcase to verify GuC/HuC load status and param value?
> -Chris
>

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