[CI 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework

[CI 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework

[Mika Kahola]

This is v2 of [1], with the following changes

- Add support for eDP on C20 phy pll on PantherLake.

- As required by the above point use the non_tc_phy instead of c10phy term
  for the PLL hooks computing the state for, getting/putting etc. the PLLs
  of the non TypeC ports/outputs (on port A and B). Use the tc_phy instead
  of the c20phy term for the PLLs of all the other TypeC ports/outputs
  (port TC1-4).Support for eDP on C20 phy pll on PantherLake.

[1] https://lore.kernel.org/intel-xe/20251001082839.2585559-1-mika.kahola@intel.com/

Imre Deak (15):
  drm/i915/display: Factor out C10 msgbus access start/end helpers
  drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag
  drm/i915/display: Sanitize calculating C20 PLL state from tables
  drm/i915/display: Track the C20 PHY VDR state in the PLL state
  drm/i915/display: Move definition of Cx0 PHY functions earlier
  drm/i915/display: Add macro to get DDI port width from a register
    value
  drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL
    state
  drm/i915/display: Sanitize C10 PHY PLL SSC register setup
  drm/i915/display: Read out the Cx0 PHY SSC enabled state
  drm/i915/display: Determine Cx0 PLL DP mode from PLL state
  drm/i915/display: Determine Cx0 PLL port clock from PLL state
  drm/i915/display: Zero Cx0 PLL state before compute and HW readout
  drm/i915/display: Print additional Cx0 PLL HW state
  drm/i915/display: PLL verify debug state print
  drm/i915/display: Add Thunderbolt support

Mika Kahola (17):
  drm/i915/display: Rename TBT functions to be ICL specific
  drm/i915/display: Remove state verification
  drm/i915/display: PLL information for MTL+
  drm/i915/display: Update C10/C20 state calculation
  drm/i915/display: Compute plls for MTL+ platform
  drm/i915/display: MTL+ .get_dplls
  drm/i915/display: MTL+ .put_dplls
  drm/i915/display: Add .update_active_dpll
  drm/i915/display: Add .update_dpll_ref_clks
  drm/i915/display: Add .dump_hw_state
  drm/i915/display: Add .compare_hw_state
  drm/i915/display: Add .get_hw_state to MTL+ platforms
  drm/i915/display: Add .get_freq to MTL+ platforms
  drm/i915/display: Add .crtc_get_dpll hook
  drm/i915/display: Add .enable_clock on DDI for MTL+ platforms
  drm/i915/display: Get configuration for C10 and C20
  drm/i915/display: Enable dpll framework for MTL+

 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 896 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  25 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  81 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  32 -
 .../gpu/drm/i915/display/intel_display_regs.h |   7 +-
 drivers/gpu/drm/i915/display/intel_dpll.c     |  24 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 314 +++++-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   7 +
 .../drm/i915/display/intel_modeset_verify.c   |   1 -
 9 files changed, 893 insertions(+), 494 deletions(-)

-- 
2.34.1

[CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific

[Mika Kahola]

Rename pll functions to include ICL platform as these are
used from ICL onwards.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8ea96cc524a1..303f03b420ae 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3754,9 +3754,9 @@ static bool combo_pll_get_hw_state(struct intel_display *display,
 	return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);
 }
 
-static bool tbt_pll_get_hw_state(struct intel_display *display,
-				 struct intel_dpll *pll,
-				 struct intel_dpll_hw_state *dpll_hw_state)
+static bool icl_tbt_pll_get_hw_state(struct intel_display *display,
+				     struct intel_dpll *pll,
+				     struct intel_dpll_hw_state *dpll_hw_state)
 {
 	return icl_pll_get_hw_state(display, pll, dpll_hw_state, TBT_PLL_ENABLE);
 }
@@ -3985,9 +3985,9 @@ static void combo_pll_enable(struct intel_display *display,
 	/* DVFS post sequence would be here. See the comment above. */
 }
 
-static void tbt_pll_enable(struct intel_display *display,
-			   struct intel_dpll *pll,
-			   const struct intel_dpll_hw_state *dpll_hw_state)
+static void icl_tbt_pll_enable(struct intel_display *display,
+			       struct intel_dpll *pll,
+			       const struct intel_dpll_hw_state *dpll_hw_state)
 {
 	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
 
@@ -4070,8 +4070,8 @@ static void combo_pll_disable(struct intel_display *display,
 	icl_pll_disable(display, pll, enable_reg);
 }
 
-static void tbt_pll_disable(struct intel_display *display,
-			    struct intel_dpll *pll)
+static void icl_tbt_pll_disable(struct intel_display *display,
+				struct intel_dpll *pll)
 {
 	icl_pll_disable(display, pll, TBT_PLL_ENABLE);
 }
@@ -4143,10 +4143,10 @@ static const struct intel_dpll_funcs combo_pll_funcs = {
 	.get_freq = icl_ddi_combo_pll_get_freq,
 };
 
-static const struct intel_dpll_funcs tbt_pll_funcs = {
-	.enable = tbt_pll_enable,
-	.disable = tbt_pll_disable,
-	.get_hw_state = tbt_pll_get_hw_state,
+static const struct intel_dpll_funcs icl_tbt_pll_funcs = {
+	.enable = icl_tbt_pll_enable,
+	.disable = icl_tbt_pll_disable,
+	.get_hw_state = icl_tbt_pll_get_hw_state,
 	.get_freq = icl_ddi_tbt_pll_get_freq,
 };
 
@@ -4160,7 +4160,7 @@ static const struct intel_dpll_funcs mg_pll_funcs = {
 static const struct dpll_info icl_plls[] = {
 	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
 	  .is_alt_port_dpll = true, },
 	{ .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
@@ -4208,7 +4208,7 @@ static const struct intel_dpll_funcs dkl_pll_funcs = {
 static const struct dpll_info tgl_plls[] = {
 	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
 	  .is_alt_port_dpll = true, },
 	{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
@@ -4286,7 +4286,7 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
 static const struct dpll_info adlp_plls[] = {
 	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
 	  .is_alt_port_dpll = true, },
 	{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
-- 
2.34.1

[CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Factor out functions to begin and complete C10 PHY programming
sequences to make the code more concise.

v2: Rename msgbus_update_config() to more descriptive
    msg_bus_access_commit() (Jani)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 62 +++++++++++---------
 1 file changed, 35 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index a74c1be225ac..94ba7db2115a 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -449,6 +449,31 @@ static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
 	}
 }
 
+static void intel_c10_msgbus_access_begin(struct intel_encoder *encoder,
+					  u8 lane_mask)
+{
+	if (!intel_encoder_is_c10phy(encoder))
+		return;
+
+	intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1),
+		      0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+}
+
+static void intel_c10_msgbus_access_commit(struct intel_encoder *encoder,
+					   u8 lane_mask, bool master_lane)
+{
+	u8 val = C10_VDR_CTRL_UPDATE_CFG;
+
+	if (!intel_encoder_is_c10phy(encoder))
+		return;
+
+	if (master_lane)
+		val |= C10_VDR_CTRL_MASTER_LANE;
+
+	intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1),
+		      0, val, MB_WRITE_COMMITTED);
+}
+
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 				     const struct intel_crtc_state *crtc_state)
 {
@@ -472,9 +497,9 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 		return;
 	}
 
+	intel_c10_msgbus_access_begin(encoder, owned_lane_mask);
+
 	if (intel_encoder_is_c10phy(encoder)) {
-		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
-			      0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
 		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3),
 			      C10_CMN3_TXVBOOST_MASK,
 			      C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
@@ -513,9 +538,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 		      0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
 		      MB_WRITE_COMMITTED);
 
-	if (intel_encoder_is_c10phy(encoder))
-		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1),
-			      0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_commit(encoder, owned_lane_mask, false);
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
@@ -2119,9 +2142,7 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 	 * According to C10 VDR Register programming Sequence we need
 	 * to do this to read PHY internal registers from MsgBus.
 	 */
-	intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1),
-		      0, C10_VDR_CTRL_MSGBUS_ACCESS,
-		      MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_begin(encoder, lane);
 
 	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
 		pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
@@ -2140,9 +2161,7 @@ static void intel_c10_pll_program(struct intel_display *display,
 {
 	int i;
 
-	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
-		      0, C10_VDR_CTRL_MSGBUS_ACCESS,
-		      MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_begin(encoder, INTEL_CX0_BOTH_LANES);
 
 	/* Program the pll values only for the master lane */
 	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
@@ -2157,9 +2176,8 @@ static void intel_c10_pll_program(struct intel_display *display,
 	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH,
 		      C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10,
 		      MB_WRITE_COMMITTED);
-	intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),
-		      0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG,
-		      MB_WRITE_COMMITTED);
+
+	intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true);
 }
 
 static void intel_c10pll_dump_hw_state(struct intel_display *display,
@@ -2959,11 +2977,7 @@ static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_c
 	bool dp_alt_mode = intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
 	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
 
-	if (intel_encoder_is_c10phy(encoder))
-		intel_cx0_rmw(encoder, owned_lane_mask,
-			      PHY_C10_VDR_CONTROL(1), 0,
-			      C10_VDR_CTRL_MSGBUS_ACCESS,
-			      MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_begin(encoder, owned_lane_mask);
 
 	if (lane_reversal)
 		disables = REG_GENMASK8(3, 0) >> lane_count;
@@ -2988,11 +3002,7 @@ static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_c
 			      MB_WRITE_COMMITTED);
 	}
 
-	if (intel_encoder_is_c10phy(encoder))
-		intel_cx0_rmw(encoder, owned_lane_mask,
-			      PHY_C10_VDR_CONTROL(1), 0,
-			      C10_VDR_CTRL_UPDATE_CFG,
-			      MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_commit(encoder, owned_lane_mask, false);
 }
 
 static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask)
@@ -3260,9 +3270,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
-	if (intel_encoder_is_c10phy(encoder))
-		intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), 0,
-			      C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
+	intel_c10_msgbus_access_begin(encoder, owned_lane_mask);
 
 	for (i = 0; i < 4; i++) {
 		int tx = i % 2 + 1;
-- 
2.34.1

[CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Sanitize setting the Cx0 PLL use_c10 flag during state computation and
HW readout, making sure they happen the same way in the
intel_c{10,20}pll_calc_state() and intel_c{10,20}pll_readout_hw_state()
functions.

Follow-up changes will add more state computation/HW readout, this
change prepares for those as well.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 23 ++++++++++++--------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 94ba7db2115a..dd4cf335f3ae 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2130,12 +2130,15 @@ static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
 					const struct intel_c10pll_state *pll_state);
 
 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
-					  struct intel_c10pll_state *pll_state)
+					  struct intel_cx0pll_state *cx0pll_state)
 {
+	struct intel_c10pll_state *pll_state = &cx0pll_state->c10;
 	u8 lane = INTEL_CX0_LANE0;
 	intel_wakeref_t wakeref;
 	int i;
 
+	cx0pll_state->use_c10 = true;
+
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
 	/*
@@ -2361,6 +2364,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 	const struct intel_c20pll_state * const *tables;
 	int i;
 
+	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
+
 	/* try computed C20 HDMI tables before using consolidated tables */
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 		if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0)
@@ -2377,7 +2382,6 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 			intel_cx0pll_update_ssc(encoder,
 						&crtc_state->dpll_hw_state.cx0pll,
 						intel_crtc_has_dp_encoder(crtc_state));
-			crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
 			return 0;
 		}
 	}
@@ -2444,13 +2448,16 @@ static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder,
 }
 
 static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
-					  struct intel_c20pll_state *pll_state)
+					  struct intel_cx0pll_state *cx0pll_state)
 {
+	struct intel_c20pll_state *pll_state = &cx0pll_state->c20;
 	struct intel_display *display = to_intel_display(encoder);
 	bool cntx;
 	intel_wakeref_t wakeref;
 	int i;
 
+	cx0pll_state->use_c10 = false;
+
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
 	/* 1. Read current context selection */
@@ -3470,12 +3477,10 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 	if (pll_state->tbt_mode)
 		return;
 
-	if (intel_encoder_is_c10phy(encoder)) {
-		intel_c10pll_readout_hw_state(encoder, &pll_state->c10);
-		pll_state->use_c10 = true;
-	} else {
-		intel_c20pll_readout_hw_state(encoder, &pll_state->c20);
-	}
+	if (intel_encoder_is_c10phy(encoder))
+		intel_c10pll_readout_hw_state(encoder, pll_state);
+	else
+		intel_c20pll_readout_hw_state(encoder, pll_state);
 }
 
 static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
-- 
2.34.1

[CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

A follow up change adds a computation for the C20 PLL VDR state, which
is common to both the HDMI algorithmic and DP/HDMI table based method.
To prepare for that streamline the code. The C10 counterpart would
benefit from the same change, leave that for later adding a TODO
comment.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 68 ++++++++++++++------
 1 file changed, 47 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index dd4cf335f3ae..0dd367457f93 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2077,6 +2077,10 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 		pll_state->c10.pll[i] = 0;
 }
 
+/*
+ * TODO: Convert the following align with intel_c20pll_find_table() and
+ * intel_c20pll_calc_state_from_table().
+ */
 static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 					      const struct intel_c10pll_state * const *tables,
 					      bool is_dp, int port_clock,
@@ -2330,7 +2334,7 @@ static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
 }
 
 static const struct intel_c20pll_state * const *
-intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
+intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,
 			 struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -2358,35 +2362,57 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
 	return NULL;
 }
 
-static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
-				   struct intel_encoder *encoder)
+static const struct intel_c20pll_state *
+intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
+			 struct intel_encoder *encoder)
 {
 	const struct intel_c20pll_state * const *tables;
 	int i;
 
-	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
-
-	/* try computed C20 HDMI tables before using consolidated tables */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
-		if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0)
-			return 0;
-	}
-
 	tables = intel_c20_pll_tables_get(crtc_state, encoder);
 	if (!tables)
+		return NULL;
+
+	for (i = 0; tables[i]; i++)
+		if (crtc_state->port_clock == tables[i]->clock)
+			return tables[i];
+
+	return NULL;
+}
+
+static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_state,
+					      struct intel_encoder *encoder)
+{
+	const struct intel_c20pll_state *table;
+
+	table = intel_c20_pll_find_table(crtc_state, encoder);
+	if (!table)
 		return -EINVAL;
 
-	for (i = 0; tables[i]; i++) {
-		if (crtc_state->port_clock == tables[i]->clock) {
-			crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
-			intel_cx0pll_update_ssc(encoder,
-						&crtc_state->dpll_hw_state.cx0pll,
-						intel_crtc_has_dp_encoder(crtc_state));
-			return 0;
-		}
-	}
+	crtc_state->dpll_hw_state.cx0pll.c20 = *table;
 
-	return -EINVAL;
+	intel_cx0pll_update_ssc(encoder, &crtc_state->dpll_hw_state.cx0pll,
+				intel_crtc_has_dp_encoder(crtc_state));
+
+	return 0;
+}
+
+static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
+				   struct intel_encoder *encoder)
+{
+	int err = -ENOENT;
+
+	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
+
+	/* try computed C20 HDMI tables before using consolidated tables */
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		/* TODO: Update SSC state for HDMI as well */
+		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
+
+	if (err)
+		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
+
+	return err;
 }
 
 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
-- 
2.34.1

[CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

The Cx0 PLL enable programming needs to know if the PLL is in DP or HDMI
mode. The PLL manager framework doesn't pass the CRTC state to the PLL's
enable hook, so prepare here for the conversion to use the PLL manager
for Cx0 PHY PLLs by tracking the DP/HDMI mode in the PLL state.

This change has the advantage, that the VDR HW/SW state can be verified
now.

A follow up change will convert the PLL enable function to retrieve the
DP/HDMI mode parameter from the PLL state.

This also allows dropping the is_dp and port clock params from the
intel_c20_pll_program() function, since it can retrieve these now from
the PLL state.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 115 +++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   5 +
 2 files changed, 89 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 0dd367457f93..0ea9c33e4ce3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2362,6 +2362,76 @@ intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,
 	return NULL;
 }
 
+static u8 intel_c20_get_dp_rate(u32 clock);
+static u8 intel_c20_get_hdmi_rate(u32 clock);
+static bool is_hdmi_frl(u32 clock);
+static int intel_get_c20_custom_width(u32 clock, bool dp);
+
+static void intel_c20_calc_vdr_params(struct intel_c20pll_vdr_state *vdr, bool is_dp,
+				      int port_clock)
+{
+	vdr->custom_width = intel_get_c20_custom_width(port_clock, is_dp);
+
+	vdr->serdes_rate = 0;
+	vdr->hdmi_rate = 0;
+
+	if (is_dp) {
+		vdr->serdes_rate = PHY_C20_IS_DP |
+				   PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
+	} else {
+		if (is_hdmi_frl(port_clock))
+			vdr->serdes_rate = PHY_C20_IS_HDMI_FRL;
+
+		vdr->hdmi_rate = intel_c20_get_hdmi_rate(port_clock);
+	}
+}
+
+#define PHY_C20_SERDES_RATE_MASK	(PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL)
+
+static void intel_c20_readout_vdr_params(struct intel_encoder *encoder,
+					 struct intel_c20pll_vdr_state *vdr, bool *cntx)
+{
+	u8 serdes;
+
+	serdes = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE);
+	*cntx = serdes & PHY_C20_CONTEXT_TOGGLE;
+
+	vdr->custom_width = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_WIDTH) &
+			    PHY_C20_CUSTOM_WIDTH_MASK;
+
+	vdr->serdes_rate = serdes & PHY_C20_SERDES_RATE_MASK;
+	if (!(vdr->serdes_rate & PHY_C20_IS_DP))
+		vdr->hdmi_rate = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_HDMI_RATE) &
+				 PHY_C20_HDMI_RATE_MASK;
+	else
+		vdr->hdmi_rate = 0;
+}
+
+static void intel_c20_program_vdr_params(struct intel_encoder *encoder,
+					 const struct intel_c20pll_vdr_state *vdr,
+					 u8 owned_lane_mask)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	drm_WARN_ON(display->drm, vdr->custom_width & ~PHY_C20_CUSTOM_WIDTH_MASK);
+	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,
+		      PHY_C20_CUSTOM_WIDTH_MASK, vdr->custom_width,
+		      MB_WRITE_COMMITTED);
+
+	drm_WARN_ON(display->drm, vdr->serdes_rate & ~PHY_C20_SERDES_RATE_MASK);
+	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
+		      PHY_C20_SERDES_RATE_MASK, vdr->serdes_rate,
+		      MB_WRITE_COMMITTED);
+
+	if (vdr->serdes_rate & PHY_C20_IS_DP)
+		return;
+
+	drm_WARN_ON(display->drm, vdr->hdmi_rate & ~PHY_C20_HDMI_RATE_MASK);
+	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
+		      PHY_C20_HDMI_RATE_MASK, vdr->hdmi_rate,
+		      MB_WRITE_COMMITTED);
+}
+
 static const struct intel_c20pll_state *
 intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
 			 struct intel_encoder *encoder)
@@ -2400,19 +2470,26 @@ static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_stat
 static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 				   struct intel_encoder *encoder)
 {
+	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
 	int err = -ENOENT;
 
 	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
 
 	/* try computed C20 HDMI tables before using consolidated tables */
-	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+	if (!is_dp)
 		/* TODO: Update SSC state for HDMI as well */
 		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
 
 	if (err)
 		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
 
-	return err;
+	if (err)
+		return err;
+
+	intel_c20_calc_vdr_params(&crtc_state->dpll_hw_state.cx0pll.c20.vdr,
+				  is_dp, crtc_state->port_clock);
+
+	return 0;
 }
 
 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
@@ -2486,8 +2563,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
-	/* 1. Read current context selection */
-	cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
+	/* 1. Read VDR params and current context selection */
+	intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
 
 	/* Read Tx configuration */
 	for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
@@ -2676,11 +2753,9 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
 
 static void intel_c20_pll_program(struct intel_display *display,
 				  struct intel_encoder *encoder,
-				  const struct intel_c20pll_state *pll_state,
-				  bool is_dp, int port_clock)
+				  const struct intel_c20pll_state *pll_state)
 {
 	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
-	u8 serdes;
 	bool cntx;
 	int i;
 
@@ -2750,30 +2825,8 @@ static void intel_c20_pll_program(struct intel_display *display,
 	}
 
 	/* 4. Program custom width to match the link protocol */
-	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH,
-		      PHY_C20_CUSTOM_WIDTH_MASK,
-		      PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(port_clock, is_dp)),
-		      MB_WRITE_COMMITTED);
-
 	/* 5. For DP or 6. For HDMI */
-	serdes = 0;
-
-	if (is_dp)
-		serdes = PHY_C20_IS_DP |
-			 PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
-	else if (is_hdmi_frl(port_clock))
-		serdes = PHY_C20_IS_HDMI_FRL;
-
-	intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE,
-		      PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL,
-		      serdes,
-		      MB_WRITE_COMMITTED);
-
-	if (!is_dp)
-		intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
-			      PHY_C20_HDMI_RATE_MASK,
-			      intel_c20_get_hdmi_rate(port_clock),
-			      MB_WRITE_COMMITTED);
+	intel_c20_program_vdr_params(encoder, &pll_state->vdr, owned_lane_mask);
 
 	/*
 	 * 7. Write Vendor specific registers to toggle context setting to load
@@ -3098,7 +3151,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 	if (intel_encoder_is_c10phy(encoder))
 		intel_c10_pll_program(display, encoder, &pll_state->c10);
 	else
-		intel_c20_pll_program(display, encoder, &pll_state->c20, is_dp, port_clock);
+		intel_c20_pll_program(display, encoder, &pll_state->c20);
 
 	/*
 	 * 6. Program the enabled and disabled owned PHY lane
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index f131bdd1c975..43c7200050e9 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -255,6 +255,11 @@ struct intel_c20pll_state {
 		u16 mplla[10];
 		u16 mpllb[11];
 	};
+	struct intel_c20pll_vdr_state {
+		u8 custom_width;
+		u8 serdes_rate;
+		u8 hdmi_rate;
+	} vdr;
 };
 
 struct intel_cx0pll_state {
-- 
2.34.1

[CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Move the definitions of the
  intel_c10pll_calc_port_clock()
  intel_c20_get_dp_rate()
  intel_c20_get_hdmi_rate()
  is_hdmi_frl()
  is_dp2()
  intel_get_c20_custom_width()
functions earlier to avoid the forward declarations.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 232 +++++++++----------
 1 file changed, 112 insertions(+), 120 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 0ea9c33e4ce3..949727d3fc6d 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2131,7 +2131,31 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 }
 
 static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
-					const struct intel_c10pll_state *pll_state);
+					const struct intel_c10pll_state *pll_state)
+{
+	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
+	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
+	int tmpclk = 0;
+
+	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
+		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
+		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
+		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
+	}
+
+	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
+		      pll_state->pll[2]) / 2 + 16;
+
+	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
+	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
+
+	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
+				     DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
+				     10 << (tx_clk_div + 16));
+	tmpclk *= (hdmi_div ? 2 : 1);
+
+	return tmpclk;
+}
 
 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 					  struct intel_cx0pll_state *cx0pll_state)
@@ -2362,10 +2386,93 @@ intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,
 	return NULL;
 }
 
-static u8 intel_c20_get_dp_rate(u32 clock);
-static u8 intel_c20_get_hdmi_rate(u32 clock);
-static bool is_hdmi_frl(u32 clock);
-static int intel_get_c20_custom_width(u32 clock, bool dp);
+static u8 intel_c20_get_dp_rate(u32 clock)
+{
+	switch (clock) {
+	case 162000: /* 1.62 Gbps DP1.4 */
+		return 0;
+	case 270000: /* 2.7 Gbps DP1.4 */
+		return 1;
+	case 540000: /* 5.4 Gbps DP 1.4 */
+		return 2;
+	case 810000: /* 8.1 Gbps DP1.4 */
+		return 3;
+	case 216000: /* 2.16 Gbps eDP */
+		return 4;
+	case 243000: /* 2.43 Gbps eDP */
+		return 5;
+	case 324000: /* 3.24 Gbps eDP */
+		return 6;
+	case 432000: /* 4.32 Gbps eDP */
+		return 7;
+	case 1000000: /* 10 Gbps DP2.0 */
+		return 8;
+	case 1350000: /* 13.5 Gbps DP2.0 */
+		return 9;
+	case 2000000: /* 20 Gbps DP2.0 */
+		return 10;
+	case 648000: /* 6.48 Gbps eDP*/
+		return 11;
+	case 675000: /* 6.75 Gbps eDP*/
+		return 12;
+	default:
+		MISSING_CASE(clock);
+		return 0;
+	}
+}
+
+static u8 intel_c20_get_hdmi_rate(u32 clock)
+{
+	if (clock >= 25175 && clock <= 600000)
+		return 0;
+
+	switch (clock) {
+	case 300000: /* 3 Gbps */
+	case 600000: /* 6 Gbps */
+	case 1200000: /* 12 Gbps */
+		return 1;
+	case 800000: /* 8 Gbps */
+		return 2;
+	case 1000000: /* 10 Gbps */
+		return 3;
+	default:
+		MISSING_CASE(clock);
+		return 0;
+	}
+}
+
+static bool is_hdmi_frl(u32 clock)
+{
+	switch (clock) {
+	case 300000: /* 3 Gbps */
+	case 600000: /* 6 Gbps */
+	case 800000: /* 8 Gbps */
+	case 1000000: /* 10 Gbps */
+	case 1200000: /* 12 Gbps */
+		return true;
+	default:
+		return false;
+	}
+}
+
+static bool is_dp2(u32 clock)
+{
+	/* DP2.0 clock rates */
+	if (clock == 1000000 || clock == 1350000 || clock  == 2000000)
+		return true;
+
+	return false;
+}
+
+static int intel_get_c20_custom_width(u32 clock, bool dp)
+{
+	if (dp && is_dp2(clock))
+		return 2;
+	else if (is_hdmi_frl(clock))
+		return 1;
+	else
+		return 0;
+}
 
 static void intel_c20_calc_vdr_params(struct intel_c20pll_vdr_state *vdr, bool is_dp,
 				      int port_clock)
@@ -2654,84 +2761,6 @@ void intel_cx0pll_dump_hw_state(struct intel_display *display,
 		intel_c20pll_dump_hw_state(display, &hw_state->c20);
 }
 
-static u8 intel_c20_get_dp_rate(u32 clock)
-{
-	switch (clock) {
-	case 162000: /* 1.62 Gbps DP1.4 */
-		return 0;
-	case 270000: /* 2.7 Gbps DP1.4 */
-		return 1;
-	case 540000: /* 5.4 Gbps DP 1.4 */
-		return 2;
-	case 810000: /* 8.1 Gbps DP1.4 */
-		return 3;
-	case 216000: /* 2.16 Gbps eDP */
-		return 4;
-	case 243000: /* 2.43 Gbps eDP */
-		return 5;
-	case 324000: /* 3.24 Gbps eDP */
-		return 6;
-	case 432000: /* 4.32 Gbps eDP */
-		return 7;
-	case 1000000: /* 10 Gbps DP2.0 */
-		return 8;
-	case 1350000: /* 13.5 Gbps DP2.0 */
-		return 9;
-	case 2000000: /* 20 Gbps DP2.0 */
-		return 10;
-	case 648000: /* 6.48 Gbps eDP*/
-		return 11;
-	case 675000: /* 6.75 Gbps eDP*/
-		return 12;
-	default:
-		MISSING_CASE(clock);
-		return 0;
-	}
-}
-
-static u8 intel_c20_get_hdmi_rate(u32 clock)
-{
-	if (clock >= 25175 && clock <= 600000)
-		return 0;
-
-	switch (clock) {
-	case 300000: /* 3 Gbps */
-	case 600000: /* 6 Gbps */
-	case 1200000: /* 12 Gbps */
-		return 1;
-	case 800000: /* 8 Gbps */
-		return 2;
-	case 1000000: /* 10 Gbps */
-		return 3;
-	default:
-		MISSING_CASE(clock);
-		return 0;
-	}
-}
-
-static bool is_dp2(u32 clock)
-{
-	/* DP2.0 clock rates */
-	if (clock == 1000000 || clock == 1350000 || clock  == 2000000)
-		return true;
-
-	return false;
-}
-
-static bool is_hdmi_frl(u32 clock)
-{
-	switch (clock) {
-	case 300000: /* 3 Gbps */
-	case 600000: /* 6 Gbps */
-	case 800000: /* 8 Gbps */
-	case 1000000: /* 10 Gbps */
-	case 1200000: /* 12 Gbps */
-		return true;
-	default:
-		return false;
-	}
-}
-
 static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
 {
 	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
@@ -2741,16 +2770,6 @@ static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
 	return intel_tc_port_in_legacy_mode(intel_dig_port);
 }
 
-static int intel_get_c20_custom_width(u32 clock, bool dp)
-{
-	if (dp && is_dp2(clock))
-		return 2;
-	else if (is_hdmi_frl(clock))
-		return 1;
-	else
-		return 0;
-}
-
 static void intel_c20_pll_program(struct intel_display *display,
 				  struct intel_encoder *encoder,
 				  const struct intel_c20pll_state *pll_state)
@@ -2837,33 +2856,6 @@ static void intel_c20_pll_program(struct intel_display *display,
 		      MB_WRITE_COMMITTED);
 }
 
-static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
-					const struct intel_c10pll_state *pll_state)
-{
-	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
-	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
-	int tmpclk = 0;
-
-	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
-		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
-		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
-		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
-	}
-
-	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 |
-		      pll_state->pll[2]) / 2 + 16;
-
-	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]);
-	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
-
-	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
-				     DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
-				     10 << (tx_clk_div + 16));
-	tmpclk *= (hdmi_div ? 2 : 1);
-
-	return tmpclk;
-}
-
 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 					 const struct intel_cx0pll_state *pll_state,
 					 bool is_dp, int port_clock,
-- 
2.34.1

[CI 07/32] drm/i915/display: Add macro to get DDI port width from a register value

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

A follow-up change will need to retrieve the DDI port field from the
register value, add a macro for this. Make things symmetric with setting
the field in the register.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9d71e26a4fa2..c14d3caa73a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2349,8 +2349,13 @@ enum skl_power_gate {
 #define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)
 #define  DDI_A_4_LANES				REG_BIT(4)
 #define  DDI_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
+#define  DDI_PORT_WIDTH_ENCODE(width)		((width) == 3 ? 4 : (width) - 1)
+#define  DDI_PORT_WIDTH_DECODE(regval)		((regval) == 4 ? 3 : (regval) + 1)
 #define  DDI_PORT_WIDTH(width)			REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
-							       ((width) == 3 ? 4 : (width) - 1))
+							       DDI_PORT_WIDTH_ENCODE(width))
+#define  DDI_PORT_WIDTH_GET(regval)		DDI_PORT_WIDTH_DECODE(REG_FIELD_GET(DDI_PORT_WIDTH_MASK, \
+										    (regval)))
+
 #define  DDI_PORT_WIDTH_SHIFT			1
 #define  DDI_INIT_DISPLAY_DETECTED		REG_BIT(0)
 
-- 
2.34.1

[CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

The Cx0 PLL enable programming requires the enabled lane count. The PLL
manager framework doesn't pass the CRTC state to the PLL's enable hook,
so prepare here for the conversion to use the PLL manager, by tracking
the enabled lane count in the PLL state as well. This has the advantage,
that the enabled lane count can be verified against the PHY/PLL's
enabled TX lanes.

This also allows dropping the lane count param from the
__intel_cx0pll_enable() function, since it can retrieve this now from
the PLL state.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 55 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
 2 files changed, 49 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 949727d3fc6d..cc5aa38c3364 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -12,6 +12,7 @@
 #include "intel_alpm.h"
 #include "intel_cx0_phy.h"
 #include "intel_cx0_phy_regs.h"
+#include "intel_display_regs.h"
 #include "intel_ddi.h"
 #include "intel_ddi_buf_trans.h"
 #include "intel_de.h"
@@ -2083,7 +2084,7 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder,
  */
 static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 					      const struct intel_c10pll_state * const *tables,
-					      bool is_dp, int port_clock,
+					      bool is_dp, int port_clock, int lane_count,
 					      struct intel_cx0pll_state *pll_state)
 {
 	int i;
@@ -2093,7 +2094,9 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 			pll_state->c10 = *tables[i];
 			intel_cx0pll_update_ssc(encoder, pll_state, is_dp);
 			intel_c10pll_update_pll(encoder, pll_state);
+
 			pll_state->use_c10 = true;
+			pll_state->lane_count = lane_count;
 
 			return 0;
 		}
@@ -2114,7 +2117,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 
 	err = intel_c10pll_calc_state_from_table(encoder, tables,
 						 intel_crtc_has_dp_encoder(crtc_state),
-						 crtc_state->port_clock,
+						 crtc_state->port_clock, crtc_state->lane_count,
 						 &crtc_state->dpll_hw_state.cx0pll);
 
 	if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
@@ -2126,6 +2129,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 	intel_c10pll_update_pll(encoder,
 				&crtc_state->dpll_hw_state.cx0pll);
 	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
+	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
 
 	return 0;
 }
@@ -2157,6 +2161,37 @@ static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
 	return tmpclk;
 }
 
+static int readout_enabled_lane_count(struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	u8 enabled_tx_lane_count = 0;
+	int max_tx_lane_count;
+	int tx_lane;
+
+	/*
+	 * TODO: also check inactive TX lanes in all PHY lanes owned by the
+	 * display. For now checking only those PHY lane(s) which are owned
+	 * based on the active TX lane count (i.e.
+	 *   1,2 active TX lanes -> PHY lane#0
+	 *   3,4 active TX lanes -> PHY lane#0 and PHY lane#1).
+	 */
+	max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display, DDI_BUF_CTL(encoder->port)));
+	if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0))
+		max_tx_lane_count = roundup_pow_of_two(max_tx_lane_count);
+
+	for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) {
+		u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1;
+		int tx = tx_lane % 2 + 1;
+		u8 val;
+
+		val = intel_cx0_read(encoder, phy_lane_mask, PHY_CX0_TX_CONTROL(tx, 2));
+		if (!(val & CONTROL2_DISABLE_SINGLE_TX))
+			enabled_tx_lane_count++;
+	}
+
+	return enabled_tx_lane_count;
+}
+
 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 					  struct intel_cx0pll_state *cx0pll_state)
 {
@@ -2175,6 +2210,8 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 	 */
 	intel_c10_msgbus_access_begin(encoder, lane);
 
+	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
+
 	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
 		pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i));
 
@@ -2581,6 +2618,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 	int err = -ENOENT;
 
 	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
+	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
 
 	/* try computed C20 HDMI tables before using consolidated tables */
 	if (!is_dp)
@@ -2670,6 +2708,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 
 	wakeref = intel_cx0_phy_transaction_begin(encoder);
 
+	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
+
 	/* 1. Read VDR params and current context selection */
 	intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
 
@@ -3107,7 +3147,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
 
 static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 				  const struct intel_cx0pll_state *pll_state,
-				  bool is_dp, int port_clock, int lane_count)
+				  bool is_dp, int port_clock)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
@@ -3149,7 +3189,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * 6. Program the enabled and disabled owned PHY lane
 	 * transmitters over message bus
 	 */
-	intel_cx0_program_phy_lane(encoder, lane_count, lane_reversal);
+	intel_cx0_program_phy_lane(encoder, pll_state->lane_count, lane_reversal);
 
 	/*
 	 * 7. Follow the Display Voltage Frequency Switching - Sequence
@@ -3192,7 +3232,7 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 {
 	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
 			      intel_crtc_has_dp_encoder(crtc_state),
-			      crtc_state->port_clock, crtc_state->lane_count);
+			      crtc_state->port_clock);
 }
 
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
@@ -3723,6 +3763,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 	for_each_intel_encoder(display->drm, encoder) {
 		struct intel_cx0pll_state pll_state = {};
 		int port_clock = 162000;
+		int lane_count = 4;
 
 		if (!intel_encoder_is_dig_port(encoder))
 			continue;
@@ -3735,7 +3776,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 
 		if (intel_c10pll_calc_state_from_table(encoder,
 						       mtl_c10_edp_tables,
-						       true, port_clock,
+						       true, port_clock, lane_count,
 						       &pll_state) < 0) {
 			drm_WARN_ON(display->drm,
 				    "Unable to calc C10 state from the tables\n");
@@ -3746,7 +3787,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 			    "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
 			    encoder->base.base.id, encoder->base.name);
 
-		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock, 4);
+		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock);
 		intel_cx0pll_disable(encoder);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 43c7200050e9..839b1a98534f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -267,6 +267,7 @@ struct intel_cx0pll_state {
 		struct intel_c10pll_state c10;
 		struct intel_c20pll_state c20;
 	};
+	int lane_count;
 	bool ssc_enabled;
 	bool use_c10;
 	bool tbt_mode;
-- 
2.34.1

[CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Define the C10 PLL SSC register range via macros, so the HW/SW state of
these register can be verified by a follow-up change, reusing these
macros.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index cc5aa38c3364..b394b0397d62 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2064,6 +2064,9 @@ static void intel_cx0pll_update_ssc(struct intel_encoder *encoder,
 	}
 }
 
+#define C10_PLL_SSC_REG_START_IDX	4
+#define C10_PLL_SSC_REG_COUNT		5
+
 static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 				    struct intel_cx0pll_state *pll_state)
 {
@@ -2073,8 +2076,11 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 	if (pll_state->ssc_enabled)
 		return;
 
-	drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
-	for (i = 4; i < 9; i++)
+	drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) <
+				  C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT);
+	for (i = C10_PLL_SSC_REG_START_IDX;
+	     i < C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT;
+	     i++)
 		pll_state->c10.pll[i] = 0;
 }
 
-- 
2.34.1

[CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Read out the C10, C20 PHY PLLs SSC enabled state, so the PLL HW/SW state
verification can check this state as well.

C10 PHY PLLs program some PLL registers zeroed out for the non-SSC case,
while programming non-zero values to the same registers for the SSC
case, so check that these PLL registers being zero or non-zero matches
the PLL's overall SSC-enabled state (stored in the
intel_c10pll_state::ssc_enabled flag).

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 ++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b394b0397d62..f6b25291cd18 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2067,6 +2067,12 @@ static void intel_cx0pll_update_ssc(struct intel_encoder *encoder,
 #define C10_PLL_SSC_REG_START_IDX	4
 #define C10_PLL_SSC_REG_COUNT		5
 
+static bool intel_c10pll_ssc_enabled(const struct intel_c10pll_state *pll_state)
+{
+	return memchr_inv(&pll_state->pll[C10_PLL_SSC_REG_START_IDX],
+			  0, sizeof(pll_state->pll[0]) * C10_PLL_SSC_REG_COUNT);
+}
+
 static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 				    struct intel_cx0pll_state *pll_state)
 {
@@ -2198,10 +2204,20 @@ static int readout_enabled_lane_count(struct intel_encoder *encoder)
 	return enabled_tx_lane_count;
 }
 
+static bool readout_ssc_state(struct intel_encoder *encoder, bool is_mpll_b)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port)) &
+		(is_mpll_b ? XELPDP_SSC_ENABLE_PLLB : XELPDP_SSC_ENABLE_PLLA);
+}
+
 static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 					  struct intel_cx0pll_state *cx0pll_state)
 {
 	struct intel_c10pll_state *pll_state = &cx0pll_state->c10;
+	struct intel_display *display = to_intel_display(encoder);
+	enum phy phy = intel_encoder_to_phy(encoder);
 	u8 lane = INTEL_CX0_LANE0;
 	intel_wakeref_t wakeref;
 	int i;
@@ -2227,6 +2243,13 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 
 	pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
+
+	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
+	drm_WARN(display->drm,
+		 cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state),
+		 "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
+		 phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
+		 intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
 }
 
 static void intel_c10_pll_program(struct intel_display *display,
@@ -2772,6 +2795,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 	pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
 
 	intel_cx0_phy_transaction_end(encoder, wakeref);
+
+	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, intel_c20phy_use_mpllb(pll_state));
 }
 
 static void intel_c20pll_dump_hw_state(struct intel_display *display,
-- 
2.34.1

[CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

The Cx0 PLL enable programming needs to know if the PLL is in DP or HDMI
mode. The PLL manager framework doesn't pass the CRTC state to the PLL's
enable hook, so prepare here for the conversion to use the PLL manager
for Cx0 PHY PLLs by determining the DP/HDMI mode from the PLL state.

For C10 PHYs use the fact that the HDMI divider value in the PLL
registers are set if and only if the PLL is in HDMI mode.

For C20 PHYs use the DP mode flag programmed to the VDR SERDES register,
which is set if and only if the PLL is in DP mode.

Assert that the above PLL/VDR SERDES register values match the DP/HDMI
mode being configured already during state computation.

This also allows dropping the is_dp param from the
__intel_cx0pll_enable() function, since it can retrieve this now from
the PLL state.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 43 ++++++++++++++++----
 1 file changed, 36 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f6b25291cd18..f1216beb5581 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2090,6 +2090,24 @@ static void intel_c10pll_update_pll(struct intel_encoder *encoder,
 		pll_state->c10.pll[i] = 0;
 }
 
+static bool c10pll_state_is_dp(const struct intel_c10pll_state *pll_state)
+{
+	return !REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]);
+}
+
+static bool c20pll_state_is_dp(const struct intel_c20pll_state *pll_state)
+{
+	return pll_state->vdr.serdes_rate & PHY_C20_IS_DP;
+}
+
+static bool cx0pll_state_is_dp(const struct intel_cx0pll_state *pll_state)
+{
+	if (pll_state->use_c10)
+		return c10pll_state_is_dp(&pll_state->c10);
+
+	return c20pll_state_is_dp(&pll_state->c20);
+}
+
 /*
  * TODO: Convert the following align with intel_c20pll_find_table() and
  * intel_c20pll_calc_state_from_table().
@@ -2099,6 +2117,7 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 					      bool is_dp, int port_clock, int lane_count,
 					      struct intel_cx0pll_state *pll_state)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	int i;
 
 	for (i = 0; tables[i]; i++) {
@@ -2110,6 +2129,8 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 			pll_state->use_c10 = true;
 			pll_state->lane_count = lane_count;
 
+			drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&pll_state->c10));
+
 			return 0;
 		}
 	}
@@ -2120,6 +2141,8 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 				   struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(encoder);
+	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
 	const struct intel_c10pll_state * const *tables;
 	int err;
 
@@ -2127,8 +2150,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 	if (!tables)
 		return -EINVAL;
 
-	err = intel_c10pll_calc_state_from_table(encoder, tables,
-						 intel_crtc_has_dp_encoder(crtc_state),
+	err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp,
 						 crtc_state->port_clock, crtc_state->lane_count,
 						 &crtc_state->dpll_hw_state.cx0pll);
 
@@ -2143,6 +2165,9 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
 	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
 
+	drm_WARN_ON(display->drm,
+		    is_dp != c10pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c10));
+
 	return 0;
 }
 
@@ -2643,6 +2668,7 @@ static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_stat
 static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 				   struct intel_encoder *encoder)
 {
+	struct intel_display *display = to_intel_display(encoder);
 	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
 	int err = -ENOENT;
 
@@ -2663,6 +2689,9 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 	intel_c20_calc_vdr_params(&crtc_state->dpll_hw_state.cx0pll.c20.vdr,
 				  is_dp, crtc_state->port_clock);
 
+	drm_WARN_ON(display->drm,
+		    is_dp != c20pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c20));
+
 	return 0;
 }
 
@@ -2929,10 +2958,11 @@ static void intel_c20_pll_program(struct intel_display *display,
 
 static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
 					 const struct intel_cx0pll_state *pll_state,
-					 bool is_dp, int port_clock,
+					 int port_clock,
 					 bool lane_reversal)
 {
 	struct intel_display *display = to_intel_display(encoder);
+	bool is_dp = cx0pll_state_is_dp(pll_state);
 	u32 val = 0;
 
 	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
@@ -3178,7 +3208,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
 
 static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 				  const struct intel_cx0pll_state *pll_state,
-				  bool is_dp, int port_clock)
+				  int port_clock)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
@@ -3192,7 +3222,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * 1. Program PORT_CLOCK_CTL REGISTER to configure
 	 * clock muxes, gating and SSC
 	 */
-	intel_program_port_clock_ctl(encoder, pll_state, is_dp, port_clock, lane_reversal);
+	intel_program_port_clock_ctl(encoder, pll_state, port_clock, lane_reversal);
 
 	/* 2. Bring PHY out of reset. */
 	intel_cx0_phy_lane_reset(encoder, lane_reversal);
@@ -3262,7 +3292,6 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 				const struct intel_crtc_state *crtc_state)
 {
 	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
-			      intel_crtc_has_dp_encoder(crtc_state),
 			      crtc_state->port_clock);
 }
 
@@ -3818,7 +3847,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 			    "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
 			    encoder->base.base.id, encoder->base.name);
 
-		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock);
+		__intel_cx0pll_enable(encoder, &pll_state, port_clock);
 		intel_cx0pll_disable(encoder);
 	}
 }
-- 
2.34.1

[CI 12/32] drm/i915/display: Determine Cx0 PLL port clock from PLL state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

The port clock is tracked in the PLL state, so there is no need to pass
it separately to __intel_cx0pll_enable(). Drop the port clock function
param accordingly.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 +++++------------
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f1216beb5581..29bcfe8fb6f5 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3206,10 +3206,10 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
 	return val;
 }
 
-static void __intel_cx0pll_enable(struct intel_encoder *encoder,
-				  const struct intel_cx0pll_state *pll_state,
-				  int port_clock)
+static void intel_cx0pll_enable(struct intel_encoder *encoder,
+				const struct intel_cx0pll_state *pll_state)
 {
+	int port_clock = pll_state->use_c10 ? pll_state->c10.clock : pll_state->c20.clock;
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
@@ -3288,13 +3288,6 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
-static void intel_cx0pll_enable(struct intel_encoder *encoder,
-				const struct intel_crtc_state *crtc_state)
-{
-	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
-			      crtc_state->port_clock);
-}
-
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
@@ -3424,7 +3417,7 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable(encoder, crtc_state);
 	else
-		intel_cx0pll_enable(encoder, crtc_state);
+		intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll);
 }
 
 /*
@@ -3847,7 +3840,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
 			    "[ENCODER:%d:%s] Applying power saving workaround on disabled PLL\n",
 			    encoder->base.base.id, encoder->base.name);
 
-		__intel_cx0pll_enable(encoder, &pll_state, port_clock);
+		intel_cx0pll_enable(encoder, &pll_state);
 		intel_cx0pll_disable(encoder);
 	}
 }
-- 
2.34.1

[CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Ensure Cx0 pll state is initialized to zero before any computation or HW
readouts, to prevent leaving some parameter in the state uninitialized
in the actual compute/HW readout functions later.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 29bcfe8fb6f5..3418fc560faf 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2698,6 +2698,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
 int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder)
 {
+	memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state));
+
 	if (intel_encoder_is_c10phy(encoder))
 		return intel_c10pll_calc_state(crtc_state, encoder);
 	return intel_c20pll_calc_state(crtc_state, encoder);
@@ -3635,7 +3637,7 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state,
 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state)
 {
-	pll_state->use_c10 = false;
+	memset(pll_state, 0, sizeof(*pll_state));
 
 	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
 	if (pll_state->tbt_mode)
-- 
2.34.1

[CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Print all the Cx0 PLL state in the PLL state dumper.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 3418fc560faf..1e68a73c2ca8 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2311,8 +2311,8 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display,
 	unsigned int multiplier, tx_clk_div;
 
 	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
-	drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
-		    str_yes_no(fracen));
+	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
+		    hw_state->clock, str_yes_no(fracen));
 
 	if (fracen) {
 		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
@@ -2835,7 +2835,7 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
 {
 	int i;
 
-	drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
+	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state->clock);
 	drm_dbg_kms(display->drm,
 		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
 		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
@@ -2851,12 +2851,24 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
 		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
 			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
 				    hw_state->mplla[i]);
+
+		/* For full coverage, also print the additional PLL B entry. */
+		WARN_ON(i + 1 != ARRAY_SIZE(hw_state->mpllb));
+		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
 	}
+
+	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
+		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
 }
 
 void intel_cx0pll_dump_hw_state(struct intel_display *display,
 				const struct intel_cx0pll_state *hw_state)
 {
+	drm_dbg_kms(display->drm,
+		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
+		    hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
+		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
+
 	if (hw_state->use_c10)
 		intel_c10pll_dump_hw_state(display, &hw_state->c10);
 	else
-- 
2.34.1

[CI 15/32] drm/i915/display: Remove state verification

[Mika Kahola]

When pll's are moved to dpll framework we no longer
need Cx0 specific state verification as we can rely
on dpll state verification instead.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 114 ------------------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   2 -
 .../drm/i915/display/intel_modeset_verify.c   |   1 -
 3 files changed, 117 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1e68a73c2ca8..5332f33800e7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3617,35 +3617,6 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
 		return ICL_PORT_DPLL_DEFAULT;
 }
 
-static void intel_c10pll_state_verify(const struct intel_crtc_state *state,
-				      struct intel_crtc *crtc,
-				      struct intel_encoder *encoder,
-				      struct intel_c10pll_state *mpllb_hw_state)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10;
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
-		u8 expected = mpllb_sw_state->pll[i];
-
-		INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i] != expected,
-					 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)",
-					 crtc->base.base.id, crtc->base.name, i,
-					 expected, mpllb_hw_state->pll[i]);
-	}
-
-	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx != mpllb_sw_state->tx,
-				 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)",
-				 crtc->base.base.id, crtc->base.name,
-				 mpllb_sw_state->tx, mpllb_hw_state->tx);
-
-	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn != mpllb_sw_state->cmn,
-				 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)",
-				 crtc->base.base.id, crtc->base.name,
-				 mpllb_sw_state->cmn, mpllb_hw_state->cmn);
-}
-
 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state)
 {
@@ -3722,91 +3693,6 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
 	return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);
 }
 
-static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
-				      struct intel_crtc *crtc,
-				      struct intel_encoder *encoder,
-				      struct intel_c20pll_state *mpll_hw_state)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20;
-	bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
-	bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
-	int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);
-	int i;
-
-	INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock,
-				 "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)",
-				 crtc->base.base.id, crtc->base.name,
-				 mpll_sw_state->clock, mpll_hw_state->clock);
-
-	INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb != hw_use_mpllb,
-				 "[CRTC:%d:%s] mismatch in C20: Register MPLLB selection (expected %d, found %d)",
-				 crtc->base.base.id, crtc->base.name,
-				 sw_use_mpllb, hw_use_mpllb);
-
-	if (hw_use_mpllb) {
-		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {
-			INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i],
-						 "[CRTC:%d:%s] mismatch in C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",
-						 crtc->base.base.id, crtc->base.name, i,
-						 mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]);
-		}
-	} else {
-		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
-			INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i],
-						 "[CRTC:%d:%s] mismatch in C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",
-						 crtc->base.base.id, crtc->base.name, i,
-						 mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]);
-		}
-	}
-
-	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {
-		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] != mpll_sw_state->tx[i],
-					 "[CRTC:%d:%s] mismatch in C20: Register TX[%i] (expected 0x%04x, found 0x%04x)",
-					 crtc->base.base.id, crtc->base.name, i,
-					 mpll_sw_state->tx[i], mpll_hw_state->tx[i]);
-	}
-
-	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) {
-		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],
-					 "[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)",
-					 crtc->base.base.id, crtc->base.name, i,
-					 mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]);
-	}
-}
-
-void intel_cx0pll_state_verify(struct intel_atomic_state *state,
-			       struct intel_crtc *crtc)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_crtc_state *new_crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_encoder *encoder;
-	struct intel_cx0pll_state mpll_hw_state = {};
-
-	if (DISPLAY_VER(display) < 14)
-		return;
-
-	if (!new_crtc_state->hw.active)
-		return;
-
-	/* intel_get_crtc_new_encoder() only works for modeset/fastset commits */
-	if (!intel_crtc_needs_modeset(new_crtc_state) &&
-	    !intel_crtc_needs_fastset(new_crtc_state))
-		return;
-
-	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
-	intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);
-
-	if (mpll_hw_state.tbt_mode)
-		return;
-
-	if (intel_encoder_is_c10phy(encoder))
-		intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10);
-	else
-		intel_c20pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c20);
-}
-
 /*
  * WA 14022081154
  * The dedicated display PHYs reset to a power state that blocks S0ix, increasing idle
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c5a7b529955b..2b934b96af81 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -35,8 +35,6 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
 
 void intel_cx0pll_dump_hw_state(struct intel_display *display,
 				const struct intel_cx0pll_state *hw_state);
-void intel_cx0pll_state_verify(struct intel_atomic_state *state,
-			       struct intel_crtc *crtc);
 bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
 				   const struct intel_cx0pll_state *b);
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index f2f6b9d9afa1..22600bdbe8c5 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -245,7 +245,6 @@ void intel_modeset_verify_crtc(struct intel_atomic_state *state,
 	verify_crtc_state(state, crtc);
 	intel_dpll_state_verify(state, crtc);
 	intel_mpllb_state_verify(state, crtc);
-	intel_cx0pll_state_verify(state, crtc);
 }
 
 void intel_modeset_verify_disabled(struct intel_atomic_state *state)
-- 
2.34.1

[CI 16/32] drm/i915/display: PLL information for MTL+

[Mika Kahola]

To add MTL+ platforms as part of PLL framework, let's
start by adding PLL information and functions.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 303f03b420ae..a9d9b7113f12 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4306,6 +4306,25 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
 	.compare_hw_state = icl_compare_hw_state,
 };
 
+static const struct intel_dpll_funcs mtl_pll_funcs = {
+};
+
+static const struct dpll_info mtl_plls[] = {
+	{ .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
+	{ .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
+	/* TODO: Add TBT PLL */
+	{ .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
+	{ .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
+	{ .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
+	{ .name = "TC PLL 4", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4, },
+	{}
+};
+
+__maybe_unused
+static const struct intel_dpll_mgr mtl_pll_mgr = {
+	.dpll_info = mtl_plls,
+};
+
 /**
  * intel_dpll_init - Initialize DPLLs
  * @display: intel_display device
-- 
2.34.1

[CI 17/32] drm/i915/display: Update C10/C20 state calculation

[Mika Kahola]

For the dpll framework, the state must be computed into
a port PLL state, which is separate from the dpll_hw_state
in crtc_state.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 68 ++++++++++----------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h |  5 +-
 drivers/gpu/drm/i915/display/intel_dpll.c    |  2 +-
 3 files changed, 40 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 5332f33800e7..f5e6634a6389 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2034,7 +2034,7 @@ static const struct intel_c20pll_state * const mtl_c20_hdmi_tables[] = {
 };
 
 static const struct intel_c10pll_state * const *
-intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
+intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state,
 			struct intel_encoder *encoder)
 {
 	if (intel_crtc_has_dp_encoder(crtc_state)) {
@@ -2138,8 +2138,9 @@ static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
 	return -EINVAL;
 }
 
-static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
-				   struct intel_encoder *encoder)
+static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,
+				   struct intel_encoder *encoder,
+				   struct intel_dpll_hw_state *hw_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
@@ -2152,21 +2153,20 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
 
 	err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp,
 						 crtc_state->port_clock, crtc_state->lane_count,
-						 &crtc_state->dpll_hw_state.cx0pll);
+						 &hw_state->cx0pll);
 
 	if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		return err;
 
 	/* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed tables */
-	intel_snps_hdmi_pll_compute_c10pll(&crtc_state->dpll_hw_state.cx0pll.c10,
+	intel_snps_hdmi_pll_compute_c10pll(&hw_state->cx0pll.c10,
 					   crtc_state->port_clock);
-	intel_c10pll_update_pll(encoder,
-				&crtc_state->dpll_hw_state.cx0pll);
-	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
-	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
+	intel_c10pll_update_pll(encoder, &hw_state->cx0pll);
 
-	drm_WARN_ON(display->drm,
-		    is_dp != c10pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c10));
+	hw_state->cx0pll.use_c10 = true;
+	hw_state->cx0pll.lane_count = crtc_state->lane_count;
+
+	drm_WARN_ON(display->drm, is_dp != c10pll_state_is_dp(&hw_state->cx0pll.c10));
 
 	return 0;
 }
@@ -2355,7 +2355,7 @@ static bool is_arrowlake_s_by_host_bridge(void)
 	return pdev && IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id);
 }
 
-static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state)
+static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	u16 tx_misc;
@@ -2379,9 +2379,9 @@ static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state)
 		C20_PHY_TX_DCC_BYPASS | C20_PHY_TX_TERM_CTL(tx_term_ctrl));
 }
 
-static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
+static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state *crtc_state,
+					   struct intel_c20pll_state *pll_state)
 {
-	struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20;
 	u64 datarate;
 	u64 mpll_tx_clk_div;
 	u64 vco_freq_shift;
@@ -2648,8 +2648,9 @@ intel_c20_pll_find_table(const struct intel_crtc_state *crtc_state,
 	return NULL;
 }
 
-static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_state,
-					      struct intel_encoder *encoder)
+static int intel_c20pll_calc_state_from_table(const struct intel_crtc_state *crtc_state,
+					      struct intel_encoder *encoder,
+					      struct intel_cx0pll_state *pll_state)
 {
 	const struct intel_c20pll_state *table;
 
@@ -2657,52 +2658,53 @@ static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_stat
 	if (!table)
 		return -EINVAL;
 
-	crtc_state->dpll_hw_state.cx0pll.c20 = *table;
+	pll_state->c20 = *table;
 
-	intel_cx0pll_update_ssc(encoder, &crtc_state->dpll_hw_state.cx0pll,
-				intel_crtc_has_dp_encoder(crtc_state));
+	intel_cx0pll_update_ssc(encoder, pll_state, intel_crtc_has_dp_encoder(crtc_state));
 
 	return 0;
 }
 
-static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
-				   struct intel_encoder *encoder)
+static int intel_c20pll_calc_state(const struct intel_crtc_state *crtc_state,
+				   struct intel_encoder *encoder,
+				   struct intel_dpll_hw_state *hw_state)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
 	int err = -ENOENT;
 
-	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
-	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
+	hw_state->cx0pll.use_c10 = false;
+	hw_state->cx0pll.lane_count = crtc_state->lane_count;
 
 	/* try computed C20 HDMI tables before using consolidated tables */
 	if (!is_dp)
 		/* TODO: Update SSC state for HDMI as well */
-		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
+		err = intel_c20_compute_hdmi_tmds_pll(crtc_state, &hw_state->cx0pll.c20);
 
 	if (err)
-		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
+		err = intel_c20pll_calc_state_from_table(crtc_state, encoder,
+							 &hw_state->cx0pll);
 
 	if (err)
 		return err;
 
-	intel_c20_calc_vdr_params(&crtc_state->dpll_hw_state.cx0pll.c20.vdr,
+	intel_c20_calc_vdr_params(&hw_state->cx0pll.c20.vdr,
 				  is_dp, crtc_state->port_clock);
 
-	drm_WARN_ON(display->drm,
-		    is_dp != c20pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c20));
+	drm_WARN_ON(display->drm, is_dp != c20pll_state_is_dp(&hw_state->cx0pll.c20));
 
 	return 0;
 }
 
-int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
-			    struct intel_encoder *encoder)
+int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
+			    struct intel_encoder *encoder,
+			    struct intel_dpll_hw_state *hw_state)
 {
-	memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state));
+	memset(hw_state, 0, sizeof(*hw_state));
 
 	if (intel_encoder_is_c10phy(encoder))
-		return intel_c10pll_calc_state(crtc_state, encoder);
-	return intel_c20pll_calc_state(crtc_state, encoder);
+		return intel_c10pll_calc_state(crtc_state, encoder, hw_state);
+	return intel_c20pll_calc_state(crtc_state, encoder, hw_state);
 }
 
 static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 2b934b96af81..7b88c3fe9de1 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -16,6 +16,7 @@ struct intel_crtc;
 struct intel_crtc_state;
 struct intel_cx0pll_state;
 struct intel_display;
+struct intel_dpll_hw_state;
 struct intel_encoder;
 struct intel_hdmi;
 
@@ -27,7 +28,9 @@ enum icl_port_dpll_id
 intel_mtl_port_pll_type(struct intel_encoder *encoder,
 			const struct intel_crtc_state *crtc_state);
 
-int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder);
+int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
+			    struct intel_encoder *encoder,
+			    struct intel_dpll_hw_state *hw_state);
 void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state);
 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index f969c5399a51..7a48d6f0db10 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1220,7 +1220,7 @@ static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
 		intel_get_crtc_new_encoder(state, crtc_state);
 	int ret;
 
-	ret = intel_cx0pll_calc_state(crtc_state, encoder);
+	ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state->dpll_hw_state);
 	if (ret)
 		return ret;
 
-- 
2.34.1

[CI 18/32] drm/i915/display: Compute plls for MTL+ platform

[Mika Kahola]

To bring MTL+ platform aligned with dpll framework we
need to call and calculate pll state from dpll
framework.

v2: Rename mtl_compute_c10phy_dpll() to mtl_compute_non_tc_phy_dpll().
    The state is computed either for a C10 or on the PTL port B eDP on
    TypeC PHY case for a C20 PHY PLL. Hence refer to this case as
    "non_tc_phy" instead of "c10phy".

    Rename mtl_compute_c20phy_dplls() to mtl_compute_tc_phy_dplls() for
    symmetry with mtl_compute_non_tc_phy_dpll().

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index a9d9b7113f12..b6a5a519e936 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4320,9 +4320,78 @@ static const struct dpll_info mtl_plls[] = {
 	{}
 };
 
+/*
+ * Compute the state for either a C10 PHY PLL, or in the case of the PTL port B,
+ * eDP on TypeC PHY case for a C20 PHY PLL.
+ */
+static int mtl_compute_non_tc_phy_dpll(struct intel_atomic_state *state,
+				       struct intel_crtc *crtc,
+				       struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	int ret;
+
+	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
+	if (ret)
+		return ret;
+
+	/* this is mainly for the fastset check */
+	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
+
+	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
+							      &port_dpll->hw_state.cx0pll);
+
+	return 0;
+}
+
+static int mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
+				    struct intel_crtc *crtc,
+				    struct intel_encoder *encoder)
+{
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	const struct intel_crtc_state *old_crtc_state =
+		intel_atomic_get_old_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll;
+	int ret;
+
+	/* TODO: Add state calculation for TBT PLL */
+
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
+	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
+	if (ret)
+		return ret;
+
+	/* this is mainly for the fastset check */
+	if (old_crtc_state->intel_dpll &&
+	    old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
+		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
+	else
+		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
+
+	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
+							      &port_dpll->hw_state.cx0pll);
+
+	return 0;
+}
+
+static int mtl_compute_dplls(struct intel_atomic_state *state,
+			     struct intel_crtc *crtc,
+			     struct intel_encoder *encoder)
+{
+	if (intel_encoder_is_tc(encoder))
+		return mtl_compute_tc_phy_dplls(state, crtc, encoder);
+	else
+		return mtl_compute_non_tc_phy_dpll(state, crtc, encoder);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
+	.compute_dplls = mtl_compute_dplls,
 };
 
 /**
-- 
2.34.1

[CI 19/32] drm/i915/display: MTL+ .get_dplls

[Mika Kahola]

Add .get_dplls function pointer for MTL+ platforms
to support dpll framework. Reusing the ICL function
pointer.

v2: Getting configuration either for a C10 or on the PTL port B
    eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
    case as "non_tc_phy" instead of "c10phy".

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
 2 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index b6a5a519e936..c6af2816594d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -203,6 +203,22 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
 	return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
 }
 
+enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port)
+{
+	if (port >= PORT_TC1)
+		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
+
+	switch (port) {
+	case PORT_A:
+		return DPLL_ID_ICL_DPLL0;
+	case PORT_B:
+		return DPLL_ID_ICL_DPLL1;
+	default:
+		MISSING_CASE(port);
+		return DPLL_ID_ICL_DPLL0;
+	}
+}
+
 static i915_reg_t
 intel_combo_pll_enable_reg(struct intel_display *display,
 			   struct intel_dpll *pll)
@@ -3491,6 +3507,35 @@ static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
 	return ret;
 }
 
+/*
+ * Get the PLL for either a port using a C10 PHY PLL, or in the
+ * PTL port B eDP on TypeC PHY case, the PLL for a port using
+ * a C20 PHY PLL.
+ */
+static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state,
+				      struct intel_crtc *crtc,
+				      struct intel_encoder *encoder)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_crtc_state *crtc_state =
+		intel_atomic_get_new_crtc_state(state, crtc);
+	struct icl_port_dpll *port_dpll =
+		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+
+	port_dpll->pll = intel_find_dpll(state, crtc,
+					 &port_dpll->hw_state,
+					 BIT(mtl_port_to_pll_id(display, encoder->port)));
+	if (!port_dpll->pll)
+		return -EINVAL;
+
+	intel_reference_dpll(state, crtc,
+			     port_dpll->pll, &port_dpll->hw_state);
+
+	icl_update_active_dpll(state, crtc, encoder);
+
+	return 0;
+}
+
 static int icl_compute_dplls(struct intel_atomic_state *state,
 			     struct intel_crtc *crtc,
 			     struct intel_encoder *encoder)
@@ -4388,10 +4433,21 @@ static int mtl_compute_dplls(struct intel_atomic_state *state,
 		return mtl_compute_non_tc_phy_dpll(state, crtc, encoder);
 }
 
+static int mtl_get_dplls(struct intel_atomic_state *state,
+			 struct intel_crtc *crtc,
+			 struct intel_encoder *encoder)
+{
+	if (intel_encoder_is_tc(encoder))
+		return icl_get_tc_phy_dplls(state, crtc, encoder);
+	else
+		return mtl_get_non_tc_phy_dpll(state, crtc, encoder);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
 	.compute_dplls = mtl_compute_dplls,
+	.get_dplls = mtl_get_dplls,
 };
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 839b1a98534f..fbb6a45d565c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -439,6 +439,7 @@ bool intel_dpll_compare_hw_state(struct intel_display *display,
 				 const struct intel_dpll_hw_state *a,
 				 const struct intel_dpll_hw_state *b);
 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
+enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display, enum port port);
 bool intel_dpll_is_combophy(enum intel_dpll_id id);
 
 void intel_dpll_state_verify(struct intel_atomic_state *state,
-- 
2.34.1

[CI 20/32] drm/i915/display: MTL+ .put_dplls

[Mika Kahola]

Add .put_dplls function pointer to support MTL+ platforms
on dpll framework. Reusing ICL function pointer.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index c6af2816594d..cd612acad6e4 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4448,6 +4448,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
 	.compute_dplls = mtl_compute_dplls,
 	.get_dplls = mtl_get_dplls,
+	.put_dplls = icl_put_dplls,
 };
 
 /**
-- 
2.34.1

[CI 21/32] drm/i915/display: Add .update_active_dpll

[Mika Kahola]

For MTL+ platforms, add .update_active_dpll function pointer
to support dpll framework. Reusing ICL function pointer.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index cd612acad6e4..3b62943e2748 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4449,6 +4449,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.compute_dplls = mtl_compute_dplls,
 	.get_dplls = mtl_get_dplls,
 	.put_dplls = icl_put_dplls,
+	.update_active_dpll = icl_update_active_dpll,
 };
 
 /**
-- 
2.34.1

[CI 22/32] drm/i915/display: Add .update_dpll_ref_clks

[Mika Kahola]

Add .update_dpll_ref_clks function pointer to MTL+
platforms to support dpll framework. Reusing ICL
function pointer.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 3b62943e2748..01e649d66f08 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4450,6 +4450,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.get_dplls = mtl_get_dplls,
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
+	.update_ref_clks = icl_update_dpll_ref_clks,
 };
 
 /**
-- 
2.34.1

[CI 23/32] drm/i915/display: Add .dump_hw_state

[Mika Kahola]

Add .dump_hw_state function pointer for MTL+ platforms
to support dpll framework. While at it, switch to use
drm_printer structure to print hw state information.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 73 ++++++++++---------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  3 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  5 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 ++
 4 files changed, 48 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f5e6634a6389..e44dfda43d38 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2302,7 +2302,7 @@ static void intel_c10_pll_program(struct intel_display *display,
 	intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true);
 }
 
-static void intel_c10pll_dump_hw_state(struct intel_display *display,
+static void intel_c10pll_dump_hw_state(struct drm_printer *p,
 				       const struct intel_c10pll_state *hw_state)
 {
 	bool fracen;
@@ -2311,33 +2311,33 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display,
 	unsigned int multiplier, tx_clk_div;
 
 	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
-	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
-		    hw_state->clock, str_yes_no(fracen));
+	drm_printf(p, "c10pll_hw_state: clock: %d, fracen: %s, ",
+		   hw_state->clock, str_yes_no(fracen));
 
 	if (fracen) {
 		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
 		frac_rem =  hw_state->pll[14] << 8 | hw_state->pll[13];
 		frac_den =  hw_state->pll[10] << 8 | hw_state->pll[9];
-		drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",
-			    frac_quot, frac_rem, frac_den);
+		drm_printf(p, "quot: %u, rem: %u, den: %u,\n",
+			   frac_quot, frac_rem, frac_den);
 	}
 
 	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
 		      hw_state->pll[2]) / 2 + 16;
 	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
-	drm_dbg_kms(display->drm,
-		    "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
+	drm_printf(p,
+		   "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
 
-	drm_dbg_kms(display->drm, "c10pll_rawhw_state:");
-	drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
-		    hw_state->cmn);
+	drm_printf(p, "c10pll_rawhw_state:");
+	drm_printf(p, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
+		   hw_state->cmn);
 
 	BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
 	for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
-		drm_dbg_kms(display->drm,
-			    "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
-			    i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
-			    i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
+		drm_printf(p,
+			   "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
+			   i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
+			   i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
 }
 
 /*
@@ -2832,49 +2832,50 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
 	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, intel_c20phy_use_mpllb(pll_state));
 }
 
-static void intel_c20pll_dump_hw_state(struct intel_display *display,
+static void intel_c20pll_dump_hw_state(struct drm_printer *p,
 				       const struct intel_c20pll_state *hw_state)
 {
 	int i;
 
-	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state->clock);
-	drm_dbg_kms(display->drm,
-		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
-		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
-	drm_dbg_kms(display->drm,
-		    "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
-		    hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
+	drm_printf(p, "c20pll_hw_state: clock: %d\n", hw_state->clock);
+	drm_printf(p,
+		   "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
+		   hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
+	drm_printf(p,
+		   "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
+		   hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
 
 	if (intel_c20phy_use_mpllb(hw_state)) {
 		for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
-			drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
-				    hw_state->mpllb[i]);
+			drm_printf(p, "mpllb[%d] = 0x%.4x\n", i,
+				   hw_state->mpllb[i]);
 	} else {
 		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
-			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
-				    hw_state->mplla[i]);
+			drm_printf(p, "mplla[%d] = 0x%.4x\n", i,
+				   hw_state->mplla[i]);
 
 		/* For full coverage, also print the additional PLL B entry. */
 		WARN_ON(i + 1 != ARRAY_SIZE(hw_state->mpllb));
-		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
+		drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
 	}
 
-	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
-		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
+	drm_printf(p,
+		   "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
+		   hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
 }
 
-void intel_cx0pll_dump_hw_state(struct intel_display *display,
+void intel_cx0pll_dump_hw_state(struct drm_printer *p,
 				const struct intel_cx0pll_state *hw_state)
 {
-	drm_dbg_kms(display->drm,
-		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
-		    hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
-		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
+	drm_printf(p,
+		   "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
+		   hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
+		   str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
 
 	if (hw_state->use_c10)
-		intel_c10pll_dump_hw_state(display, &hw_state->c10);
+		intel_c10pll_dump_hw_state(p, &hw_state->c10);
 	else
-		intel_c20pll_dump_hw_state(display, &hw_state->c20);
+		intel_c20pll_dump_hw_state(p, &hw_state->c20);
 }
 
 static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 7b88c3fe9de1..03441138ec01 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -8,6 +8,7 @@
 
 #include <linux/types.h>
 
+struct drm_printer;
 enum icl_port_dpll_id;
 struct intel_atomic_state;
 struct intel_c10pll_state;
@@ -36,7 +37,7 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
 				 const struct intel_cx0pll_state *pll_state);
 
-void intel_cx0pll_dump_hw_state(struct intel_display *display,
+void intel_cx0pll_dump_hw_state(struct drm_printer *p,
 				const struct intel_cx0pll_state *hw_state);
 bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
 				   const struct intel_cx0pll_state *b);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a8b4619de347..2e927d6cd577 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4939,15 +4939,14 @@ pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
 			    const struct intel_cx0pll_state *a,
 			    const struct intel_cx0pll_state *b)
 {
-	struct intel_display *display = to_intel_display(crtc);
 	char *chipname = a->use_c10 ? "C10" : "C20";
 
 	pipe_config_mismatch(p, fastset, crtc, name, chipname);
 
 	drm_printf(p, "expected:\n");
-	intel_cx0pll_dump_hw_state(display, a);
+	intel_cx0pll_dump_hw_state(p, a);
 	drm_printf(p, "found:\n");
-	intel_cx0pll_dump_hw_state(display, b);
+	intel_cx0pll_dump_hw_state(p, b);
 }
 
 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 01e649d66f08..d4b58c426044 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4443,6 +4443,12 @@ static int mtl_get_dplls(struct intel_atomic_state *state,
 		return mtl_get_non_tc_phy_dpll(state, crtc, encoder);
 }
 
+static void mtl_dump_hw_state(struct drm_printer *p,
+			      const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	intel_cx0pll_dump_hw_state(p, &dpll_hw_state->cx0pll);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
@@ -4451,6 +4457,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.put_dplls = icl_put_dplls,
 	.update_active_dpll = icl_update_active_dpll,
 	.update_ref_clks = icl_update_dpll_ref_clks,
+	.dump_hw_state = mtl_dump_hw_state,
 };
 
 /**
-- 
2.34.1

[CI 24/32] drm/i915/display: Add .compare_hw_state

[Mika Kahola]

Add .compare_hw_state function pointer for MTL+ platforms
to support dpll framework.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d4b58c426044..d22771cf2ebd 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4449,6 +4449,15 @@ static void mtl_dump_hw_state(struct drm_printer *p,
 	intel_cx0pll_dump_hw_state(p, &dpll_hw_state->cx0pll);
 }
 
+static bool mtl_compare_hw_state(const struct intel_dpll_hw_state *_a,
+				 const struct intel_dpll_hw_state *_b)
+{
+	const struct intel_cx0pll_state *a = &_a->cx0pll;
+	const struct intel_cx0pll_state *b = &_b->cx0pll;
+
+	return intel_cx0pll_compare_hw_state(a, b);
+}
+
 __maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
@@ -4458,6 +4467,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.update_active_dpll = icl_update_active_dpll,
 	.update_ref_clks = icl_update_dpll_ref_clks,
 	.dump_hw_state = mtl_dump_hw_state,
+	.compare_hw_state = mtl_compare_hw_state,
 };
 
 /**
-- 
2.34.1

[CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms

[Mika Kahola]

Add .get_hw_state hook to MTL+ platforms for dpll framework.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  9 ++++--
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  2 +-
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++++
 3 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index e44dfda43d38..15ba3522b5b3 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3620,19 +3620,24 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
 		return ICL_PORT_DPLL_DEFAULT;
 }
 
-void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
+bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state)
 {
 	memset(pll_state, 0, sizeof(*pll_state));
 
 	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
 	if (pll_state->tbt_mode)
-		return;
+		return true;
+
+	if (!intel_cx0_pll_is_enabled(encoder))
+		return false;
 
 	if (intel_encoder_is_c10phy(encoder))
 		intel_c10pll_readout_hw_state(encoder, pll_state);
 	else
 		intel_c20pll_readout_hw_state(encoder, pll_state);
+
+	return true;
 }
 
 static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 03441138ec01..13eaf6d280ff 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -32,7 +32,7 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
 int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder,
 			    struct intel_dpll_hw_state *hw_state);
-void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
+bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 				   struct intel_cx0pll_state *pll_state);
 int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
 				 const struct intel_cx0pll_state *pll_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d22771cf2ebd..db6ae7bc63d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4351,7 +4351,36 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
 	.compare_hw_state = icl_compare_hw_state,
 };
 
+static struct intel_encoder *get_intel_encoder(struct intel_display *display,
+					       const struct intel_dpll *pll)
+{
+	struct intel_encoder *encoder;
+	enum intel_dpll_id mtl_id;
+
+	for_each_intel_encoder(display->drm, encoder) {
+		mtl_id = mtl_port_to_pll_id(display, encoder->port);
+
+		if (mtl_id == pll->info->id)
+			return encoder;
+	}
+
+	return NULL;
+}
+
+static bool mtl_pll_get_hw_state(struct intel_display *display,
+				 struct intel_dpll *pll,
+				 struct intel_dpll_hw_state *dpll_hw_state)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (!encoder)
+		return false;
+
+	return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state->cx0pll);
+}
+
 static const struct intel_dpll_funcs mtl_pll_funcs = {
+	.get_hw_state = mtl_pll_get_hw_state,
 };
 
 static const struct dpll_info mtl_plls[] = {
-- 
2.34.1

[CI 26/32] drm/i915/display: Add .get_freq to MTL+ platforms

[Mika Kahola]

Add .get_freq hook to support dpll framework for MTL+
platforms.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index db6ae7bc63d6..07bc99ae689c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4379,8 +4379,21 @@ static bool mtl_pll_get_hw_state(struct intel_display *display,
 	return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state->cx0pll);
 }
 
+static int mtl_pll_get_freq(struct intel_display *display,
+			    const struct intel_dpll *pll,
+			    const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (drm_WARN_ON(display->drm, !encoder))
+		return -EINVAL;
+
+	return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll);
+}
+
 static const struct intel_dpll_funcs mtl_pll_funcs = {
 	.get_hw_state = mtl_pll_get_hw_state,
+	.get_freq = mtl_pll_get_freq,
 };
 
 static const struct dpll_info mtl_plls[] = {
-- 
2.34.1

[CI 27/32] drm/i915/display: Add .crtc_get_dpll hook

[Mika Kahola]

Add .crtc_get_dpll function pointer to support MTL+
platforms.

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 7a48d6f0db10..46ae05976191 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1693,6 +1693,7 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
 
 static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
 	.crtc_compute_clock = mtl_crtc_compute_clock,
+	.crtc_get_dpll = hsw_crtc_get_dpll,
 };
 
 static const struct intel_dpll_global_funcs dg2_dpll_funcs = {
-- 
2.34.1

[CI 28/32] drm/i915/display: PLL verify debug state print

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Print out hw and sw pll states for better debugging support.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 07bc99ae689c..6cc85a9a781f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4882,11 +4882,18 @@ verify_single_dpll_state(struct intel_display *display,
 				 "%s: pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
 				 pll->info->name, pipe_mask, pll->state.pipe_mask);
 
-	INTEL_DISPLAY_STATE_WARN(display,
-				 pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
-						   sizeof(dpll_hw_state)),
-				 "%s: pll hw state mismatch\n",
-				 pll->info->name);
+	if (INTEL_DISPLAY_STATE_WARN(display,
+				     pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
+						       sizeof(dpll_hw_state)),
+				     "%s: pll hw state mismatch\n",
+				     pll->info->name)) {
+		struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL);
+
+		drm_printf(&p, "PLL %s HW state:\n", pll->info->name);
+		intel_dpll_dump_hw_state(display, &p, &dpll_hw_state);
+		drm_printf(&p, "PLL %s SW state:\n", pll->info->name);
+		intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
+	}
 }
 
 static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
-- 
2.34.1

[CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms

[Mika Kahola]

To enable pll clock on DDI we need to move part of the
pll enabling sequence to a ddi clock enabling function.

Simlilarly, we do the pll disabling sequence.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 34 +++++++++++++------
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  7 +++-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  6 ++--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 25 ++++++++++++++
 4 files changed, 58 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 15ba3522b5b3..b82a1f891eae 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3301,7 +3301,6 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	 * Frequency Change. We handle this step in bxt_set_cdclk().
 	 */
 
-	/* TODO: enable TBT-ALT mode */
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
@@ -3367,8 +3366,7 @@ static int intel_mtl_tbt_clock_select(struct intel_display *display,
 	}
 }
 
-static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
-				     const struct intel_crtc_state *crtc_state)
+static void intel_mtl_tbt_pll_enable_clock(struct intel_encoder *encoder, int port_clock)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
@@ -3382,7 +3380,7 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
 
 	mask = XELPDP_DDI_CLOCK_SELECT_MASK(display);
 	val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
-					    intel_mtl_tbt_clock_select(display, crtc_state->port_clock));
+					    intel_mtl_tbt_clock_select(display, port_clock));
 
 	mask |= XELPDP_FORWARD_CLOCK_UNGATE;
 	val |= XELPDP_FORWARD_CLOCK_UNGATE;
@@ -3423,18 +3421,26 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
 	 * clock frequency.
 	 */
 	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
-		       crtc_state->port_clock);
+		       port_clock);
 }
 
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
-			  const struct intel_crtc_state *crtc_state)
+			  struct intel_dpll *pll,
+			  const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	intel_cx0pll_enable(encoder, &dpll_hw_state->cx0pll);
+}
+
+void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
-		intel_mtl_tbt_pll_enable(encoder, crtc_state);
+		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
 	else
-		intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll);
+		/* TODO: remove when PLL mgr is in place. */
+		intel_mtl_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state);
 }
 
 /*
@@ -3550,7 +3556,7 @@ static bool intel_cx0_pll_is_enabled(struct intel_encoder *encoder)
 			     intel_cx0_get_pclk_pll_request(lane);
 }
 
-static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
+static void intel_mtl_tbt_pll_disable_clock(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 	enum phy phy = intel_encoder_to_phy(encoder);
@@ -3590,13 +3596,19 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
 }
 
 void intel_mtl_pll_disable(struct intel_encoder *encoder)
+{
+	intel_cx0pll_disable(encoder);
+}
+
+void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
 {
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
-		intel_mtl_tbt_pll_disable(encoder);
+		intel_mtl_tbt_pll_disable_clock(encoder);
 	else
-		intel_cx0pll_disable(encoder);
+		/* TODO: remove when PLL mgr is in place. */
+		intel_mtl_pll_disable(encoder);
 }
 
 enum icl_port_dpll_id
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 13eaf6d280ff..13fa001129f7 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -17,17 +17,22 @@ struct intel_crtc;
 struct intel_crtc_state;
 struct intel_cx0pll_state;
 struct intel_display;
+struct intel_dpll;
 struct intel_dpll_hw_state;
 struct intel_encoder;
 struct intel_hdmi;
 
 bool intel_encoder_is_c10phy(struct intel_encoder *encoder);
 void intel_mtl_pll_enable(struct intel_encoder *encoder,
-			  const struct intel_crtc_state *crtc_state);
+			  struct intel_dpll *pll,
+			  const struct intel_dpll_hw_state *dpll_hw_state);
 void intel_mtl_pll_disable(struct intel_encoder *encoder);
 enum icl_port_dpll_id
 intel_mtl_port_pll_type(struct intel_encoder *encoder,
 			const struct intel_crtc_state *crtc_state);
+void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
+				const struct intel_crtc_state *crtc_state);
+void intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
 
 int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
 			    struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 870140340342..d0bfa7f397dc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -88,6 +88,8 @@
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 
+struct intel_dpll;
+
 static const u8 index_to_dp_signal_levels[] = {
 	[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
 	[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
@@ -5232,8 +5234,8 @@ void intel_ddi_init(struct intel_display *display,
 	encoder->pipe_mask = ~0;
 
 	if (DISPLAY_VER(display) >= 14) {
-		encoder->enable_clock = intel_mtl_pll_enable;
-		encoder->disable_clock = intel_mtl_pll_disable;
+		encoder->enable_clock = intel_mtl_pll_enable_clock;
+		encoder->disable_clock = intel_mtl_pll_disable_clock;
 		encoder->port_pll_type = intel_mtl_port_pll_type;
 		encoder->get_config = mtl_ddi_get_config;
 	} else if (display->platform.dg2) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 6cc85a9a781f..8220ef69f685 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4391,7 +4391,32 @@ static int mtl_pll_get_freq(struct intel_display *display,
 	return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state->cx0pll);
 }
 
+static void mtl_pll_enable(struct intel_display *display,
+			   struct intel_dpll *pll,
+			   const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (drm_WARN_ON(display->drm, !encoder))
+		return;
+
+	intel_mtl_pll_enable(encoder, pll, dpll_hw_state);
+}
+
+static void mtl_pll_disable(struct intel_display *display,
+			    struct intel_dpll *pll)
+{
+	struct intel_encoder *encoder = get_intel_encoder(display, pll);
+
+	if (drm_WARN_ON(display->drm, !encoder))
+		return;
+
+	intel_mtl_pll_disable(encoder);
+}
+
 static const struct intel_dpll_funcs mtl_pll_funcs = {
+	.enable = mtl_pll_enable,
+	.disable = mtl_pll_disable,
 	.get_hw_state = mtl_pll_get_hw_state,
 	.get_freq = mtl_pll_get_freq,
 };
-- 
2.34.1

[CI 30/32] drm/i915/display: Get configuration for C10 and C20

[Mika Kahola]

For DDI initialization get configuration for C10 and C20
chips.

v2: Getting configuration either for a C10 or on the PTL port B
    eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
    case as "non_tc_phy" instead of "c10phy".

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 81 ++++++++++++++++++++++--
 1 file changed, 75 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d0bfa7f397dc..f554921f59a3 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4255,6 +4255,77 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder,
 	intel_ddi_get_config(encoder, crtc_state);
 }
 
+static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
+{
+	return pll->info->id == DPLL_ID_ICL_TBTPLL;
+}
+
+static void mtl_ddi_cx0_get_config(struct intel_encoder *encoder,
+				   struct intel_crtc_state *crtc_state,
+				   enum icl_port_dpll_id port_dpll_id,
+				   enum intel_dpll_id pll_id)
+{
+	struct intel_display *display = to_intel_display(encoder);
+	struct icl_port_dpll *port_dpll;
+	struct intel_dpll *pll;
+	bool pll_active;
+
+	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
+	pll = intel_get_dpll_by_id(display, pll_id);
+
+	if (drm_WARN_ON(display->drm, !pll))
+		return;
+
+	port_dpll->pll = pll;
+	pll_active = intel_dpll_get_hw_state(display, pll, &port_dpll->hw_state);
+	drm_WARN_ON(display->drm, !pll_active);
+
+	icl_set_active_port_dpll(crtc_state, port_dpll_id);
+
+	if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))
+		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
+	else
+		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,
+							     &crtc_state->dpll_hw_state);
+
+	intel_ddi_get_config(encoder, crtc_state);
+}
+
+/*
+ * Get the configuration for either a port using a C10 PHY PLL, or in the case of
+ * the PTL port B eDP on TypeC PHY case the configuration of a port using a C20
+ * PHY PLL.
+ */
+static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
+					     struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	/* TODO: Remove when the PLL manager is in place. */
+	mtl_ddi_get_config(encoder, crtc_state);
+	return;
+
+	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
+			       mtl_port_to_pll_id(display, encoder->port));
+}
+
+static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
+				      struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(encoder);
+
+	/* TODO: Remove when the PLL manager is in place. */
+	mtl_ddi_get_config(encoder, crtc_state);
+	return;
+
+	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
+		mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
+				       DPLL_ID_ICL_TBTPLL);
+	else
+		mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_MG_PHY,
+				       mtl_port_to_pll_id(display, encoder->port));
+}
+
 static void dg2_ddi_get_config(struct intel_encoder *encoder,
 				struct intel_crtc_state *crtc_state)
 {
@@ -4292,11 +4363,6 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
 	intel_ddi_get_config(encoder, crtc_state);
 }
 
-static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
-{
-	return pll->info->id == DPLL_ID_ICL_TBTPLL;
-}
-
 static enum icl_port_dpll_id
 icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
 			 const struct intel_crtc_state *crtc_state)
@@ -5237,7 +5303,10 @@ void intel_ddi_init(struct intel_display *display,
 		encoder->enable_clock = intel_mtl_pll_enable_clock;
 		encoder->disable_clock = intel_mtl_pll_disable_clock;
 		encoder->port_pll_type = intel_mtl_port_pll_type;
-		encoder->get_config = mtl_ddi_get_config;
+		if (intel_encoder_is_tc(encoder))
+			encoder->get_config = mtl_ddi_tc_phy_get_config;
+		else
+			encoder->get_config = mtl_ddi_non_tc_phy_get_config;
 	} else if (display->platform.dg2) {
 		encoder->enable_clock = intel_mpllb_enable;
 		encoder->disable_clock = intel_mpllb_disable;
-- 
2.34.1

[CI 31/32] drm/i915/display: Add Thunderbolt support

[Mika Kahola]

From: Imre Deak <imre.deak@intel.com>

Add the PLL hooks for the TBT PLL on MTL+. These are simple stubs
similarly to the TBT PLL on earlier platforms, since this PLL is always
on from the display POV - so no PLL enable/disable programming is
required as opposed to the non-TBT PLLs - and the clocks for different
link rates are enabled/disabled at a different level, via the
intel_encoder::enable_clock()/disable_clock() interface.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 18 +++++++++
 drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  6 +++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 37 ++++++++++++++++++-
 3 files changed, 59 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index b82a1f891eae..432cdf56a6ed 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3304,6 +3304,24 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
 	intel_cx0_phy_transaction_end(encoder, wakeref);
 }
 
+void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state)
+{
+	memset(hw_state, 0, sizeof(*hw_state));
+
+	hw_state->cx0pll.tbt_mode = true;
+}
+
+bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
+					struct intel_dpll *pll,
+					struct intel_dpll_hw_state *hw_state)
+{
+	memset(hw_state, 0, sizeof(*hw_state));
+
+	hw_state->cx0pll.tbt_mode = true;
+
+	return true;
+}
+
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 13fa001129f7..bfd69029e2b4 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -48,7 +48,13 @@ bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
 				   const struct intel_cx0pll_state *b);
 void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
 				     const struct intel_crtc_state *crtc_state);
+
+void intel_mtl_tbt_pll_calc_state(struct intel_dpll_hw_state *hw_state);
+bool intel_mtl_tbt_pll_readout_hw_state(struct intel_display *display,
+					struct intel_dpll *pll,
+					struct intel_dpll_hw_state *hw_state);
 int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
+
 void intel_cx0_pll_power_save_wa(struct intel_display *display);
 void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
 				 const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 8220ef69f685..ddc763d89aac 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4421,10 +4421,42 @@ static const struct intel_dpll_funcs mtl_pll_funcs = {
 	.get_freq = mtl_pll_get_freq,
 };
 
+static void mtl_tbt_pll_enable(struct intel_display *display,
+			       struct intel_dpll *pll,
+			       const struct intel_dpll_hw_state *hw_state)
+{
+}
+
+static void mtl_tbt_pll_disable(struct intel_display *display,
+				struct intel_dpll *pll)
+{
+}
+
+static int mtl_tbt_pll_get_freq(struct intel_display *display,
+				const struct intel_dpll *pll,
+				const struct intel_dpll_hw_state *dpll_hw_state)
+{
+	/*
+	 * The PLL outputs multiple frequencies at the same time, selection is
+	 * made at DDI clock mux level.
+	 */
+	drm_WARN_ON(display->drm, 1);
+
+	return 0;
+}
+
+static const struct intel_dpll_funcs mtl_tbt_pll_funcs = {
+	.enable = mtl_tbt_pll_enable,
+	.disable = mtl_tbt_pll_disable,
+	.get_hw_state = intel_mtl_tbt_pll_readout_hw_state,
+	.get_freq = mtl_tbt_pll_get_freq,
+};
+
 static const struct dpll_info mtl_plls[] = {
 	{ .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
 	{ .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
-	/* TODO: Add TBT PLL */
+	{ .name = "TBT PLL", .funcs = &mtl_tbt_pll_funcs, .id = DPLL_ID_ICL_TBTPLL,
+	  .is_alt_port_dpll = true, .always_on = true },
 	{ .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1, },
 	{ .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2, },
 	{ .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3, },
@@ -4470,7 +4502,8 @@ static int mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
 	struct icl_port_dpll *port_dpll;
 	int ret;
 
-	/* TODO: Add state calculation for TBT PLL */
+	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
+	intel_mtl_tbt_pll_calc_state(&port_dpll->hw_state);
 
 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
 	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
-- 
2.34.1

[CI 32/32] drm/i915/display: Enable dpll framework for MTL+

[Mika Kahola]

Now that MTL+ platforms are supported by dpll framework
we can remove a separate check for hw comparison and
rely solely on dpll framework hw comparison.

Finally, we have all required hooks in place so we can
initialize the PLL manager for MTL+ platforms and remove
the redirections to the legacy code paths from the following
interfaces:

* intel_encoder::clock_enable/disable()
* intel_encoder::get_config()
* intel_dpll_funcs::get_hw_state()
* intel_ddi_update_active_dpll()
* pipe_config_pll_mismatch()

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 10 ------
 drivers/gpu/drm/i915/display/intel_ddi.c      | 26 ++--------------
 drivers/gpu/drm/i915/display/intel_display.c  | 31 -------------------
 drivers/gpu/drm/i915/display/intel_dpll.c     | 23 +-------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  5 +--
 5 files changed, 6 insertions(+), 89 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 432cdf56a6ed..2005a3a93f74 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -3456,9 +3456,6 @@ void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock);
-	else
-		/* TODO: remove when PLL mgr is in place. */
-		intel_mtl_pll_enable(encoder, NULL, &crtc_state->dpll_hw_state);
 }
 
 /*
@@ -3624,9 +3621,6 @@ void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
 
 	if (intel_tc_port_in_tbt_alt_mode(dig_port))
 		intel_mtl_tbt_pll_disable_clock(encoder);
-	else
-		/* TODO: remove when PLL mgr is in place. */
-		intel_mtl_pll_disable(encoder);
 }
 
 enum icl_port_dpll_id
@@ -3655,10 +3649,6 @@ bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
 {
 	memset(pll_state, 0, sizeof(*pll_state));
 
-	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
-	if (pll_state->tbt_mode)
-		return true;
-
 	if (!intel_cx0_pll_is_enabled(encoder))
 		return false;
 
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index f554921f59a3..7a981b11b029 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3667,8 +3667,7 @@ void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_crtc *pipe_crtc;
 
-	/* FIXME: Add MTL pll_mgr */
-	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
+	if (!intel_encoder_is_tc(encoder))
 		return;
 
 	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
@@ -4242,19 +4241,6 @@ void intel_ddi_get_clock(struct intel_encoder *encoder,
 						     &crtc_state->dpll_hw_state);
 }
 
-static void mtl_ddi_get_config(struct intel_encoder *encoder,
-			       struct intel_crtc_state *crtc_state)
-{
-	intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll);
-
-	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
-		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
-	else
-		crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
-
-	intel_ddi_get_config(encoder, crtc_state);
-}
-
 static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
 {
 	return pll->info->id == DPLL_ID_ICL_TBTPLL;
@@ -4301,10 +4287,6 @@ static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 
-	/* TODO: Remove when the PLL manager is in place. */
-	mtl_ddi_get_config(encoder, crtc_state);
-	return;
-
 	mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
 			       mtl_port_to_pll_id(display, encoder->port));
 }
@@ -4314,10 +4296,6 @@ static void mtl_ddi_tc_phy_get_config(struct intel_encoder *encoder,
 {
 	struct intel_display *display = to_intel_display(encoder);
 
-	/* TODO: Remove when the PLL manager is in place. */
-	mtl_ddi_get_config(encoder, crtc_state);
-	return;
-
 	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
 		mtl_ddi_cx0_get_config(encoder, crtc_state, ICL_PORT_DPLL_DEFAULT,
 				       DPLL_ID_ICL_TBTPLL);
@@ -5302,7 +5280,7 @@ void intel_ddi_init(struct intel_display *display,
 	if (DISPLAY_VER(display) >= 14) {
 		encoder->enable_clock = intel_mtl_pll_enable_clock;
 		encoder->disable_clock = intel_mtl_pll_disable_clock;
-		encoder->port_pll_type = intel_mtl_port_pll_type;
+		encoder->port_pll_type = icl_ddi_tc_port_pll_type;
 		if (intel_encoder_is_tc(encoder))
 			encoder->get_config = mtl_ddi_tc_phy_get_config;
 		else
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2e927d6cd577..5b569ad8157b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4932,23 +4932,6 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
 	intel_dpll_dump_hw_state(display, p, b);
 }
 
-static void
-pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
-			    const struct intel_crtc *crtc,
-			    const char *name,
-			    const struct intel_cx0pll_state *a,
-			    const struct intel_cx0pll_state *b)
-{
-	char *chipname = a->use_c10 ? "C10" : "C20";
-
-	pipe_config_mismatch(p, fastset, crtc, name, chipname);
-
-	drm_printf(p, "expected:\n");
-	intel_cx0pll_dump_hw_state(p, a);
-	drm_printf(p, "found:\n");
-	intel_cx0pll_dump_hw_state(p, b);
-}
-
 static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
 {
 	struct intel_display *display = to_intel_display(old_crtc_state);
@@ -5082,16 +5065,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
-#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
-	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
-					   &pipe_config->name)) { \
-		pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
-					    &current_config->name, \
-					    &pipe_config->name); \
-		ret = false; \
-	} \
-} while (0)
-
 #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
 	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
 	PIPE_CONF_CHECK_I(name.crtc_htotal); \
@@ -5315,10 +5288,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	if (display->dpll.mgr || HAS_GMCH(display))
 		PIPE_CONF_CHECK_PLL(dpll_hw_state);
 
-	/* FIXME convert MTL+ platforms over to dpll_mgr */
-	if (DISPLAY_VER(display) >= 14)
-		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
-
 	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
 	PIPE_CONF_CHECK_X(dsi_pll.div);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 46ae05976191..f744f61b291a 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1211,27 +1211,6 @@ static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
 	return 0;
 }
 
-static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
-				  struct intel_crtc *crtc)
-{
-	struct intel_crtc_state *crtc_state =
-		intel_atomic_get_new_crtc_state(state, crtc);
-	struct intel_encoder *encoder =
-		intel_get_crtc_new_encoder(state, crtc_state);
-	int ret;
-
-	ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state->dpll_hw_state);
-	if (ret)
-		return ret;
-
-	/* TODO: Do the readback via intel_dpll_compute() */
-	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
-
-	crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state);
-
-	return 0;
-}
-
 static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
@@ -1692,7 +1671,7 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
 }
 
 static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
-	.crtc_compute_clock = mtl_crtc_compute_clock,
+	.crtc_compute_clock = hsw_crtc_compute_clock,
 	.crtc_get_dpll = hsw_crtc_get_dpll,
 };
 
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index ddc763d89aac..77ef6a0419d0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4558,7 +4558,6 @@ static bool mtl_compare_hw_state(const struct intel_dpll_hw_state *_a,
 	return intel_cx0pll_compare_hw_state(a, b);
 }
 
-__maybe_unused
 static const struct intel_dpll_mgr mtl_pll_mgr = {
 	.dpll_info = mtl_plls,
 	.compute_dplls = mtl_compute_dplls,
@@ -4584,9 +4583,11 @@ void intel_dpll_init(struct intel_display *display)
 
 	mutex_init(&display->dpll.lock);
 
-	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
+	if (display->platform.dg2)
 		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
 		dpll_mgr = NULL;
+	else if (DISPLAY_VER(display) >= 14)
+		dpll_mgr = &mtl_pll_mgr;
 	else if (display->platform.alderlake_p)
 		dpll_mgr = &adlp_pll_mgr;
 	else if (display->platform.alderlake_s)
-- 
2.34.1

✓ i915.CI.BAT: success for drm/i915/display: Add MTL+ platforms to support dpll framework (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3124 bytes --]

== Series Details ==

Series: drm/i915/display: Add MTL+ platforms to support dpll framework (rev2)
URL   : https://patchwork.freedesktop.org/series/155279/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17462 -> Patchwork_155279v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/index.html

Participating hosts (46 -> 45)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_155279v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_hotunplug@unbind-rebind:
    - bat-rpls-4:         [PASS][1] -> [DMESG-WARN][2] ([i915#13400])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/bat-rpls-4/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/bat-rpls-4/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-6:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/bat-arls-6/igt@i915_selftest@live@workarounds.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-tgl-1115g4:      [PASS][5] -> [FAIL][6] ([i915#14867])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/fi-tgl-1115g4/igt@kms_hdmi_inject@inject-audio.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/fi-tgl-1115g4/igt@kms_hdmi_inject@inject-audio.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [DMESG-FAIL][7] ([i915#12061]) -> [PASS][8] +1 other test pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [DMESG-FAIL][9] ([i915#12061]) -> [PASS][10] +1 other test pass
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13400]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13400
  [i915#14867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14867


Build changes
-------------

  * Linux: CI_DRM_17462 -> Patchwork_155279v2

  CI-20190529: 20190529
  CI_DRM_17462: e2df6bac5c3868532a64c869ff7546587aa3dbad @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8604: 8604
  Patchwork_155279v2: e2df6bac5c3868532a64c869ff7546587aa3dbad @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/index.html

[-- Attachment #2: Type: text/html, Size: 3957 bytes --]

✗ i915.CI.Full: failure for drm/i915/display: Add MTL+ platforms to support dpll framework (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 132857 bytes --]

== Series Details ==

Series: drm/i915/display: Add MTL+ platforms to support dpll framework (rev2)
URL   : https://patchwork.freedesktop.org/series/155279/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17462_full -> Patchwork_155279v2_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_155279v2_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_155279v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 10)
------------------------------

  Missing    (1): shard-dg2-set2 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_155279v2_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb@pipe-a:
    - shard-glk:          NOTRUN -> [INCOMPLETE][1] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk5/igt@kms_busy@extended-pageflip-modeset-hang-oldfb@pipe-a.html

  
New tests
---------

  New tests have been introduced between CI_DRM_17462_full and Patchwork_155279v2_full:

### New IGT tests (5) ###

  * igt@kms_invalid_mode@int-max-clock@pipe-a-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.08] s

  * igt@kms_invalid_mode@int-max-clock@pipe-b-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@int-max-clock@pipe-c-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@int-max-clock@pipe-d-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_plane_alpha_blend@constant-alpha-max@pipe-d-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.95] s

  

Known issues
------------

  Here are the changes found in Patchwork_155279v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@crc32:
    - shard-dg1:          NOTRUN -> [SKIP][2] ([i915#6230])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@api_intel_bb@crc32.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu-1:       NOTRUN -> [SKIP][3] ([i915#11078])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@fbdev@write:
    - shard-rkl:          [PASS][4] -> [SKIP][5] ([i915#14544] / [i915#2582])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@fbdev@write.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@fbdev@write.html

  * igt@gem_basic@multigpu-create-close:
    - shard-dg1:          NOTRUN -> [SKIP][6] ([i915#7697])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-dg1:          NOTRUN -> [SKIP][7] ([i915#9323])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          [PASS][8] -> [INCOMPLETE][9] ([i915#13356])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg2-6/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-4/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html

  * igt@gem_create@hog-create:
    - shard-rkl:          [PASS][10] -> [DMESG-WARN][11] ([i915#12964]) +13 other tests dmesg-warn
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@gem_create@hog-create.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gem_create@hog-create.html

  * igt@gem_ctx_persistence@heartbeat-close:
    - shard-dg1:          NOTRUN -> [SKIP][12] ([i915#8555])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@gem_ctx_persistence@heartbeat-close.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
    - shard-snb:          NOTRUN -> [SKIP][13] ([i915#1099])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-snb7/igt@gem_ctx_persistence@legacy-engines-mixed.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-dg2:          NOTRUN -> [SKIP][14] ([i915#280]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-dg1:          NOTRUN -> [SKIP][15] ([i915#280])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_exec_balancer@bonded-pair:
    - shard-dg2:          NOTRUN -> [SKIP][16] ([i915#4771])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@gem_exec_balancer@bonded-pair.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          NOTRUN -> [SKIP][17] ([i915#6344])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_endless@dispatch@vcs1:
    - shard-dg1:          [PASS][18] -> [TIMEOUT][19] ([i915#3778]) +1 other test timeout
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg1-13/igt@gem_exec_endless@dispatch@vcs1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-12/igt@gem_exec_endless@dispatch@vcs1.html

  * igt@gem_exec_fence@submit3:
    - shard-dg1:          NOTRUN -> [SKIP][20] ([i915#4812]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@gem_exec_fence@submit3.html

  * igt@gem_exec_flush@basic-uc-prw-default:
    - shard-dg1:          NOTRUN -> [SKIP][21] ([i915#3539])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@gem_exec_flush@basic-uc-prw-default.html

  * igt@gem_exec_flush@basic-wb-rw-before-default:
    - shard-dg2:          NOTRUN -> [SKIP][22] ([i915#3539] / [i915#4852]) +1 other test skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@gem_exec_flush@basic-wb-rw-before-default.html

  * igt@gem_exec_reloc@basic-gtt-read:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#3281]) +4 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@gem_exec_reloc@basic-gtt-read.html

  * igt@gem_exec_reloc@basic-range-active:
    - shard-dg1:          NOTRUN -> [SKIP][24] ([i915#3281]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@gem_exec_reloc@basic-range-active.html

  * igt@gem_exec_reloc@basic-write-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#3281]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@gem_exec_reloc@basic-write-gtt.html

  * igt@gem_exec_schedule@preempt-queue-contexts:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#4537] / [i915#4812])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@gem_exec_schedule@preempt-queue-contexts.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - shard-tglu-1:       NOTRUN -> [FAIL][27] ([i915#15136]) +1 other test fail
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#4860])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@gem_lmem_swapping@basic:
    - shard-tglu:         NOTRUN -> [SKIP][29] ([i915#4613]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-tglu-1:       NOTRUN -> [SKIP][30] ([i915#4613])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_lmem_swapping@verify-ccs:
    - shard-glk:          NOTRUN -> [SKIP][31] ([i915#4613]) +3 other tests skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk6/igt@gem_lmem_swapping@verify-ccs.html
    - shard-rkl:          NOTRUN -> [SKIP][32] ([i915#4613])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@gem_lmem_swapping@verify-ccs.html

  * igt@gem_mmap_gtt@cpuset-big-copy-odd:
    - shard-dg1:          NOTRUN -> [SKIP][33] ([i915#4077]) +3 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@gem_mmap_gtt@cpuset-big-copy-odd.html

  * igt@gem_mmap_wc@write:
    - shard-dg1:          NOTRUN -> [SKIP][34] ([i915#4083])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@gem_mmap_wc@write.html

  * igt@gem_mmap_wc@write-cpu-read-wc-unflushed:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4083]) +2 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@gem_mmap_wc@write-cpu-read-wc-unflushed.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-dg1:          NOTRUN -> [SKIP][36] ([i915#3282])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-dg2:          NOTRUN -> [SKIP][37] ([i915#3282]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_partial_pwrite_pread@write-display:
    - shard-rkl:          NOTRUN -> [SKIP][38] ([i915#3282])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@gem_partial_pwrite_pread@write-display.html

  * igt@gem_pread@exhaustion:
    - shard-glk:          NOTRUN -> [WARN][39] ([i915#2658])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk5/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-rkl:          NOTRUN -> [TIMEOUT][40] ([i915#12917] / [i915#12964])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_pxp@reject-modify-context-protection-off-2:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#4270])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@gem_pxp@reject-modify-context-protection-off-2.html

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - shard-rkl:          [PASS][42] -> [TIMEOUT][43] ([i915#12917] / [i915#12964]) +1 other test timeout
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
    - shard-dg1:          NOTRUN -> [SKIP][44] ([i915#4270])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
    - shard-rkl:          NOTRUN -> [SKIP][45] ([i915#4270])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@gem_pxp@verify-pxp-stale-ctx-execution.html

  * igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#5190] / [i915#8428]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          NOTRUN -> [SKIP][47] ([i915#8411]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][48] ([i915#4885])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_tiled_pread_basic:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#4079]) +1 other test skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@gem_tiled_pread_basic.html

  * igt@gem_tiling_max_stride:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#4077]) +2 other tests skip
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@gem_tiling_max_stride.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-tglu-1:       NOTRUN -> [SKIP][51] ([i915#3297])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][52] ([i915#3297]) +3 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([i915#3297])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
    - shard-rkl:          NOTRUN -> [SKIP][54] ([i915#3297])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@gem_userptr_blits@unsync-unmap-after-close.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-glk10:        NOTRUN -> [SKIP][55] +86 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk10/igt@gen7_exec_parse@bitmasks.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#2856]) +2 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@bb-large:
    - shard-tglu-1:       NOTRUN -> [SKIP][57] ([i915#2527] / [i915#2856])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@gen9_exec_parse@bb-large.html
    - shard-dg1:          NOTRUN -> [SKIP][58] ([i915#2527]) +1 other test skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-tglu:         NOTRUN -> [SKIP][59] ([i915#2527] / [i915#2856])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_drm_fdinfo@isolation@rcs0:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#14073]) +7 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@i915_drm_fdinfo@isolation@rcs0.html

  * igt@i915_drm_fdinfo@virtual-busy-idle:
    - shard-dg1:          NOTRUN -> [SKIP][61] ([i915#14118])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@i915_drm_fdinfo@virtual-busy-idle.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][62] ([i915#8399])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-rkl:          NOTRUN -> [SKIP][63] +2 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_pm_rpm@gem-pread:
    - shard-rkl:          [PASS][64] -> [SKIP][65] ([i915#13328])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@i915_pm_rpm@gem-pread.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-5/igt@i915_pm_rpm@gem-pread.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [PASS][66] -> [SKIP][67] ([i915#7984])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-mtlp-2/igt@i915_power@sanity.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-mtlp-8/igt@i915_power@sanity.html

  * igt@i915_query@hwconfig_table:
    - shard-rkl:          NOTRUN -> [SKIP][68] ([i915#6245])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@i915_query@hwconfig_table.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-glk:          NOTRUN -> [INCOMPLETE][69] ([i915#12761]) +1 other test incomplete
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk3/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_async_flips@crc:
    - shard-rkl:          [PASS][70] -> [SKIP][71] ([i915#14544]) +38 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_async_flips@crc.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_async_flips@crc.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-glk10:        NOTRUN -> [SKIP][72] ([i915#1769])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk10/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-glk:          NOTRUN -> [SKIP][73] ([i915#1769])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk5/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [FAIL][74] ([i915#5956]) +1 other test fail
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-tglu:         NOTRUN -> [SKIP][75] ([i915#5286]) +2 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-dg1:          NOTRUN -> [SKIP][76] ([i915#5286]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
    - shard-tglu-1:       NOTRUN -> [SKIP][77] ([i915#5286]) +2 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#5286]) +2 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-dg1:          NOTRUN -> [SKIP][79] ([i915#3638]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][80] ([i915#3638])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([i915#4538] / [i915#5190]) +4 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#5190])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-dg1:          NOTRUN -> [SKIP][83] ([i915#4538]) +1 other test skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][84] ([i915#6095]) +35 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][85] ([i915#12313]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][86] ([i915#6095]) +133 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][87] ([i915#6095]) +34 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_ccs@crc-primary-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][88] ([i915#14098] / [i915#6095]) +35 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-4/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][89] ([i915#12313]) +1 other test skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
    - shard-dg1:          NOTRUN -> [SKIP][90] ([i915#12313])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#10307] / [i915#6095]) +114 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][92] ([i915#12805])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
    - shard-dg1:          NOTRUN -> [SKIP][93] ([i915#12805])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][94] ([i915#6095]) +12 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-4/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][95] ([i915#6095]) +19 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_cdclk@plane-scaling:
    - shard-tglu:         NOTRUN -> [SKIP][96] ([i915#3742])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
    - shard-tglu:         NOTRUN -> [SKIP][97] ([i915#11151] / [i915#7828]) +4 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-dg1:          NOTRUN -> [SKIP][98] ([i915#11151] / [i915#7828]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#11151] / [i915#7828]) +4 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_chamelium_hpd@hdmi-hpd-for-each-pipe.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#11151] / [i915#7828]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
    - shard-tglu-1:       NOTRUN -> [SKIP][101] ([i915#11151] / [i915#7828]) +3 other tests skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][102] ([i915#3116] / [i915#3299])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          NOTRUN -> [SKIP][103] ([i915#7118] / [i915#9424])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@srm:
    - shard-dg1:          NOTRUN -> [SKIP][104] ([i915#7116])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@type1:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#7118] / [i915#9424])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_content_protection@type1.html

  * igt@kms_content_protection@uevent:
    - shard-tglu-1:       NOTRUN -> [SKIP][106] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-tglu-1:       NOTRUN -> [SKIP][107] ([i915#13049])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-rkl:          NOTRUN -> [SKIP][108] ([i915#13049])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-tglu:         NOTRUN -> [FAIL][109] ([i915#13566]) +1 other test fail
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][110] ([i915#13049]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-tglu:         NOTRUN -> [SKIP][111] ([i915#3555]) +1 other test skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][112] ([i915#13566]) +3 other tests fail
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-tglu-1:       NOTRUN -> [SKIP][113] ([i915#3555]) +2 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [PASS][114] -> [FAIL][115] ([i915#13028])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#4103])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][117] ([i915#4103] / [i915#4213])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([i915#13046] / [i915#5354]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#3804])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_aux_dev:
    - shard-tglu:         NOTRUN -> [SKIP][120] ([i915#1257])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-dg1:          NOTRUN -> [SKIP][121] ([i915#13748])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-dg2:          [PASS][122] -> [SKIP][123] ([i915#13707])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg2-11/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-8/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-dg1:          NOTRUN -> [SKIP][124] ([i915#13707])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-basic:
    - shard-tglu:         NOTRUN -> [SKIP][125] ([i915#3555] / [i915#3840])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#3840] / [i915#9053])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@psr:
    - shard-dg1:          NOTRUN -> [SKIP][127] ([i915#3469])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@display-2x:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#1839])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@psr1:
    - shard-rkl:          NOTRUN -> [SKIP][129] ([i915#658])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-dg1:          NOTRUN -> [SKIP][130] ([i915#9934]) +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-tglu:         NOTRUN -> [SKIP][131] ([i915#3637] / [i915#9934]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-fences:
    - shard-dg2:          NOTRUN -> [SKIP][132] ([i915#8381])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_flip@2x-flip-vs-fences.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][133] ([i915#3637] / [i915#9934]) +2 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][134] ([i915#9934]) +1 other test skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-rkl:          [PASS][135] -> [SKIP][136] ([i915#14544] / [i915#3637]) +9 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_flip@flip-vs-suspend.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-dg2:          [PASS][137] -> [ABORT][138] ([i915#15132])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg2-5/igt@kms_flip@flip-vs-suspend-interruptible.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-10/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][139] ([i915#6113])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend-interruptible@d-dp3:
    - shard-dg2:          NOTRUN -> [ABORT][140] ([i915#15132])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-10/igt@kms_flip@flip-vs-suspend-interruptible@d-dp3.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#2672] / [i915#3555])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][142] ([i915#2672]) +3 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][143] ([i915#2587] / [i915#2672]) +2 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][144] ([i915#2672] / [i915#3555]) +1 other test skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-rkl:          [PASS][145] -> [SKIP][146] ([i915#14544] / [i915#3555]) +2 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][147] ([i915#2587] / [i915#2672] / [i915#3555])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][148] ([i915#2672]) +2 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][149] ([i915#2672] / [i915#3555])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][150] ([i915#2587] / [i915#2672]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][151] ([i915#2672] / [i915#3555]) +2 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][152] ([i915#2672] / [i915#3555] / [i915#5190]) +1 other test skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][153] ([i915#15104])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
    - shard-rkl:          [PASS][154] -> [SKIP][155] ([i915#14544] / [i915#1849] / [i915#5354]) +4 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][156] ([i915#8708]) +5 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][157] ([i915#8708]) +7 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-tglu-1:       NOTRUN -> [SKIP][158] +27 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][159] +17 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary:
    - shard-dg2:          [PASS][160] -> [FAIL][161] ([i915#6880])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][162] ([i915#15102])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][163] ([i915#15102])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][164] ([i915#15102]) +1 other test skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][165] ([i915#15102] / [i915#3458]) +9 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][166] ([i915#1825]) +10 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][167] ([i915#15102]) +13 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-render:
    - shard-tglu:         NOTRUN -> [SKIP][168] ([i915#15102]) +11 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][169] ([i915#15102] / [i915#3023]) +3 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([i915#5354]) +14 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-tglu:         NOTRUN -> [SKIP][171] +29 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-dg1:          NOTRUN -> [SKIP][172] ([i915#15102] / [i915#3458]) +7 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_hdr@bpc-switch:
    - shard-dg2:          NOTRUN -> [SKIP][173] ([i915#3555] / [i915#8228])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-tglu-1:       NOTRUN -> [SKIP][174] ([i915#3555] / [i915#8228])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@static-toggle:
    - shard-tglu:         NOTRUN -> [SKIP][175] ([i915#3555] / [i915#8228])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_hdr@static-toggle.html

  * igt@kms_invalid_mode@zero-clock:
    - shard-rkl:          [PASS][176] -> [SKIP][177] ([i915#14544] / [i915#3555] / [i915#8826])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_invalid_mode@zero-clock.html
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_invalid_mode@zero-clock.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#12388])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][179] ([i915#12394])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][180] ([i915#12339])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_joiner@invalid-modeset-ultra-joiner.html
    - shard-dg1:          NOTRUN -> [SKIP][181] ([i915#12339])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-tglu:         NOTRUN -> [SKIP][182] ([i915#1839])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes:
    - shard-dg2:          NOTRUN -> [SKIP][183] +4 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_pipe_b_c_ivb@from-pipe-c-to-b-with-3-lanes.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-tglu-1:       NOTRUN -> [SKIP][184] ([i915#14712])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
    - shard-dg1:          NOTRUN -> [SKIP][185] ([i915#14712])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][186] ([i915#13026]) +1 other test incomplete
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk10/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane@plane-position-hole-dpms:
    - shard-rkl:          [PASS][187] -> [SKIP][188] ([i915#14544] / [i915#8825])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_plane@plane-position-hole-dpms.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane@plane-position-hole-dpms.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk10:        NOTRUN -> [FAIL][189] ([i915#10647] / [i915#12169])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk10/igt@kms_plane_alpha_blend@alpha-opaque-fb.html
    - shard-rkl:          [PASS][190] -> [SKIP][191] ([i915#14544] / [i915#7294])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_plane_alpha_blend@alpha-opaque-fb.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-c-hdmi-a-1:
    - shard-glk10:        NOTRUN -> [FAIL][192] ([i915#10647]) +1 other test fail
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk10/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-c-hdmi-a-1.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-tglu-1:       NOTRUN -> [SKIP][193] ([i915#13958]) +1 other test skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-dg1:          NOTRUN -> [SKIP][194] ([i915#13958])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-tglu:         NOTRUN -> [SKIP][195] ([i915#13958])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-d:
    - shard-tglu-1:       NOTRUN -> [SKIP][196] ([i915#12247]) +4 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-d.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c:
    - shard-rkl:          NOTRUN -> [SKIP][197] ([i915#12247])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-c.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers:
    - shard-rkl:          [PASS][198] -> [SKIP][199] ([i915#14544] / [i915#8152])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-20x20-with-modifiers.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
    - shard-dg1:          NOTRUN -> [SKIP][200] ([i915#12247]) +9 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
    - shard-rkl:          [PASS][201] -> [SKIP][202] ([i915#12247] / [i915#14544] / [i915#6953] / [i915#8152])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b:
    - shard-rkl:          [PASS][203] -> [SKIP][204] ([i915#12247] / [i915#14544] / [i915#8152]) +2 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75:
    - shard-rkl:          [PASS][205] -> [SKIP][206] ([i915#12247] / [i915#14544] / [i915#3555] / [i915#6953] / [i915#8152])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a:
    - shard-rkl:          [PASS][207] -> [SKIP][208] ([i915#12247] / [i915#14544]) +2 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-a.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-tglu-1:       NOTRUN -> [SKIP][209] ([i915#9812])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-tglu:         NOTRUN -> [SKIP][210] ([i915#9812])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-tglu:         NOTRUN -> [SKIP][211] ([i915#9685])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#3828])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          [PASS][213] -> [SKIP][214] ([i915#9340])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg2-4/igt@kms_pm_lpsp@kms-lpsp.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-7/igt@kms_pm_lpsp@kms-lpsp.html
    - shard-tglu-1:       NOTRUN -> [SKIP][215] ([i915#3828])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-dg2:          NOTRUN -> [SKIP][216] ([i915#8430])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-rkl:          [PASS][217] -> [SKIP][218] ([i915#15073])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [PASS][219] -> [SKIP][220] ([i915#14544] / [i915#15073]) +1 other test skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-tglu-1:       NOTRUN -> [SKIP][221] ([i915#15073])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@fences-dpms:
    - shard-rkl:          [PASS][222] -> [SKIP][223] ([i915#14544] / [i915#1849])
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_pm_rpm@fences-dpms.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_pm_rpm@fences-dpms.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          [PASS][224] -> [SKIP][225] ([i915#15073]) +1 other test skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@system-suspend-idle:
    - shard-dg1:          [PASS][226] -> [DMESG-WARN][227] ([i915#4423])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg1-12/igt@kms_pm_rpm@system-suspend-idle.html
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-18/igt@kms_pm_rpm@system-suspend-idle.html

  * igt@kms_prime@d3hot:
    - shard-tglu:         NOTRUN -> [SKIP][228] ([i915#6524])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_prime@d3hot.html

  * igt@kms_properties@crtc-properties-atomic:
    - shard-rkl:          [PASS][229] -> [SKIP][230] ([i915#11521] / [i915#14544])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_properties@crtc-properties-atomic.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_properties@crtc-properties-atomic.html

  * igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#11520]) +3 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#11520])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][233] ([i915#11520]) +3 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
    - shard-dg1:          NOTRUN -> [SKIP][234] ([i915#11520]) +3 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-tglu:         NOTRUN -> [SKIP][235] ([i915#11520]) +3 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-snb:          NOTRUN -> [SKIP][236] ([i915#11520])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-snb7/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][237] ([i915#11520]) +6 other tests skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk5/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
    - shard-glk10:        NOTRUN -> [SKIP][238] ([i915#11520]) +2 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk10/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-pr-sprite-plane-onoff:
    - shard-tglu-1:       NOTRUN -> [SKIP][239] ([i915#9732]) +9 other tests skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_psr@fbc-pr-sprite-plane-onoff.html
    - shard-dg1:          NOTRUN -> [SKIP][240] ([i915#1072] / [i915#9732]) +8 other tests skip
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_psr@fbc-pr-sprite-plane-onoff.html

  * igt@kms_psr@fbc-psr2-cursor-mmap-gtt:
    - shard-glk:          NOTRUN -> [SKIP][241] +265 other tests skip
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk6/igt@kms_psr@fbc-psr2-cursor-mmap-gtt.html
    - shard-rkl:          NOTRUN -> [SKIP][242] ([i915#1072] / [i915#9732]) +3 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_psr@fbc-psr2-cursor-mmap-gtt.html

  * igt@kms_psr@pr-primary-page-flip:
    - shard-tglu:         NOTRUN -> [SKIP][243] ([i915#9732]) +10 other tests skip
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_psr@pr-primary-page-flip.html

  * igt@kms_psr@psr-sprite-blt:
    - shard-snb:          NOTRUN -> [SKIP][244] +31 other tests skip
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-snb7/igt@kms_psr@psr-sprite-blt.html

  * igt@kms_psr@psr-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][245] ([i915#1072] / [i915#9732]) +10 other tests skip
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_psr@psr-suspend.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-dg1:          NOTRUN -> [SKIP][246] ([i915#9685])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-rkl:          NOTRUN -> [SKIP][247] ([i915#5289])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-tglu-1:       NOTRUN -> [SKIP][248] ([i915#5289])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-dg2:          NOTRUN -> [SKIP][249] ([i915#3555]) +1 other test skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_selftest@drm_dp_mst_helper@drm_test_dp_mst_calc_pbn_div:
    - shard-tglu-1:       NOTRUN -> [FAIL][250] ([i915#15119]) +3 other tests fail
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_selftest@drm_dp_mst_helper@drm_test_dp_mst_calc_pbn_div.html
    - shard-dg1:          NOTRUN -> [FAIL][251] ([i915#15119]) +3 other tests fail
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@kms_selftest@drm_dp_mst_helper@drm_test_dp_mst_calc_pbn_div.html

  * igt@kms_selftest@drm_plane_helper@drm_test_check_plane_state:
    - shard-tglu:         NOTRUN -> [FAIL][252] ([i915#15119]) +2 other tests fail
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@kms_selftest@drm_plane_helper@drm_test_check_plane_state.html

  * igt@kms_setmode@basic:
    - shard-snb:          [PASS][253] -> [FAIL][254] ([i915#15106]) +1 other test fail
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-snb4/igt@kms_setmode@basic.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-snb4/igt@kms_setmode@basic.html
    - shard-tglu:         [PASS][255] -> [FAIL][256] ([i915#15106]) +2 other tests fail
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-tglu-8/igt@kms_setmode@basic.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-4/igt@kms_setmode@basic.html

  * igt@kms_setmode@basic@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][257] ([i915#15106]) +2 other tests fail
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_setmode@basic@pipe-b-hdmi-a-2.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2:          NOTRUN -> [SKIP][258] ([i915#8623])
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][259] ([i915#12276]) +1 other test incomplete
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk3/igt@kms_vblank@ts-continuation-suspend.html
    - shard-rkl:          [PASS][260] -> [ABORT][261] ([i915#15132])
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_vblank@ts-continuation-suspend.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-4/igt@kms_vblank@ts-continuation-suspend.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [ABORT][262] ([i915#15132])
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-4/igt@kms_vblank@ts-continuation-suspend@pipe-b-hdmi-a-1.html

  * igt@kms_vrr@negative-basic:
    - shard-tglu:         NOTRUN -> [SKIP][263] ([i915#3555] / [i915#9906])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-5/igt@kms_vrr@negative-basic.html

  * igt@kms_writeback@writeback-check-output-xrgb2101010:
    - shard-tglu-1:       NOTRUN -> [SKIP][264] ([i915#2437] / [i915#9412])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@kms_writeback@writeback-check-output-xrgb2101010.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-glk:          NOTRUN -> [SKIP][265] ([i915#2437]) +1 other test skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk3/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg2:          NOTRUN -> [SKIP][266] ([i915#2437])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@global-sseu-config:
    - shard-dg2:          NOTRUN -> [SKIP][267] ([i915#7387])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@perf@global-sseu-config.html

  * igt@prime_busy@hang-wait@bcs0:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][268] ([i915#12964]) +5 other tests dmesg-warn
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@prime_busy@hang-wait@bcs0.html

  * igt@prime_mmap@test_aperture_limit:
    - shard-dg2:          NOTRUN -> [SKIP][269] ([i915#14121]) +1 other test skip
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@prime_mmap@test_aperture_limit.html

  * igt@prime_vgem@basic-fence-flip:
    - shard-dg1:          NOTRUN -> [SKIP][270] ([i915#3708])
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-14/igt@prime_vgem@basic-fence-flip.html
    - shard-rkl:          [PASS][271] -> [SKIP][272] ([i915#14544] / [i915#3708])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@prime_vgem@basic-fence-flip.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-write:
    - shard-dg2:          NOTRUN -> [SKIP][273] ([i915#3291] / [i915#3708])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-1/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@coherency-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][274] ([i915#3708] / [i915#4077])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@prime_vgem@coherency-gtt.html

  * igt@sriov_basic@bind-unbind-vf@vf-4:
    - shard-tglu:         NOTRUN -> [FAIL][275] ([i915#12910]) +18 other tests fail
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-7/igt@sriov_basic@bind-unbind-vf@vf-4.html

  * igt@sriov_basic@enable-vfs-autoprobe-off@numvfs-random:
    - shard-tglu-1:       NOTRUN -> [FAIL][276] ([i915#12910]) +9 other tests fail
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-1/igt@sriov_basic@enable-vfs-autoprobe-off@numvfs-random.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-dg2:          NOTRUN -> [SKIP][277] ([i915#9917])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@preemptive-hang:
    - shard-rkl:          [DMESG-WARN][278] ([i915#12964]) -> [PASS][279] +7 other tests pass
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@gem_exec_schedule@preemptive-hang.html
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@gem_exec_schedule@preemptive-hang.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - shard-rkl:          [FAIL][280] ([i915#15136]) -> [PASS][281] +1 other test pass
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@gem_exec_suspend@basic-s4-devices.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@gem_pxp@create-regular-context-2:
    - shard-rkl:          [TIMEOUT][282] ([i915#12917] / [i915#12964]) -> [PASS][283] +1 other test pass
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-7/igt@gem_pxp@create-regular-context-2.html
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@gem_pxp@create-regular-context-2.html

  * igt@gem_workarounds@suspend-resume:
    - shard-glk:          [INCOMPLETE][284] ([i915#13356] / [i915#14586]) -> [PASS][285]
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-glk8/igt@gem_workarounds@suspend-resume.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk5/igt@gem_workarounds@suspend-resume.html
    - shard-rkl:          [ABORT][286] -> [PASS][287]
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-4/igt@gem_workarounds@suspend-resume.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@gem_workarounds@suspend-resume.html

  * igt@i915_module_load@reload-no-display:
    - shard-snb:          [DMESG-WARN][288] ([i915#14545]) -> [PASS][289]
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-snb5/igt@i915_module_load@reload-no-display.html
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-snb1/igt@i915_module_load@reload-no-display.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-rkl:          [DMESG-FAIL][290] ([i915#12964]) -> [PASS][291] +1 other test pass
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [INCOMPLETE][292] ([i915#13729] / [i915#13821]) -> [PASS][293]
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-snb1/igt@i915_pm_rps@reset.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-snb7/igt@i915_pm_rps@reset.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [INCOMPLETE][294] ([i915#4817]) -> [PASS][295]
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1:
    - shard-tglu:         [FAIL][296] -> [PASS][297] +1 other test pass
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-tglu-2/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-tglu-9/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [FAIL][298] ([i915#5138]) -> [PASS][299]
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_color@gamma:
    - shard-rkl:          [SKIP][300] ([i915#12655] / [i915#14544]) -> [PASS][301] +1 other test pass
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_color@gamma.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_color@gamma.html

  * igt@kms_flip@basic-flip-vs-dpms:
    - shard-dg1:          [DMESG-WARN][302] ([i915#4423]) -> [PASS][303] +4 other tests pass
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg1-14/igt@kms_flip@basic-flip-vs-dpms.html
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-19/igt@kms_flip@basic-flip-vs-dpms.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank:
    - shard-dg1:          [FAIL][304] -> [PASS][305] +1 other test pass
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg1-19/igt@kms_flip@flip-vs-absolute-wf_vblank.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-17/igt@kms_flip@flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][306] ([i915#14544] / [i915#3637]) -> [PASS][307] +2 other tests pass
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
    - shard-rkl:          [SKIP][308] ([i915#14544] / [i915#3555]) -> [PASS][309] +2 other tests pass
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt:
    - shard-rkl:          [SKIP][310] ([i915#14544] / [i915#1849] / [i915#5354]) -> [PASS][311] +5 other tests pass
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-farfromfence-mmap-gtt.html

  * igt@kms_invalid_mode@bad-vsync-end:
    - shard-rkl:          [SKIP][312] ([i915#14544] / [i915#3555] / [i915#8826]) -> [PASS][313]
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_invalid_mode@bad-vsync-end.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_invalid_mode@bad-vsync-end.html

  * igt@kms_lease@lease-invalid-plane:
    - shard-rkl:          [SKIP][314] ([i915#14544]) -> [PASS][315] +31 other tests pass
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_lease@lease-invalid-plane.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_lease@lease-invalid-plane.html

  * igt@kms_pipe_crc_basic@read-crc:
    - shard-rkl:          [SKIP][316] ([i915#11190] / [i915#14544]) -> [PASS][317]
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_pipe_crc_basic@read-crc.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_pipe_crc_basic@read-crc.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25:
    - shard-rkl:          [SKIP][318] ([i915#14544] / [i915#6953] / [i915#8152]) -> [PASS][319]
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25@pipe-a:
    - shard-rkl:          [SKIP][320] ([i915#12247] / [i915#14544]) -> [PASS][321] +2 other tests pass
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25@pipe-a.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25@pipe-a.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25:
    - shard-rkl:          [SKIP][322] ([i915#14544] / [i915#3555] / [i915#6953] / [i915#8152]) -> [PASS][323] +1 other test pass
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_plane_scaling@planes-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b:
    - shard-rkl:          [SKIP][324] ([i915#12247] / [i915#14544] / [i915#8152]) -> [PASS][325] +3 other tests pass
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b.html

  * igt@kms_pm_rpm@cursor:
    - shard-rkl:          [SKIP][326] ([i915#14544] / [i915#1849]) -> [PASS][327]
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_pm_rpm@cursor.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_pm_rpm@cursor.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-rkl:          [SKIP][328] ([i915#15073]) -> [PASS][329]
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_properties@plane-properties-legacy:
    - shard-rkl:          [SKIP][330] ([i915#11521] / [i915#14544]) -> [PASS][331]
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_properties@plane-properties-legacy.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_properties@plane-properties-legacy.html

  * igt@kms_setmode@basic:
    - shard-mtlp:         [FAIL][332] ([i915#15106]) -> [PASS][333] +1 other test pass
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-mtlp-2/igt@kms_setmode@basic.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-mtlp-4/igt@kms_setmode@basic.html

  * igt@prime_busy@hang:
    - shard-rkl:          [DMESG-WARN][334] ([i915#12917] / [i915#12964]) -> [PASS][335] +1 other test pass
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-7/igt@prime_busy@hang.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@prime_busy@hang.html

  
#### Warnings ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-rkl:          [SKIP][336] ([i915#8411]) -> [SKIP][337] ([i915#14544] / [i915#8411])
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@api_intel_bb@blit-reloc-keep-cache.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          [SKIP][338] ([i915#14544] / [i915#9323]) -> [SKIP][339] ([i915#9323]) +1 other test skip
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@gem_ccs@suspend-resume.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@gem_ccs@suspend-resume.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          [SKIP][340] ([i915#14544] / [i915#7697]) -> [SKIP][341] ([i915#7697])
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_exec_balancer@parallel-keep-in-fence:
    - shard-rkl:          [SKIP][342] ([i915#14544] / [i915#4525]) -> [SKIP][343] ([i915#4525])
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-in-fence.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@gem_exec_balancer@parallel-keep-in-fence.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-rkl:          [SKIP][344] ([i915#4525]) -> [SKIP][345] ([i915#14544] / [i915#4525])
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@gem_exec_balancer@parallel-keep-submit-fence.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_reloc@basic-write-cpu:
    - shard-rkl:          [SKIP][346] ([i915#3281]) -> [SKIP][347] ([i915#14544] / [i915#3281]) +8 other tests skip
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@gem_exec_reloc@basic-write-cpu.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gem_exec_reloc@basic-write-cpu.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - shard-rkl:          [SKIP][348] ([i915#14544] / [i915#3281]) -> [SKIP][349] ([i915#3281]) +1 other test skip
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@gem_exec_reloc@basic-write-read-noreloc.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          [SKIP][350] ([i915#4613] / [i915#7582]) -> [SKIP][351] ([i915#14544] / [i915#4613] / [i915#7582])
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@gem_lmem_evict@dontneed-evict-race.html
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-rkl:          [SKIP][352] ([i915#4613]) -> [SKIP][353] ([i915#14544] / [i915#4613])
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@gem_lmem_swapping@heavy-multi.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-rkl:          [SKIP][354] ([i915#14544] / [i915#4613]) -> [SKIP][355] ([i915#4613]) +1 other test skip
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_pread@self:
    - shard-rkl:          [SKIP][356] ([i915#14544] / [i915#3282]) -> [SKIP][357] ([i915#3282]) +1 other test skip
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@gem_pread@self.html
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@gem_pread@self.html

  * igt@gem_pread@snoop:
    - shard-rkl:          [SKIP][358] ([i915#3282]) -> [SKIP][359] ([i915#14544] / [i915#3282]) +2 other tests skip
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@gem_pread@snoop.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gem_pread@snoop.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-rkl:          [SKIP][360] ([i915#3297]) -> [SKIP][361] ([i915#14544] / [i915#3297])
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@gem_userptr_blits@unsync-unmap.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-rkl:          [SKIP][362] ([i915#14544] / [i915#2527]) -> [SKIP][363] ([i915#2527]) +1 other test skip
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@gen9_exec_parse@bb-secure.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@gen9_exec_parse@bb-secure.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-rkl:          [SKIP][364] ([i915#2527]) -> [SKIP][365] ([i915#14544] / [i915#2527]) +2 other tests skip
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@gen9_exec_parse@bb-start-far.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-rkl:          [SKIP][366] ([i915#14544] / [i915#6590]) -> [SKIP][367] ([i915#6590]) +1 other test skip
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@i915_pm_freq_mult@media-freq@gt0.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rc6_residency@media-rc6-accuracy:
    - shard-rkl:          [SKIP][368] -> [SKIP][369] ([i915#14544]) +8 other tests skip
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@i915_pm_rc6_residency@media-rc6-accuracy.html

  * igt@i915_suspend@debugfs-reader:
    - shard-rkl:          [INCOMPLETE][370] ([i915#4817]) -> [ABORT][371] ([i915#15131])
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-3/igt@i915_suspend@debugfs-reader.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-4/igt@i915_suspend@debugfs-reader.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          [SKIP][372] ([i915#14544]) -> [SKIP][373] ([i915#9531])
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          [SKIP][374] ([i915#1769] / [i915#3555]) -> [SKIP][375] ([i915#14544])
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-rkl:          [SKIP][376] ([i915#14544]) -> [SKIP][377] ([i915#5286]) +2 other tests skip
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-rkl:          [SKIP][378] ([i915#5286]) -> [SKIP][379] ([i915#14544]) +2 other tests skip
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-rkl:          [SKIP][380] ([i915#14544]) -> [SKIP][381] ([i915#3638])
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-rkl:          [SKIP][382] ([i915#3638]) -> [SKIP][383] ([i915#14544]) +4 other tests skip
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][384] ([i915#14098] / [i915#6095]) -> [SKIP][385] ([i915#6095]) +4 other tests skip
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-2.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
    - shard-rkl:          [SKIP][386] ([i915#14098] / [i915#6095]) -> [SKIP][387] ([i915#14544]) +10 other tests skip
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][388] ([i915#12313]) -> [SKIP][389] ([i915#14544])
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][390] ([i915#6095]) -> [SKIP][391] ([i915#14098] / [i915#6095]) +5 other tests skip
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-b-hdmi-a-2.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][392] ([i915#12805]) -> [SKIP][393] ([i915#14544])
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs:
    - shard-rkl:          [SKIP][394] ([i915#14544]) -> [SKIP][395] ([i915#14098] / [i915#6095]) +5 other tests skip
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][396] ([i915#14544]) -> [SKIP][397] ([i915#12805])
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_chamelium_color@degamma:
    - shard-rkl:          [SKIP][398] ([i915#14544]) -> [SKIP][399] +6 other tests skip
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_chamelium_color@degamma.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-rkl:          [SKIP][400] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][401] ([i915#11151] / [i915#7828]) +3 other tests skip
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_chamelium_frames@dp-crc-fast.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - shard-rkl:          [SKIP][402] ([i915#11151] / [i915#7828]) -> [SKIP][403] ([i915#11151] / [i915#14544] / [i915#7828]) +6 other tests skip
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_chamelium_frames@hdmi-crc-fast.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_color@deep-color:
    - shard-rkl:          [SKIP][404] ([i915#12655] / [i915#3555]) -> [SKIP][405] ([i915#12655] / [i915#14544] / [i915#3555])
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_color@deep-color.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_color@deep-color.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          [SKIP][406] ([i915#7118] / [i915#9424]) -> [SKIP][407] ([i915#14544])
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_content_protection@atomic.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-rkl:          [SKIP][408] ([i915#14544]) -> [SKIP][409] ([i915#3116])
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-rkl:          [SKIP][410] ([i915#13049]) -> [SKIP][411] ([i915#14544])
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          [SKIP][412] ([i915#3555]) -> [SKIP][413] ([i915#14544]) +5 other tests skip
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-rkl:          [SKIP][414] ([i915#14544]) -> [FAIL][415] ([i915#13566])
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-64x21.html
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_cursor_crc@cursor-sliding-64x64:
    - shard-rkl:          [DMESG-WARN][416] ([i915#12964]) -> [SKIP][417] ([i915#14544])
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-64x64.html
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-64x64.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-rkl:          [SKIP][418] ([i915#4103]) -> [SKIP][419] ([i915#14544])
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          [SKIP][420] ([i915#14544]) -> [SKIP][421] ([i915#3555] / [i915#3804])
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-rkl:          [SKIP][422] ([i915#3555] / [i915#3840]) -> [SKIP][423] ([i915#14544])
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_dsc@dsc-with-bpc-formats.html
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-rkl:          [SKIP][424] ([i915#14544]) -> [SKIP][425] ([i915#3555] / [i915#3840])
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_dsc@dsc-with-formats.html
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_feature_discovery@chamelium:
    - shard-rkl:          [SKIP][426] ([i915#4854]) -> [SKIP][427] ([i915#14544] / [i915#4854])
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_feature_discovery@chamelium.html
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-3x:
    - shard-rkl:          [SKIP][428] ([i915#14544] / [i915#1839]) -> [SKIP][429] ([i915#1839])
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_feature_discovery@display-3x.html
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_feature_discovery@display-3x.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][430] ([i915#12314] / [i915#12745] / [i915#4839] / [i915#6113]) -> [INCOMPLETE][431] ([i915#12745] / [i915#4839] / [i915#6113])
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-glk5/igt@kms_flip@2x-flip-vs-suspend.html
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk3/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [INCOMPLETE][432] ([i915#12314] / [i915#4839] / [i915#6113]) -> [INCOMPLETE][433] ([i915#4839] / [i915#6113])
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-glk5/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk3/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-rkl:          [SKIP][434] ([i915#9934]) -> [SKIP][435] ([i915#14544] / [i915#9934]) +3 other tests skip
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-rkl:          [SKIP][436] ([i915#14544] / [i915#9934]) -> [SKIP][437] ([i915#9934]) +2 other tests skip
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-dpms-on-nop-interruptible:
    - shard-rkl:          [SKIP][438] ([i915#14544] / [i915#3637]) -> [DMESG-WARN][439] ([i915#12964])
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_flip@flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-rkl:          [SKIP][440] ([i915#14544] / [i915#3637]) -> [INCOMPLETE][441] ([i915#6113])
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-rkl:          [SKIP][442] ([i915#2672] / [i915#3555]) -> [SKIP][443] ([i915#14544] / [i915#3555]) +2 other tests skip
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-rkl:          [SKIP][444] ([i915#14544] / [i915#3555]) -> [SKIP][445] ([i915#2672] / [i915#3555]) +1 other test skip
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
    - shard-dg2:          [SKIP][446] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][447] ([i915#15102] / [i915#3458]) +2 other tests skip
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
    - shard-dg1:          [SKIP][448] ([i915#4423] / [i915#8708]) -> [SKIP][449] ([i915#8708])
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
    - shard-rkl:          [SKIP][450] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][451]
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
    - shard-rkl:          [SKIP][452] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][453] ([i915#15102] / [i915#3023]) +8 other tests skip
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][454] ([i915#14544]) -> [SKIP][455] ([i915#15102])
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][456] ([i915#15102]) -> [SKIP][457] ([i915#14544]) +4 other tests skip
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-dg2:          [SKIP][458] ([i915#15102] / [i915#3458]) -> [SKIP][459] ([i915#10433] / [i915#15102] / [i915#3458])
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][460] ([i915#1825]) -> [SKIP][461] ([i915#14544] / [i915#1849] / [i915#5354]) +23 other tests skip
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move:
    - shard-rkl:          [SKIP][462] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][463] ([i915#1825]) +17 other tests skip
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move.html
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render:
    - shard-dg1:          [SKIP][464] ([i915#4423]) -> [SKIP][465]
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-dg1-15/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-suspend:
    - shard-rkl:          [SKIP][466] ([i915#15102] / [i915#3023]) -> [SKIP][467] ([i915#14544] / [i915#1849] / [i915#5354]) +13 other tests skip
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_frontbuffer_tracking@psr-suspend.html
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-suspend.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-rkl:          [SKIP][468] ([i915#14544]) -> [SKIP][469] ([i915#3555] / [i915#8228])
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_hdr@bpc-switch-suspend.html
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-rkl:          [SKIP][470] ([i915#3555] / [i915#8228]) -> [SKIP][471] ([i915#14544]) +1 other test skip
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_hdr@invalid-metadata-sizes.html
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-rkl:          [SKIP][472] ([i915#10656] / [i915#14544]) -> [SKIP][473] ([i915#10656])
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_joiner@invalid-modeset-big-joiner.html
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@invalid-modeset-ultra-joiner:
    - shard-rkl:          [SKIP][474] ([i915#12339]) -> [SKIP][475] ([i915#12339] / [i915#14544])
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_joiner@invalid-modeset-ultra-joiner.html
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_joiner@invalid-modeset-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-rkl:          [SKIP][476] ([i915#13522]) -> [SKIP][477] ([i915#13522] / [i915#14544])
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-rkl:          [SKIP][478] ([i915#14544]) -> [SKIP][479] ([i915#6301])
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_panel_fitting@atomic-fastset.html
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          [SKIP][480] ([i915#6301]) -> [SKIP][481] ([i915#14544])
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_panel_fitting@legacy.html
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-rkl:          [SKIP][482] ([i915#14712]) -> [SKIP][483] ([i915#14544])
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-rkl:          [SKIP][484] ([i915#13958]) -> [SKIP][485] ([i915#14544])
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_plane_multiple@2x-tiling-x.html
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-rkl:          [SKIP][486] ([i915#14544]) -> [SKIP][487] ([i915#14259])
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_plane_multiple@tiling-4.html
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a:
    - shard-rkl:          [SKIP][488] ([i915#12247]) -> [SKIP][489] ([i915#12247] / [i915#14544]) +1 other test skip
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a.html
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b:
    - shard-rkl:          [SKIP][490] ([i915#12247]) -> [SKIP][491] ([i915#12247] / [i915#14544] / [i915#8152]) +2 other tests skip
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b.html
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
    - shard-rkl:          [SKIP][492] ([i915#3555]) -> [SKIP][493] ([i915#14544] / [i915#3555] / [i915#8152])
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          [FAIL][494] ([i915#9295]) -> [SKIP][495] ([i915#3361])
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-7/igt@kms_pm_dc@dc6-dpms.html
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_rpm@pm-caching:
    - shard-rkl:          [DMESG-WARN][496] ([i915#12964]) -> [SKIP][497] ([i915#12916] / [i915#14544])
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_pm_rpm@pm-caching.html
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_pm_rpm@pm-caching.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          [SKIP][498] ([i915#14544] / [i915#6524]) -> [SKIP][499] ([i915#6524])
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_prime@basic-modeset-hybrid.html
   [499]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area:
    - shard-rkl:          [SKIP][500] ([i915#11520] / [i915#14544]) -> [SKIP][501] ([i915#11520]) +3 other tests skip
   [500]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html
   [501]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][502] ([i915#11520]) -> [SKIP][503] ([i915#11520] / [i915#14544]) +5 other tests skip
   [502]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-8/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
   [503]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-rkl:          [SKIP][504] ([i915#9683]) -> [SKIP][505] ([i915#14544] / [i915#9683])
   [504]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_psr2_su@page_flip-nv12.html
   [505]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@fbc-psr2-primary-blt:
    - shard-rkl:          [SKIP][506] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][507] ([i915#1072] / [i915#9732]) +9 other tests skip
   [506]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_psr@fbc-psr2-primary-blt.html
   [507]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_psr@fbc-psr2-primary-blt.html

  * igt@kms_psr@psr-sprite-plane-move:
    - shard-rkl:          [SKIP][508] ([i915#1072] / [i915#9732]) -> [SKIP][509] ([i915#1072] / [i915#14544] / [i915#9732]) +14 other tests skip
   [508]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-2/igt@kms_psr@psr-sprite-plane-move.html
   [509]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_psr@psr-sprite-plane-move.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-rkl:          [SKIP][510] ([i915#14544] / [i915#9685]) -> [SKIP][511] ([i915#9685])
   [510]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [511]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-rkl:          [SKIP][512] ([i915#14544]) -> [DMESG-WARN][513] ([i915#12964]) +1 other test dmesg-warn
   [512]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_rotation_crc@sprite-rotation-90.html
   [513]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-rkl:          [SKIP][514] ([i915#14544] / [i915#3555]) -> [SKIP][515] ([i915#3555]) +1 other test skip
   [514]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_setmode@clone-exclusive-crtc.html
   [515]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-rkl:          [SKIP][516] ([i915#14544]) -> [SKIP][517] ([i915#8623])
   [516]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [517]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vblank@query-forked-hang:
    - shard-rkl:          [DMESG-WARN][518] ([i915#12917] / [i915#12964]) -> [SKIP][519] ([i915#14544])
   [518]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@kms_vblank@query-forked-hang.html
   [519]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@kms_vblank@query-forked-hang.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-rkl:          [SKIP][520] ([i915#14544]) -> [SKIP][521] ([i915#9906])
   [520]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-virtual.html
   [521]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-8/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@perf_pmu@rc6-suspend:
    - shard-glk:          [INCOMPLETE][522] ([i915#13356] / [i915#14242]) -> [INCOMPLETE][523] ([i915#13356])
   [522]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-glk5/igt@perf_pmu@rc6-suspend.html
   [523]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-glk8/igt@perf_pmu@rc6-suspend.html

  * igt@prime_vgem@basic-read:
    - shard-rkl:          [SKIP][524] ([i915#14544] / [i915#3291] / [i915#3708]) -> [SKIP][525] ([i915#3291] / [i915#3708])
   [524]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-6/igt@prime_vgem@basic-read.html
   [525]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-2/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@fence-flip-hang:
    - shard-rkl:          [SKIP][526] ([i915#3708]) -> [SKIP][527] ([i915#14544] / [i915#3708])
   [526]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17462/shard-rkl-5/igt@prime_vgem@fence-flip-hang.html
   [527]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/shard-rkl-6/igt@prime_vgem@fence-flip-hang.html

  
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11190
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11521]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11521
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#12916]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12916
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
  [i915#13028]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13028
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13328]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13328
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13729
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13821
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#14121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14121
  [i915#14242]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14242
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15106]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15106
  [i915#15119]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15119
  [i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15136]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15136
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7294]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7294
  [i915#7387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7387
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8152
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8825
  [i915#8826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8826
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_17462 -> Patchwork_155279v2

  CI-20190529: 20190529
  CI_DRM_17462: e2df6bac5c3868532a64c869ff7546587aa3dbad @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8604: 8604
  Patchwork_155279v2: e2df6bac5c3868532a64c869ff7546587aa3dbad @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155279v2/index.html

[-- Attachment #2: Type: text/html, Size: 177958 bytes --]

RE: [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific

[Kandpal, Suraj]

> Subject: [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific
> 
> Rename pll functions to include ICL platform as these are used from ICL
> onwards.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 +++++++++----------
>  1 file changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 8ea96cc524a1..303f03b420ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -3754,9 +3754,9 @@ static bool combo_pll_get_hw_state(struct
> intel_display *display,
>  	return icl_pll_get_hw_state(display, pll, dpll_hw_state, enable_reg);  }
> 
> -static bool tbt_pll_get_hw_state(struct intel_display *display,
> -				 struct intel_dpll *pll,
> -				 struct intel_dpll_hw_state *dpll_hw_state)
> +static bool icl_tbt_pll_get_hw_state(struct intel_display *display,
> +				     struct intel_dpll *pll,
> +				     struct intel_dpll_hw_state *dpll_hw_state)
>  {
>  	return icl_pll_get_hw_state(display, pll, dpll_hw_state,
> TBT_PLL_ENABLE);  } @@ -3985,9 +3985,9 @@ static void
> combo_pll_enable(struct intel_display *display,
>  	/* DVFS post sequence would be here. See the comment above. */  }
> 
> -static void tbt_pll_enable(struct intel_display *display,
> -			   struct intel_dpll *pll,
> -			   const struct intel_dpll_hw_state *dpll_hw_state)
> +static void icl_tbt_pll_enable(struct intel_display *display,
> +			       struct intel_dpll *pll,
> +			       const struct intel_dpll_hw_state *dpll_hw_state)
>  {
>  	const struct icl_dpll_hw_state *hw_state = &dpll_hw_state->icl;
> 
> @@ -4070,8 +4070,8 @@ static void combo_pll_disable(struct intel_display
> *display,
>  	icl_pll_disable(display, pll, enable_reg);  }
> 
> -static void tbt_pll_disable(struct intel_display *display,
> -			    struct intel_dpll *pll)
> +static void icl_tbt_pll_disable(struct intel_display *display,
> +				struct intel_dpll *pll)
>  {
>  	icl_pll_disable(display, pll, TBT_PLL_ENABLE);  } @@ -4143,10
> +4143,10 @@ static const struct intel_dpll_funcs combo_pll_funcs = {
>  	.get_freq = icl_ddi_combo_pll_get_freq,  };
> 
> -static const struct intel_dpll_funcs tbt_pll_funcs = {
> -	.enable = tbt_pll_enable,
> -	.disable = tbt_pll_disable,
> -	.get_hw_state = tbt_pll_get_hw_state,
> +static const struct intel_dpll_funcs icl_tbt_pll_funcs = {
> +	.enable = icl_tbt_pll_enable,
> +	.disable = icl_tbt_pll_disable,
> +	.get_hw_state = icl_tbt_pll_get_hw_state,
>  	.get_freq = icl_ddi_tbt_pll_get_freq,
>  };
> 
> @@ -4160,7 +4160,7 @@ static const struct intel_dpll_funcs mg_pll_funcs = {
> static const struct dpll_info icl_plls[] = {
>  	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id =
> DPLL_ID_ICL_DPLL0, },
>  	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id =
> DPLL_ID_ICL_DPLL1, },
> -	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id =
> DPLL_ID_ICL_TBTPLL,
> +	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id =
> +DPLL_ID_ICL_TBTPLL,
>  	  .is_alt_port_dpll = true, },
>  	{ .name = "MG PLL 1", .funcs = &mg_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL1, },
>  	{ .name = "MG PLL 2", .funcs = &mg_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL2, }, @@ -4208,7 +4208,7 @@ static const struct
> intel_dpll_funcs dkl_pll_funcs = {  static const struct dpll_info tgl_plls[] = {
>  	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id =
> DPLL_ID_ICL_DPLL0, },
>  	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id =
> DPLL_ID_ICL_DPLL1, },
> -	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id =
> DPLL_ID_ICL_TBTPLL,
> +	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id =
> +DPLL_ID_ICL_TBTPLL,
>  	  .is_alt_port_dpll = true, },
>  	{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL1, },
>  	{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL2, }, @@ -4286,7 +4286,7 @@ static const struct
> intel_dpll_mgr adls_pll_mgr = {  static const struct dpll_info adlp_plls[] = {
>  	{ .name = "DPLL 0", .funcs = &combo_pll_funcs, .id =
> DPLL_ID_ICL_DPLL0, },
>  	{ .name = "DPLL 1", .funcs = &combo_pll_funcs, .id =
> DPLL_ID_ICL_DPLL1, },
> -	{ .name = "TBT PLL", .funcs = &tbt_pll_funcs, .id =
> DPLL_ID_ICL_TBTPLL,
> +	{ .name = "TBT PLL", .funcs = &icl_tbt_pll_funcs, .id =
> +DPLL_ID_ICL_TBTPLL,
>  	  .is_alt_port_dpll = true, },
>  	{ .name = "TC PLL 1", .funcs = &dkl_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL1, },
>  	{ .name = "TC PLL 2", .funcs = &dkl_pll_funcs, .id =
> DPLL_ID_ICL_MGPLL2, },
> --
> 2.34.1

RE: [CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers

[Kandpal, Suraj]

> Subject: [CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end
> helpers
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Factor out functions to begin and complete C10 PHY programming sequences
> to make the code more concise.
> 
> v2: Rename msgbus_update_config() to more descriptive
>     msg_bus_access_commit() (Jani)
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 62 +++++++++++---------
>  1 file changed, 35 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index a74c1be225ac..94ba7db2115a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -449,6 +449,31 @@ static u8 intel_c10_get_tx_term_ctl(const struct
> intel_crtc_state *crtc_state)
>  	}
>  }
> 
> +static void intel_c10_msgbus_access_begin(struct intel_encoder *encoder,
> +					  u8 lane_mask)
> +{
> +	if (!intel_encoder_is_c10phy(encoder))
> +		return;
> +
> +	intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1),
> +		      0, C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED); }
> +
> +static void intel_c10_msgbus_access_commit(struct intel_encoder *encoder,
> +					   u8 lane_mask, bool master_lane) {
> +	u8 val = C10_VDR_CTRL_UPDATE_CFG;
> +
> +	if (!intel_encoder_is_c10phy(encoder))
> +		return;
> +
> +	if (master_lane)
> +		val |= C10_VDR_CTRL_MASTER_LANE;
> +
> +	intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1),
> +		      0, val, MB_WRITE_COMMITTED);
> +}
> +
>  void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
>  				     const struct intel_crtc_state *crtc_state)  {
> @@ -472,9 +497,9 @@ void intel_cx0_phy_set_signal_levels(struct
> intel_encoder *encoder,
>  		return;
>  	}
> 
> +	intel_c10_msgbus_access_begin(encoder, owned_lane_mask);
> +
>  	if (intel_encoder_is_c10phy(encoder)) {
> -		intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C10_VDR_CONTROL(1),
> -			      0, C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
>  		intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C10_VDR_CMN(3),
>  			      C10_CMN3_TXVBOOST_MASK,
> 
> C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
> @@ -513,9 +538,7 @@ void intel_cx0_phy_set_signal_levels(struct
> intel_encoder *encoder,
>  		      0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
>  		      MB_WRITE_COMMITTED);
> 
> -	if (intel_encoder_is_c10phy(encoder))
> -		intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C10_VDR_CONTROL(1),
> -			      0, C10_VDR_CTRL_UPDATE_CFG,
> MB_WRITE_COMMITTED);
> +	intel_c10_msgbus_access_commit(encoder, owned_lane_mask,
> false);
> 
>  	intel_cx0_phy_transaction_end(encoder, wakeref);  } @@ -2119,9
> +2142,7 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder
> *encoder,
>  	 * According to C10 VDR Register programming Sequence we need
>  	 * to do this to read PHY internal registers from MsgBus.
>  	 */
> -	intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1),
> -		      0, C10_VDR_CTRL_MSGBUS_ACCESS,
> -		      MB_WRITE_COMMITTED);
> +	intel_c10_msgbus_access_begin(encoder, lane);
> 
>  	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
>  		pll_state->pll[i] = intel_cx0_read(encoder, lane,
> PHY_C10_VDR_PLL(i)); @@ -2140,9 +2161,7 @@ static void
> intel_c10_pll_program(struct intel_display *display,  {
>  	int i;
> 
> -	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CONTROL(1),
> -		      0, C10_VDR_CTRL_MSGBUS_ACCESS,
> -		      MB_WRITE_COMMITTED);
> +	intel_c10_msgbus_access_begin(encoder, INTEL_CX0_BOTH_LANES);
> 
>  	/* Program the pll values only for the master lane */
>  	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) @@ -2157,9 +2176,8
> @@ static void intel_c10_pll_program(struct intel_display *display,
>  	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES,
> PHY_C10_VDR_CUSTOM_WIDTH,
>  		      C10_VDR_CUSTOM_WIDTH_MASK,
> C10_VDR_CUSTOM_WIDTH_8_10,
>  		      MB_WRITE_COMMITTED);
> -	intel_cx0_rmw(encoder, INTEL_CX0_LANE0,
> PHY_C10_VDR_CONTROL(1),
> -		      0, C10_VDR_CTRL_MASTER_LANE |
> C10_VDR_CTRL_UPDATE_CFG,
> -		      MB_WRITE_COMMITTED);
> +
> +	intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true);
>  }
> 
>  static void intel_c10pll_dump_hw_state(struct intel_display *display, @@ -
> 2959,11 +2977,7 @@ static void intel_cx0_program_phy_lane(struct
> intel_encoder *encoder, int lane_c
>  	bool dp_alt_mode =
> intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder));
>  	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> 
> -	if (intel_encoder_is_c10phy(encoder))
> -		intel_cx0_rmw(encoder, owned_lane_mask,
> -			      PHY_C10_VDR_CONTROL(1), 0,
> -			      C10_VDR_CTRL_MSGBUS_ACCESS,
> -			      MB_WRITE_COMMITTED);
> +	intel_c10_msgbus_access_begin(encoder, owned_lane_mask);
> 
>  	if (lane_reversal)
>  		disables = REG_GENMASK8(3, 0) >> lane_count; @@ -
> 2988,11 +3002,7 @@ static void intel_cx0_program_phy_lane(struct
> intel_encoder *encoder, int lane_c
>  			      MB_WRITE_COMMITTED);
>  	}
> 
> -	if (intel_encoder_is_c10phy(encoder))
> -		intel_cx0_rmw(encoder, owned_lane_mask,
> -			      PHY_C10_VDR_CONTROL(1), 0,
> -			      C10_VDR_CTRL_UPDATE_CFG,
> -			      MB_WRITE_COMMITTED);
> +	intel_c10_msgbus_access_commit(encoder, owned_lane_mask,
> false);
>  }
> 
>  static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask) @@ -3260,9
> +3270,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
> 
>  	wakeref = intel_cx0_phy_transaction_begin(encoder);
> 
> -	if (intel_encoder_is_c10phy(encoder))
> -		intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C10_VDR_CONTROL(1), 0,
> -			      C10_VDR_CTRL_MSGBUS_ACCESS,
> MB_WRITE_COMMITTED);
> +	intel_c10_msgbus_access_begin(encoder, owned_lane_mask);
> 
>  	for (i = 0; i < 4; i++) {
>  		int tx = i % 2 + 1;
> --
> 2.34.1

RE: [CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag

[Kandpal, Suraj]

> Subject: [CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Sanitize setting the Cx0 PLL use_c10 flag during state computation and HW
> readout, making sure they happen the same way in the
> intel_c{10,20}pll_calc_state() and intel_c{10,20}pll_readout_hw_state()
> functions.
> 
> Follow-up changes will add more state computation/HW readout, this change
> prepares for those as well.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 23 ++++++++++++--------
>  1 file changed, 14 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 94ba7db2115a..dd4cf335f3ae 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2130,12 +2130,15 @@ static int intel_c10pll_calc_port_clock(struct
> intel_encoder *encoder,
>  					const struct intel_c10pll_state
> *pll_state);
> 
>  static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> -					  struct intel_c10pll_state *pll_state)
> +					  struct intel_cx0pll_state
> *cx0pll_state)
>  {
> +	struct intel_c10pll_state *pll_state = &cx0pll_state->c10;
>  	u8 lane = INTEL_CX0_LANE0;
>  	intel_wakeref_t wakeref;
>  	int i;
> 
> +	cx0pll_state->use_c10 = true;
> +
>  	wakeref = intel_cx0_phy_transaction_begin(encoder);
> 
>  	/*
> @@ -2361,6 +2364,8 @@ static int intel_c20pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  	const struct intel_c20pll_state * const *tables;
>  	int i;
> 
> +	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> +
>  	/* try computed C20 HDMI tables before using consolidated tables */
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
>  		if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0) @@ -
> 2377,7 +2382,6 @@ static int intel_c20pll_calc_state(struct intel_crtc_state
> *crtc_state,
>  			intel_cx0pll_update_ssc(encoder,
>  						&crtc_state-
> >dpll_hw_state.cx0pll,
> 
> 	intel_crtc_has_dp_encoder(crtc_state));
> -			crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
>  			return 0;
>  		}
>  	}
> @@ -2444,13 +2448,16 @@ static int intel_c20pll_calc_port_clock(struct
> intel_encoder *encoder,  }
> 
>  static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> -					  struct intel_c20pll_state *pll_state)
> +					  struct intel_cx0pll_state
> *cx0pll_state)
>  {
> +	struct intel_c20pll_state *pll_state = &cx0pll_state->c20;
>  	struct intel_display *display = to_intel_display(encoder);
>  	bool cntx;
>  	intel_wakeref_t wakeref;
>  	int i;
> 
> +	cx0pll_state->use_c10 = false;
> +
>  	wakeref = intel_cx0_phy_transaction_begin(encoder);
> 
>  	/* 1. Read current context selection */ @@ -3470,12 +3477,10 @@
> void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>  	if (pll_state->tbt_mode)
>  		return;
> 
> -	if (intel_encoder_is_c10phy(encoder)) {
> -		intel_c10pll_readout_hw_state(encoder, &pll_state->c10);
> -		pll_state->use_c10 = true;
> -	} else {
> -		intel_c20pll_readout_hw_state(encoder, &pll_state->c20);
> -	}
> +	if (intel_encoder_is_c10phy(encoder))
> +		intel_c10pll_readout_hw_state(encoder, pll_state);
> +	else
> +		intel_c20pll_readout_hw_state(encoder, pll_state);
>  }
> 
>  static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
> --
> 2.34.1

RE: [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables

[Kandpal, Suraj]

> Subject: [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from
> tables
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> A follow up change adds a computation for the C20 PLL VDR state, which is
> common to both the HDMI algorithmic and DP/HDMI table based method.
> To prepare for that streamline the code. The C10 counterpart would benefit
> from the same change, leave that for later adding a TODO comment.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 68 ++++++++++++++------
>  1 file changed, 47 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index dd4cf335f3ae..0dd367457f93 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2077,6 +2077,10 @@ static void intel_c10pll_update_pll(struct
> intel_encoder *encoder,
>  		pll_state->c10.pll[i] = 0;
>  }
> 
> +/*
> + * TODO: Convert the following align with intel_c20pll_find_table() and
> + * intel_c20pll_calc_state_from_table().

* " following to align with..."

> + */
>  static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
>  					      const struct intel_c10pll_state *
> const *tables,
>  					      bool is_dp, int port_clock,
> @@ -2330,7 +2334,7 @@ static int
> intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)  }
> 
>  static const struct intel_c20pll_state * const * -intel_c20_pll_tables_get(struct
> intel_crtc_state *crtc_state,
> +intel_c20_pll_tables_get(const struct intel_crtc_state *crtc_state,
>  			 struct intel_encoder *encoder)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state); @@ -
> 2358,35 +2362,57 @@ intel_c20_pll_tables_get(struct intel_crtc_state
> *crtc_state,
>  	return NULL;
>  }
> 
> -static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> -				   struct intel_encoder *encoder)
> +static const struct intel_c20pll_state * intel_c20_pll_find_table(const
> +struct intel_crtc_state *crtc_state,
> +			 struct intel_encoder *encoder)
>  {
>  	const struct intel_c20pll_state * const *tables;
>  	int i;
> 
> -	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> -
> -	/* try computed C20 HDMI tables before using consolidated tables */
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> -		if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0)
> -			return 0;
> -	}
> -
>  	tables = intel_c20_pll_tables_get(crtc_state, encoder);
>  	if (!tables)
> +		return NULL;
> +
> +	for (i = 0; tables[i]; i++)
> +		if (crtc_state->port_clock == tables[i]->clock)
> +			return tables[i];
> +
> +	return NULL;
> +}
> +
> +static int intel_c20pll_calc_state_from_table(struct intel_crtc_state
> *crtc_state,
> +					      struct intel_encoder *encoder) {
> +	const struct intel_c20pll_state *table;
> +
> +	table = intel_c20_pll_find_table(crtc_state, encoder);
> +	if (!table)
>  		return -EINVAL;
> 
> -	for (i = 0; tables[i]; i++) {
> -		if (crtc_state->port_clock == tables[i]->clock) {
> -			crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
> -			intel_cx0pll_update_ssc(encoder,
> -						&crtc_state-
> >dpll_hw_state.cx0pll,
> -
> 	intel_crtc_has_dp_encoder(crtc_state));
> -			return 0;
> -		}
> -	}
> +	crtc_state->dpll_hw_state.cx0pll.c20 = *table;
> 
> -	return -EINVAL;
> +	intel_cx0pll_update_ssc(encoder, &crtc_state->dpll_hw_state.cx0pll,
> +				intel_crtc_has_dp_encoder(crtc_state));
> +
> +	return 0;
> +}
> +
> +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> +				   struct intel_encoder *encoder)
> +{
> +	int err = -ENOENT;
> +
> +	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> +
> +	/* try computed C20 HDMI tables before using consolidated tables */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		/* TODO: Update SSC state for HDMI as well */
> +		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> +
> +	if (err)
> +		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);


So this is something I have been meaning to fix we should really be using the HDMI tables already defined
Computing them ourselves, that should be reserved for only when we do not have any HDMI table for the said port clock available.
Also if we use the computed tables directly that means we never end up using the defined tables.

SO the flow here should be

err = intel_c20pll_calc_state_from_table(crtc_state, encoder);

if (err && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)))
	err = intel_c20_compute_hdmi_tmds_pll(crtc_state);

something like this.

Regards,
Suraj Kandpal
 
> +
> +	return err;
>  }
> 
>  int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> --
> 2.34.1

RE: [CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state

[Kandpal, Suraj]

> Subject: [CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL
> state
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> The Cx0 PLL enable programming needs to know if the PLL is in DP or HDMI
> mode. The PLL manager framework doesn't pass the CRTC state to the PLL's
> enable hook, so prepare here for the conversion to use the PLL manager for
> Cx0 PHY PLLs by tracking the DP/HDMI mode in the PLL state.
> 
> This change has the advantage, that the VDR HW/SW state can be verified
> now.
> 
> A follow up change will convert the PLL enable function to retrieve the
> DP/HDMI mode parameter from the PLL state.
> 
> This also allows dropping the is_dp and port clock params from the
> intel_c20_pll_program() function, since it can retrieve these now from the PLL
> state.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 115 +++++++++++++-----
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |   5 +
>  2 files changed, 89 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 0dd367457f93..0ea9c33e4ce3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2362,6 +2362,76 @@ intel_c20_pll_tables_get(const struct
> intel_crtc_state *crtc_state,
>  	return NULL;
>  }
> 
> +static u8 intel_c20_get_dp_rate(u32 clock); static u8
> +intel_c20_get_hdmi_rate(u32 clock); static bool is_hdmi_frl(u32 clock);
> +static int intel_get_c20_custom_width(u32 clock, bool dp);
> +
> +static void intel_c20_calc_vdr_params(struct intel_c20pll_vdr_state *vdr,
> bool is_dp,
> +				      int port_clock)
> +{
> +	vdr->custom_width = intel_get_c20_custom_width(port_clock,
> is_dp);
> +
> +	vdr->serdes_rate = 0;
> +	vdr->hdmi_rate = 0;
> +
> +	if (is_dp) {
> +		vdr->serdes_rate = PHY_C20_IS_DP |
> +
> PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
> +	} else {
> +		if (is_hdmi_frl(port_clock))
> +			vdr->serdes_rate = PHY_C20_IS_HDMI_FRL;
> +
> +		vdr->hdmi_rate = intel_c20_get_hdmi_rate(port_clock);
> +	}
> +}
> +
> +#define PHY_C20_SERDES_RATE_MASK	(PHY_C20_IS_DP |
> PHY_C20_DP_RATE_MASK | PHY_C20_IS_HDMI_FRL)
> +
> +static void intel_c20_readout_vdr_params(struct intel_encoder *encoder,
> +					 struct intel_c20pll_vdr_state *vdr,
> bool *cntx) {
> +	u8 serdes;
> +
> +	serdes = intel_cx0_read(encoder, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_SERDES_RATE);
> +	*cntx = serdes & PHY_C20_CONTEXT_TOGGLE;
> +
> +	vdr->custom_width = intel_cx0_read(encoder, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_WIDTH) &
> +			    PHY_C20_CUSTOM_WIDTH_MASK;
> +
> +	vdr->serdes_rate = serdes & PHY_C20_SERDES_RATE_MASK;
> +	if (!(vdr->serdes_rate & PHY_C20_IS_DP))
> +		vdr->hdmi_rate = intel_cx0_read(encoder, INTEL_CX0_LANE0,
> PHY_C20_VDR_HDMI_RATE) &
> +				 PHY_C20_HDMI_RATE_MASK;
> +	else
> +		vdr->hdmi_rate = 0;
> +}
> +
> +static void intel_c20_program_vdr_params(struct intel_encoder *encoder,
> +					 const struct intel_c20pll_vdr_state
> *vdr,
> +					 u8 owned_lane_mask)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +
> +	drm_WARN_ON(display->drm, vdr->custom_width &
> ~PHY_C20_CUSTOM_WIDTH_MASK);
> +	intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_WIDTH,
> +		      PHY_C20_CUSTOM_WIDTH_MASK, vdr->custom_width,
> +		      MB_WRITE_COMMITTED);
> +
> +	drm_WARN_ON(display->drm, vdr->serdes_rate &
> ~PHY_C20_SERDES_RATE_MASK);
> +	intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> +		      PHY_C20_SERDES_RATE_MASK, vdr->serdes_rate,
> +		      MB_WRITE_COMMITTED);
> +
> +	if (vdr->serdes_rate & PHY_C20_IS_DP)
> +		return;
> +
> +	drm_WARN_ON(display->drm, vdr->hdmi_rate &
> ~PHY_C20_HDMI_RATE_MASK);
> +	intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES,
> PHY_C20_VDR_HDMI_RATE,
> +		      PHY_C20_HDMI_RATE_MASK, vdr->hdmi_rate,
> +		      MB_WRITE_COMMITTED);
> +}
> +
>  static const struct intel_c20pll_state *  intel_c20_pll_find_table(const struct
> intel_crtc_state *crtc_state,
>  			 struct intel_encoder *encoder)
> @@ -2400,19 +2470,26 @@ static int
> intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_stat  static int
> intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
>  				   struct intel_encoder *encoder)
>  {
> +	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
>  	int err = -ENOENT;
> 
>  	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> 
>  	/* try computed C20 HDMI tables before using consolidated tables */
> -	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +	if (!is_dp)
>  		/* TODO: Update SSC state for HDMI as well */
>  		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> 
>  	if (err)
>  		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> 
> -	return err;
> +	if (err)
> +		return err;
> +
> +	intel_c20_calc_vdr_params(&crtc_state-
> >dpll_hw_state.cx0pll.c20.vdr,
> +				  is_dp, crtc_state->port_clock);
> +
> +	return 0;
>  }
> 
>  int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, @@ -2486,8
> +2563,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder
> *encoder,
> 
>  	wakeref = intel_cx0_phy_transaction_begin(encoder);
> 
> -	/* 1. Read current context selection */
> -	cntx = intel_cx0_read(encoder, INTEL_CX0_LANE0,
> PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_C20_CONTEXT_TOGGLE;
> +	/* 1. Read VDR params and current context selection */
> +	intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
> 
>  	/* Read Tx configuration */
>  	for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { @@ -2676,11 +2753,9
> @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
> 
>  static void intel_c20_pll_program(struct intel_display *display,
>  				  struct intel_encoder *encoder,
> -				  const struct intel_c20pll_state *pll_state,
> -				  bool is_dp, int port_clock)
> +				  const struct intel_c20pll_state *pll_state)
>  {
>  	u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> -	u8 serdes;
>  	bool cntx;
>  	int i;
> 
> @@ -2750,30 +2825,8 @@ static void intel_c20_pll_program(struct
> intel_display *display,
>  	}
> 
>  	/* 4. Program custom width to match the link protocol */
> -	intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_WIDTH,
> -		      PHY_C20_CUSTOM_WIDTH_MASK,
> -
> PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(port_clock, is_dp)),
> -		      MB_WRITE_COMMITTED);
> -
>  	/* 5. For DP or 6. For HDMI */
> -	serdes = 0;

With this 4,5 can be under the same multi comment now

Regards,
Suraj Kandpal

> -
> -	if (is_dp)
> -		serdes = PHY_C20_IS_DP |
> -
> PHY_C20_DP_RATE(intel_c20_get_dp_rate(port_clock));
> -	else if (is_hdmi_frl(port_clock))
> -		serdes = PHY_C20_IS_HDMI_FRL;
> -
> -	intel_cx0_rmw(encoder, owned_lane_mask,
> PHY_C20_VDR_CUSTOM_SERDES_RATE,
> -		      PHY_C20_IS_DP | PHY_C20_DP_RATE_MASK |
> PHY_C20_IS_HDMI_FRL,
> -		      serdes,
> -		      MB_WRITE_COMMITTED);
> -
> -	if (!is_dp)
> -		intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES,
> PHY_C20_VDR_HDMI_RATE,
> -			      PHY_C20_HDMI_RATE_MASK,
> -			      intel_c20_get_hdmi_rate(port_clock),
> -			      MB_WRITE_COMMITTED);
> +	intel_c20_program_vdr_params(encoder, &pll_state->vdr,
> +owned_lane_mask);
> 
>  	/*
>  	 * 7. Write Vendor specific registers to toggle context setting to load
> @@ -3098,7 +3151,7 @@ static void __intel_cx0pll_enable(struct
> intel_encoder *encoder,
>  	if (intel_encoder_is_c10phy(encoder))
>  		intel_c10_pll_program(display, encoder, &pll_state->c10);
>  	else
> -		intel_c20_pll_program(display, encoder, &pll_state->c20,
> is_dp, port_clock);
> +		intel_c20_pll_program(display, encoder, &pll_state->c20);
> 
>  	/*
>  	 * 6. Program the enabled and disabled owned PHY lane diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index f131bdd1c975..43c7200050e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -255,6 +255,11 @@ struct intel_c20pll_state {
>  		u16 mplla[10];
>  		u16 mpllb[11];
>  	};
> +	struct intel_c20pll_vdr_state {
> +		u8 custom_width;
> +		u8 serdes_rate;
> +		u8 hdmi_rate;
> +	} vdr;
>  };
> 
>  struct intel_cx0pll_state {
> --
> 2.34.1

RE: [CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier

[Kandpal, Suraj]

> Subject: [CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions
> earlier
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Move the definitions of the
>   intel_c10pll_calc_port_clock()
>   intel_c20_get_dp_rate()
>   intel_c20_get_hdmi_rate()
>   is_hdmi_frl()
>   is_dp2()
>   intel_get_c20_custom_width()
> functions earlier to avoid the forward declarations.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 232 +++++++++----------
>  1 file changed, 112 insertions(+), 120 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 0ea9c33e4ce3..949727d3fc6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2131,7 +2131,31 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,  }
> 
>  static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> -					const struct intel_c10pll_state
> *pll_state);
> +					const struct intel_c10pll_state
> *pll_state) {
> +	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> +	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
> +	int tmpclk = 0;
> +
> +	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> +		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> +		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
> +		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
> +	}
> +
> +	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK,
> pll_state->pll[3]) << 8 |
> +		      pll_state->pll[2]) / 2 + 16;
> +
> +	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state-
> >pll[15]);
> +	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state-
> >pll[15]);
> +
> +	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier
> << 16) + frac_quot) +
> +				     DIV_ROUND_CLOSEST(refclk * frac_rem,
> frac_den),
> +				     10 << (tx_clk_div + 16));
> +	tmpclk *= (hdmi_div ? 2 : 1);
> +
> +	return tmpclk;
> +}
> 
>  static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
>  					  struct intel_cx0pll_state
> *cx0pll_state) @@ -2362,10 +2386,93 @@ intel_c20_pll_tables_get(const
> struct intel_crtc_state *crtc_state,
>  	return NULL;
>  }
> 
> -static u8 intel_c20_get_dp_rate(u32 clock); -static u8
> intel_c20_get_hdmi_rate(u32 clock); -static bool is_hdmi_frl(u32 clock); -
> static int intel_get_c20_custom_width(u32 clock, bool dp);
> +static u8 intel_c20_get_dp_rate(u32 clock) {
> +	switch (clock) {
> +	case 162000: /* 1.62 Gbps DP1.4 */
> +		return 0;
> +	case 270000: /* 2.7 Gbps DP1.4 */
> +		return 1;
> +	case 540000: /* 5.4 Gbps DP 1.4 */
> +		return 2;
> +	case 810000: /* 8.1 Gbps DP1.4 */
> +		return 3;
> +	case 216000: /* 2.16 Gbps eDP */
> +		return 4;
> +	case 243000: /* 2.43 Gbps eDP */
> +		return 5;
> +	case 324000: /* 3.24 Gbps eDP */
> +		return 6;
> +	case 432000: /* 4.32 Gbps eDP */
> +		return 7;
> +	case 1000000: /* 10 Gbps DP2.0 */
> +		return 8;
> +	case 1350000: /* 13.5 Gbps DP2.0 */
> +		return 9;
> +	case 2000000: /* 20 Gbps DP2.0 */
> +		return 10;
> +	case 648000: /* 6.48 Gbps eDP*/
> +		return 11;
> +	case 675000: /* 6.75 Gbps eDP*/
> +		return 12;
> +	default:
> +		MISSING_CASE(clock);
> +		return 0;
> +	}
> +}
> +
> +static u8 intel_c20_get_hdmi_rate(u32 clock) {
> +	if (clock >= 25175 && clock <= 600000)
> +		return 0;
> +
> +	switch (clock) {
> +	case 300000: /* 3 Gbps */
> +	case 600000: /* 6 Gbps */
> +	case 1200000: /* 12 Gbps */
> +		return 1;
> +	case 800000: /* 8 Gbps */
> +		return 2;
> +	case 1000000: /* 10 Gbps */
> +		return 3;
> +	default:
> +		MISSING_CASE(clock);
> +		return 0;
> +	}
> +}
> +
> +static bool is_hdmi_frl(u32 clock)
> +{
> +	switch (clock) {
> +	case 300000: /* 3 Gbps */
> +	case 600000: /* 6 Gbps */
> +	case 800000: /* 8 Gbps */
> +	case 1000000: /* 10 Gbps */
> +	case 1200000: /* 12 Gbps */
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool is_dp2(u32 clock)
> +{
> +	/* DP2.0 clock rates */
> +	if (clock == 1000000 || clock == 1350000 || clock  == 2000000)
> +		return true;
> +
> +	return false;
> +}
> +
> +static int intel_get_c20_custom_width(u32 clock, bool dp) {
> +	if (dp && is_dp2(clock))
> +		return 2;
> +	else if (is_hdmi_frl(clock))
> +		return 1;
> +	else
> +		return 0;
> +}
> 
>  static void intel_c20_calc_vdr_params(struct intel_c20pll_vdr_state *vdr, bool
> is_dp,
>  				      int port_clock)
> @@ -2654,84 +2761,6 @@ void intel_cx0pll_dump_hw_state(struct
> intel_display *display,
>  		intel_c20pll_dump_hw_state(display, &hw_state->c20);  }
> 
> -static u8 intel_c20_get_dp_rate(u32 clock) -{
> -	switch (clock) {
> -	case 162000: /* 1.62 Gbps DP1.4 */
> -		return 0;
> -	case 270000: /* 2.7 Gbps DP1.4 */
> -		return 1;
> -	case 540000: /* 5.4 Gbps DP 1.4 */
> -		return 2;
> -	case 810000: /* 8.1 Gbps DP1.4 */
> -		return 3;
> -	case 216000: /* 2.16 Gbps eDP */
> -		return 4;
> -	case 243000: /* 2.43 Gbps eDP */
> -		return 5;
> -	case 324000: /* 3.24 Gbps eDP */
> -		return 6;
> -	case 432000: /* 4.32 Gbps eDP */
> -		return 7;
> -	case 1000000: /* 10 Gbps DP2.0 */
> -		return 8;
> -	case 1350000: /* 13.5 Gbps DP2.0 */
> -		return 9;
> -	case 2000000: /* 20 Gbps DP2.0 */
> -		return 10;
> -	case 648000: /* 6.48 Gbps eDP*/
> -		return 11;
> -	case 675000: /* 6.75 Gbps eDP*/
> -		return 12;
> -	default:
> -		MISSING_CASE(clock);
> -		return 0;
> -	}
> -}
> -
> -static u8 intel_c20_get_hdmi_rate(u32 clock) -{
> -	if (clock >= 25175 && clock <= 600000)
> -		return 0;
> -
> -	switch (clock) {
> -	case 300000: /* 3 Gbps */
> -	case 600000: /* 6 Gbps */
> -	case 1200000: /* 12 Gbps */
> -		return 1;
> -	case 800000: /* 8 Gbps */
> -		return 2;
> -	case 1000000: /* 10 Gbps */
> -		return 3;
> -	default:
> -		MISSING_CASE(clock);
> -		return 0;
> -	}
> -}
> -
> -static bool is_dp2(u32 clock)
> -{
> -	/* DP2.0 clock rates */
> -	if (clock == 1000000 || clock == 1350000 || clock  == 2000000)
> -		return true;
> -
> -	return false;
> -}
> -
> -static bool is_hdmi_frl(u32 clock)
> -{
> -	switch (clock) {
> -	case 300000: /* 3 Gbps */
> -	case 600000: /* 6 Gbps */
> -	case 800000: /* 8 Gbps */
> -	case 1000000: /* 10 Gbps */
> -	case 1200000: /* 12 Gbps */
> -		return true;
> -	default:
> -		return false;
> -	}
> -}
> -
>  static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder)  {
>  	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
> @@ -2741,16 +2770,6 @@ static bool
> intel_c20_protocol_switch_valid(struct intel_encoder *encoder)
>  	return intel_tc_port_in_legacy_mode(intel_dig_port);
>  }
> 
> -static int intel_get_c20_custom_width(u32 clock, bool dp) -{
> -	if (dp && is_dp2(clock))
> -		return 2;
> -	else if (is_hdmi_frl(clock))
> -		return 1;
> -	else
> -		return 0;
> -}
> -
>  static void intel_c20_pll_program(struct intel_display *display,
>  				  struct intel_encoder *encoder,
>  				  const struct intel_c20pll_state *pll_state)
> @@ -2837,33 +2856,6 @@ static void intel_c20_pll_program(struct
> intel_display *display,
>  		      MB_WRITE_COMMITTED);
>  }
> 
> -static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder,
> -					const struct intel_c10pll_state
> *pll_state)
> -{
> -	unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
> -	unsigned int multiplier, tx_clk_div, hdmi_div, refclk = 38400;
> -	int tmpclk = 0;
> -
> -	if (pll_state->pll[0] & C10_PLL0_FRACEN) {
> -		frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11];
> -		frac_rem =  pll_state->pll[14] << 8 | pll_state->pll[13];
> -		frac_den =  pll_state->pll[10] << 8 | pll_state->pll[9];
> -	}
> -
> -	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK,
> pll_state->pll[3]) << 8 |
> -		      pll_state->pll[2]) / 2 + 16;
> -
> -	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state-
> >pll[15]);
> -	hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state-
> >pll[15]);
> -
> -	tmpclk = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier
> << 16) + frac_quot) +
> -				     DIV_ROUND_CLOSEST(refclk * frac_rem,
> frac_den),
> -				     10 << (tx_clk_div + 16));
> -	tmpclk *= (hdmi_div ? 2 : 1);
> -
> -	return tmpclk;
> -}
> -
>  static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>  					 const struct intel_cx0pll_state
> *pll_state,
>  					 bool is_dp, int port_clock,
> --
> 2.34.1

RE: [CI 07/32] drm/i915/display: Add macro to get DDI port width from a register value

[Kandpal, Suraj]

> Subject: [CI 07/32] drm/i915/display: Add macro to get DDI port width from a
> register value
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> A follow-up change will need to retrieve the DDI port field from the register
> value, add a macro for this. Make things symmetric with setting the field in the
> register.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9d71e26a4fa2..c14d3caa73a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -2349,8 +2349,13 @@ enum skl_power_gate {
>  #define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)
>  #define  DDI_A_4_LANES				REG_BIT(4)
>  #define  DDI_PORT_WIDTH_MASK			REG_GENMASK(3, 1)
> +#define  DDI_PORT_WIDTH_ENCODE(width)		((width) == 3 ? 4 :
> (width) - 1)
> +#define  DDI_PORT_WIDTH_DECODE(regval)		((regval) == 4 ? 3 :
> (regval) + 1)
>  #define  DDI_PORT_WIDTH(width)
> 	REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \
> -							       ((width) == 3 ? 4 :
> (width) - 1))
> +
> DDI_PORT_WIDTH_ENCODE(width))
> +#define  DDI_PORT_WIDTH_GET(regval)
> 	DDI_PORT_WIDTH_DECODE(REG_FIELD_GET(DDI_PORT_WIDTH_MAS
> K, \
> +
> 	    (regval)))
> +
>  #define  DDI_PORT_WIDTH_SHIFT			1
>  #define  DDI_INIT_DISPLAY_DETECTED		REG_BIT(0)
> 
> --
> 2.34.1

RE: [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state

[Kandpal, Suraj]

> Subject: [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in
> the PLL state
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> The Cx0 PLL enable programming requires the enabled lane count. The PLL
> manager framework doesn't pass the CRTC state to the PLL's enable hook, so
> prepare here for the conversion to use the PLL manager, by tracking the
> enabled lane count in the PLL state as well. This has the advantage, that the
> enabled lane count can be verified against the PHY/PLL's enabled TX lanes.
> 
> This also allows dropping the lane count param from the
> __intel_cx0pll_enable() function, since it can retrieve this now from the PLL
> state.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 55 ++++++++++++++++---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
>  2 files changed, 49 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 949727d3fc6d..cc5aa38c3364 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -12,6 +12,7 @@
>  #include "intel_alpm.h"
>  #include "intel_cx0_phy.h"
>  #include "intel_cx0_phy_regs.h"
> +#include "intel_display_regs.h"
>  #include "intel_ddi.h"
>  #include "intel_ddi_buf_trans.h"
>  #include "intel_de.h"
> @@ -2083,7 +2084,7 @@ static void intel_c10pll_update_pll(struct
> intel_encoder *encoder,
>   */
>  static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
>  					      const struct intel_c10pll_state *
> const *tables,
> -					      bool is_dp, int port_clock,
> +					      bool is_dp, int port_clock, int
> lane_count,
>  					      struct intel_cx0pll_state *pll_state)
> {
>  	int i;
> @@ -2093,7 +2094,9 @@ static int intel_c10pll_calc_state_from_table(struct
> intel_encoder *encoder,
>  			pll_state->c10 = *tables[i];
>  			intel_cx0pll_update_ssc(encoder, pll_state, is_dp);
>  			intel_c10pll_update_pll(encoder, pll_state);
> +
>  			pll_state->use_c10 = true;
> +			pll_state->lane_count = lane_count;
> 
>  			return 0;
>  		}
> @@ -2114,7 +2117,7 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
> 
>  	err = intel_c10pll_calc_state_from_table(encoder, tables,
> 
> intel_crtc_has_dp_encoder(crtc_state),
> -						 crtc_state->port_clock,
> +						 crtc_state->port_clock,
> crtc_state->lane_count,
>  						 &crtc_state-
> >dpll_hw_state.cx0pll);
> 
>  	if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> @@ -2126,6 +2129,7 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  	intel_c10pll_update_pll(encoder,
>  				&crtc_state->dpll_hw_state.cx0pll);
>  	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
> +	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
> 
>  	return 0;
>  }
> @@ -2157,6 +2161,37 @@ static int intel_c10pll_calc_port_clock(struct
> intel_encoder *encoder,
>  	return tmpclk;
>  }
> 
> +static int readout_enabled_lane_count(struct intel_encoder *encoder) {
> +	struct intel_display *display = to_intel_display(encoder);
> +	u8 enabled_tx_lane_count = 0;
> +	int max_tx_lane_count;
> +	int tx_lane;
> +
> +	/*
> +	 * TODO: also check inactive TX lanes in all PHY lanes owned by the
> +	 * display. For now checking only those PHY lane(s) which are owned
> +	 * based on the active TX lane count (i.e.
> +	 *   1,2 active TX lanes -> PHY lane#0
> +	 *   3,4 active TX lanes -> PHY lane#0 and PHY lane#1).
> +	 */
> +	max_tx_lane_count = DDI_PORT_WIDTH_GET(intel_de_read(display,
> DDI_BUF_CTL(encoder->port)));
> +	if (!drm_WARN_ON(display->drm, max_tx_lane_count == 0))
> +		max_tx_lane_count =
> roundup_pow_of_two(max_tx_lane_count);
> +
> +	for (tx_lane = 0; tx_lane < max_tx_lane_count; tx_lane++) {
> +		u8 phy_lane_mask = tx_lane < 2 ? INTEL_CX0_LANE0 :
> INTEL_CX0_LANE1;
> +		int tx = tx_lane % 2 + 1;
> +		u8 val;
> +
> +		val = intel_cx0_read(encoder, phy_lane_mask,
> PHY_CX0_TX_CONTROL(tx, 2));
> +		if (!(val & CONTROL2_DISABLE_SINGLE_TX))
> +			enabled_tx_lane_count++;
> +	}
> +
> +	return enabled_tx_lane_count;
> +}
> +
>  static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
>  					  struct intel_cx0pll_state
> *cx0pll_state)  { @@ -2175,6 +2210,8 @@ static void
> intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
>  	 */
>  	intel_c10_msgbus_access_begin(encoder, lane);
> 
> +	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
> +
>  	for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++)
>  		pll_state->pll[i] = intel_cx0_read(encoder, lane,
> PHY_C10_VDR_PLL(i));
> 
> @@ -2581,6 +2618,7 @@ static int intel_c20pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  	int err = -ENOENT;
> 
>  	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> +	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
> 
>  	/* try computed C20 HDMI tables before using consolidated tables */
>  	if (!is_dp)
> @@ -2670,6 +2708,8 @@ static void intel_c20pll_readout_hw_state(struct
> intel_encoder *encoder,
> 
>  	wakeref = intel_cx0_phy_transaction_begin(encoder);
> 
> +	cx0pll_state->lane_count = readout_enabled_lane_count(encoder);
> +
>  	/* 1. Read VDR params and current context selection */
>  	intel_c20_readout_vdr_params(encoder, &pll_state->vdr, &cntx);
> 
> @@ -3107,7 +3147,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8
> lane_mask)
> 
>  static void __intel_cx0pll_enable(struct intel_encoder *encoder,
>  				  const struct intel_cx0pll_state *pll_state,
> -				  bool is_dp, int port_clock, int lane_count)
> +				  bool is_dp, int port_clock)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	enum phy phy = intel_encoder_to_phy(encoder); @@ -3149,7
> +3189,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
>  	 * 6. Program the enabled and disabled owned PHY lane
>  	 * transmitters over message bus
>  	 */
> -	intel_cx0_program_phy_lane(encoder, lane_count, lane_reversal);
> +	intel_cx0_program_phy_lane(encoder, pll_state->lane_count,
> +lane_reversal);
> 
>  	/*
>  	 * 7. Follow the Display Voltage Frequency Switching - Sequence @@ -
> 3192,7 +3232,7 @@ static void intel_cx0pll_enable(struct intel_encoder
> *encoder,  {
>  	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
>  			      intel_crtc_has_dp_encoder(crtc_state),
> -			      crtc_state->port_clock, crtc_state->lane_count);
> +			      crtc_state->port_clock);
>  }
> 
>  int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder) @@ -3723,6
> +3763,7 @@ void intel_cx0_pll_power_save_wa(struct intel_display *display)
>  	for_each_intel_encoder(display->drm, encoder) {
>  		struct intel_cx0pll_state pll_state = {};
>  		int port_clock = 162000;
> +		int lane_count = 4;
> 
>  		if (!intel_encoder_is_dig_port(encoder))
>  			continue;
> @@ -3735,7 +3776,7 @@ void intel_cx0_pll_power_save_wa(struct
> intel_display *display)
> 
>  		if (intel_c10pll_calc_state_from_table(encoder,
>  						       mtl_c10_edp_tables,
> -						       true, port_clock,
> +						       true, port_clock,
> lane_count,
>  						       &pll_state) < 0) {
>  			drm_WARN_ON(display->drm,
>  				    "Unable to calc C10 state from the
> tables\n"); @@ -3746,7 +3787,7 @@ void
> intel_cx0_pll_power_save_wa(struct intel_display *display)
>  			    "[ENCODER:%d:%s] Applying power saving
> workaround on disabled PLL\n",
>  			    encoder->base.base.id, encoder->base.name);
> 
> -		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock,
> 4);
> +		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock);
>  		intel_cx0pll_disable(encoder);
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 43c7200050e9..839b1a98534f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -267,6 +267,7 @@ struct intel_cx0pll_state {
>  		struct intel_c10pll_state c10;
>  		struct intel_c20pll_state c20;
>  	};
> +	int lane_count;
>  	bool ssc_enabled;
>  	bool use_c10;
>  	bool tbt_mode;
> --
> 2.34.1

RE: [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup

[Kandpal, Suraj]

> Subject: [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Define the C10 PLL SSC register range via macros, so the HW/SW state of these
> register can be verified by a follow-up change, reusing these macros.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index cc5aa38c3364..b394b0397d62 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2064,6 +2064,9 @@ static void intel_cx0pll_update_ssc(struct
> intel_encoder *encoder,
>  	}
>  }
> 
> +#define C10_PLL_SSC_REG_START_IDX	4
> +#define C10_PLL_SSC_REG_COUNT		5
> +
>  static void intel_c10pll_update_pll(struct intel_encoder *encoder,
>  				    struct intel_cx0pll_state *pll_state)  { @@ -
> 2073,8 +2076,11 @@ static void intel_c10pll_update_pll(struct intel_encoder
> *encoder,
>  	if (pll_state->ssc_enabled)
>  		return;
> 
> -	drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
> -	for (i = 4; i < 9; i++)
> +	drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) <
> +				  C10_PLL_SSC_REG_START_IDX +
> C10_PLL_SSC_REG_COUNT);
> +	for (i = C10_PLL_SSC_REG_START_IDX;
> +	     i < C10_PLL_SSC_REG_START_IDX + C10_PLL_SSC_REG_COUNT;
> +	     i++)
>  		pll_state->c10.pll[i] = 0;
>  }
> 
> --
> 2.34.1

RE: [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state

[Kandpal, Suraj]

> Subject: [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL
> state
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> The Cx0 PLL enable programming needs to know if the PLL is in DP or HDMI
> mode. The PLL manager framework doesn't pass the CRTC state to the PLL's
> enable hook, so prepare here for the conversion to use the PLL manager for
> Cx0 PHY PLLs by determining the DP/HDMI mode from the PLL state.
> 
> For C10 PHYs use the fact that the HDMI divider value in the PLL registers are
> set if and only if the PLL is in HDMI mode.
> 
> For C20 PHYs use the DP mode flag programmed to the VDR SERDES register,
> which is set if and only if the PLL is in DP mode.
> 
> Assert that the above PLL/VDR SERDES register values match the DP/HDMI
> mode being configured already during state computation.
> 
> This also allows dropping the is_dp param from the
> __intel_cx0pll_enable() function, since it can retrieve this now from the PLL
> state.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 43 ++++++++++++++++----
>  1 file changed, 36 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f6b25291cd18..f1216beb5581 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2090,6 +2090,24 @@ static void intel_c10pll_update_pll(struct
> intel_encoder *encoder,
>  		pll_state->c10.pll[i] = 0;
>  }
> 
> +static bool c10pll_state_is_dp(const struct intel_c10pll_state
> +*pll_state) {
> +	return !REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state-
> >pll[15]); }
> +
> +static bool c20pll_state_is_dp(const struct intel_c20pll_state
> +*pll_state) {
> +	return pll_state->vdr.serdes_rate & PHY_C20_IS_DP; }
> +
> +static bool cx0pll_state_is_dp(const struct intel_cx0pll_state
> +*pll_state) {
> +	if (pll_state->use_c10)
> +		return c10pll_state_is_dp(&pll_state->c10);
> +
> +	return c20pll_state_is_dp(&pll_state->c20);
> +}
> +
>  /*
>   * TODO: Convert the following align with intel_c20pll_find_table() and
>   * intel_c20pll_calc_state_from_table().
> @@ -2099,6 +2117,7 @@ static int intel_c10pll_calc_state_from_table(struct
> intel_encoder *encoder,
>  					      bool is_dp, int port_clock, int
> lane_count,
>  					      struct intel_cx0pll_state *pll_state)
> {
> +	struct intel_display *display = to_intel_display(encoder);
>  	int i;
> 
>  	for (i = 0; tables[i]; i++) {
> @@ -2110,6 +2129,8 @@ static int intel_c10pll_calc_state_from_table(struct
> intel_encoder *encoder,
>  			pll_state->use_c10 = true;
>  			pll_state->lane_count = lane_count;
> 
> +			drm_WARN_ON(display->drm, is_dp !=
> +c10pll_state_is_dp(&pll_state->c10));
> +
>  			return 0;
>  		}
>  	}
> @@ -2120,6 +2141,8 @@ static int intel_c10pll_calc_state_from_table(struct
> intel_encoder *encoder,  static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  				   struct intel_encoder *encoder)
>  {
> +	struct intel_display *display = to_intel_display(encoder);
> +	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
>  	const struct intel_c10pll_state * const *tables;
>  	int err;
> 
> @@ -2127,8 +2150,7 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  	if (!tables)
>  		return -EINVAL;
> 
> -	err = intel_c10pll_calc_state_from_table(encoder, tables,
> -
> intel_crtc_has_dp_encoder(crtc_state),
> +	err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp,
>  						 crtc_state->port_clock,
> crtc_state->lane_count,
>  						 &crtc_state-
> >dpll_hw_state.cx0pll);
> 
> @@ -2143,6 +2165,9 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
>  	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
> 
> +	drm_WARN_ON(display->drm,
> +		    is_dp !=
> +c10pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c10));
> +
>  	return 0;
>  }
> 
> @@ -2643,6 +2668,7 @@ static int intel_c20pll_calc_state_from_table(struct
> intel_crtc_state *crtc_stat  static int intel_c20pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  				   struct intel_encoder *encoder)
>  {
> +	struct intel_display *display = to_intel_display(encoder);
>  	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
>  	int err = -ENOENT;
> 
> @@ -2663,6 +2689,9 @@ static int intel_c20pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  	intel_c20_calc_vdr_params(&crtc_state-
> >dpll_hw_state.cx0pll.c20.vdr,
>  				  is_dp, crtc_state->port_clock);
> 
> +	drm_WARN_ON(display->drm,
> +		    is_dp !=
> +c20pll_state_is_dp(&crtc_state->dpll_hw_state.cx0pll.c20));
> +
>  	return 0;
>  }
> 
> @@ -2929,10 +2958,11 @@ static void intel_c20_pll_program(struct
> intel_display *display,
> 
>  static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
>  					 const struct intel_cx0pll_state
> *pll_state,
> -					 bool is_dp, int port_clock,
> +					 int port_clock,
>  					 bool lane_reversal)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
> +	bool is_dp = cx0pll_state_is_dp(pll_state);

Wouldn't a simple check of drm_encoder's type tell us if it is dp or not ?

Regards,
Suraj Kandpal

>  	u32 val = 0;
> 
>  	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder-
> >port), @@ -3178,7 +3208,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8
> lane_mask)
> 
>  static void __intel_cx0pll_enable(struct intel_encoder *encoder,
>  				  const struct intel_cx0pll_state *pll_state,
> -				  bool is_dp, int port_clock)
> +				  int port_clock)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	enum phy phy = intel_encoder_to_phy(encoder); @@ -3192,7
> +3222,7 @@ static void __intel_cx0pll_enable(struct intel_encoder *encoder,
>  	 * 1. Program PORT_CLOCK_CTL REGISTER to configure
>  	 * clock muxes, gating and SSC
>  	 */
> -	intel_program_port_clock_ctl(encoder, pll_state, is_dp, port_clock,
> lane_reversal);
> +	intel_program_port_clock_ctl(encoder, pll_state, port_clock,
> +lane_reversal);
> 
>  	/* 2. Bring PHY out of reset. */
>  	intel_cx0_phy_lane_reset(encoder, lane_reversal); @@ -3262,7
> +3292,6 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>  				const struct intel_crtc_state *crtc_state)  {
>  	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
> -			      intel_crtc_has_dp_encoder(crtc_state),
>  			      crtc_state->port_clock);
>  }
> 
> @@ -3818,7 +3847,7 @@ void intel_cx0_pll_power_save_wa(struct
> intel_display *display)
>  			    "[ENCODER:%d:%s] Applying power saving
> workaround on disabled PLL\n",
>  			    encoder->base.base.id, encoder->base.name);
> 
> -		__intel_cx0pll_enable(encoder, &pll_state, true, port_clock);
> +		__intel_cx0pll_enable(encoder, &pll_state, port_clock);
>  		intel_cx0pll_disable(encoder);
>  	}
>  }
> --
> 2.34.1

RE: [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock from PLL state

[Kandpal, Suraj]

> Subject: [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock from PLL
> state
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> The port clock is tracked in the PLL state, so there is no need to pass it
> separately to __intel_cx0pll_enable(). Drop the port clock function param
> accordingly.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 +++++------------
>  1 file changed, 5 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f1216beb5581..29bcfe8fb6f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3206,10 +3206,10 @@ static u32 intel_cx0_get_pclk_pll_ack(u8
> lane_mask)
>  	return val;
>  }
> 
> -static void __intel_cx0pll_enable(struct intel_encoder *encoder,
> -				  const struct intel_cx0pll_state *pll_state,
> -				  int port_clock)
> +static void intel_cx0pll_enable(struct intel_encoder *encoder,
> +				const struct intel_cx0pll_state *pll_state)
>  {
> +	int port_clock = pll_state->use_c10 ? pll_state->c10.clock :
> +pll_state->c20.clock;
>  	struct intel_display *display = to_intel_display(encoder);
>  	enum phy phy = intel_encoder_to_phy(encoder);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder); @@ -
> 3288,13 +3288,6 @@ static void __intel_cx0pll_enable(struct intel_encoder
> *encoder,
>  	intel_cx0_phy_transaction_end(encoder, wakeref);  }
> 
> -static void intel_cx0pll_enable(struct intel_encoder *encoder,
> -				const struct intel_crtc_state *crtc_state)
> -{
> -	__intel_cx0pll_enable(encoder, &crtc_state->dpll_hw_state.cx0pll,
> -			      crtc_state->port_clock);
> -}
> -
>  int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)  {
>  	struct intel_display *display = to_intel_display(encoder); @@ -3424,7
> +3417,7 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder,
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_enable(encoder, crtc_state);
>  	else
> -		intel_cx0pll_enable(encoder, crtc_state);
> +		intel_cx0pll_enable(encoder, &crtc_state-
> >dpll_hw_state.cx0pll);
>  }
> 
>  /*
> @@ -3847,7 +3840,7 @@ void intel_cx0_pll_power_save_wa(struct
> intel_display *display)
>  			    "[ENCODER:%d:%s] Applying power saving
> workaround on disabled PLL\n",
>  			    encoder->base.base.id, encoder->base.name);
> 
> -		__intel_cx0pll_enable(encoder, &pll_state, port_clock);
> +		intel_cx0pll_enable(encoder, &pll_state);
>  		intel_cx0pll_disable(encoder);
>  	}
>  }
> --
> 2.34.1

RE: [CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout

[Kandpal, Suraj]

> Subject: [CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and
> HW readout
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Ensure Cx0 pll state is initialized to zero before any computation or HW
> readouts, to prevent leaving some parameter in the state uninitialized in the
> actual compute/HW readout functions later.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 29bcfe8fb6f5..3418fc560faf 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2698,6 +2698,8 @@ static int intel_c20pll_calc_state(struct
> intel_crtc_state *crtc_state,  int intel_cx0pll_calc_state(struct intel_crtc_state
> *crtc_state,
>  			    struct intel_encoder *encoder)
>  {
> +	memset(&crtc_state->dpll_hw_state, 0,
> +sizeof(crtc_state->dpll_hw_state));
> +
>  	if (intel_encoder_is_c10phy(encoder))
>  		return intel_c10pll_calc_state(crtc_state, encoder);
>  	return intel_c20pll_calc_state(crtc_state, encoder); @@ -3635,7
> +3637,7 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state
> *state,  void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>  				   struct intel_cx0pll_state *pll_state)  {
> -	pll_state->use_c10 = false;
> +	memset(pll_state, 0, sizeof(*pll_state));
> 
>  	pll_state->tbt_mode =
> intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
>  	if (pll_state->tbt_mode)
> --
> 2.34.1

RE: [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state

[Kandpal, Suraj]

> Subject: [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Print all the Cx0 PLL state in the PLL state dumper.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 3418fc560faf..1e68a73c2ca8 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2311,8 +2311,8 @@ static void intel_c10pll_dump_hw_state(struct
> intel_display *display,
>  	unsigned int multiplier, tx_clk_div;
> 
>  	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> -	drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
> -		    str_yes_no(fracen));
> +	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s,
> ",
> +		    hw_state->clock, str_yes_no(fracen));
> 
>  	if (fracen) {
>  		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; @@ -
> 2835,7 +2835,7 @@ static void intel_c20pll_dump_hw_state(struct
> intel_display *display,  {
>  	int i;
> 
> -	drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
> +	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n",
> +hw_state->clock);

No deletion required just add a new drm db kms which gives us the clock

Regards,
Suraj Kandpal

>  	drm_dbg_kms(display->drm,
>  		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
>  		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); @@ -
> 2851,12 +2851,24 @@ static void intel_c20pll_dump_hw_state(struct
> intel_display *display,
>  		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
>  			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n",
> i,
>  				    hw_state->mplla[i]);
> +
> +		/* For full coverage, also print the additional PLL B entry. */
> +		WARN_ON(i + 1 != ARRAY_SIZE(hw_state->mpllb));
> +		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
> +hw_state->mpllb[i]);
>  	}
> +
> +	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes
> rate: 0x%02x, hdmi rate: 0x%02x\n",
> +		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate,
> +hw_state->vdr.hdmi_rate);
>  }
> 
>  void intel_cx0pll_dump_hw_state(struct intel_display *display,
>  				const struct intel_cx0pll_state *hw_state)  {
> +	drm_dbg_kms(display->drm,
> +		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s,
> use_c10: %s, tbt_mode: %s\n",
> +		    hw_state->lane_count, str_yes_no(hw_state-
> >ssc_enabled),
> +		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state-
> >tbt_mode));
> +
>  	if (hw_state->use_c10)
>  		intel_c10pll_dump_hw_state(display, &hw_state->c10);
>  	else
> --
> 2.34.1

RE: [CI 15/32] drm/i915/display: Remove state verification

[Kandpal, Suraj]

> Subject: [CI 15/32] drm/i915/display: Remove state verification
> 
> When pll's are moved to dpll framework we no longer need Cx0 specific state
> verification as we can rely on dpll state verification instead.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 114 ------------------
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   2 -
>  .../drm/i915/display/intel_modeset_verify.c   |   1 -
>  3 files changed, 117 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 1e68a73c2ca8..5332f33800e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3617,35 +3617,6 @@ intel_mtl_port_pll_type(struct intel_encoder
> *encoder,
>  		return ICL_PORT_DPLL_DEFAULT;
>  }
> 
> -static void intel_c10pll_state_verify(const struct intel_crtc_state *state,
> -				      struct intel_crtc *crtc,
> -				      struct intel_encoder *encoder,
> -				      struct intel_c10pll_state *mpllb_hw_state)
> -{
> -	struct intel_display *display = to_intel_display(state);
> -	const struct intel_c10pll_state *mpllb_sw_state = &state-
> >dpll_hw_state.cx0pll.c10;
> -	int i;
> -
> -	for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) {
> -		u8 expected = mpllb_sw_state->pll[i];
> -
> -		INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->pll[i]
> != expected,
> -					 "[CRTC:%d:%s] mismatch in
> C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)",
> -					 crtc->base.base.id, crtc->base.name,
> i,
> -					 expected, mpllb_hw_state->pll[i]);
> -	}
> -
> -	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->tx !=
> mpllb_sw_state->tx,
> -				 "[CRTC:%d:%s] mismatch in C10MPLLB:
> Register TX0 (expected 0x%02x, found 0x%02x)",
> -				 crtc->base.base.id, crtc->base.name,
> -				 mpllb_sw_state->tx, mpllb_hw_state->tx);
> -
> -	INTEL_DISPLAY_STATE_WARN(display, mpllb_hw_state->cmn !=
> mpllb_sw_state->cmn,
> -				 "[CRTC:%d:%s] mismatch in C10MPLLB:
> Register CMN0 (expected 0x%02x, found 0x%02x)",
> -				 crtc->base.base.id, crtc->base.name,
> -				 mpllb_sw_state->cmn, mpllb_hw_state-
> >cmn);
> -}
> -
>  void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>  				   struct intel_cx0pll_state *pll_state)  { @@ -
> 3722,91 +3693,6 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder
> *encoder,
>  	return intel_c20pll_calc_port_clock(encoder, &pll_state->c20);  }
> 
> -static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
> -				      struct intel_crtc *crtc,
> -				      struct intel_encoder *encoder,
> -				      struct intel_c20pll_state *mpll_hw_state)
> -{
> -	struct intel_display *display = to_intel_display(state);
> -	const struct intel_c20pll_state *mpll_sw_state = &state-
> >dpll_hw_state.cx0pll.c20;
> -	bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state);
> -	bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state);
> -	int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state);
> -	int i;
> -
> -	INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->clock != clock,
> -				 "[CRTC:%d:%s] mismatch in C20: Register
> CLOCK (expected %d, found %d)",
> -				 crtc->base.base.id, crtc->base.name,
> -				 mpll_sw_state->clock, mpll_hw_state-
> >clock);
> -
> -	INTEL_DISPLAY_STATE_WARN(display, sw_use_mpllb !=
> hw_use_mpllb,
> -				 "[CRTC:%d:%s] mismatch in C20: Register
> MPLLB selection (expected %d, found %d)",
> -				 crtc->base.base.id, crtc->base.name,
> -				 sw_use_mpllb, hw_use_mpllb);
> -
> -	if (hw_use_mpllb) {
> -		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) {
> -			INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state-
> >mpllb[i] != mpll_sw_state->mpllb[i],
> -						 "[CRTC:%d:%s] mismatch in
> C20MPLLB: Register[%d] (expected 0x%04x, found 0x%04x)",
> -						 crtc->base.base.id, crtc-
> >base.name, i,
> -						 mpll_sw_state->mpllb[i],
> mpll_hw_state->mpllb[i]);
> -		}
> -	} else {
> -		for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) {
> -			INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state-
> >mplla[i] != mpll_sw_state->mplla[i],
> -						 "[CRTC:%d:%s] mismatch in
> C20MPLLA: Register[%d] (expected 0x%04x, found 0x%04x)",
> -						 crtc->base.base.id, crtc-
> >base.name, i,
> -						 mpll_sw_state->mplla[i],
> mpll_hw_state->mplla[i]);
> -		}
> -	}
> -
> -	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) {
> -		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->tx[i] !=
> mpll_sw_state->tx[i],
> -					 "[CRTC:%d:%s] mismatch in C20:
> Register TX[%i] (expected 0x%04x, found 0x%04x)",
> -					 crtc->base.base.id, crtc->base.name,
> i,
> -					 mpll_sw_state->tx[i], mpll_hw_state-
> >tx[i]);
> -	}
> -
> -	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) {
> -		INTEL_DISPLAY_STATE_WARN(display, mpll_hw_state->cmn[i]
> != mpll_sw_state->cmn[i],
> -					 "[CRTC:%d:%s] mismatch in C20:
> Register CMN[%i] (expected 0x%04x, found 0x%04x)",
> -					 crtc->base.base.id, crtc->base.name,
> i,
> -					 mpll_sw_state->cmn[i],
> mpll_hw_state->cmn[i]);
> -	}
> -}
> -
> -void intel_cx0pll_state_verify(struct intel_atomic_state *state,
> -			       struct intel_crtc *crtc)
> -{
> -	struct intel_display *display = to_intel_display(state);
> -	const struct intel_crtc_state *new_crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct intel_encoder *encoder;
> -	struct intel_cx0pll_state mpll_hw_state = {};
> -
> -	if (DISPLAY_VER(display) < 14)
> -		return;
> -
> -	if (!new_crtc_state->hw.active)
> -		return;
> -
> -	/* intel_get_crtc_new_encoder() only works for modeset/fastset
> commits */
> -	if (!intel_crtc_needs_modeset(new_crtc_state) &&
> -	    !intel_crtc_needs_fastset(new_crtc_state))
> -		return;
> -
> -	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
> -	intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);
> -
> -	if (mpll_hw_state.tbt_mode)
> -		return;
> -
> -	if (intel_encoder_is_c10phy(encoder))
> -		intel_c10pll_state_verify(new_crtc_state, crtc, encoder,
> &mpll_hw_state.c10);
> -	else
> -		intel_c20pll_state_verify(new_crtc_state, crtc, encoder,
> &mpll_hw_state.c20);
> -}
> -
>  /*
>   * WA 14022081154
>   * The dedicated display PHYs reset to a power state that blocks S0ix,
> increasing idle diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index c5a7b529955b..2b934b96af81 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -35,8 +35,6 @@ int intel_cx0pll_calc_port_clock(struct intel_encoder
> *encoder,
> 
>  void intel_cx0pll_dump_hw_state(struct intel_display *display,
>  				const struct intel_cx0pll_state *hw_state); -
> void intel_cx0pll_state_verify(struct intel_atomic_state *state,
> -			       struct intel_crtc *crtc);
>  bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
>  				   const struct intel_cx0pll_state *b);  void
> intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, diff --git
> a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index f2f6b9d9afa1..22600bdbe8c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -245,7 +245,6 @@ void intel_modeset_verify_crtc(struct
> intel_atomic_state *state,
>  	verify_crtc_state(state, crtc);
>  	intel_dpll_state_verify(state, crtc);
>  	intel_mpllb_state_verify(state, crtc);
> -	intel_cx0pll_state_verify(state, crtc);
>  }
> 
>  void intel_modeset_verify_disabled(struct intel_atomic_state *state)
> --
> 2.34.1

Re: [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables

[Imre Deak]

On Tue, Nov 11, 2025 at 07:36:47AM +0200, Suraj Kandpal wrote:
> > + [...]
> > +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> > +				   struct intel_encoder *encoder)
> > +{
> > +	int err = -ENOENT;
> > +
> > +	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> > +
> > +	/* try computed C20 HDMI tables before using consolidated tables */
> > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > +		/* TODO: Update SSC state for HDMI as well */
> > +		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> > +
> > +	if (err)
> > +		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> 
> So this is something I have been meaning to fix we should really be
> using the HDMI tables already defined. Computing them ourselves, that
> should be reserved for only when we do not have any HDMI table for the
> said port clock available.

> Also if we use the computed tables directly that means we never end up
> using the defined tables.
> 
> SO the flow here should be
> 
> err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> 
> if (err && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)))
> 	err = intel_c20_compute_hdmi_tmds_pll(crtc_state);

This patch is not meant to change the logic, it simply wants to make the
logic clearer to the reader. What you suggest should be a separate
patch.

> something like this.
> 
> Regards,
> Suraj Kandpal
>  
> > +
> > +	return err;
> >  }
> > 
> >  int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > --
> > 2.34.1

Re: [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state

[Imre Deak]

On Tue, Nov 11, 2025 at 08:08:34AM +0200, Suraj Kandpal wrote:
> [...]
> > @@ -2929,10 +2958,11 @@ static void intel_c20_pll_program(struct
> > intel_display *display,
> > 
> >  static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> >  					 const struct intel_cx0pll_state *pll_state,
> > -					 bool is_dp, int port_clock,
> > +					 int port_clock,
> >  					 bool lane_reversal)
> >  {
> >  	struct intel_display *display = to_intel_display(encoder);
> > +	bool is_dp = cx0pll_state_is_dp(pll_state);
> 
> Wouldn't a simple check of drm_encoder's type tell us if it is dp or not ?

For a DDI encoder drm_encoder::encoder_type is DRM_MODE_ENCODER_TMDS,
from which you can't determine if the encoder is used for a DP or HDMI
output. This also applies to intel_encoder_is_dp(), which will return
true if for instance a DDI encoder wired to a DP++ connector is used for
an HDMI output.

> Regards,
> Suraj Kandpal

Re: [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state

[Jani Nikula]

On Fri, 31 Oct 2025, Mika Kahola <mika.kahola@intel.com> wrote:
> From: Imre Deak <imre.deak@intel.com>
>
> Print all the Cx0 PLL state in the PLL state dumper.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 +++++++++++++++---
>  1 file changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 3418fc560faf..1e68a73c2ca8 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2311,8 +2311,8 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display,
>  	unsigned int multiplier, tx_clk_div;
>  
>  	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> -	drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
> -		    str_yes_no(fracen));
> +	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
> +		    hw_state->clock, str_yes_no(fracen));
>  
>  	if (fracen) {
>  		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
> @@ -2835,7 +2835,7 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
>  {
>  	int i;
>  
> -	drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
> +	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state->clock);
>  	drm_dbg_kms(display->drm,
>  		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
>  		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
> @@ -2851,12 +2851,24 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
>  		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
>  			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
>  				    hw_state->mplla[i]);
> +
> +		/* For full coverage, also print the additional PLL B entry. */
> +		WARN_ON(i + 1 != ARRAY_SIZE(hw_state->mpllb));

Why? What if we hit this? At the very least please use
drm_WARN_ON(). What does the comment have to do with the WARN?

> +		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
>  	}
> +
> +	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
> +		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
>  }
>  
>  void intel_cx0pll_dump_hw_state(struct intel_display *display,
>  				const struct intel_cx0pll_state *hw_state)
>  {
> +	drm_dbg_kms(display->drm,
> +		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
> +		    hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
> +		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
> +
>  	if (hw_state->use_c10)
>  		intel_c10pll_dump_hw_state(display, &hw_state->c10);
>  	else

-- 
Jani Nikula, Intel

Re: [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state

[Jani Nikula]

On Tue, 11 Nov 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Fri, 31 Oct 2025, Mika Kahola <mika.kahola@intel.com> wrote:
>> From: Imre Deak <imre.deak@intel.com>
>>
>> Print all the Cx0 PLL state in the PLL state dumper.
>>
>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 +++++++++++++++---
>>  1 file changed, 15 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> index 3418fc560faf..1e68a73c2ca8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>> @@ -2311,8 +2311,8 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display,
>>  	unsigned int multiplier, tx_clk_div;
>>  
>>  	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
>> -	drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
>> -		    str_yes_no(fracen));
>> +	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
>> +		    hw_state->clock, str_yes_no(fracen));
>>  
>>  	if (fracen) {
>>  		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
>> @@ -2835,7 +2835,7 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
>>  {
>>  	int i;
>>  
>> -	drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
>> +	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state->clock);
>>  	drm_dbg_kms(display->drm,
>>  		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
>>  		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
>> @@ -2851,12 +2851,24 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
>>  		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
>>  			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
>>  				    hw_state->mplla[i]);
>> +
>> +		/* For full coverage, also print the additional PLL B entry. */
>> +		WARN_ON(i + 1 != ARRAY_SIZE(hw_state->mpllb));
>
> Why? What if we hit this? At the very least please use
> drm_WARN_ON(). What does the comment have to do with the WARN?

Besides after the loop i == ARRAY_SIZE(hw_state->mplla), i.e. the whole
thing can be

	BUILD_BUG_ON(ARRAY_SIZE(hw_state->mplla) + 1 != ARRAY_SIZE(hw_state->mpllb));

>
>> +		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
>>  	}
>> +
>> +	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
>> +		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
>>  }
>>  
>>  void intel_cx0pll_dump_hw_state(struct intel_display *display,
>>  				const struct intel_cx0pll_state *hw_state)
>>  {
>> +	drm_dbg_kms(display->drm,
>> +		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
>> +		    hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
>> +		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
>> +
>>  	if (hw_state->use_c10)
>>  		intel_c10pll_dump_hw_state(display, &hw_state->c10);
>>  	else

-- 
Jani Nikula, Intel

Re: [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state

[Imre Deak]

On Tue, Nov 11, 2025 at 01:16:46PM +0200, Jani Nikula wrote:
> On Tue, 11 Nov 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Fri, 31 Oct 2025, Mika Kahola <mika.kahola@intel.com> wrote:
> >> From: Imre Deak <imre.deak@intel.com>
> >>
> >> Print all the Cx0 PLL state in the PLL state dumper.
> >>
> >> Signed-off-by: Imre Deak <imre.deak@intel.com>
> >> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 18 +++++++++++++++---
> >>  1 file changed, 15 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> index 3418fc560faf..1e68a73c2ca8 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> >> @@ -2311,8 +2311,8 @@ static void intel_c10pll_dump_hw_state(struct intel_display *display,
> >>  	unsigned int multiplier, tx_clk_div;
> >>  
> >>  	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> >> -	drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
> >> -		    str_yes_no(fracen));
> >> +	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
> >> +		    hw_state->clock, str_yes_no(fracen));
> >>  
> >>  	if (fracen) {
> >>  		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
> >> @@ -2835,7 +2835,7 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
> >>  {
> >>  	int i;
> >>  
> >> -	drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
> >> +	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state->clock);
> >>  	drm_dbg_kms(display->drm,
> >>  		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
> >>  		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
> >> @@ -2851,12 +2851,24 @@ static void intel_c20pll_dump_hw_state(struct intel_display *display,
> >>  		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> >>  			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
> >>  				    hw_state->mplla[i]);
> >> +
> >> +		/* For full coverage, also print the additional PLL B entry. */
> >> +		WARN_ON(i + 1 != ARRAY_SIZE(hw_state->mpllb));
> >
> > Why? What if we hit this? At the very least please use
> > drm_WARN_ON(). What does the comment have to do with the WARN?

The WARN verifies that the additional entry to include in the print
exists and it is the only entry to print.

> Besides after the loop i == ARRAY_SIZE(hw_state->mplla), i.e. the whole
> thing can be
> 
> 	BUILD_BUG_ON(ARRAY_SIZE(hw_state->mplla) + 1 != ARRAY_SIZE(hw_state->mpllb));

Yes, BUILD_BUG_ON() is better here, no reason for delaying the check
until runtime.

> >
> >> +		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
> >>  	}
> >> +
> >> +	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate: 0x%02x\n",
> >> +		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate, hw_state->vdr.hdmi_rate);
> >>  }
> >>  
> >>  void intel_cx0pll_dump_hw_state(struct intel_display *display,
> >>  				const struct intel_cx0pll_state *hw_state)
> >>  {
> >> +	drm_dbg_kms(display->drm,
> >> +		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10: %s, tbt_mode: %s\n",
> >> +		    hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
> >> +		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state->tbt_mode));
> >> +
> >>  	if (hw_state->use_c10)
> >>  		intel_c10pll_dump_hw_state(display, &hw_state->c10);
> >>  	else
> 
> -- 
> Jani Nikula, Intel

RE: [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables

[Kandpal, Suraj]

> Subject: Re: [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from
> tables
> 
> On Tue, Nov 11, 2025 at 07:36:47AM +0200, Suraj Kandpal wrote:
> > > + [...]
> > > +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> > > +				   struct intel_encoder *encoder) {
> > > +	int err = -ENOENT;
> > > +
> > > +	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> > > +
> > > +	/* try computed C20 HDMI tables before using consolidated tables */
> > > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > > +		/* TODO: Update SSC state for HDMI as well */
> > > +		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> > > +
> > > +	if (err)
> > > +		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> >
> > So this is something I have been meaning to fix we should really be
> > using the HDMI tables already defined. Computing them ourselves, that
> > should be reserved for only when we do not have any HDMI table for the
> > said port clock available.
> 
> > Also if we use the computed tables directly that means we never end up
> > using the defined tables.
> >
> > SO the flow here should be
> >
> > err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> >
> > if (err && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)))
> > 	err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> 
> This patch is not meant to change the logic, it simply wants to make the logic
> clearer to the reader. What you suggest should be a separate patch

I am fine with that do you want to add that as a part of this series or should I send a separate
Patch fixing this.

Either way
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> > something like this.
> >
> > Regards,
> > Suraj Kandpal
> >
> > > +
> > > +	return err;
> > >  }
> > >
> > >  int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > > --
> > > 2.34.1

RE: [CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state

[Kandpal, Suraj]

> Cc: Deak, Imre <imre.deak@intel.com>; Kahola, Mika <mika.kahola@intel.com>
> Subject: [CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Read out the C10, C20 PHY PLLs SSC enabled state, so the PLL HW/SW state
> verification can check this state as well.
> 
> C10 PHY PLLs program some PLL registers zeroed out for the non-SSC case, while
> programming non-zero values to the same registers for the SSC case, so check
> that these PLL registers being zero or non-zero matches the PLL's overall SSC-
> enabled state (stored in the intel_c10pll_state::ssc_enabled flag).
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 25 ++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index b394b0397d62..f6b25291cd18 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2067,6 +2067,12 @@ static void intel_cx0pll_update_ssc(struct
> intel_encoder *encoder,
>  #define C10_PLL_SSC_REG_START_IDX	4
>  #define C10_PLL_SSC_REG_COUNT		5
> 
> +static bool intel_c10pll_ssc_enabled(const struct intel_c10pll_state
> +*pll_state) {
> +	return memchr_inv(&pll_state->pll[C10_PLL_SSC_REG_START_IDX],
> +			  0, sizeof(pll_state->pll[0]) *
> C10_PLL_SSC_REG_COUNT); }
> +
>  static void intel_c10pll_update_pll(struct intel_encoder *encoder,
>  				    struct intel_cx0pll_state *pll_state)  { @@ -
> 2198,10 +2204,20 @@ static int readout_enabled_lane_count(struct
> intel_encoder *encoder)
>  	return enabled_tx_lane_count;
>  }
> 
> +static bool readout_ssc_state(struct intel_encoder *encoder, bool
> +is_mpll_b) {
> +	struct intel_display *display = to_intel_display(encoder);
> +
> +	return intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display,
> encoder->port)) &
> +		(is_mpll_b ? XELPDP_SSC_ENABLE_PLLB :
> XELPDP_SSC_ENABLE_PLLA); }
> +
>  static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
>  					  struct intel_cx0pll_state *cx0pll_state)
> {
>  	struct intel_c10pll_state *pll_state = &cx0pll_state->c10;
> +	struct intel_display *display = to_intel_display(encoder);
> +	enum phy phy = intel_encoder_to_phy(encoder);
>  	u8 lane = INTEL_CX0_LANE0;
>  	intel_wakeref_t wakeref;
>  	int i;
> @@ -2227,6 +2243,13 @@ static void intel_c10pll_readout_hw_state(struct
> intel_encoder *encoder,
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
> 
>  	pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
> +
> +	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
> +	drm_WARN(display->drm,
> +		 cx0pll_state->ssc_enabled !=
> intel_c10pll_ssc_enabled(pll_state),
> +		 "PHY %c: SSC enabled state (%s), doesn't match PLL
> configuration (%s)\n",
> +		 phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
> +		 intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" :
> +"SSC-disabled");
>  }
> 
>  static void intel_c10_pll_program(struct intel_display *display, @@ -2772,6
> +2795,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder
> *encoder,
>  	pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state);
> 
>  	intel_cx0_phy_transaction_end(encoder, wakeref);
> +
> +	cx0pll_state->ssc_enabled = readout_ssc_state(encoder,
> +intel_c20phy_use_mpllb(pll_state));
>  }
> 
>  static void intel_c20pll_dump_hw_state(struct intel_display *display,
> --
> 2.34.1

RE: [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state

[Kandpal, Suraj]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Tuesday, November 11, 2025 3:42 PM
> To: Kandpal, Suraj <suraj.kandpal@intel.com>
> Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Subject: Re: [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL
> state
> 
> On Tue, Nov 11, 2025 at 08:08:34AM +0200, Suraj Kandpal wrote:
> > [...]
> > > @@ -2929,10 +2958,11 @@ static void intel_c20_pll_program(struct
> > > intel_display *display,
> > >
> > >  static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> > >  					 const struct intel_cx0pll_state
> *pll_state,
> > > -					 bool is_dp, int port_clock,
> > > +					 int port_clock,
> > >  					 bool lane_reversal)
> > >  {
> > >  	struct intel_display *display = to_intel_display(encoder);
> > > +	bool is_dp = cx0pll_state_is_dp(pll_state);
> >
> > Wouldn't a simple check of drm_encoder's type tell us if it is dp or not ?
> 
> For a DDI encoder drm_encoder::encoder_type is
> DRM_MODE_ENCODER_TMDS, from which you can't determine if the encoder is
> used for a DP or HDMI output. This also applies to intel_encoder_is_dp(), which
> will return true if for instance a DDI encoder wired to a DP++ connector is used
> for an HDMI output.
> 

In that case LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> > Regards,
> > Suraj Kandpal

RE: [CI 16/32] drm/i915/display: PLL information for MTL+

[Kandpal, Suraj]

> Subject: [CI 16/32] drm/i915/display: PLL information for MTL+
> 
> To add MTL+ platforms as part of PLL framework, let's start by adding PLL
> information and functions.

Keep the language of commit message imperative.
Also a Bspec link stating the available PLL's for MTL+

Regards,
Suraj Kandpal

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 303f03b420ae..a9d9b7113f12 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4306,6 +4306,25 @@ static const struct intel_dpll_mgr adlp_pll_mgr = {
>  	.compare_hw_state = icl_compare_hw_state,  };
> 
> +static const struct intel_dpll_funcs mtl_pll_funcs = { };
> +
> +static const struct dpll_info mtl_plls[] = {
> +	{ .name = "DPLL 0", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL0, },
> +	{ .name = "DPLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_DPLL1, },
> +	/* TODO: Add TBT PLL */
> +	{ .name = "TC PLL 1", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL1,
> },
> +	{ .name = "TC PLL 2", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL2,
> },
> +	{ .name = "TC PLL 3", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL3,
> },
> +	{ .name = "TC PLL 4", .funcs = &mtl_pll_funcs, .id = DPLL_ID_ICL_MGPLL4,
> },
> +	{}
> +};
> +
> +__maybe_unused
> +static const struct intel_dpll_mgr mtl_pll_mgr = {
> +	.dpll_info = mtl_plls,
> +};
> +
>  /**
>   * intel_dpll_init - Initialize DPLLs
>   * @display: intel_display device
> --
> 2.34.1

RE: [CI 17/32] drm/i915/display: Update C10/C20 state calculation

[Kandpal, Suraj]

> Subject: [CI 17/32] drm/i915/display: Update C10/C20 state calculation
> 
> For the dpll framework, the state must be computed into a port PLL state, which
> is separate from the dpll_hw_state in crtc_state.

You have state the problem here but failed to mention what the commit does.
Also port PLL state?
Also two different changes are happening here struct crtc_state argument becomes
const struct crtc_state and a addition of a new param dpll_hw_state maybe these need
to be two separate patches.

> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 68 ++++++++++----------
> drivers/gpu/drm/i915/display/intel_cx0_phy.h |  5 +-
>  drivers/gpu/drm/i915/display/intel_dpll.c    |  2 +-
>  3 files changed, 40 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 5332f33800e7..f5e6634a6389 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2034,7 +2034,7 @@ static const struct intel_c20pll_state * const
> mtl_c20_hdmi_tables[] = {  };
> 
>  static const struct intel_c10pll_state * const * -intel_c10pll_tables_get(struct
> intel_crtc_state *crtc_state,
> +intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state,
>  			struct intel_encoder *encoder)
>  {
>  	if (intel_crtc_has_dp_encoder(crtc_state)) { @@ -2138,8 +2138,9 @@
> static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
>  	return -EINVAL;
>  }
> 
> -static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
> -				   struct intel_encoder *encoder)
> +static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,
> +				   struct intel_encoder *encoder,
> +				   struct intel_dpll_hw_state *hw_state)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
> @@ -2152,21 +2153,20 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
> 
>  	err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp,
>  						 crtc_state->port_clock,
> crtc_state->lane_count,
> -						 &crtc_state-
> >dpll_hw_state.cx0pll);
> +						 &hw_state->cx0pll);
> 
>  	if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		return err;
> 
>  	/* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed
> tables */
> -	intel_snps_hdmi_pll_compute_c10pll(&crtc_state-
> >dpll_hw_state.cx0pll.c10,
> +	intel_snps_hdmi_pll_compute_c10pll(&hw_state->cx0pll.c10,
>  					   crtc_state->port_clock);
> -	intel_c10pll_update_pll(encoder,
> -				&crtc_state->dpll_hw_state.cx0pll);
> -	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
> -	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
> +	intel_c10pll_update_pll(encoder, &hw_state->cx0pll);
> 
> -	drm_WARN_ON(display->drm,
> -		    is_dp != c10pll_state_is_dp(&crtc_state-
> >dpll_hw_state.cx0pll.c10));
> +	hw_state->cx0pll.use_c10 = true;
> +	hw_state->cx0pll.lane_count = crtc_state->lane_count;
> +
> +	drm_WARN_ON(display->drm, is_dp !=
> +c10pll_state_is_dp(&hw_state->cx0pll.c10));
> 
>  	return 0;
>  }
> @@ -2355,7 +2355,7 @@ static bool is_arrowlake_s_by_host_bridge(void)
>  	return pdev &&
> IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id);
>  }
> 
> -static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state *crtc_state)
> +static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state
> +*crtc_state)
>  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	u16 tx_misc;
> @@ -2379,9 +2379,9 @@ static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct
> intel_crtc_state *crtc_state)
>  		C20_PHY_TX_DCC_BYPASS |
> C20_PHY_TX_TERM_CTL(tx_term_ctrl));
>  }
> 
> -static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state *crtc_state)
> +static int intel_c20_compute_hdmi_tmds_pll(const struct intel_crtc_state
> *crtc_state,
> +					   struct intel_c20pll_state *pll_state)
>  {
> -	struct intel_c20pll_state *pll_state = &crtc_state-
> >dpll_hw_state.cx0pll.c20;
>  	u64 datarate;
>  	u64 mpll_tx_clk_div;
>  	u64 vco_freq_shift;
> @@ -2648,8 +2648,9 @@ intel_c20_pll_find_table(const struct intel_crtc_state
> *crtc_state,
>  	return NULL;
>  }
> 
> -static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_state,
> -					      struct intel_encoder *encoder)
> +static int intel_c20pll_calc_state_from_table(const struct intel_crtc_state
> *crtc_state,
> +					      struct intel_encoder *encoder,
> +					      struct intel_cx0pll_state *pll_state)
>  {
>  	const struct intel_c20pll_state *table;
> 
> @@ -2657,52 +2658,53 @@ static int intel_c20pll_calc_state_from_table(struct
> intel_crtc_state *crtc_stat
>  	if (!table)
>  		return -EINVAL;
> 
> -	crtc_state->dpll_hw_state.cx0pll.c20 = *table;
> +	pll_state->c20 = *table;
> 
> -	intel_cx0pll_update_ssc(encoder, &crtc_state->dpll_hw_state.cx0pll,
> -				intel_crtc_has_dp_encoder(crtc_state));
> +	intel_cx0pll_update_ssc(encoder, pll_state,
> +intel_crtc_has_dp_encoder(crtc_state));
> 
>  	return 0;
>  }
> 
> -static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> -				   struct intel_encoder *encoder)
> +static int intel_c20pll_calc_state(const struct intel_crtc_state *crtc_state,
> +				   struct intel_encoder *encoder,
> +				   struct intel_dpll_hw_state *hw_state)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
>  	int err = -ENOENT;
> 
> -	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> -	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
> +	hw_state->cx0pll.use_c10 = false;
> +	hw_state->cx0pll.lane_count = crtc_state->lane_count;
> 
>  	/* try computed C20 HDMI tables before using consolidated tables */
>  	if (!is_dp)
>  		/* TODO: Update SSC state for HDMI as well */
> -		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> +		err = intel_c20_compute_hdmi_tmds_pll(crtc_state,
> +&hw_state->cx0pll.c20);
> 
>  	if (err)
> -		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> +		err = intel_c20pll_calc_state_from_table(crtc_state, encoder,
> +							 &hw_state->cx0pll);
> 
>  	if (err)
>  		return err;
> 
> -	intel_c20_calc_vdr_params(&crtc_state->dpll_hw_state.cx0pll.c20.vdr,
> +	intel_c20_calc_vdr_params(&hw_state->cx0pll.c20.vdr,
>  				  is_dp, crtc_state->port_clock);
> 
> -	drm_WARN_ON(display->drm,
> -		    is_dp != c20pll_state_is_dp(&crtc_state-
> >dpll_hw_state.cx0pll.c20));
> +	drm_WARN_ON(display->drm, is_dp !=
> +c20pll_state_is_dp(&hw_state->cx0pll.c20));
> 
>  	return 0;
>  }
> 
> -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> -			    struct intel_encoder *encoder)
> +int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
> +			    struct intel_encoder *encoder,
> +			    struct intel_dpll_hw_state *hw_state)
>  {
> -	memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state-
> >dpll_hw_state));
> +	memset(hw_state, 0, sizeof(*hw_state));
> 
>  	if (intel_encoder_is_c10phy(encoder))
> -		return intel_c10pll_calc_state(crtc_state, encoder);
> -	return intel_c20pll_calc_state(crtc_state, encoder);
> +		return intel_c10pll_calc_state(crtc_state, encoder, hw_state);
> +	return intel_c20pll_calc_state(crtc_state, encoder, hw_state);
>  }
> 
>  static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state *state) diff --
> git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 2b934b96af81..7b88c3fe9de1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -16,6 +16,7 @@ struct intel_crtc;
>  struct intel_crtc_state;
>  struct intel_cx0pll_state;
>  struct intel_display;
> +struct intel_dpll_hw_state;
>  struct intel_encoder;
>  struct intel_hdmi;
> 
> @@ -27,7 +28,9 @@ enum icl_port_dpll_id
>  intel_mtl_port_pll_type(struct intel_encoder *encoder,
>  			const struct intel_crtc_state *crtc_state);
> 
> -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state, struct
> intel_encoder *encoder);
> +int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
> +			    struct intel_encoder *encoder,
> +			    struct intel_dpll_hw_state *hw_state);
>  void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>  				   struct intel_cx0pll_state *pll_state);  int
> intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, diff --git
> a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index f969c5399a51..7a48d6f0db10 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1220,7 +1220,7 @@ static int mtl_crtc_compute_clock(struct
> intel_atomic_state *state,
>  		intel_get_crtc_new_encoder(state, crtc_state);
>  	int ret;
> 
> -	ret = intel_cx0pll_calc_state(crtc_state, encoder);
> +	ret = intel_cx0pll_calc_state(crtc_state, encoder,
> +&crtc_state->dpll_hw_state);

So you are adding a new param which can be derived from the param you are still passing to
the function ?

Regards,
Suraj Kandpal

>  	if (ret)
>  		return ret;
> 
> --
> 2.34.1

RE: [CI 18/32] drm/i915/display: Compute plls for MTL+ platform

[Kandpal, Suraj]

> Subject: [CI 18/32] drm/i915/display: Compute plls for MTL+ platform

*PLL's
Keep acronyms in capital wherever possible

> 
> To bring MTL+ platform aligned with dpll framework we need to call and
> calculate pll state from dpll framework.

Ditto 
Also try avoid statement like "we need to call.."
something like " To bring MTL+ platform aligned call & calculate PLL state from dpll framework 

> 
> v2: Rename mtl_compute_c10phy_dpll() to mtl_compute_non_tc_phy_dpll().
>     The state is computed either for a C10 or on the PTL port B eDP on
>     TypeC PHY case for a C20 PHY PLL. Hence refer to this case as
>     "non_tc_phy" instead of "c10phy".
> 
>     Rename mtl_compute_c20phy_dplls() to mtl_compute_tc_phy_dplls() for
>     symmetry with mtl_compute_non_tc_phy_dpll().
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 +++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index a9d9b7113f12..b6a5a519e936 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4320,9 +4320,78 @@ static const struct dpll_info mtl_plls[] = {
>  	{}
>  };
> 
> +/*
> + * Compute the state for either a C10 PHY PLL, or in the case of the
> +PTL port B,
> + * eDP on TypeC PHY case for a C20 PHY PLL.

* eDP over TypeC

> + */
> +static int mtl_compute_non_tc_phy_dpll(struct intel_atomic_state *state,
> +				       struct intel_crtc *crtc,
> +				       struct intel_encoder *encoder) {
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll =
> +		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> +	int ret;
> +
> +	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
> +	if (ret)
> +		return ret;
> +
> +	/* this is mainly for the fastset check */

Capitalize the first letter

With that fixed LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> +	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> +
> +	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> +							      &port_dpll-
> >hw_state.cx0pll);
> +
> +	return 0;
> +}
> +
> +static int mtl_compute_tc_phy_dplls(struct intel_atomic_state *state,
> +				    struct intel_crtc *crtc,
> +				    struct intel_encoder *encoder)
> +{
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	const struct intel_crtc_state *old_crtc_state =
> +		intel_atomic_get_old_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll;
> +	int ret;
> +
> +	/* TODO: Add state calculation for TBT PLL */
> +
> +	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
> +	ret = intel_cx0pll_calc_state(crtc_state, encoder, &port_dpll->hw_state);
> +	if (ret)
> +		return ret;
> +
> +	/* this is mainly for the fastset check */
> +	if (old_crtc_state->intel_dpll &&
> +	    old_crtc_state->intel_dpll->info->id == DPLL_ID_ICL_TBTPLL)
> +		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
> +	else
> +		icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
> +
> +	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> +							      &port_dpll-
> >hw_state.cx0pll);
> +
> +	return 0;
> +}
> +
> +static int mtl_compute_dplls(struct intel_atomic_state *state,
> +			     struct intel_crtc *crtc,
> +			     struct intel_encoder *encoder)
> +{
> +	if (intel_encoder_is_tc(encoder))
> +		return mtl_compute_tc_phy_dplls(state, crtc, encoder);
> +	else
> +		return mtl_compute_non_tc_phy_dpll(state, crtc, encoder); }
> +
>  __maybe_unused
>  static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
> +	.compute_dplls = mtl_compute_dplls,
>  };
> 
>  /**
> --
> 2.34.1

RE: [CI 19/32] drm/i915/display: MTL+ .get_dplls

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Mika
> Kahola
> Sent: Friday, October 31, 2025 4:06 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Deak, Imre <imre.deak@intel.com>
> Subject: [CI 19/32] drm/i915/display: MTL+ .get_dplls
> 
> Add .get_dplls function pointer for MTL+ platforms to support dpll framework.
> Reusing the ICL function pointer.
> 
> v2: Getting configuration either for a C10 or on the PTL port B
>     eDP on TypeC PHY case for a C20 PHY PLL. Hence refer to this
>     case as "non_tc_phy" instead of "c10phy".
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 56 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  1 +
>  2 files changed, 57 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index b6a5a519e936..c6af2816594d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -203,6 +203,22 @@ enum intel_dpll_id icl_tc_port_to_pll_id(enum
> tc_port tc_port)
>  	return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;  }
> 
> +enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display,
> +enum port port) {
> +	if (port >= PORT_TC1)
> +		return icl_tc_port_to_pll_id(intel_port_to_tc(display, port));
> +
> +	switch (port) {
> +	case PORT_A:
> +		return DPLL_ID_ICL_DPLL0;
> +	case PORT_B:
> +		return DPLL_ID_ICL_DPLL1;
> +	default:
> +		MISSING_CASE(port);
> +		return DPLL_ID_ICL_DPLL0;
> +	}
> +}
> +
>  static i915_reg_t
>  intel_combo_pll_enable_reg(struct intel_display *display,
>  			   struct intel_dpll *pll)
> @@ -3491,6 +3507,35 @@ static int icl_get_tc_phy_dplls(struct
> intel_atomic_state *state,
>  	return ret;
>  }
> 
> +/*
> + * Get the PLL for either a port using a C10 PHY PLL, or in the
> + * PTL port B eDP on TypeC PHY case, the PLL for a port using

*eDP over TypeC

> + * a C20 PHY PLL.
> + */
> +static int mtl_get_non_tc_phy_dpll(struct intel_atomic_state *state,
> +				      struct intel_crtc *crtc,
> +				      struct intel_encoder *encoder) {
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_crtc_state *crtc_state =
> +		intel_atomic_get_new_crtc_state(state, crtc);
> +	struct icl_port_dpll *port_dpll =
> +		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
> +
> +	port_dpll->pll = intel_find_dpll(state, crtc,
> +					 &port_dpll->hw_state,
> +					 BIT(mtl_port_to_pll_id(display,
> encoder->port)));

I would rather have this as a separate variable than inline like this.

Regards,
Suraj Kandpal

> +	if (!port_dpll->pll)
> +		return -EINVAL;
> +
> +	intel_reference_dpll(state, crtc,
> +			     port_dpll->pll, &port_dpll->hw_state);
> +
> +	icl_update_active_dpll(state, crtc, encoder);
> +
> +	return 0;
> +}
> +
>  static int icl_compute_dplls(struct intel_atomic_state *state,
>  			     struct intel_crtc *crtc,
>  			     struct intel_encoder *encoder)
> @@ -4388,10 +4433,21 @@ static int mtl_compute_dplls(struct
> intel_atomic_state *state,
>  		return mtl_compute_non_tc_phy_dpll(state, crtc, encoder);  }
> 
> +static int mtl_get_dplls(struct intel_atomic_state *state,
> +			 struct intel_crtc *crtc,
> +			 struct intel_encoder *encoder)
> +{
> +	if (intel_encoder_is_tc(encoder))
> +		return icl_get_tc_phy_dplls(state, crtc, encoder);
> +	else
> +		return mtl_get_non_tc_phy_dpll(state, crtc, encoder); }
> +
>  __maybe_unused
>  static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
>  	.compute_dplls = mtl_compute_dplls,
> +	.get_dplls = mtl_get_dplls,
>  };
> 
>  /**
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 839b1a98534f..fbb6a45d565c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -439,6 +439,7 @@ bool intel_dpll_compare_hw_state(struct intel_display
> *display,
>  				 const struct intel_dpll_hw_state *a,
>  				 const struct intel_dpll_hw_state *b);  enum
> intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
> +enum intel_dpll_id mtl_port_to_pll_id(struct intel_display *display,
> +enum port port);
>  bool intel_dpll_is_combophy(enum intel_dpll_id id);
> 
>  void intel_dpll_state_verify(struct intel_atomic_state *state,
> --
> 2.34.1

RE: [CI 20/32] drm/i915/display: MTL+ .put_dplls

[Kandpal, Suraj]

> Subject: [CI 20/32] drm/i915/display: MTL+ .put_dplls
> 
> Add .put_dplls function pointer to support MTL+ platforms on dpll framework.
> Reusing ICL function pointer.

Keep commit message imperative
*Reuse ICL function pointer
With that fixed
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index c6af2816594d..cd612acad6e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4448,6 +4448,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
>  	.compute_dplls = mtl_compute_dplls,
>  	.get_dplls = mtl_get_dplls,
> +	.put_dplls = icl_put_dplls,
>  };
> 
>  /**
> --
> 2.34.1

RE: [CI 21/32] drm/i915/display: Add .update_active_dpll

[Kandpal, Suraj]

> Subject: [CI 21/32] drm/i915/display: Add .update_active_dpll
> 
> For MTL+ platforms, add .update_active_dpll function pointer to support dpll
> framework. Reusing ICL function pointer.

Make this imperative same as last one
With that fixed
LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index cd612acad6e4..3b62943e2748 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4449,6 +4449,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.compute_dplls = mtl_compute_dplls,
>  	.get_dplls = mtl_get_dplls,
>  	.put_dplls = icl_put_dplls,
> +	.update_active_dpll = icl_update_active_dpll,
>  };
> 
>  /**
> --
> 2.34.1

RE: [CI 22/32] drm/i915/display: Add .update_dpll_ref_clks

[Kandpal, Suraj]

> Subject: [CI 22/32] drm/i915/display: Add .update_dpll_ref_clks
> 
> Add .update_dpll_ref_clks function pointer to MTL+ platforms to support dpll
> framework. Reusing ICL function pointer.

Keep this imperative
With that fixed
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 3b62943e2748..01e649d66f08 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4450,6 +4450,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.get_dplls = mtl_get_dplls,
>  	.put_dplls = icl_put_dplls,
>  	.update_active_dpll = icl_update_active_dpll,
> +	.update_ref_clks = icl_update_dpll_ref_clks,
>  };
> 
>  /**
> --
> 2.34.1

RE: [CI 23/32] drm/i915/display: Add .dump_hw_state

[Kandpal, Suraj]

> Subject: [CI 23/32] drm/i915/display: Add .dump_hw_state
> 
> Add .dump_hw_state function pointer for MTL+ platforms to support dpll
> framework. While at it, switch to use drm_printer structure to print hw state
> information.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 73 ++++++++++---------
> drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  3 +-
> drivers/gpu/drm/i915/display/intel_display.c  |  5 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  7 ++
>  4 files changed, 48 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f5e6634a6389..e44dfda43d38 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2302,7 +2302,7 @@ static void intel_c10_pll_program(struct
> intel_display *display,
>  	intel_c10_msgbus_access_commit(encoder, INTEL_CX0_LANE0, true);  }
> 
> -static void intel_c10pll_dump_hw_state(struct intel_display *display,
> +static void intel_c10pll_dump_hw_state(struct drm_printer *p,
>  				       const struct intel_c10pll_state *hw_state)  {
>  	bool fracen;
> @@ -2311,33 +2311,33 @@ static void intel_c10pll_dump_hw_state(struct
> intel_display *display,
>  	unsigned int multiplier, tx_clk_div;
> 
>  	fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> -	drm_dbg_kms(display->drm, "c10pll_hw_state: clock: %d, fracen: %s, ",
> -		    hw_state->clock, str_yes_no(fracen));
> +	drm_printf(p, "c10pll_hw_state: clock: %d, fracen: %s, ",
> +		   hw_state->clock, str_yes_no(fracen));
> 
>  	if (fracen) {
>  		frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
>  		frac_rem =  hw_state->pll[14] << 8 | hw_state->pll[13];
>  		frac_den =  hw_state->pll[10] << 8 | hw_state->pll[9];
> -		drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",
> -			    frac_quot, frac_rem, frac_den);
> +		drm_printf(p, "quot: %u, rem: %u, den: %u,\n",
> +			   frac_quot, frac_rem, frac_den);
>  	}
> 
>  	multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK,
> hw_state->pll[3]) << 8 |
>  		      hw_state->pll[2]) / 2 + 16;
>  	tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state-
> >pll[15]);
> -	drm_dbg_kms(display->drm,
> -		    "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
> +	drm_printf(p,
> +		   "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
> 
> -	drm_dbg_kms(display->drm, "c10pll_rawhw_state:");
> -	drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
> -		    hw_state->cmn);
> +	drm_printf(p, "c10pll_rawhw_state:");
> +	drm_printf(p, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
> +		   hw_state->cmn);

Can fit in the same line

> 
>  	BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
>  	for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
> -		drm_dbg_kms(display->drm,
> -			    "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x,
> pll[%d] = 0x%x\n",
> -			    i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
> -			    i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> +		drm_printf(p,
> +			   "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x,
> pll[%d] = 0x%x\n",
> +			   i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
> +			   i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
>  }
> 
>  /*
> @@ -2832,49 +2832,50 @@ static void intel_c20pll_readout_hw_state(struct
> intel_encoder *encoder,
>  	cx0pll_state->ssc_enabled = readout_ssc_state(encoder,
> intel_c20phy_use_mpllb(pll_state));
>  }
> 
> -static void intel_c20pll_dump_hw_state(struct intel_display *display,
> +static void intel_c20pll_dump_hw_state(struct drm_printer *p,
>  				       const struct intel_c20pll_state *hw_state)  {
>  	int i;
> 
> -	drm_dbg_kms(display->drm, "c20pll_hw_state clock: %d:\n", hw_state-
> >clock);
> -	drm_dbg_kms(display->drm,
> -		    "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
> -		    hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
> -	drm_dbg_kms(display->drm,
> -		    "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3]
> = 0x%.4x\n",
> -		    hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2],
> hw_state->cmn[3]);
> +	drm_printf(p, "c20pll_hw_state: clock: %d\n", hw_state->clock);
> +	drm_printf(p,
> +		   "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",

Same here

> +		   hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
> +	drm_printf(p,
> +		   "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3]
> = 0x%.4x\n",
> +		   hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2],
> +hw_state->cmn[3]);
> 
>  	if (intel_c20phy_use_mpllb(hw_state)) {
>  		for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
> -			drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
> -				    hw_state->mpllb[i]);
> +			drm_printf(p, "mpllb[%d] = 0x%.4x\n", i,
> +				   hw_state->mpllb[i]);
>  	} else {
>  		for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> -			drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
> -				    hw_state->mplla[i]);
> +			drm_printf(p, "mplla[%d] = 0x%.4x\n", i,
> +				   hw_state->mplla[i]);

Ditto
Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
>  		/* For full coverage, also print the additional PLL B entry. */
>  		WARN_ON(i + 1 != ARRAY_SIZE(hw_state->mpllb));
> -		drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
> hw_state->mpllb[i]);
> +		drm_printf(p, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
>  	}
> 
> -	drm_dbg_kms(display->drm, "vdr: custom width: 0x%02x, serdes rate:
> 0x%02x, hdmi rate: 0x%02x\n",
> -		    hw_state->vdr.custom_width, hw_state->vdr.serdes_rate,
> hw_state->vdr.hdmi_rate);
> +	drm_printf(p,
> +		   "vdr: custom width: 0x%02x, serdes rate: 0x%02x, hdmi rate:
> 0x%02x\n",
> +		   hw_state->vdr.custom_width, hw_state->vdr.serdes_rate,
> +hw_state->vdr.hdmi_rate);
>  }
> 
> -void intel_cx0pll_dump_hw_state(struct intel_display *display,
> +void intel_cx0pll_dump_hw_state(struct drm_printer *p,
>  				const struct intel_cx0pll_state *hw_state)  {
> -	drm_dbg_kms(display->drm,
> -		    "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10:
> %s, tbt_mode: %s\n",
> -		    hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
> -		    str_yes_no(hw_state->use_c10), str_yes_no(hw_state-
> >tbt_mode));
> +	drm_printf(p,
> +		   "cx0pll_hw_state: lane_count: %d, ssc_enabled: %s, use_c10:
> %s, tbt_mode: %s\n",
> +		   hw_state->lane_count, str_yes_no(hw_state->ssc_enabled),
> +		   str_yes_no(hw_state->use_c10), str_yes_no(hw_state-
> >tbt_mode));
> 
>  	if (hw_state->use_c10)
> -		intel_c10pll_dump_hw_state(display, &hw_state->c10);
> +		intel_c10pll_dump_hw_state(p, &hw_state->c10);
>  	else
> -		intel_c20pll_dump_hw_state(display, &hw_state->c20);
> +		intel_c20pll_dump_hw_state(p, &hw_state->c20);
>  }
> 
>  static bool intel_c20_protocol_switch_valid(struct intel_encoder *encoder) diff -
> -git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 7b88c3fe9de1..03441138ec01 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -8,6 +8,7 @@
> 
>  #include <linux/types.h>
> 
> +struct drm_printer;
>  enum icl_port_dpll_id;
>  struct intel_atomic_state;
>  struct intel_c10pll_state;
> @@ -36,7 +37,7 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder
> *encoder,  int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
>  				 const struct intel_cx0pll_state *pll_state);
> 
> -void intel_cx0pll_dump_hw_state(struct intel_display *display,
> +void intel_cx0pll_dump_hw_state(struct drm_printer *p,
>  				const struct intel_cx0pll_state *hw_state);  bool
> intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,
>  				   const struct intel_cx0pll_state *b); diff --git
> a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index a8b4619de347..2e927d6cd577 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4939,15 +4939,14 @@ pipe_config_cx0pll_mismatch(struct drm_printer
> *p, bool fastset,
>  			    const struct intel_cx0pll_state *a,
>  			    const struct intel_cx0pll_state *b)  {
> -	struct intel_display *display = to_intel_display(crtc);
>  	char *chipname = a->use_c10 ? "C10" : "C20";
> 
>  	pipe_config_mismatch(p, fastset, crtc, name, chipname);
> 
>  	drm_printf(p, "expected:\n");
> -	intel_cx0pll_dump_hw_state(display, a);
> +	intel_cx0pll_dump_hw_state(p, a);
>  	drm_printf(p, "found:\n");
> -	intel_cx0pll_dump_hw_state(display, b);
> +	intel_cx0pll_dump_hw_state(p, b);
>  }
> 
>  static bool allow_vblank_delay_fastset(const struct intel_crtc_state
> *old_crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 01e649d66f08..d4b58c426044 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4443,6 +4443,12 @@ static int mtl_get_dplls(struct intel_atomic_state
> *state,
>  		return mtl_get_non_tc_phy_dpll(state, crtc, encoder);  }
> 
> +static void mtl_dump_hw_state(struct drm_printer *p,
> +			      const struct intel_dpll_hw_state *dpll_hw_state) {
> +	intel_cx0pll_dump_hw_state(p, &dpll_hw_state->cx0pll); }
> +
>  __maybe_unused
>  static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
> @@ -4451,6 +4457,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.put_dplls = icl_put_dplls,
>  	.update_active_dpll = icl_update_active_dpll,
>  	.update_ref_clks = icl_update_dpll_ref_clks,
> +	.dump_hw_state = mtl_dump_hw_state,
>  };
> 
>  /**
> --
> 2.34.1

RE: [CI 24/32] drm/i915/display: Add .compare_hw_state

[Kandpal, Suraj]

> Subject: [CI 24/32] drm/i915/display: Add .compare_hw_state
> 
> Add .compare_hw_state function pointer for MTL+ platforms to support dpll
> framework.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index d4b58c426044..d22771cf2ebd 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4449,6 +4449,15 @@ static void mtl_dump_hw_state(struct
> drm_printer *p,
>  	intel_cx0pll_dump_hw_state(p, &dpll_hw_state->cx0pll);  }
> 
> +static bool mtl_compare_hw_state(const struct intel_dpll_hw_state *_a,
> +				 const struct intel_dpll_hw_state *_b) {
> +	const struct intel_cx0pll_state *a = &_a->cx0pll;
> +	const struct intel_cx0pll_state *b = &_b->cx0pll;
> +
> +	return intel_cx0pll_compare_hw_state(a, b); }
> +
>  __maybe_unused
>  static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
> @@ -4458,6 +4467,7 @@ static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.update_active_dpll = icl_update_active_dpll,
>  	.update_ref_clks = icl_update_dpll_ref_clks,
>  	.dump_hw_state = mtl_dump_hw_state,
> +	.compare_hw_state = mtl_compare_hw_state,
>  };
> 
>  /**
> --
> 2.34.1

RE: [CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms

[Kandpal, Suraj]

> Subject: [CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms
> 
> Add .get_hw_state hook to MTL+ platforms for dpll framework.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  9 ++++--
> drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  2 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 29 +++++++++++++++++++
>  3 files changed, 37 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index e44dfda43d38..15ba3522b5b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3620,19 +3620,24 @@ intel_mtl_port_pll_type(struct intel_encoder
> *encoder,
>  		return ICL_PORT_DPLL_DEFAULT;
>  }
> 
> -void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> +bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>  				   struct intel_cx0pll_state *pll_state)  {
>  	memset(pll_state, 0, sizeof(*pll_state));
> 
>  	pll_state->tbt_mode =
> intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
>  	if (pll_state->tbt_mode)
> -		return;
> +		return true;
> +
> +	if (!intel_cx0_pll_is_enabled(encoder))
> +		return false;
> 
>  	if (intel_encoder_is_c10phy(encoder))
>  		intel_c10pll_readout_hw_state(encoder, pll_state);
>  	else
>  		intel_c20pll_readout_hw_state(encoder, pll_state);
> +
> +	return true;
>  }
> 
>  static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a,
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 03441138ec01..13eaf6d280ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -32,7 +32,7 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
> int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
>  			    struct intel_encoder *encoder,
>  			    struct intel_dpll_hw_state *hw_state); -void
> intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> +bool intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
>  				   struct intel_cx0pll_state *pll_state);  int
> intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
>  				 const struct intel_cx0pll_state *pll_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index d22771cf2ebd..db6ae7bc63d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4351,7 +4351,36 @@ static const struct intel_dpll_mgr adlp_pll_mgr =
> {
>  	.compare_hw_state = icl_compare_hw_state,  };
> 
> +static struct intel_encoder *get_intel_encoder(struct intel_display *display,
> +					       const struct intel_dpll *pll) {
> +	struct intel_encoder *encoder;
> +	enum intel_dpll_id mtl_id;
> +
> +	for_each_intel_encoder(display->drm, encoder) {
> +		mtl_id = mtl_port_to_pll_id(display, encoder->port);
> +
> +		if (mtl_id == pll->info->id)
> +			return encoder;
> +	}
> +
> +	return NULL;
> +}
> +
> +static bool mtl_pll_get_hw_state(struct intel_display *display,
> +				 struct intel_dpll *pll,
> +				 struct intel_dpll_hw_state *dpll_hw_state) {
> +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> +
> +	if (!encoder)
> +		return false;
> +
> +	return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state-
> >cx0pll);
> +}
> +
>  static const struct intel_dpll_funcs mtl_pll_funcs = {
> +	.get_hw_state = mtl_pll_get_hw_state,
>  };
> 
>  static const struct dpll_info mtl_plls[] = {
> --
> 2.34.1

RE: [CI 26/32] drm/i915/display: Add .get_freq to MTL+ platforms

[Kandpal, Suraj]

> Subject: [CI 26/32] drm/i915/display: Add .get_freq to MTL+ platforms
> 
> Add .get_freq hook to support dpll framework for MTL+ platforms.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index db6ae7bc63d6..07bc99ae689c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4379,8 +4379,21 @@ static bool mtl_pll_get_hw_state(struct
> intel_display *display,
>  	return intel_cx0pll_readout_hw_state(encoder, &dpll_hw_state-
> >cx0pll);  }
> 
> +static int mtl_pll_get_freq(struct intel_display *display,
> +			    const struct intel_dpll *pll,
> +			    const struct intel_dpll_hw_state *dpll_hw_state) {
> +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> +
> +	if (drm_WARN_ON(display->drm, !encoder))
> +		return -EINVAL;
> +
> +	return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state-
> >cx0pll);
> +}
> +
>  static const struct intel_dpll_funcs mtl_pll_funcs = {
>  	.get_hw_state = mtl_pll_get_hw_state,
> +	.get_freq = mtl_pll_get_freq,
>  };
> 
>  static const struct dpll_info mtl_plls[] = {
> --
> 2.34.1

RE: [CI 27/32] drm/i915/display: Add .crtc_get_dpll hook

[Kandpal, Suraj]

.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>
> Subject: [CI 27/32] drm/i915/display: Add .crtc_get_dpll hook
> 
> Add .crtc_get_dpll function pointer to support MTL+ platforms.
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 7a48d6f0db10..46ae05976191 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1693,6 +1693,7 @@ static int i8xx_crtc_compute_clock(struct
> intel_atomic_state *state,
> 
>  static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
>  	.crtc_compute_clock = mtl_crtc_compute_clock,
> +	.crtc_get_dpll = hsw_crtc_get_dpll,
>  };
> 
>  static const struct intel_dpll_global_funcs dg2_dpll_funcs = {
> --
> 2.34.1

RE: [CI 28/32] drm/i915/display: PLL verify debug state print

[Kandpal, Suraj]

> Subject: [CI 28/32] drm/i915/display: PLL verify debug state print
> 
> From: Imre Deak <imre.deak@intel.com>
> 
> Print out hw and sw pll states for better debugging support.
> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 17 ++++++++++++-----
>  1 file changed, 12 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 07bc99ae689c..6cc85a9a781f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4882,11 +4882,18 @@ verify_single_dpll_state(struct intel_display
> *display,
>  				 "%s: pll enabled crtcs mismatch (expected
> 0x%x in 0x%x)\n",
>  				 pll->info->name, pipe_mask, pll-
> >state.pipe_mask);
> 
> -	INTEL_DISPLAY_STATE_WARN(display,
> -				 pll->on && memcmp(&pll->state.hw_state,
> &dpll_hw_state,
> -						   sizeof(dpll_hw_state)),
> -				 "%s: pll hw state mismatch\n",
> -				 pll->info->name);
> +	if (INTEL_DISPLAY_STATE_WARN(display,
> +				     pll->on && memcmp(&pll-
> >state.hw_state, &dpll_hw_state,
> +						       sizeof(dpll_hw_state)),
> +				     "%s: pll hw state mismatch\n",
> +				     pll->info->name)) {
> +		struct drm_printer p = drm_dbg_printer(display->drm,
> DRM_UT_KMS, NULL);
> +
> +		drm_printf(&p, "PLL %s HW state:\n", pll->info->name);
> +		intel_dpll_dump_hw_state(display, &p, &dpll_hw_state);
> +		drm_printf(&p, "PLL %s SW state:\n", pll->info->name);
> +		intel_dpll_dump_hw_state(display, &p, &pll->state.hw_state);
> +	}
>  }
> 
>  static bool has_alt_port_dpll(const struct intel_dpll *old_pll,
> --
> 2.34.1

RE: [CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms

[Kandpal, Suraj]

> Subject: [CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+
> platforms
> 
> To enable pll clock on DDI we need to move part of the pll enabling
> sequence to a ddi clock enabling function.
> 
> Simlilarly, we do the pll disabling sequence.

Avoid using We do , we need keep it imperative with that fixed

Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> 
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 34 +++++++++++++------
> drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  7 +++-
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  6 ++--
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 25 ++++++++++++++
>  4 files changed, 58 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 15ba3522b5b3..b82a1f891eae 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3301,7 +3301,6 @@ static void intel_cx0pll_enable(struct
> intel_encoder *encoder,
>  	 * Frequency Change. We handle this step in bxt_set_cdclk().
>  	 */
> 
> -	/* TODO: enable TBT-ALT mode */
>  	intel_cx0_phy_transaction_end(encoder, wakeref);  }
> 
> @@ -3367,8 +3366,7 @@ static int intel_mtl_tbt_clock_select(struct
> intel_display *display,
>  	}
>  }
> 
> -static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> -				     const struct intel_crtc_state *crtc_state)
> +static void intel_mtl_tbt_pll_enable_clock(struct intel_encoder
> +*encoder, int port_clock)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	enum phy phy = intel_encoder_to_phy(encoder); @@ -3382,7
> +3380,7 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder
> *encoder,
> 
>  	mask = XELPDP_DDI_CLOCK_SELECT_MASK(display);
>  	val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
> -					    intel_mtl_tbt_clock_select(display,
> crtc_state->port_clock));
> +					    intel_mtl_tbt_clock_select(display,
> port_clock));
> 
>  	mask |= XELPDP_FORWARD_CLOCK_UNGATE;
>  	val |= XELPDP_FORWARD_CLOCK_UNGATE;
> @@ -3423,18 +3421,26 @@ static void intel_mtl_tbt_pll_enable(struct
> intel_encoder *encoder,
>  	 * clock frequency.
>  	 */
>  	intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> -		       crtc_state->port_clock);
> +		       port_clock);
>  }
> 
>  void intel_mtl_pll_enable(struct intel_encoder *encoder,
> -			  const struct intel_crtc_state *crtc_state)
> +			  struct intel_dpll *pll,
> +			  const struct intel_dpll_hw_state *dpll_hw_state) {
> +	intel_cx0pll_enable(encoder, &dpll_hw_state->cx0pll); }
> +
> +void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
> +				const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> -		intel_mtl_tbt_pll_enable(encoder, crtc_state);
> +		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
>  	else
> -		intel_cx0pll_enable(encoder, &crtc_state-
> >dpll_hw_state.cx0pll);
> +		/* TODO: remove when PLL mgr is in place. */
> +		intel_mtl_pll_enable(encoder, NULL, &crtc_state-
> >dpll_hw_state);
>  }
> 
>  /*
> @@ -3550,7 +3556,7 @@ static bool intel_cx0_pll_is_enabled(struct
> intel_encoder *encoder)
>  			     intel_cx0_get_pclk_pll_request(lane);
>  }
> 
> -static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> +static void intel_mtl_tbt_pll_disable_clock(struct intel_encoder
> +*encoder)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  	enum phy phy = intel_encoder_to_phy(encoder); @@ -3590,13
> +3596,19 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder
> *encoder)  }
> 
>  void intel_mtl_pll_disable(struct intel_encoder *encoder)
> +{
> +	intel_cx0pll_disable(encoder);
> +}
> +
> +void intel_mtl_pll_disable_clock(struct intel_encoder *encoder)
>  {
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
> -		intel_mtl_tbt_pll_disable(encoder);
> +		intel_mtl_tbt_pll_disable_clock(encoder);
>  	else
> -		intel_cx0pll_disable(encoder);
> +		/* TODO: remove when PLL mgr is in place. */
> +		intel_mtl_pll_disable(encoder);
>  }
> 
>  enum icl_port_dpll_id
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 13eaf6d280ff..13fa001129f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -17,17 +17,22 @@ struct intel_crtc;
>  struct intel_crtc_state;
>  struct intel_cx0pll_state;
>  struct intel_display;
> +struct intel_dpll;
>  struct intel_dpll_hw_state;
>  struct intel_encoder;
>  struct intel_hdmi;
> 
>  bool intel_encoder_is_c10phy(struct intel_encoder *encoder);  void
> intel_mtl_pll_enable(struct intel_encoder *encoder,
> -			  const struct intel_crtc_state *crtc_state);
> +			  struct intel_dpll *pll,
> +			  const struct intel_dpll_hw_state *dpll_hw_state);
>  void intel_mtl_pll_disable(struct intel_encoder *encoder);  enum
> icl_port_dpll_id  intel_mtl_port_pll_type(struct intel_encoder *encoder,
>  			const struct intel_crtc_state *crtc_state);
> +void intel_mtl_pll_enable_clock(struct intel_encoder *encoder,
> +				const struct intel_crtc_state *crtc_state); void
> +intel_mtl_pll_disable_clock(struct intel_encoder *encoder);
> 
>  int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
>  			    struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 870140340342..d0bfa7f397dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -88,6 +88,8 @@
>  #include "skl_scaler.h"
>  #include "skl_universal_plane.h"
> 
> +struct intel_dpll;
> +
>  static const u8 index_to_dp_signal_levels[] = {
>  	[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
> DP_TRAIN_PRE_EMPH_LEVEL_0,
>  	[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 |
> DP_TRAIN_PRE_EMPH_LEVEL_1, @@ -5232,8 +5234,8 @@ void
> intel_ddi_init(struct intel_display *display,
>  	encoder->pipe_mask = ~0;
> 
>  	if (DISPLAY_VER(display) >= 14) {
> -		encoder->enable_clock = intel_mtl_pll_enable;
> -		encoder->disable_clock = intel_mtl_pll_disable;
> +		encoder->enable_clock = intel_mtl_pll_enable_clock;
> +		encoder->disable_clock = intel_mtl_pll_disable_clock;
>  		encoder->port_pll_type = intel_mtl_port_pll_type;
>  		encoder->get_config = mtl_ddi_get_config;
>  	} else if (display->platform.dg2) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 6cc85a9a781f..8220ef69f685 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4391,7 +4391,32 @@ static int mtl_pll_get_freq(struct intel_display
> *display,
>  	return intel_cx0pll_calc_port_clock(encoder, &dpll_hw_state-
> >cx0pll);  }
> 
> +static void mtl_pll_enable(struct intel_display *display,
> +			   struct intel_dpll *pll,
> +			   const struct intel_dpll_hw_state *dpll_hw_state) {
> +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> +
> +	if (drm_WARN_ON(display->drm, !encoder))
> +		return;
> +
> +	intel_mtl_pll_enable(encoder, pll, dpll_hw_state); }
> +
> +static void mtl_pll_disable(struct intel_display *display,
> +			    struct intel_dpll *pll)
> +{
> +	struct intel_encoder *encoder = get_intel_encoder(display, pll);
> +
> +	if (drm_WARN_ON(display->drm, !encoder))
> +		return;
> +
> +	intel_mtl_pll_disable(encoder);
> +}
> +
>  static const struct intel_dpll_funcs mtl_pll_funcs = {
> +	.enable = mtl_pll_enable,
> +	.disable = mtl_pll_disable,
>  	.get_hw_state = mtl_pll_get_hw_state,
>  	.get_freq = mtl_pll_get_freq,
>  };
> --
> 2.34.1

RE: [CI 32/32] drm/i915/display: Enable dpll framework for MTL+

[Kandpal, Suraj]

> Subject: [CI 32/32] drm/i915/display: Enable dpll framework for MTL+
> 
> Now that MTL+ platforms are supported by dpll framework we can remove a
> separate check for hw comparison and rely solely on dpll framework hw
> comparison.
> 
> Finally, we have all required hooks in place so we can initialize the PLL
> manager for MTL+ platforms and remove the redirections to the legacy code
> paths from the following
> interfaces:

Avoid using we

> 
> * intel_encoder::clock_enable/disable()
> * intel_encoder::get_config()
> * intel_dpll_funcs::get_hw_state()
> * intel_ddi_update_active_dpll()
> * pipe_config_pll_mismatch()
> 
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 10 ------
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 26 ++--------------
>  drivers/gpu/drm/i915/display/intel_display.c  | 31 -------------------
>  drivers/gpu/drm/i915/display/intel_dpll.c     | 23 +-------------
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  5 +--
>  5 files changed, 6 insertions(+), 89 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 432cdf56a6ed..2005a3a93f74 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -3456,9 +3456,6 @@ void intel_mtl_pll_enable_clock(struct
> intel_encoder *encoder,
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_enable_clock(encoder, crtc_state-
> >port_clock);
> -	else
> -		/* TODO: remove when PLL mgr is in place. */
> -		intel_mtl_pll_enable(encoder, NULL, &crtc_state-
> >dpll_hw_state);
>  }
> 
>  /*
> @@ -3624,9 +3621,6 @@ void intel_mtl_pll_disable_clock(struct
> intel_encoder *encoder)
> 
>  	if (intel_tc_port_in_tbt_alt_mode(dig_port))
>  		intel_mtl_tbt_pll_disable_clock(encoder);
> -	else
> -		/* TODO: remove when PLL mgr is in place. */
> -		intel_mtl_pll_disable(encoder);
>  }
> 
>  enum icl_port_dpll_id
> @@ -3655,10 +3649,6 @@ bool intel_cx0pll_readout_hw_state(struct
> intel_encoder *encoder,  {
>  	memset(pll_state, 0, sizeof(*pll_state));
> 
> -	pll_state->tbt_mode =
> intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));
> -	if (pll_state->tbt_mode)
> -		return true;
> -
>  	if (!intel_cx0_pll_is_enabled(encoder))
>  		return false;
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index f554921f59a3..7a981b11b029 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3667,8 +3667,7 @@ void intel_ddi_update_active_dpll(struct
> intel_atomic_state *state,
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_crtc *pipe_crtc;
> 
> -	/* FIXME: Add MTL pll_mgr */
> -	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
> +	if (!intel_encoder_is_tc(encoder))

Also if !HAS_LT_PHY check here

Regards,
Suraj Kandpal

>  		return;
> 
>  	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc, @@ -
> 4242,19 +4241,6 @@ void intel_ddi_get_clock(struct intel_encoder
> *encoder,
>  						     &crtc_state-
> >dpll_hw_state);  }
> 
> -static void mtl_ddi_get_config(struct intel_encoder *encoder,
> -			       struct intel_crtc_state *crtc_state)
> -{
> -	intel_cx0pll_readout_hw_state(encoder, &crtc_state-
> >dpll_hw_state.cx0pll);
> -
> -	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
> -		crtc_state->port_clock =
> intel_mtl_tbt_calc_port_clock(encoder);
> -	else
> -		crtc_state->port_clock =
> intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);
> -
> -	intel_ddi_get_config(encoder, crtc_state);
> -}
> -
>  static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)  {
>  	return pll->info->id == DPLL_ID_ICL_TBTPLL; @@ -4301,10 +4287,6
> @@ static void mtl_ddi_non_tc_phy_get_config(struct intel_encoder
> *encoder,  {
>  	struct intel_display *display = to_intel_display(encoder);
> 
> -	/* TODO: Remove when the PLL manager is in place. */
> -	mtl_ddi_get_config(encoder, crtc_state);
> -	return;
> -
>  	mtl_ddi_cx0_get_config(encoder, crtc_state,
> ICL_PORT_DPLL_DEFAULT,
>  			       mtl_port_to_pll_id(display, encoder->port));  }
> @@ -4314,10 +4296,6 @@ static void mtl_ddi_tc_phy_get_config(struct
> intel_encoder *encoder,  {
>  	struct intel_display *display = to_intel_display(encoder);
> 
> -	/* TODO: Remove when the PLL manager is in place. */
> -	mtl_ddi_get_config(encoder, crtc_state);
> -	return;
> -
>  	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
>  		mtl_ddi_cx0_get_config(encoder, crtc_state,
> ICL_PORT_DPLL_DEFAULT,
>  				       DPLL_ID_ICL_TBTPLL);
> @@ -5302,7 +5280,7 @@ void intel_ddi_init(struct intel_display *display,
>  	if (DISPLAY_VER(display) >= 14) {
>  		encoder->enable_clock = intel_mtl_pll_enable_clock;
>  		encoder->disable_clock = intel_mtl_pll_disable_clock;
> -		encoder->port_pll_type = intel_mtl_port_pll_type;
> +		encoder->port_pll_type = icl_ddi_tc_port_pll_type;
>  		if (intel_encoder_is_tc(encoder))
>  			encoder->get_config = mtl_ddi_tc_phy_get_config;
>  		else
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 2e927d6cd577..5b569ad8157b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4932,23 +4932,6 @@ pipe_config_pll_mismatch(struct drm_printer *p,
> bool fastset,
>  	intel_dpll_dump_hw_state(display, p, b);  }
> 
> -static void
> -pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
> -			    const struct intel_crtc *crtc,
> -			    const char *name,
> -			    const struct intel_cx0pll_state *a,
> -			    const struct intel_cx0pll_state *b)
> -{
> -	char *chipname = a->use_c10 ? "C10" : "C20";
> -
> -	pipe_config_mismatch(p, fastset, crtc, name, chipname);
> -
> -	drm_printf(p, "expected:\n");
> -	intel_cx0pll_dump_hw_state(p, a);
> -	drm_printf(p, "found:\n");
> -	intel_cx0pll_dump_hw_state(p, b);
> -}
> -
>  static bool allow_vblank_delay_fastset(const struct intel_crtc_state
> *old_crtc_state)  {
>  	struct intel_display *display = to_intel_display(old_crtc_state); @@ -
> 5082,16 +5065,6 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  	} \
>  } while (0)
> 
> -#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
> -	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
> -					   &pipe_config->name)) { \
> -		pipe_config_cx0pll_mismatch(&p, fastset, crtc,
> __stringify(name), \
> -					    &current_config->name, \
> -					    &pipe_config->name); \
> -		ret = false; \
> -	} \
> -} while (0)
> -
>  #define PIPE_CONF_CHECK_TIMINGS(name) do {     \
>  	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
>  	PIPE_CONF_CHECK_I(name.crtc_htotal); \ @@ -5315,10 +5288,6 @@
> intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	if (display->dpll.mgr || HAS_GMCH(display))
>  		PIPE_CONF_CHECK_PLL(dpll_hw_state);
> 
> -	/* FIXME convert MTL+ platforms over to dpll_mgr */
> -	if (DISPLAY_VER(display) >= 14)
> -		PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
> -
>  	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
>  	PIPE_CONF_CHECK_X(dsi_pll.div);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
> b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 46ae05976191..f744f61b291a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1211,27 +1211,6 @@ static int dg2_crtc_compute_clock(struct
> intel_atomic_state *state,
>  	return 0;
>  }
> 
> -static int mtl_crtc_compute_clock(struct intel_atomic_state *state,
> -				  struct intel_crtc *crtc)
> -{
> -	struct intel_crtc_state *crtc_state =
> -		intel_atomic_get_new_crtc_state(state, crtc);
> -	struct intel_encoder *encoder =
> -		intel_get_crtc_new_encoder(state, crtc_state);
> -	int ret;
> -
> -	ret = intel_cx0pll_calc_state(crtc_state, encoder, &crtc_state-
> >dpll_hw_state);
> -	if (ret)
> -		return ret;
> -
> -	/* TODO: Do the readback via intel_dpll_compute() */
> -	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder,
> &crtc_state->dpll_hw_state.cx0pll);
> -
> -	crtc_state->hw.adjusted_mode.crtc_clock =
> intel_crtc_dotclock(crtc_state);
> -
> -	return 0;
> -}
> -
>  static int ilk_fb_cb_factor(const struct intel_crtc_state *crtc_state)  {
>  	struct intel_display *display = to_intel_display(crtc_state); @@ -
> 1692,7 +1671,7 @@ static int i8xx_crtc_compute_clock(struct
> intel_atomic_state *state,  }
> 
>  static const struct intel_dpll_global_funcs mtl_dpll_funcs = {
> -	.crtc_compute_clock = mtl_crtc_compute_clock,
> +	.crtc_compute_clock = hsw_crtc_compute_clock,
>  	.crtc_get_dpll = hsw_crtc_get_dpll,
>  };
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index ddc763d89aac..77ef6a0419d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -4558,7 +4558,6 @@ static bool mtl_compare_hw_state(const struct
> intel_dpll_hw_state *_a,
>  	return intel_cx0pll_compare_hw_state(a, b);  }
> 
> -__maybe_unused
>  static const struct intel_dpll_mgr mtl_pll_mgr = {
>  	.dpll_info = mtl_plls,
>  	.compute_dplls = mtl_compute_dplls,
> @@ -4584,9 +4583,11 @@ void intel_dpll_init(struct intel_display *display)
> 
>  	mutex_init(&display->dpll.lock);
> 
> -	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
> +	if (display->platform.dg2)
>  		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
>  		dpll_mgr = NULL;
> +	else if (DISPLAY_VER(display) >= 14)
> +		dpll_mgr = &mtl_pll_mgr;
>  	else if (display->platform.alderlake_p)
>  		dpll_mgr = &adlp_pll_mgr;
>  	else if (display->platform.alderlake_s)
> --
> 2.34.1

Re: [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables

[Imre Deak]

On Wed, Nov 12, 2025 at 06:10:36AM +0200, Suraj Kandpal wrote:
> > Subject: Re: [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables
> > 
> > On Tue, Nov 11, 2025 at 07:36:47AM +0200, Suraj Kandpal wrote:
> > > > + [...]
> > > > +static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> > > > +				   struct intel_encoder *encoder) {
> > > > +	int err = -ENOENT;
> > > > +
> > > > +	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> > > > +
> > > > +	/* try computed C20 HDMI tables before using consolidated tables */
> > > > +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> > > > +		/* TODO: Update SSC state for HDMI as well */
> > > > +		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> > > > +
> > > > +	if (err)
> > > > +		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> > >
> > > So this is something I have been meaning to fix we should really be
> > > using the HDMI tables already defined. Computing them ourselves, that
> > > should be reserved for only when we do not have any HDMI table for the
> > > said port clock available.
> > 
> > > Also if we use the computed tables directly that means we never end up
> > > using the defined tables.
> > >
> > > SO the flow here should be
> > >
> > > err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> > >
> > > if (err && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)))
> > > 	err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> > 
> > This patch is not meant to change the logic, it simply wants to make the logic
> > clearer to the reader. What you suggest should be a separate patch
> 
> I am fine with that do you want to add that as a part of this series
> or should I send a separate Patch fixing this.

I think that change is not in the scope of this patchset, so it would be
better if you could follow up with it separately.

> Either way
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

Thanks.

> > 
> > > something like this.
> > >
> > > Regards,
> > > Suraj Kandpal
> > >
> > > > +
> > > > +	return err;
> > > >  }
> > > >
> > > >  int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > > > --
> > > > 2.34.1

RE: [CI 17/32] drm/i915/display: Update C10/C20 state calculation

[Kahola, Mika]

> -----Original Message-----
> From: Kandpal, Suraj <suraj.kandpal@intel.com>
> Sent: Wednesday, 12 November 2025 6.29
> To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Deak, Imre <imre.deak@intel.com>
> Subject: RE: [CI 17/32] drm/i915/display: Update C10/C20 state calculation
> 
> > Subject: [CI 17/32] drm/i915/display: Update C10/C20 state calculation
> >
> > For the dpll framework, the state must be computed into a port PLL
> > state, which is separate from the dpll_hw_state in crtc_state.
> 
> You have state the problem here but failed to mention what the commit does.
> Also port PLL state?
Ok, I will try to reword the commit message to better reflect what the patch does.

> Also two different changes are happening here struct crtc_state argument becomes const struct crtc_state and a addition of a
> new param dpll_hw_state maybe these need to be two separate patches.
Switching to const struct crtc_state seemed to me a small change that could embedded into this patch. I will try to reword commit message include reasoning for this change.

> 
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 68
> > ++++++++++---------- drivers/gpu/drm/i915/display/intel_cx0_phy.h |  5 +-
> >  drivers/gpu/drm/i915/display/intel_dpll.c    |  2 +-
> >  3 files changed, 40 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 5332f33800e7..f5e6634a6389 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -2034,7 +2034,7 @@ static const struct intel_c20pll_state * const
> > mtl_c20_hdmi_tables[] = {  };
> >
> >  static const struct intel_c10pll_state * const *
> > -intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
> > +intel_c10pll_tables_get(const struct intel_crtc_state *crtc_state,
> >  			struct intel_encoder *encoder)
> >  {
> >  	if (intel_crtc_has_dp_encoder(crtc_state)) { @@ -2138,8 +2138,9 @@
> > static int intel_c10pll_calc_state_from_table(struct intel_encoder *encoder,
> >  	return -EINVAL;
> >  }
> >
> > -static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
> > -				   struct intel_encoder *encoder)
> > +static int intel_c10pll_calc_state(const struct intel_crtc_state *crtc_state,
> > +				   struct intel_encoder *encoder,
> > +				   struct intel_dpll_hw_state *hw_state)
> >  {
> >  	struct intel_display *display = to_intel_display(encoder);
> >  	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
> > @@ -2152,21 +2153,20 @@ static int intel_c10pll_calc_state(struct
> > intel_crtc_state *crtc_state,
> >
> >  	err = intel_c10pll_calc_state_from_table(encoder, tables, is_dp,
> >  						 crtc_state->port_clock,
> > crtc_state->lane_count,
> > -						 &crtc_state-
> > >dpll_hw_state.cx0pll);
> > +						 &hw_state->cx0pll);
> >
> >  	if (err == 0 || !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> >  		return err;
> >
> >  	/* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed
> > tables */
> > -	intel_snps_hdmi_pll_compute_c10pll(&crtc_state-
> > >dpll_hw_state.cx0pll.c10,
> > +	intel_snps_hdmi_pll_compute_c10pll(&hw_state->cx0pll.c10,
> >  					   crtc_state->port_clock);
> > -	intel_c10pll_update_pll(encoder,
> > -				&crtc_state->dpll_hw_state.cx0pll);
> > -	crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
> > -	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
> > +	intel_c10pll_update_pll(encoder, &hw_state->cx0pll);
> >
> > -	drm_WARN_ON(display->drm,
> > -		    is_dp != c10pll_state_is_dp(&crtc_state-
> > >dpll_hw_state.cx0pll.c10));
> > +	hw_state->cx0pll.use_c10 = true;
> > +	hw_state->cx0pll.lane_count = crtc_state->lane_count;
> > +
> > +	drm_WARN_ON(display->drm, is_dp !=
> > +c10pll_state_is_dp(&hw_state->cx0pll.c10));
> >
> >  	return 0;
> >  }
> > @@ -2355,7 +2355,7 @@ static bool is_arrowlake_s_by_host_bridge(void)
> >  	return pdev &&
> > IS_ARROWLAKE_S_BY_HOST_BRIDGE_ID(host_bridge_pci_dev_id);
> >  }
> >
> > -static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct intel_crtc_state
> > *crtc_state)
> > +static u16 intel_c20_hdmi_tmds_tx_cgf_1(const struct intel_crtc_state
> > +*crtc_state)
> >  {
> >  	struct intel_display *display = to_intel_display(crtc_state);
> >  	u16 tx_misc;
> > @@ -2379,9 +2379,9 @@ static u16 intel_c20_hdmi_tmds_tx_cgf_1(struct
> > intel_crtc_state *crtc_state)
> >  		C20_PHY_TX_DCC_BYPASS |
> > C20_PHY_TX_TERM_CTL(tx_term_ctrl));
> >  }
> >
> > -static int intel_c20_compute_hdmi_tmds_pll(struct intel_crtc_state
> > *crtc_state)
> > +static int intel_c20_compute_hdmi_tmds_pll(const struct
> > +intel_crtc_state
> > *crtc_state,
> > +					   struct intel_c20pll_state *pll_state)
> >  {
> > -	struct intel_c20pll_state *pll_state = &crtc_state-
> > >dpll_hw_state.cx0pll.c20;
> >  	u64 datarate;
> >  	u64 mpll_tx_clk_div;
> >  	u64 vco_freq_shift;
> > @@ -2648,8 +2648,9 @@ intel_c20_pll_find_table(const struct
> > intel_crtc_state *crtc_state,
> >  	return NULL;
> >  }
> >
> > -static int intel_c20pll_calc_state_from_table(struct intel_crtc_state *crtc_state,
> > -					      struct intel_encoder *encoder)
> > +static int intel_c20pll_calc_state_from_table(const struct
> > +intel_crtc_state
> > *crtc_state,
> > +					      struct intel_encoder *encoder,
> > +					      struct intel_cx0pll_state *pll_state)
> >  {
> >  	const struct intel_c20pll_state *table;
> >
> > @@ -2657,52 +2658,53 @@ static int
> > intel_c20pll_calc_state_from_table(struct
> > intel_crtc_state *crtc_stat
> >  	if (!table)
> >  		return -EINVAL;
> >
> > -	crtc_state->dpll_hw_state.cx0pll.c20 = *table;
> > +	pll_state->c20 = *table;
> >
> > -	intel_cx0pll_update_ssc(encoder, &crtc_state->dpll_hw_state.cx0pll,
> > -				intel_crtc_has_dp_encoder(crtc_state));
> > +	intel_cx0pll_update_ssc(encoder, pll_state,
> > +intel_crtc_has_dp_encoder(crtc_state));
> >
> >  	return 0;
> >  }
> >
> > -static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
> > -				   struct intel_encoder *encoder)
> > +static int intel_c20pll_calc_state(const struct intel_crtc_state *crtc_state,
> > +				   struct intel_encoder *encoder,
> > +				   struct intel_dpll_hw_state *hw_state)
> >  {
> >  	struct intel_display *display = to_intel_display(encoder);
> >  	bool is_dp = intel_crtc_has_dp_encoder(crtc_state);
> >  	int err = -ENOENT;
> >
> > -	crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
> > -	crtc_state->dpll_hw_state.cx0pll.lane_count = crtc_state->lane_count;
> > +	hw_state->cx0pll.use_c10 = false;
> > +	hw_state->cx0pll.lane_count = crtc_state->lane_count;
> >
> >  	/* try computed C20 HDMI tables before using consolidated tables */
> >  	if (!is_dp)
> >  		/* TODO: Update SSC state for HDMI as well */
> > -		err = intel_c20_compute_hdmi_tmds_pll(crtc_state);
> > +		err = intel_c20_compute_hdmi_tmds_pll(crtc_state,
> > +&hw_state->cx0pll.c20);
> >
> >  	if (err)
> > -		err = intel_c20pll_calc_state_from_table(crtc_state, encoder);
> > +		err = intel_c20pll_calc_state_from_table(crtc_state, encoder,
> > +							 &hw_state->cx0pll);
> >
> >  	if (err)
> >  		return err;
> >
> > -	intel_c20_calc_vdr_params(&crtc_state->dpll_hw_state.cx0pll.c20.vdr,
> > +	intel_c20_calc_vdr_params(&hw_state->cx0pll.c20.vdr,
> >  				  is_dp, crtc_state->port_clock);
> >
> > -	drm_WARN_ON(display->drm,
> > -		    is_dp != c20pll_state_is_dp(&crtc_state-
> > >dpll_hw_state.cx0pll.c20));
> > +	drm_WARN_ON(display->drm, is_dp !=
> > +c20pll_state_is_dp(&hw_state->cx0pll.c20));
> >
> >  	return 0;
> >  }
> >
> > -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > -			    struct intel_encoder *encoder)
> > +int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
> > +			    struct intel_encoder *encoder,
> > +			    struct intel_dpll_hw_state *hw_state)
> >  {
> > -	memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state-
> > >dpll_hw_state));
> > +	memset(hw_state, 0, sizeof(*hw_state));
> >
> >  	if (intel_encoder_is_c10phy(encoder))
> > -		return intel_c10pll_calc_state(crtc_state, encoder);
> > -	return intel_c20pll_calc_state(crtc_state, encoder);
> > +		return intel_c10pll_calc_state(crtc_state, encoder, hw_state);
> > +	return intel_c20pll_calc_state(crtc_state, encoder, hw_state);
> >  }
> >
> >  static bool intel_c20phy_use_mpllb(const struct intel_c20pll_state
> > *state) diff -- git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > index 2b934b96af81..7b88c3fe9de1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> > @@ -16,6 +16,7 @@ struct intel_crtc;
> >  struct intel_crtc_state;
> >  struct intel_cx0pll_state;
> >  struct intel_display;
> > +struct intel_dpll_hw_state;
> >  struct intel_encoder;
> >  struct intel_hdmi;
> >
> > @@ -27,7 +28,9 @@ enum icl_port_dpll_id
> > intel_mtl_port_pll_type(struct intel_encoder *encoder,
> >  			const struct intel_crtc_state *crtc_state);
> >
> > -int intel_cx0pll_calc_state(struct intel_crtc_state *crtc_state,
> > struct intel_encoder *encoder);
> > +int intel_cx0pll_calc_state(const struct intel_crtc_state *crtc_state,
> > +			    struct intel_encoder *encoder,
> > +			    struct intel_dpll_hw_state *hw_state);
> >  void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> >  				   struct intel_cx0pll_state *pll_state);  int
> > intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, diff --git
> > a/drivers/gpu/drm/i915/display/intel_dpll.c
> > b/drivers/gpu/drm/i915/display/intel_dpll.c
> > index f969c5399a51..7a48d6f0db10 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> > @@ -1220,7 +1220,7 @@ static int mtl_crtc_compute_clock(struct
> > intel_atomic_state *state,
> >  		intel_get_crtc_new_encoder(state, crtc_state);
> >  	int ret;
> >
> > -	ret = intel_cx0pll_calc_state(crtc_state, encoder);
> > +	ret = intel_cx0pll_calc_state(crtc_state, encoder,
> > +&crtc_state->dpll_hw_state);
> 
> So you are adding a new param which can be derived from the param you are still passing to the function ?
At this stage yes as the intel_cx0pll_calc_state() changed. This is, however, an intermediate step as we end up removing the whole mtl_crtc_compute_clock() function. 

> 
> Regards,
> Suraj Kandpal
> 
> >  	if (ret)
> >  		return ret;
> >
> > --
> > 2.34.1