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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Garg, Nemesa" <nemesa.garg@intel.com>
Cc: "Kandpal, Suraj" <suraj.kandpal@intel.com>,
	"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
Subject: Re: [PATCH] drm/i915/display: Disable DMG Clock Gating
Date: Tue, 20 Jan 2026 18:13:23 +0200	[thread overview]
Message-ID: <aW-po67khakWTsNR@intel.com> (raw)
In-Reply-To: <IA1PR11MB646765DC8252C407F4218656E389A@IA1PR11MB6467.namprd11.prod.outlook.com>

On Tue, Jan 20, 2026 at 08:23:17AM +0000, Garg, Nemesa wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Suraj
> > Kandpal
> > Sent: Tuesday, January 20, 2026 10:31 AM
> > To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kandpal, Suraj
> > <suraj.kandpal@intel.com>
> > Subject: [PATCH] drm/i915/display: Disable DMG Clock Gating
> > 
> > Disable DMG Clock gating during display initialization.
> > 
> > WA: 22021451799
> > Bspec: 69095
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_modeset_setup.c | 7 +++++++
> >  drivers/gpu/drm/i915/i915_reg.h                    | 1 +
> >  2 files changed, 8 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > index d10cbf69a5f8..2d46f00bd0d8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> > @@ -910,6 +910,13 @@ get_encoder_power_domains(struct intel_display
> > *display)
> > 
> >  static void intel_early_display_was(struct intel_display *display)  {
> > +	/*
> > +	 * Wa_22021451799
> > +	 * Disable DMG Clock gating
> > +	 */
> > +	if (DISPLAY_VER(display) == 35)
> > +		intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0,
> > DMG_GATING_DIS);
> > +
> >  	/*
> I guess we can remove the comment, only wa no. itself is sufficient.

At least the commit message (if not the comment) should describe what
this does. I do not want to have to trawl bspec to figure that out.

> 
> With this fix LGTM,
> Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
> 
> >  	 * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
> >  	 * Also known as Wa_14010480278.
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 5bf3b4ab2baa..f928db78a3fa
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -763,6 +763,7 @@
> >   */
> >  #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
> >  #define   DARBF_GATING_DIS		REG_BIT(27)
> > +#define   DMG_GATING_DIS		REG_BIT(21)
> >  #define   MTL_PIPEDMC_GATING_DIS(pipe)	REG_BIT(15 - (pipe))
> >  #define   PWM2_GATING_DIS		REG_BIT(14)
> >  #define   PWM1_GATING_DIS		REG_BIT(13)
> > --
> > 2.34.1

-- 
Ville Syrjälä
Intel

  parent reply	other threads:[~2026-01-20 16:13 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-20  5:00 [PATCH] drm/i915/display: Disable DMG Clock Gating Suraj Kandpal
2026-01-20  5:58 ` ✓ i915.CI.BAT: success for " Patchwork
2026-01-20  8:23 ` [PATCH] " Garg, Nemesa
2026-01-20  8:25   ` Kandpal, Suraj
2026-01-20 16:13   ` Ville Syrjälä [this message]
2026-01-21  2:55     ` Kandpal, Suraj
2026-01-20 11:05 ` ✗ i915.CI.Full: failure for " Patchwork
2026-01-21  3:02 ` [PATCH v2] " Suraj Kandpal
2026-01-21  3:58   ` Nautiyal, Ankit K
2026-01-21  5:14     ` Kandpal, Suraj
2026-01-21 10:34   ` Jani Nikula
2026-01-21  3:05 ` ✗ Fi.CI.BUILD: failure for drm/i915/display: Disable DMG Clock Gating (rev2) Patchwork
2026-01-22  3:18 ` [PATCH v3] drm/i915/display: Disable DMG Clock Gating Suraj Kandpal
2026-01-22  4:20 ` ✓ i915.CI.BAT: success for drm/i915/display: Disable DMG Clock Gating (rev3) Patchwork
2026-01-22 11:59 ` ✓ i915.CI.Full: " Patchwork

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