* [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers
@ 2021-09-27 19:23 Fangzhi Zuo
2021-09-28 12:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp: Add Additional DP2 Headers (rev3) Patchwork
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Fangzhi Zuo @ 2021-09-27 19:23 UTC (permalink / raw)
To: dri-devel, amd-gfx, intel-gfx, harry.wentland, jani.nikula
Cc: Nicholas.Kazlauskas, wayne.lin, Fangzhi Zuo
Include FEC, DSC, Link Training related headers.
Change since v2
- Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
---
This patch is based on top of the other DP2.0 work in
"drm/dp: add LTTPR DP 2.0 DPCD addresses"
---
include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1d5b3dbb6e56..a1df35aa6e68 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -453,6 +453,7 @@ struct drm_panel;
# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
+#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
@@ -537,6 +538,9 @@ struct drm_panel;
#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
+/* DFP Capability Extension */
+#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+
/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
@@ -688,6 +692,7 @@ struct drm_panel;
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
# define DP_DECOMPRESSION_EN (1 << 0)
+#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE BIT(0)
@@ -743,6 +748,7 @@ struct drm_panel;
# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
# define DP_RECEIVE_PORT_1_STATUS (1 << 1)
# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
+# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
#define DP_ADJUST_REQUEST_LANE0_1 0x206
#define DP_ADJUST_REQUEST_LANE2_3 0x207
@@ -865,6 +871,8 @@ struct drm_panel;
# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
# define DP_PHY_TEST_PATTERN_CP2520 0x5
+#define DP_PHY_SQUARE_PATTERN 0x249
+
#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
@@ -1109,6 +1117,18 @@ struct drm_panel;
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
+#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
+#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
+
+/* DSC Extended Capability Branch Total DSC Resources */
+#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
+# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
+# define DP_DSC_DECODER_COUNT_SHIFT 5
+#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
+# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
+
/* Protocol Converter Extension */
/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
#define DP_CEC_TUNNELING_CAPABILITY 0x3000
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp: Add Additional DP2 Headers (rev3) 2021-09-27 19:23 [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo @ 2021-09-28 12:28 ` Patchwork 2021-09-28 12:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (3 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2021-09-28 12:28 UTC (permalink / raw) To: Fangzhi Zuo; +Cc: intel-gfx == Series Details == Series: drm/dp: Add Additional DP2 Headers (rev3) URL : https://patchwork.freedesktop.org/series/95104/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ + #define DP_DFP_CAPABILITY_EX ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/dp: Add Additional DP2 Headers (rev3) 2021-09-27 19:23 [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo 2021-09-28 12:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp: Add Additional DP2 Headers (rev3) Patchwork @ 2021-09-28 12:55 ` Patchwork 2021-09-28 14:17 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2021-09-28 12:55 UTC (permalink / raw) To: Fangzhi Zuo; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 5515 bytes --] == Series Details == Series: drm/dp: Add Additional DP2 Headers (rev3) URL : https://patchwork.freedesktop.org/series/95104/ State : success == Summary == CI Bug Log - changes from CI_DRM_10654 -> Patchwork_21175 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/index.html Known issues ------------ Here are the changes found in Patchwork_21175 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_cs_nop@sync-fork-compute0: - fi-snb-2600: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html * igt@gem_huc_copy@huc-copy: - fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html * igt@i915_pm_backlight@basic-brightness: - fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([i915#1155]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html * igt@i915_pm_rpm@module-reload: - fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][4] ([i915#4006] / [i915#4193]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@i915_pm_rpm@module-reload.html * igt@kms_addfb_basic@too-wide: - fi-tgl-1115g4: NOTRUN -> [DMESG-WARN][5] ([i915#4002]) +89 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@kms_addfb_basic@too-wide.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([i915#4103]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([fdo#109285]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_psr@primary_mmap_gtt: - fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#1072]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html * igt@kms_psr@primary_page_flip: - fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([i915#1072] / [i915#1385]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@kms_psr@primary_page_flip.html * igt@prime_vgem@basic-userptr: - fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#3301]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html * igt@runner@aborted: - fi-tgl-1115g4: NOTRUN -> [FAIL][12] ([i915#2722] / [i915#4193]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-tgl-1115g4/igt@runner@aborted.html #### Possible fixes #### * igt@i915_selftest@live@hangcheck: - fi-snb-2600: [INCOMPLETE][13] ([i915#3921]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/fi-snb-2600/igt@i915_selftest@live@hangcheck.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/fi-snb-2600/igt@i915_selftest@live@hangcheck.html [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1385]: https://gitlab.freedesktop.org/drm/intel/issues/1385 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4002]: https://gitlab.freedesktop.org/drm/intel/issues/4002 [i915#4006]: https://gitlab.freedesktop.org/drm/intel/issues/4006 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4193]: https://gitlab.freedesktop.org/drm/intel/issues/4193 Participating hosts (45 -> 35) ------------------------------ Additional (1): fi-tgl-1115g4 Missing (11): fi-kbl-soraka fi-ilk-m540 bat-adls-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-4 fi-ctg-p8600 fi-bdw-samus fi-tgl-y bat-jsl-2 bat-jsl-1 Build changes ------------- * Linux: CI_DRM_10654 -> Patchwork_21175 CI-20190529: 20190529 CI_DRM_10654: 7006e15e0a109ce092026c4b576fe8a206e8b756 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6224: 2f4e6430a97f04284d1cafb1479e7c1b0b2d596a @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21175: 803095ab68fd39140515400ff655eee124f0d420 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 803095ab68fd drm/dp: Add Additional DP2 Headers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/index.html [-- Attachment #2: Type: text/html, Size: 6569 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/dp: Add Additional DP2 Headers (rev3) 2021-09-27 19:23 [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo 2021-09-28 12:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp: Add Additional DP2 Headers (rev3) Patchwork 2021-09-28 12:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-09-28 14:17 ` Patchwork 2021-09-28 15:19 ` [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Harry Wentland 2022-02-03 11:58 ` [Intel-gfx] binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) Jani Nikula 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2021-09-28 14:17 UTC (permalink / raw) To: Fangzhi Zuo; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30264 bytes --] == Series Details == Series: drm/dp: Add Additional DP2 Headers (rev3) URL : https://patchwork.freedesktop.org/series/95104/ State : success == Summary == CI Bug Log - changes from CI_DRM_10654_full -> Patchwork_21175_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_21175_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@feature_discovery@display-3x: - shard-glk: NOTRUN -> [SKIP][1] ([fdo#109271]) +39 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk8/igt@feature_discovery@display-3x.html * igt@gem_create@create-massive: - shard-snb: NOTRUN -> [DMESG-WARN][2] ([i915#3002]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-snb2/igt@gem_create@create-massive.html - shard-tglb: NOTRUN -> [DMESG-WARN][3] ([i915#3002]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb3/igt@gem_create@create-massive.html * igt@gem_ctx_persistence@legacy-engines-mixed: - shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +2 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-snb2/igt@gem_ctx_persistence@legacy-engines-mixed.html * igt@gem_eio@in-flight-1us: - shard-skl: [PASS][5] -> [TIMEOUT][6] ([i915#3063]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl7/igt@gem_eio@in-flight-1us.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl5/igt@gem_eio@in-flight-1us.html * igt@gem_exec_fair@basic-deadline: - shard-glk: NOTRUN -> [FAIL][7] ([i915#2846]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk8/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl10/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842]) +2 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][11] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][12] ([i915#2658]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl6/igt@gem_pread@exhaustion.html * igt@gem_userptr_blits@dmabuf-sync: - shard-apl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3323]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl1/igt@gem_userptr_blits@dmabuf-sync.html * igt@gen9_exec_parse@allowed-all: - shard-glk: [PASS][14] -> [DMESG-WARN][15] ([i915#1436] / [i915#716]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-glk7/igt@gen9_exec_parse@allowed-all.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk2/igt@gen9_exec_parse@allowed-all.html * igt@gen9_exec_parse@batch-zero-length: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#2856]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@gen9_exec_parse@batch-zero-length.html * igt@i915_pm_sseu@full-enable: - shard-tglb: NOTRUN -> [SKIP][17] ([fdo#109288]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb7/igt@i915_pm_sseu@full-enable.html * igt@i915_selftest@live@hangcheck: - shard-snb: [PASS][18] -> [INCOMPLETE][19] ([i915#3921]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-snb5/igt@i915_selftest@live@hangcheck.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-snb6/igt@i915_selftest@live@hangcheck.html * igt@i915_suspend@fence-restore-untiled: - shard-apl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-apl7/igt@i915_suspend@fence-restore-untiled.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl8/igt@i915_suspend@fence-restore-untiled.html * igt@kms_addfb_basic@invalid-smem-bo-on-discrete: - shard-tglb: NOTRUN -> [SKIP][22] ([i915#3826]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html * igt@kms_atomic@plane-primary-overlay-mutable-zpos: - shard-tglb: NOTRUN -> [SKIP][23] ([i915#404]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html * igt@kms_big_fb@linear-64bpp-rotate-90: - shard-tglb: NOTRUN -> [SKIP][24] ([fdo#111614]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb8/igt@kms_big_fb@linear-64bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-glk: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3777]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip: - shard-kbl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777]) +1 similar issue [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180: - shard-tglb: NOTRUN -> [SKIP][27] ([fdo#111615]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc: - shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +8 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl3/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl3/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886]) +3 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl4/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: - shard-glk: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk8/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][32] ([i915#3689]) +6 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb8/igt@kms_ccs@pipe-c-missing-ccs-buffer-yf_tiled_ccs.html * igt@kms_chamelium@hdmi-hpd: - shard-glk: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +3 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk8/igt@kms_chamelium@hdmi-hpd.html * igt@kms_chamelium@vga-hpd-after-suspend: - shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +1 similar issue [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl3/igt@kms_chamelium@vga-hpd-after-suspend.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-snb: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +16 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-snb2/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-a-ctm-limited-range: - shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +21 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl3/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html * igt@kms_color_chamelium@pipe-b-gamma: - shard-kbl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +3 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl3/igt@kms_color_chamelium@pipe-b-gamma.html * igt@kms_color_chamelium@pipe-d-ctm-limited-range: - shard-tglb: NOTRUN -> [SKIP][38] ([fdo#109284] / [fdo#111827]) +7 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@kms_color_chamelium@pipe-d-ctm-limited-range.html * igt@kms_content_protection@atomic: - shard-apl: NOTRUN -> [TIMEOUT][39] ([i915#1319]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl1/igt@kms_content_protection@atomic.html * igt@kms_cursor_crc@pipe-a-cursor-size-change: - shard-snb: NOTRUN -> [FAIL][40] ([i915#4024]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-snb2/igt@kms_cursor_crc@pipe-a-cursor-size-change.html - shard-apl: NOTRUN -> [FAIL][41] ([i915#3444]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl3/igt@kms_cursor_crc@pipe-a-cursor-size-change.html * igt@kms_cursor_crc@pipe-b-cursor-32x10-rapid-movement: - shard-tglb: NOTRUN -> [SKIP][42] ([i915#3359]) +1 similar issue [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x10-rapid-movement.html * igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen: - shard-tglb: NOTRUN -> [SKIP][43] ([fdo#109279] / [i915#3359]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen.html * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge: - shard-snb: NOTRUN -> [SKIP][44] ([fdo#109271]) +339 similar issues [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-snb2/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-skl: [PASS][45] -> [FAIL][46] ([i915#2346]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_cursor_legacy@pipe-d-single-bo: - shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#533]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl6/igt@kms_cursor_legacy@pipe-d-single-bo.html * igt@kms_cursor_legacy@pipe-d-torture-bo: - shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#533]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl3/igt@kms_cursor_legacy@pipe-d-torture-bo.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: NOTRUN -> [INCOMPLETE][49] ([i915#180] / [i915#1982]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html - shard-kbl: [PASS][50] -> [INCOMPLETE][51] ([i915#155] / [i915#180] / [i915#636]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [PASS][52] -> [FAIL][53] ([i915#79]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: NOTRUN -> [DMESG-WARN][54] ([i915#180]) +2 similar issues [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_flip@flip-vs-suspend@a-edp1: - shard-tglb: [PASS][55] -> [INCOMPLETE][56] ([i915#2411] / [i915#4173] / [i915#456]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-tglb6/igt@kms_flip@flip-vs-suspend@a-edp1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb7/igt@kms_flip@flip-vs-suspend@a-edp1.html * igt@kms_flip@plain-flip-ts-check@b-edp1: - shard-skl: [PASS][57] -> [FAIL][58] ([i915#2122]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl10/igt@kms_flip@plain-flip-ts-check@b-edp1.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl10/igt@kms_flip@plain-flip-ts-check@b-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs: - shard-tglb: NOTRUN -> [SKIP][59] ([i915#2587]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html - shard-iclb: [PASS][60] -> [SKIP][61] ([i915#3701]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt: - shard-kbl: NOTRUN -> [SKIP][62] ([fdo#109271]) +64 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary: - shard-glk: [PASS][63] -> [FAIL][64] ([i915#1888] / [i915#2546]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-glk9/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk9/igt@kms_frontbuffer_tracking@fbc-indfb-scaledprimary.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff: - shard-tglb: NOTRUN -> [SKIP][65] ([fdo#111825]) +14 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-onoff.html * igt@kms_frontbuffer_tracking@fbcpsr-suspend: - shard-tglb: [PASS][66] -> [INCOMPLETE][67] ([i915#2411] / [i915#456]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html * igt@kms_hdr@bpc-switch-suspend: - shard-skl: [PASS][68] -> [FAIL][69] ([i915#1188]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl2/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_hdr@static-swap: - shard-tglb: NOTRUN -> [SKIP][70] ([i915#1187]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb8/igt@kms_hdr@static-swap.html * igt@kms_invalid_dotclock: - shard-tglb: NOTRUN -> [SKIP][71] ([fdo#110577]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@kms_invalid_dotclock.html * igt@kms_multipipe_modeset@basic-max-pipe-crc-check: - shard-tglb: NOTRUN -> [SKIP][72] ([i915#1839]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - shard-tglb: [PASS][73] -> [INCOMPLETE][74] ([i915#456]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-tglb6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes: - shard-kbl: [PASS][75] -> [DMESG-WARN][76] ([i915#180]) +3 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: - shard-apl: NOTRUN -> [FAIL][77] ([fdo#108145] / [i915#265]) +3 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][78] ([i915#265]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-glk: NOTRUN -> [FAIL][79] ([fdo#108145] / [i915#265]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][80] -> [FAIL][81] ([fdo#108145] / [i915#265]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_cursor@pipe-d-overlay-size-256: - shard-iclb: NOTRUN -> [SKIP][82] ([fdo#109278]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-iclb7/igt@kms_plane_cursor@pipe-d-overlay-size-256.html * igt@kms_plane_lowres@pipe-c-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][83] ([fdo#112054]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb3/igt@kms_plane_lowres@pipe-c-tiling-yf.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-tglb: NOTRUN -> [SKIP][84] ([i915#2920]) +1 similar issue [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4: - shard-apl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#658]) +6 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-4.html * igt@kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: [PASS][86] -> [SKIP][87] ([fdo#109441]) +1 similar issue [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-iclb5/igt@kms_psr@psr2_sprite_mmap_cpu.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-apl: NOTRUN -> [DMESG-WARN][88] ([i915#180] / [i915#295]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@kms_vblank@pipe-d-ts-continuation-idle: - shard-apl: NOTRUN -> [SKIP][89] ([fdo#109271]) +213 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl1/igt@kms_vblank@pipe-d-ts-continuation-idle.html * igt@kms_vrr@flip-suspend: - shard-tglb: NOTRUN -> [SKIP][90] ([fdo#109502]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb7/igt@kms_vrr@flip-suspend.html * igt@kms_writeback@writeback-invalid-parameters: - shard-apl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#2437]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl3/igt@kms_writeback@writeback-invalid-parameters.html * igt@kms_writeback@writeback-pixel-formats: - shard-tglb: NOTRUN -> [SKIP][92] ([i915#2437]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@kms_writeback@writeback-pixel-formats.html * igt@nouveau_crc@pipe-c-source-outp-inactive: - shard-tglb: NOTRUN -> [SKIP][93] ([i915#2530]) +1 similar issue [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb7/igt@nouveau_crc@pipe-c-source-outp-inactive.html * igt@perf@polling-parameterized: - shard-glk: [PASS][94] -> [FAIL][95] ([i915#1542]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-glk6/igt@perf@polling-parameterized.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk7/igt@perf@polling-parameterized.html - shard-skl: [PASS][96] -> [FAIL][97] ([i915#1542]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl6/igt@perf@polling-parameterized.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl7/igt@perf@polling-parameterized.html * igt@perf@polling-small-buf: - shard-skl: [PASS][98] -> [FAIL][99] ([i915#1722]) [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl9/igt@perf@polling-small-buf.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl1/igt@perf@polling-small-buf.html * igt@perf@short-reads: - shard-skl: [PASS][100] -> [FAIL][101] ([i915#51]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl4/igt@perf@short-reads.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl3/igt@perf@short-reads.html * igt@prime_nv_pcopy@test3_5: - shard-tglb: NOTRUN -> [SKIP][102] ([fdo#109291]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@prime_nv_pcopy@test3_5.html * igt@runner@aborted: - shard-tglb: NOTRUN -> [FAIL][103] ([i915#3002]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb3/igt@runner@aborted.html - shard-snb: NOTRUN -> [FAIL][104] ([i915#3002]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-snb2/igt@runner@aborted.html * igt@sysfs_clients@recycle-many: - shard-kbl: NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#2994]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl3/igt@sysfs_clients@recycle-many.html * igt@sysfs_clients@sema-50: - shard-apl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2994]) +1 similar issue [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl1/igt@sysfs_clients@sema-50.html * igt@sysfs_clients@split-50: - shard-tglb: NOTRUN -> [SKIP][107] ([i915#2994]) [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb3/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@gem_ctx_isolation@preservation-s3@bcs0: - shard-tglb: [INCOMPLETE][108] ([i915#456]) -> [PASS][109] +1 similar issue [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-tglb7/igt@gem_ctx_isolation@preservation-s3@bcs0.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb1/igt@gem_ctx_isolation@preservation-s3@bcs0.html * igt@gem_eio@in-flight-contexts-immediate: - shard-tglb: [TIMEOUT][110] ([i915#3063]) -> [PASS][111] [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-tglb3/igt@gem_eio@in-flight-contexts-immediate.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb7/igt@gem_eio@in-flight-contexts-immediate.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [FAIL][112] ([i915#2842]) -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [FAIL][114] ([i915#2842]) -> [PASS][115] [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-glk: [FAIL][116] ([i915#2842]) -> [PASS][117] +1 similar issue [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-glk1/igt@gem_exec_fair@basic-pace@vcs0.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk1/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_mmap_wc@copy: - shard-skl: [DMESG-WARN][118] ([i915#1982]) -> [PASS][119] +1 similar issue [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl5/igt@gem_mmap_wc@copy.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl9/igt@gem_mmap_wc@copy.html * igt@i915_suspend@fence-restore-tiled2untiled: - shard-apl: [DMESG-WARN][120] ([i915#180]) -> [PASS][121] +2 similar issues [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html * igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2: - shard-glk: [FAIL][122] ([i915#2122]) -> [PASS][123] [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html * igt@kms_hdr@bpc-switch-suspend: - shard-kbl: [DMESG-WARN][124] ([i915#180]) -> [PASS][125] +2 similar issues [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: - shard-tglb: [INCOMPLETE][126] ([i915#4182]) -> [PASS][127] [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-tglb7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-tglb3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html * igt@kms_psr@psr2_primary_mmap_cpu: - shard-iclb: [SKIP][128] ([fdo#109441]) -> [PASS][129] +1 similar issue [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html #### Warnings #### * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][130] ([i915#1804] / [i915#2684]) -> [WARN][131] ([i915#2684]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip: - shard-skl: [FAIL][132] ([i915#3722]) -> [FAIL][133] ([i915#3743]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-skl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-skl5/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-3: - shard-iclb: [SKIP][134] ([i915#2920]) -> [SKIP][135] ([i915#658]) +1 similar issue [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-iclb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4: - shard-iclb: [SKIP][136] ([i915#658]) -> [SKIP][137] ([i915#2920]) +4 similar issues [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html * igt@runner@aborted: - shard-kbl: ([FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363]) -> ([FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3363] / [i915#602] / [i915#92]) [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10654/shard-kbl3/igt@runner@aborted.html [139]: https:/ == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21175/index.html [-- Attachment #2: Type: text/html, Size: 33610 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers 2021-09-27 19:23 [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo ` (2 preceding siblings ...) 2021-09-28 14:17 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2021-09-28 15:19 ` Harry Wentland 2021-09-30 21:21 ` Rodrigo Siqueira 2022-02-03 11:58 ` [Intel-gfx] binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) Jani Nikula 4 siblings, 1 reply; 10+ messages in thread From: Harry Wentland @ 2021-09-28 15:19 UTC (permalink / raw) To: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, jani.nikula Cc: Nicholas.Kazlauskas, wayne.lin On 2021-09-27 15:23, Fangzhi Zuo wrote: > Include FEC, DSC, Link Training related headers. > > Change since v2 > - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT > > Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Harry > --- > This patch is based on top of the other DP2.0 work in > "drm/dp: add LTTPR DP 2.0 DPCD addresses" > --- > include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > index 1d5b3dbb6e56..a1df35aa6e68 100644 > --- a/include/drm/drm_dp_helper.h > +++ b/include/drm/drm_dp_helper.h > @@ -453,6 +453,7 @@ struct drm_panel; > # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) > # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) > # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) > +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ > > /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ > #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ > @@ -537,6 +538,9 @@ struct drm_panel; > #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 > #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 > > +/* DFP Capability Extension */ > +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ > + > /* Link Configuration */ > #define DP_LINK_BW_SET 0x100 > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ > @@ -688,6 +692,7 @@ struct drm_panel; > > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ > # define DP_DECOMPRESSION_EN (1 << 0) > +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ > > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > # define DP_PSR_ENABLE BIT(0) > @@ -743,6 +748,7 @@ struct drm_panel; > # define DP_RECEIVE_PORT_0_STATUS (1 << 0) > # define DP_RECEIVE_PORT_1_STATUS (1 << 1) > # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ > +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ > > #define DP_ADJUST_REQUEST_LANE0_1 0x206 > #define DP_ADJUST_REQUEST_LANE2_3 0x207 > @@ -865,6 +871,8 @@ struct drm_panel; > # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 > # define DP_PHY_TEST_PATTERN_CP2520 0x5 > > +#define DP_PHY_SQUARE_PATTERN 0x249 > + > #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A > #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 > #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 > @@ -1109,6 +1117,18 @@ struct drm_panel; > #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ > # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f > > +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 > +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 > + > +/* DSC Extended Capability Branch Total DSC Resources */ > +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ > +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) > +# define DP_DSC_DECODER_COUNT_SHIFT 5 > +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ > +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 > + > /* Protocol Converter Extension */ > /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ > #define DP_CEC_TUNNELING_CAPABILITY 0x3000 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers 2021-09-28 15:19 ` [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Harry Wentland @ 2021-09-30 21:21 ` Rodrigo Siqueira 2021-10-08 8:36 ` Tvrtko Ursulin 0 siblings, 1 reply; 10+ messages in thread From: Rodrigo Siqueira @ 2021-09-30 21:21 UTC (permalink / raw) To: Harry Wentland Cc: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, jani.nikula, Nicholas.Kazlauskas, wayne.lin Applied to drm-misc-next. Thanks On 09/28, Harry Wentland wrote: > On 2021-09-27 15:23, Fangzhi Zuo wrote: > > Include FEC, DSC, Link Training related headers. > > > > Change since v2 > > - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT > > > > Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> > > Reviewed-by: Harry Wentland <harry.wentland@amd.com> > > Harry > > > --- > > This patch is based on top of the other DP2.0 work in > > "drm/dp: add LTTPR DP 2.0 DPCD addresses" > > --- > > include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++ > > 1 file changed, 20 insertions(+) > > > > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h > > index 1d5b3dbb6e56..a1df35aa6e68 100644 > > --- a/include/drm/drm_dp_helper.h > > +++ b/include/drm/drm_dp_helper.h > > @@ -453,6 +453,7 @@ struct drm_panel; > > # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) > > # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) > > # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) > > +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ > > > > /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ > > #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ > > @@ -537,6 +538,9 @@ struct drm_panel; > > #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 > > #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 > > > > +/* DFP Capability Extension */ > > +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ > > + > > /* Link Configuration */ > > #define DP_LINK_BW_SET 0x100 > > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ > > @@ -688,6 +692,7 @@ struct drm_panel; > > > > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ > > # define DP_DECOMPRESSION_EN (1 << 0) > > +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ > > > > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ > > # define DP_PSR_ENABLE BIT(0) > > @@ -743,6 +748,7 @@ struct drm_panel; > > # define DP_RECEIVE_PORT_0_STATUS (1 << 0) > > # define DP_RECEIVE_PORT_1_STATUS (1 << 1) > > # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ > > +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ > > > > #define DP_ADJUST_REQUEST_LANE0_1 0x206 > > #define DP_ADJUST_REQUEST_LANE2_3 0x207 > > @@ -865,6 +871,8 @@ struct drm_panel; > > # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 > > # define DP_PHY_TEST_PATTERN_CP2520 0x5 > > > > +#define DP_PHY_SQUARE_PATTERN 0x249 > > + > > #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A > > #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 > > #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 > > @@ -1109,6 +1117,18 @@ struct drm_panel; > > #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ > > # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f > > > > +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 > > +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 > > + > > +/* DSC Extended Capability Branch Total DSC Resources */ > > +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ > > +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) > > +# define DP_DSC_DECODER_COUNT_SHIFT 5 > > +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ > > +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) > > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) > > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 > > + > > /* Protocol Converter Extension */ > > /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ > > #define DP_CEC_TUNNELING_CAPABILITY 0x3000 > > > -- Rodrigo Siqueira https://siqueira.tech ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers 2021-09-30 21:21 ` Rodrigo Siqueira @ 2021-10-08 8:36 ` Tvrtko Ursulin 2021-10-08 21:03 ` Harry Wentland 0 siblings, 1 reply; 10+ messages in thread From: Tvrtko Ursulin @ 2021-10-08 8:36 UTC (permalink / raw) To: Rodrigo Siqueira, Harry Wentland Cc: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, jani.nikula, Nicholas.Kazlauskas, wayne.lin Hi, Is it my checkout only or this causes a lot of build warnings for everyone? ./include/drm/drm_dp_helper.h:1120: warning: "DP_TEST_264BIT_CUSTOM_PATTERN_7_0" redefined 1120 | #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 | In file included from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:35, from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30, from ./drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26, from drivers/gpu/drm/amd/amdgpu/amdgpu.h:66, from drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:40: ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:871: note: this is the location of the previous definition Etc.. Regards, Tvrtko On 30/09/2021 22:21, Rodrigo Siqueira wrote: > Applied to drm-misc-next. > > Thanks > > On 09/28, Harry Wentland wrote: >> On 2021-09-27 15:23, Fangzhi Zuo wrote: >>> Include FEC, DSC, Link Training related headers. >>> >>> Change since v2 >>> - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT >>> >>> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> >> >> Reviewed-by: Harry Wentland <harry.wentland@amd.com> >> >> Harry >> >>> --- >>> This patch is based on top of the other DP2.0 work in >>> "drm/dp: add LTTPR DP 2.0 DPCD addresses" >>> --- >>> include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++ >>> 1 file changed, 20 insertions(+) >>> >>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >>> index 1d5b3dbb6e56..a1df35aa6e68 100644 >>> --- a/include/drm/drm_dp_helper.h >>> +++ b/include/drm/drm_dp_helper.h >>> @@ -453,6 +453,7 @@ struct drm_panel; >>> # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) >>> # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) >>> # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) >>> +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ >>> >>> /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ >>> #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ >>> @@ -537,6 +538,9 @@ struct drm_panel; >>> #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 >>> #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 >>> >>> +/* DFP Capability Extension */ >>> +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ >>> + >>> /* Link Configuration */ >>> #define DP_LINK_BW_SET 0x100 >>> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ >>> @@ -688,6 +692,7 @@ struct drm_panel; >>> >>> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ >>> # define DP_DECOMPRESSION_EN (1 << 0) >>> +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ >>> >>> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ >>> # define DP_PSR_ENABLE BIT(0) >>> @@ -743,6 +748,7 @@ struct drm_panel; >>> # define DP_RECEIVE_PORT_0_STATUS (1 << 0) >>> # define DP_RECEIVE_PORT_1_STATUS (1 << 1) >>> # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ >>> +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ >>> >>> #define DP_ADJUST_REQUEST_LANE0_1 0x206 >>> #define DP_ADJUST_REQUEST_LANE2_3 0x207 >>> @@ -865,6 +871,8 @@ struct drm_panel; >>> # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 >>> # define DP_PHY_TEST_PATTERN_CP2520 0x5 >>> >>> +#define DP_PHY_SQUARE_PATTERN 0x249 >>> + >>> #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A >>> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 >>> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 >>> @@ -1109,6 +1117,18 @@ struct drm_panel; >>> #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ >>> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f >>> >>> +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 >>> +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 >>> + >>> +/* DSC Extended Capability Branch Total DSC Resources */ >>> +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ >>> +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) >>> +# define DP_DSC_DECODER_COUNT_SHIFT 5 >>> +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ >>> +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) >>> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) >>> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 >>> + >>> /* Protocol Converter Extension */ >>> /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ >>> #define DP_CEC_TUNNELING_CAPABILITY 0x3000 >>> >> > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers 2021-10-08 8:36 ` Tvrtko Ursulin @ 2021-10-08 21:03 ` Harry Wentland 0 siblings, 0 replies; 10+ messages in thread From: Harry Wentland @ 2021-10-08 21:03 UTC (permalink / raw) To: Tvrtko Ursulin, Rodrigo Siqueira Cc: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, jani.nikula, Nicholas.Kazlauskas, wayne.lin On 2021-10-08 04:36, Tvrtko Ursulin wrote: > > Hi, > > Is it my checkout only or this causes a lot of build warnings for everyone? > > ./include/drm/drm_dp_helper.h:1120: warning: "DP_TEST_264BIT_CUSTOM_PATTERN_7_0" redefined > 1120 | #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 > | > In file included from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:35, > from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30, > from ./drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26, > from drivers/gpu/drm/amd/amdgpu/amdgpu.h:66, > from drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:40: > ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:871: note: this is the location of the previous definition > > Etc.. > Fixed by https://patchwork.freedesktop.org/patch/456190/?series=95166&rev=2 but looks like it's not in drm-misc-next. Siqueira, do you have bandwidth to pull that patch into drm-misc-next? Harry > Regards, > > Tvrtko > > > On 30/09/2021 22:21, Rodrigo Siqueira wrote: >> Applied to drm-misc-next. >> >> Thanks >> >> On 09/28, Harry Wentland wrote: >>> On 2021-09-27 15:23, Fangzhi Zuo wrote: >>>> Include FEC, DSC, Link Training related headers. >>>> >>>> Change since v2 >>>> - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT >>>> >>>> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> >>> >>> Reviewed-by: Harry Wentland <harry.wentland@amd.com> >>> >>> Harry >>> >>>> --- >>>> This patch is based on top of the other DP2.0 work in >>>> "drm/dp: add LTTPR DP 2.0 DPCD addresses" >>>> --- >>>> include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++ >>>> 1 file changed, 20 insertions(+) >>>> >>>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h >>>> index 1d5b3dbb6e56..a1df35aa6e68 100644 >>>> --- a/include/drm/drm_dp_helper.h >>>> +++ b/include/drm/drm_dp_helper.h >>>> @@ -453,6 +453,7 @@ struct drm_panel; >>>> # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1) >>>> # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2) >>>> # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3) >>>> +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */ >>>> /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */ >>>> #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */ >>>> @@ -537,6 +538,9 @@ struct drm_panel; >>>> #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 >>>> #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 >>>> +/* DFP Capability Extension */ >>>> +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ >>>> + >>>> /* Link Configuration */ >>>> #define DP_LINK_BW_SET 0x100 >>>> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ >>>> @@ -688,6 +692,7 @@ struct drm_panel; >>>> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */ >>>> # define DP_DECOMPRESSION_EN (1 << 0) >>>> +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */ >>>> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ >>>> # define DP_PSR_ENABLE BIT(0) >>>> @@ -743,6 +748,7 @@ struct drm_panel; >>>> # define DP_RECEIVE_PORT_0_STATUS (1 << 0) >>>> # define DP_RECEIVE_PORT_1_STATUS (1 << 1) >>>> # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */ >>>> +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */ >>>> #define DP_ADJUST_REQUEST_LANE0_1 0x206 >>>> #define DP_ADJUST_REQUEST_LANE2_3 0x207 >>>> @@ -865,6 +871,8 @@ struct drm_panel; >>>> # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4 >>>> # define DP_PHY_TEST_PATTERN_CP2520 0x5 >>>> +#define DP_PHY_SQUARE_PATTERN 0x249 >>>> + >>>> #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A >>>> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 >>>> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 >>>> @@ -1109,6 +1117,18 @@ struct drm_panel; >>>> #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ >>>> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f >>>> +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230 >>>> +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250 >>>> + >>>> +/* DSC Extended Capability Branch Total DSC Resources */ >>>> +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ >>>> +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) >>>> +# define DP_DSC_DECODER_COUNT_SHIFT 5 >>>> +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ >>>> +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) >>>> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) >>>> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 >>>> + >>>> /* Protocol Converter Extension */ >>>> /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */ >>>> #define DP_CEC_TUNNELING_CAPABILITY 0x3000 >>>> >>> >> ^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) 2021-09-27 19:23 [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo ` (3 preceding siblings ...) 2021-09-28 15:19 ` [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Harry Wentland @ 2022-02-03 11:58 ` Jani Nikula 2022-02-03 12:57 ` Daniel Vetter 4 siblings, 1 reply; 10+ messages in thread From: Jani Nikula @ 2022-02-03 11:58 UTC (permalink / raw) To: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, harry.wentland Cc: Daniel Vetter, Fangzhi Zuo, Dave Airlie, Nicholas.Kazlauskas, wayne.lin On Mon, 27 Sep 2021, Fangzhi Zuo <Jerry.Zuo@amd.com> wrote: > +/* DSC Extended Capability Branch Total DSC Resources */ > +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ > +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) > +# define DP_DSC_DECODER_COUNT_SHIFT 5 > +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ > +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 The patch was merged a while back, but only now I noticed the use of binary constants, which in C is a GCC and Clang extension [1][2]. There are some instances in the kernel, but not a whole lot. Do we want to avoid or embrace them going forward? Or meh? BR, Jani. [1] https://gcc.gnu.org/onlinedocs/gcc/Binary-constants.html [2] https://clang.llvm.org/docs/LanguageExtensions.html#c-14-binary-literals -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) 2022-02-03 11:58 ` [Intel-gfx] binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) Jani Nikula @ 2022-02-03 12:57 ` Daniel Vetter 0 siblings, 0 replies; 10+ messages in thread From: Daniel Vetter @ 2022-02-03 12:57 UTC (permalink / raw) To: Jani Nikula Cc: Dave Airlie, intel-gfx, amd-gfx, Fangzhi Zuo, dri-devel, Wayne.Lin, harry.wentland, nicholas.kazlauskas On Thu, Feb 3, 2022 at 12:58 PM Jani Nikula <jani.nikula@intel.com> wrote: > > On Mon, 27 Sep 2021, Fangzhi Zuo <Jerry.Zuo@amd.com> wrote: > > +/* DSC Extended Capability Branch Total DSC Resources */ > > +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */ > > +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) > > +# define DP_DSC_DECODER_COUNT_SHIFT 5 > > +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */ > > +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) > > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) > > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 > > The patch was merged a while back, but only now I noticed the use of > binary constants, which in C is a GCC and Clang extension [1][2]. There > are some instances in the kernel, but not a whole lot. > > Do we want to avoid or embrace them going forward? Or meh? $ git grep '\<0b[01]*\>' Gives me almost exclusive hits in - .rst files - .S assembler files - comments and strings So I think probably not? I mean there's also BIT() and BIT_MASK() macros and stuff like that, and reading small masks is pretty simple. -Daniel > > > BR, > Jani. > > > [1] https://gcc.gnu.org/onlinedocs/gcc/Binary-constants.html > [2] https://clang.llvm.org/docs/LanguageExtensions.html#c-14-binary-literals > > -- > Jani Nikula, Intel Open Source Graphics Center -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-02-03 12:57 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-09-27 19:23 [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo 2021-09-28 12:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp: Add Additional DP2 Headers (rev3) Patchwork 2021-09-28 12:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-09-28 14:17 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-09-28 15:19 ` [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers Harry Wentland 2021-09-30 21:21 ` Rodrigo Siqueira 2021-10-08 8:36 ` Tvrtko Ursulin 2021-10-08 21:03 ` Harry Wentland 2022-02-03 11:58 ` [Intel-gfx] binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) Jani Nikula 2022-02-03 12:57 ` Daniel Vetter
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