From: Chris Wilson <chris@chris-wilson.co.uk>
To: Alexey Fisher <bug-track@fisher-privat.net>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT
Date: Thu, 30 Dec 2010 18:06:20 +0000 [thread overview]
Message-ID: <b9dded$hh573p@orsmga002.jf.intel.com> (raw)
In-Reply-To: <1293708204.6744.2.camel@zwerg>
Ok, understood my mistake, that line was indeed incorrect.
Thanks,
-Chris
commit dc3bfebcf77d943b7e8495d30d0ee3d01b3042a5
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Dec 30 18:02:21 2010 +0000
drm/i915: Don't skip ring flushes if only invalidating
Commit 15056d2 tried to optimize away a flush if there were no
outstanding writes on a ring (in order to prevent a too-early-flush
during ring init). However, this has the unfortunate side-effect of
eliminating the texture cache invalidation, and so causing rendering
artefacts.
Reported-by: Alexey Fisher <bug-track@fisher-privat.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
--
Chris Wilson, Intel Open Source Technology Centre
prev parent reply other threads:[~2010-12-30 18:06 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-30 9:36 [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT Alexey Fisher
2010-12-30 9:51 ` Chris Wilson
2010-12-30 10:09 ` Alexey Fisher
2010-12-30 10:31 ` Chris Wilson
2010-12-30 11:23 ` Alexey Fisher
2010-12-30 18:06 ` Chris Wilson [this message]
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