* [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT
@ 2010-12-30 9:36 Alexey Fisher
2010-12-30 9:51 ` Chris Wilson
0 siblings, 1 reply; 6+ messages in thread
From: Alexey Fisher @ 2010-12-30 9:36 UTC (permalink / raw)
To: intel-gfx
Hi,
after this patch i get some rendering issues on my Intel DG45ID board,
(Vendor: 0x8086, Device: 0x2e22, Revision: 0x03 (A3))
removing this lines fix it:
diff --git a/drivers/gpu/drm/i915/i915_gem.c
b/drivers/gpu/drm/i915/i915_gem.c
index cecaa07..3a12cbf 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2148,8 +2148,8 @@ i915_gem_flush_ring(struct drm_device *dev,
uint32_t invalidate_domains,
uint32_t flush_domains)
{
- if (list_empty(&ring->gpu_write_list))
- return;
+// if (list_empty(&ring->gpu_write_list))
+// return;
ring->flush(ring, invalidate_domains, flush_domains);
i915_gem_process_flushing_list(dev, flush_domains, ring);
commit 15056d2c06862627ead868e035fcacc59dce1b1a
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Tue Dec 21 17:04:23 2010 +0000
drm/i915: Flush pending writes on i830/i845 after updating GTT
There is an erratum on these two chipsets that causes the wrong PTE
entries to be invalidate after updating the GTT and when used from the
BLT engine. The workaround is to flush any pending writes before those
PTEs are used by the BLT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
--
Regards,
Alexey
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT
2010-12-30 9:36 [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT Alexey Fisher
@ 2010-12-30 9:51 ` Chris Wilson
2010-12-30 10:09 ` Alexey Fisher
0 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2010-12-30 9:51 UTC (permalink / raw)
To: Alexey Fisher, intel-gfx
On Thu, 30 Dec 2010 10:36:35 +0100, Alexey Fisher <bug-track@fisher-privat.net> wrote:
> Hi,
> after this patch i get some rendering issues on my Intel DG45ID board,
> (Vendor: 0x8086, Device: 0x2e22, Revision: 0x03 (A3))
I need a few more details on the nature of the rendering issue and
driver versions.
The idea is to skip the flush in case we have nothing to flush (this is
required to avoid the too-early-flush during initialisation of the ring
buffer). Finding the circumstances of the flush that causes the issue
should help determine the root cause of the bug.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT
2010-12-30 9:51 ` Chris Wilson
@ 2010-12-30 10:09 ` Alexey Fisher
2010-12-30 10:31 ` Chris Wilson
0 siblings, 1 reply; 6+ messages in thread
From: Alexey Fisher @ 2010-12-30 10:09 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 1050 bytes --]
Am Donnerstag, den 30.12.2010, 09:51 +0000 schrieb Chris Wilson:
> On Thu, 30 Dec 2010 10:36:35 +0100, Alexey Fisher <bug-track@fisher-privat.net> wrote:
> > Hi,
> > after this patch i get some rendering issues on my Intel DG45ID board,
> > (Vendor: 0x8086, Device: 0x2e22, Revision: 0x03 (A3))
>
> I need a few more details on the nature of the rendering issue and
> driver versions.
>
> The idea is to skip the flush in case we have nothing to flush (this is
> required to avoid the too-early-flush during initialisation of the ring
> buffer). Finding the circumstances of the flush that causes the issue
> should help determine the root cause of the bug.
> -Chris
apt-cache policy xserver-xorg-video-intel
xserver-xorg-video-intel:
Installiert: 2:2.13.902+git20101227.7667ad84-0ubuntu0sarvatt~maverick
apt-cache policy xserver-xorg
xserver-xorg:
Installiert: 1:7.5+6+xserver1.9
uname -a
Linux zwerg 2.6.37-rc7-02332-g608ca70 #114 SMP Wed Dec 29 13:30:12 CET
2010 x86_64 GNU/Linux
The screencast is attached.
--
Regards,
Alexey
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[-- Type: video/ogg, Size: 1329488 bytes --]
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT
2010-12-30 10:09 ` Alexey Fisher
@ 2010-12-30 10:31 ` Chris Wilson
2010-12-30 11:23 ` Alexey Fisher
0 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2010-12-30 10:31 UTC (permalink / raw)
To: Alexey Fisher; +Cc: intel-gfx
On Thu, 30 Dec 2010 11:09:56 +0100, Alexey Fisher <bug-track@fisher-privat.net> wrote:
> The screencast is attached.
Yeah, definitely looks like a missing RenderCache flush. Is compiz part of
the critical path?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT
2010-12-30 10:31 ` Chris Wilson
@ 2010-12-30 11:23 ` Alexey Fisher
2010-12-30 18:06 ` Chris Wilson
0 siblings, 1 reply; 6+ messages in thread
From: Alexey Fisher @ 2010-12-30 11:23 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Am Donnerstag, den 30.12.2010, 10:31 +0000 schrieb Chris Wilson:
> On Thu, 30 Dec 2010 11:09:56 +0100, Alexey Fisher <bug-track@fisher-privat.net> wrote:
> > The screencast is attached.
>
> Yeah, definitely looks like a missing RenderCache flush. Is compiz part of
> the critical path?
> -Chris
No. I get same issue without compiz too. Some gtk programs get
destruction too.
--
Regards,
Alexey
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT
2010-12-30 11:23 ` Alexey Fisher
@ 2010-12-30 18:06 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2010-12-30 18:06 UTC (permalink / raw)
To: Alexey Fisher; +Cc: intel-gfx
Ok, understood my mistake, that line was indeed incorrect.
Thanks,
-Chris
commit dc3bfebcf77d943b7e8495d30d0ee3d01b3042a5
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu Dec 30 18:02:21 2010 +0000
drm/i915: Don't skip ring flushes if only invalidating
Commit 15056d2 tried to optimize away a flush if there were no
outstanding writes on a ring (in order to prevent a too-early-flush
during ring init). However, this has the unfortunate side-effect of
eliminating the texture cache invalidation, and so causing rendering
artefacts.
Reported-by: Alexey Fisher <bug-track@fisher-privat.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
--
Chris Wilson, Intel Open Source Technology Centre
^ permalink raw reply [flat|nested] 6+ messages in thread
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2010-12-30 9:36 [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT Alexey Fisher
2010-12-30 9:51 ` Chris Wilson
2010-12-30 10:09 ` Alexey Fisher
2010-12-30 10:31 ` Chris Wilson
2010-12-30 11:23 ` Alexey Fisher
2010-12-30 18:06 ` Chris Wilson
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