From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Cc: Eugeni Dodonov <eugeni.dodonov@intel.com>
Subject: Re: [PATCH 07/37] drm/i915: add DP_TP_CTL registers
Date: Thu, 22 Mar 2012 10:43:57 +0000 [thread overview]
Message-ID: <c55c5d$2ck5cd@AZSMGA002.ch.intel.com> (raw)
In-Reply-To: <1332378612-3814-8-git-send-email-eugeni.dodonov@intel.com>
On Wed, 21 Mar 2012 22:09:42 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> This is one set of those registers for each pipe.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 09b2267..7a9232e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3890,4 +3890,20 @@
> #define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
> #define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
>
> +/* DisplayPort Transport Control */
> +#define DP_TP_CTL_A 0x64040
> +#define DP_TP_CTL_B 0x64140
> +#define DP_TP_CTL_C 0x64240
> +#define DP_TP_CTL_D 0x64340
> +#define DP_TP_CTL_E 0x64440
> +#define DP_TP_CTL_ENABLE (1<<31)
> +#define DP_TP_CTL_MODE_SST (0<<27)
> +#define DP_TP_CTL_MODE_MST (1<<27)
> +#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
> +#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
> +#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
> +#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
> +#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
> +#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
Would these not benefit from a #define DP_TP_CTL(pipe)?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-03-22 10:44 UTC|newest]
Thread overview: 95+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-22 1:09 [RFC] [PATCH 00/38] Haswell Eugeni Dodonov
2012-03-22 1:09 ` [PATCH 01/37] drm/i915: add Haswell devices and their PCI IDs Eugeni Dodonov
2012-03-22 9:57 ` Daniel Vetter
2012-03-22 1:09 ` [PATCH 02/37] drm/i915: add support for LynxPoint PCH Eugeni Dodonov
2012-03-26 18:58 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 03/37] drm/i915: add HAS_PLL_SPLIT macro Eugeni Dodonov
2012-03-22 10:06 ` Daniel Vetter
2012-03-22 1:09 ` [PATCH 04/37] drm/i915: add haswell into the PCH SPLIT company Eugeni Dodonov
2012-03-22 9:59 ` Daniel Vetter
2012-03-22 1:09 ` [PATCH 05/37] drm/i915: add support for power wells Eugeni Dodonov
2012-03-26 17:32 ` Rodrigo Vivi
2012-03-26 17:58 ` Eugeni Dodonov
2012-03-22 1:09 ` [PATCH 06/37] drm/i915: add DDI registers Eugeni Dodonov
2012-03-26 17:35 ` Rodrigo Vivi
2012-03-26 17:58 ` Eugeni Dodonov
2012-03-26 18:01 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 07/37] drm/i915: add DP_TP_CTL registers Eugeni Dodonov
2012-03-22 10:43 ` Chris Wilson [this message]
2012-03-22 12:18 ` Eugeni Dodonov
2012-03-22 12:28 ` Daniel Vetter
2012-03-22 1:09 ` [PATCH 08/37] drm/i915: add DP_TP_STATUS registers Eugeni Dodonov
2012-03-22 10:47 ` Chris Wilson
2012-03-22 1:09 ` [PATCH 09/37] drm/i915: add definitions for DDI_BUF_CTL registers Eugeni Dodonov
2012-03-26 17:36 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 10/37] drm/i915: add definition of LPT FDI port width registers Eugeni Dodonov
2012-03-26 18:31 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 11/37] drm/i915: add definition of DDI buffer translations regs Eugeni Dodonov
2012-03-26 17:46 ` Rodrigo Vivi
2012-03-27 13:37 ` Daniel Vetter
2012-03-22 1:09 ` [PATCH 12/37] drm/i915: add SBI registers Eugeni Dodonov
2012-03-26 17:40 ` Rodrigo Vivi
2012-03-26 17:48 ` Rodrigo Vivi
2012-03-26 17:56 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 13/37] drm/i915: add support for SBI ops Eugeni Dodonov
2012-03-22 10:09 ` Daniel Vetter
2012-03-22 10:49 ` Chris Wilson
2012-03-22 1:09 ` [PATCH 14/37] drm/i915: add PIXCLK_GATE register Eugeni Dodonov
2012-03-26 17:39 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 15/37] drm/i915: add S PLL control Eugeni Dodonov
2012-03-26 17:41 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 16/37] drm/i915: add port clock selection support for HSW Eugeni Dodonov
2012-03-26 17:39 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 17/37] drm/i915: add SSC offsets for SBI access Eugeni Dodonov
2012-03-26 17:40 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 18/37] drm/i915: add GTC registers Eugeni Dodonov
2012-03-22 10:51 ` Chris Wilson
2012-03-26 17:45 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 19/37] drm/i915: add LCPLL control registers Eugeni Dodonov
2012-03-26 17:42 ` Rodrigo Vivi
2012-03-26 17:46 ` Daniel Vetter
2012-03-26 17:53 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 20/37] drm/i915: add WM_LINETIME registers Eugeni Dodonov
2012-03-26 17:40 ` Rodrigo Vivi
2012-03-22 1:09 ` [PATCH 21/37] drm/i915: calculate watermarks on Gen7 archs in one place Eugeni Dodonov
2012-03-22 10:52 ` Chris Wilson
2012-03-22 11:13 ` Daniel Vetter
2012-03-22 1:09 ` [PATCH 22/37] drm/i915: program WM_LINETIME on Haswell Eugeni Dodonov
2012-03-22 10:58 ` Chris Wilson
2012-03-22 1:09 ` [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell Eugeni Dodonov
2012-03-22 10:16 ` Daniel Vetter
2012-03-22 12:14 ` Eugeni Dodonov
2012-03-22 1:09 ` [PATCH 24/37] drm/i915: share forcewaking code between IVB and HSW Eugeni Dodonov
2012-03-26 17:56 ` Rodrigo Vivi
2012-03-22 1:10 ` [PATCH 25/37] drm/i915: haswell has 3 pipes as well Eugeni Dodonov
2012-03-26 17:50 ` Rodrigo Vivi
2012-03-22 1:10 ` [PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell Eugeni Dodonov
2012-03-22 10:22 ` Daniel Vetter
2012-03-22 12:16 ` Eugeni Dodonov
2012-03-22 1:10 ` [PATCH 27/37] drm/i915: share pipe count handling with Ivybridge Eugeni Dodonov
2012-03-26 17:50 ` Rodrigo Vivi
2012-03-22 1:10 ` [PATCH 28/37] drm/i915: share IVB cursor routine with Haswell Eugeni Dodonov
2012-03-26 17:52 ` Rodrigo Vivi
2012-03-22 1:10 ` [PATCH 29/37] drm/i915: enable power wells on haswell init Eugeni Dodonov
2012-03-22 11:03 ` Chris Wilson
2012-03-22 1:10 ` [PATCH 30/37] drm/i915: disable rc6 on haswell for now Eugeni Dodonov
2012-03-26 17:53 ` Rodrigo Vivi
2012-03-22 1:10 ` [PATCH 31/37] drm/i915: enable PCH earlier Eugeni Dodonov
2012-03-22 11:05 ` Chris Wilson
2012-03-28 19:32 ` Jesse Barnes
2012-03-28 19:52 ` Eugeni Dodonov
2012-03-22 1:10 ` [PATCH 32/37] drm/i915: perform Haswell DDI link training in FDI mode Eugeni Dodonov
2012-03-26 17:49 ` Rodrigo Vivi
2012-03-22 1:10 ` [PATCH 33/37] drm/i915: double-write DDI translation table Eugeni Dodonov
2012-03-26 17:51 ` Rodrigo Vivi
2012-03-22 1:10 ` [PATCH 34/37] drm/i915: do not use fdi_normal_train on haswell Eugeni Dodonov
2012-03-26 17:50 ` Rodrigo Vivi
2012-03-22 1:10 ` [PATCH 35/37] drm/i915: program iCLKIP on Lynx Point Eugeni Dodonov
2012-03-22 10:31 ` Daniel Vetter
2012-03-26 18:00 ` Rodrigo Vivi
2012-03-28 18:46 ` Jesse Barnes
2012-03-22 1:10 ` [PATCH 36/37] drm/i915: add warning when using old bits on Haswell/LPT Eugeni Dodonov
2012-03-26 17:49 ` Rodrigo Vivi
2012-03-22 1:10 ` [PATCH 37/37] drm/i915: dump registers read/write ops Eugeni Dodonov
2012-03-22 11:15 ` Chris Wilson
2012-03-22 10:50 ` [RFC] [PATCH 00/38] Haswell Daniel Vetter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='c55c5d$2ck5cd@AZSMGA002.ch.intel.com' \
--to=chris@chris-wilson.co.uk \
--cc=eugeni.dodonov@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox