Re: [PATCH 29/37] drm/i915: enable power wells on haswell init

[Chris Wilson <chris@chris-wilson.co.uk>]

On Wed, 21 Mar 2012 22:10:04 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> This attempts to enable all the available power wells during the
> initialization.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3b3dc15..2c5b953 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9142,6 +9142,34 @@ static void i915_disable_vga(struct drm_device *dev)
>  	POSTING_READ(vga_reg);
>  }
>  
> +/* Starting with Haswell, we have different power wells for
> + * different parts of the GPU. This attempts to enable them all.
> + */
> +static void intel_init_power_wells(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long power_wells[] = {
> +		HSW_PWR_WELL_CTL1,
> +		HSW_PWR_WELL_CTL2,
> +		HSW_PWR_WELL_CTL4
> +	};
> +	int i;
> +
> +	mutex_lock(&dev->struct_mutex);
> +
> +	for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
> +		int well = I915_READ(power_wells[i]);
> +
> +		if ((well & HSW_PWR_WELL_STATE) == 0) {
> +			I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
> +			if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
> +				DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
> +		}
> +	}

Out of curiosity, can we enable the powerwells in parallel or must it be
done sequentially?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre