[PATCH v4 00/12] Add support for Common SDP Transmission Line

[PATCH v4 00/12] Add support for Common SDP Transmission Line

[Ankit Nautiyal]

Xe3p_lpd introduces new register bits to program a common SDP
Transmission line that will be used by the Hardware to position the
SDPs. Along with this, another new register is also added to stagger
the different SDPs.

This series adds support for programming the Common SDP Transmission Line
(CMN_SDP_TL) and its stagger control registers.

Rev2:
 - Add tracking for AS SDP Transmission line first. Instead of directly
   programming it in the register, compute the state during
   compute_config_late() and write the value from crtc_state.
   Readout from the register through a vrr helper, since the register is
   defined in context of VRR and will be used for both DP and HDMI VRR
   packets.
 - Add support to track other SDP transmission lines, instead of stagger
   values.
 - Compute the transmission lines in compute_config_late path and add
   readout.
 - Always write the Common SDP Transmission line and other stagger
   values, whether the packets are sent or not.
 - Dump SDP transmission lines in crtc_state.

Rev3:
 - Introduce new files for handling the Data Island Packets (DIPs)
   programming in one place. (Ville)
 - Extract the Transmission Line programming for
   HDMI Extended Metadata Packet (EMP) and Adaptive Sync SDP (AS SDP)
   i.e. EMP_AS_SDP_TL in the new file.
 - Add programming for Common Base SDP Transmission lines and other
   stagger offsets in the new file.
 - Add a #TODO to extract other helpers that deal with Data Island Packets
   and VIDEO_DIP registers.
 - Place the HAS_* Macros related to DIP in the intel_dip.h file
   instead of intel_display_devices.h (Jani) 
 - Make function names more descriptive and avoid overuse of multiple
   acronyms. (Jani)

Note:
 - Though I have fixed the naming as suggested in most places, I
   have retained HAS_EMP_AS_SDP_TL for the following reasons:
   1) Lack of an apt name that avoids the acronym for
      'Extended Metadata Packet Adaptive Sync Secondary Packet Transmission
      Line'.
   2) Keeping this name makes it easier to find and map with the exact name
      for such a complex register name.

   However, I am open to suggestions for a better name.

Rev4:
 - Drop the patch to check for DP encoder before writing EMP_AS_SDP_TL
   register. Instead reset the register to 0 for non DP encoder case.

Ankit Nautiyal (11):
  drm/i915/dip: Add new file to handle Data Island Packet hardware
  drm/i915/vrr: Use the helper to write EMP_AS_SDP_TL register
  drm/i915/intel_dip: Add check for DP encoder
  drm/i915/dp: Add helper to get AS SDP Transmission Line
  drm/i915/display: Add crtc state for DIP transmission lines
  drm/i915/dip: Store and use AS SDP transmission line from crtc state
  drm/i915/display: Add HAS_COMMON_SDP_TL macro
  drm/i915/dp: Store SDP transmission lines in crtc_state
  drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission
    line
  drm/i915/dip: Enable Common SDP Transmission line
  drm/i915/display: Dump DIP Transmission lines

Arun R Murthy (1):
  drm/i915/nvl: Add register definitions for common SDP Transmission
    Line

 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../drm/i915/display/intel_crtc_state_dump.c  |   9 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |   5 +
 drivers/gpu/drm/i915/display/intel_dip.c      | 193 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dip.h      |  67 ++++++
 drivers/gpu/drm/i915/display/intel_dip_regs.h |  36 ++++
 drivers/gpu/drm/i915/display/intel_display.c  |   7 +
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  23 +++
 drivers/gpu/drm/i915/display/intel_dp.h       |   1 +
 drivers/gpu/drm/i915/display/intel_vrr.c      |  13 +-
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |   6 -
 drivers/gpu/drm/xe/Makefile                   |   1 +
 13 files changed, 348 insertions(+), 17 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip_regs.h

-- 
2.45.2

[PATCH v4 01/12] drm/i915/dip: Add new file to handle Data Island Packet hardware

[Ankit Nautiyal]

Add new files intel_dip.c, intel_dip.h, and intel_dip_regs.h to handle
low level hardware programming related to Data Island Packets.

Currently only programming of the Transmission Line for HDMI 2.1
Extended Metadata Packet (EMP) and DP Adaptive-Sync Secondary Data
Packet (SDP) is added (MMIO register EMP_AS_SDP_TL).

This will serve as a common place for DIP related code, which is currently
scattered across DP and HDMI files. A TODO has been added for extracting
the remaining DIP helpers.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |  1 +
 drivers/gpu/drm/i915/display/intel_dip.c      | 39 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dip.h      | 38 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dip_regs.h | 17 ++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      |  1 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  6 ---
 drivers/gpu/drm/xe/Makefile                   |  1 +
 7 files changed, 97 insertions(+), 6 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_dip_regs.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 07802a7f4ce5..04624d35447c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -349,6 +349,7 @@ i915-y += \
 	display/intel_cx0_phy.o \
 	display/intel_ddi.o \
 	display/intel_ddi_buf_trans.o \
+	display/intel_dip.o \
 	display/intel_display_device.o \
 	display/intel_display_trace.o \
 	display/intel_dkl_phy.o \
diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
new file mode 100644
index 000000000000..2e2bdb2b199c
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ *
+ */
+
+#include "intel_de.h"
+#include "intel_dip.h"
+#include "intel_dip_regs.h"
+#include "intel_display_types.h"
+
+u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 val;
+
+	if (!HAS_EMP_AS_SDP_TL(display))
+		return 0;
+
+	val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
+	return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val);
+}
+
+void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+	if (!HAS_EMP_AS_SDP_TL(display))
+		return;
+	/*
+	 * Since currently we support VRR only for DP/eDP, so this is programmed
+	 * only for Adaptive Sync SDP to Vsync start.
+	 */
+	intel_de_write(display,
+		       EMP_AS_SDP_TL(display, cpu_transcoder),
+		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
new file mode 100644
index 000000000000..25bae4a04d6b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __INTEL_DIP_H__
+#define __INTEL_DIP_H__
+
+#include "intel_display_device.h"
+
+/*
+ * Video DIP (Data Island Packet) helpers.
+ *
+ * This file contains helpers for programming video DIP related hardware.
+ *
+ * TODO: Currently, this is only used for programming EMP_AS_SDP_TL i.e. to
+ * program Transmission Line for HDMI 2.1 Extended Metadata Packet (EMP) and
+ * DP Adaptive Sync (AS) Secondary Data Packet (SDP). However, all low level
+ * DIP buffer read/write and related helpers should be extracted here later.
+ */
+
+struct intel_crtc_state;
+
+/*
+ * EMP AS SDP TL: Extended Metadata Packet (EMP) Adaptive Sync (AS)
+ * Secondary Data Packet (SDP) Transmission Line (TL).
+ *
+ * Starting with BMG (display ver 14.01) and LNL+ (display ver 20+),
+ * the AS SDP transmission line is programmable via the EMP AS SDP TL
+ * register.
+ */
+#define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || \
+					 DISPLAY_VER(__display) >= 20)
+
+u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
+void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
+
+#endif /* __INTEL_DIP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dip_regs.h b/drivers/gpu/drm/i915/display/intel_dip_regs.h
new file mode 100644
index 000000000000..85dcbf42e77d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dip_regs.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef __INTEL_DIP_REGS_H__
+#define __INTEL_DIP_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/* EMP (Extended Metadata Packet) AS (Adaptive Sync) SDP Transmission Line */
+#define _EMP_AS_SDP_TL_A			0x60204
+#define EMP_AS_SDP_TL(display, trans)		_MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)
+#define   EMP_AS_SDP_DB_TL_MASK			REG_GENMASK(12, 0)
+#define   EMP_AS_SDP_DB_TL(db_transmit_line)	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
+
+#endif /* __INTEL_DIP_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index e03b5daac5be..6130854a706c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "intel_alpm.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
+#include "intel_dip_regs.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_dmc.h"
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 9d4d6573a149..ba8631cbc672 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -174,12 +174,6 @@
 #define   VRR_VSYNC_START_MASK			REG_GENMASK(12, 0)
 #define   VRR_VSYNC_START(vsync_start)		REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
 
-/* Common register for HDMI EMP and DP AS SDP */
-#define _EMP_AS_SDP_TL_A			0x60204
-#define EMP_AS_SDP_TL(display, trans)		_MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)
-#define   EMP_AS_SDP_DB_TL_MASK			REG_GENMASK(12, 0)
-#define   EMP_AS_SDP_DB_TL(db_transmit_line)	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
-
 #define _TRANS_CMRR_M_LO_A			0x604F0
 #define TRANS_CMRR_M_LO(display, trans)		_MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A)
 
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 09661f079d03..9e826d164951 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -256,6 +256,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_ddi.o \
 	i915-display/intel_ddi_buf_trans.o \
 	i915-display/intel_de.o \
+	i915-display/intel_dip.o \
 	i915-display/intel_display.o \
 	i915-display/intel_display_conversion.o \
 	i915-display/intel_display_device.o \
-- 
2.45.2

[PATCH v4 02/12] drm/i915/vrr: Use the helper to write EMP_AS_SDP_TL register

[Ankit Nautiyal]

Now that intel_dip_write_emp_as_sdp_tl() exists, use it instead of
the open-coded EMP_AS_SDP_TL programming sequence in
intel_vrr_set_transcoder_timings().

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++------------
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 6130854a706c..a3dfeaa12e8b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,7 +9,7 @@
 #include "intel_alpm.h"
 #include "intel_crtc.h"
 #include "intel_de.h"
-#include "intel_dip_regs.h"
+#include "intel_dip.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
 #include "intel_dmc.h"
@@ -658,17 +658,7 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
 			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
 
-	/*
-	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for programming
-	 * double buffering point and transmission line for VRR packets for
-	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
-	 * Since currently we support VRR only for DP/eDP, so this is programmed
-	 * to for Adaptive Sync SDP to Vsync start.
-	 */
-	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
-		intel_de_write(display,
-			       EMP_AS_SDP_TL(display, cpu_transcoder),
-			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+	intel_dip_write_emp_as_sdp_tl(crtc_state);
 }
 
 void
-- 
2.45.2

[PATCH v4 03/12] drm/i915/intel_dip: Add check for DP encoder

[Ankit Nautiyal]

At the moment, the common register for programming Transmission line for
Extended Metadata Packet and Adaptive-Sync Secondary Data Packet
(EMP_AS_SDP_TL) is only used to program Adaptive-Sync SDP (AS SDP).

Since VRR and Video Timing Extended Metadat Packet (VTEMP) are not yet
implemented for HDMI, add an explicit check to write the register only
for DP encoders (that may use AS SDP) and reset the register for non-DP
encoders.

In subsequent changes, instead of directly writing the value,
appropriate helpers will be called, that will supply the transmission line
for these packets.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index 2e2bdb2b199c..450a599b5053 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -26,14 +26,19 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u32 transmission_line = 0;
 
 	if (!HAS_EMP_AS_SDP_TL(display))
 		return;
 	/*
-	 * Since currently we support VRR only for DP/eDP, so this is programmed
-	 * only for Adaptive Sync SDP to Vsync start.
+	 * Since currently we support VRR only for DP/eDP, program the register
+	 * for Adaptive Sync SDP using vsync start. For non-DP encoders,
+	 * the register is reset to 0.
 	 */
+	if (intel_crtc_has_dp_encoder(crtc_state))
+		transmission_line = crtc_state->vrr.vsync_start;
+
 	intel_de_write(display,
 		       EMP_AS_SDP_TL(display, cpu_transcoder),
-		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
+		       EMP_AS_SDP_DB_TL(transmission_line));
 }
-- 
2.45.2

[PATCH v4 04/12] drm/i915/dp: Add helper to get AS SDP Transmission Line

[Ankit Nautiyal]

Introduce a DP helper to compute the Adaptive Sync SDP transmission line
and use it when programming the EMP_AS_SDP_TL register.

Currently the AS SDP transmission line is programmed to the T1 position.
This can be extended in the future to support programming the T2 position
as well.

While at it, improve the documentation: the AS SDP transmission line
corresponds to the T1 position, which maps to the start of the VSYNC
pulse.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.c |  7 ++++---
 drivers/gpu/drm/i915/display/intel_dp.c  | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_dp.h  |  1 +
 3 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index 450a599b5053..504a2edadd0e 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -8,6 +8,7 @@
 #include "intel_dip.h"
 #include "intel_dip_regs.h"
 #include "intel_display_types.h"
+#include "intel_dp.h"
 
 u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 {
@@ -32,11 +33,11 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 		return;
 	/*
 	 * Since currently we support VRR only for DP/eDP, program the register
-	 * for Adaptive Sync SDP using vsync start. For non-DP encoders,
-	 * the register is reset to 0.
+	 * for Adaptive Sync SDP. For non-DP encoders, the register is reset
+	 * to 0.
 	 */
 	if (intel_crtc_has_dp_encoder(crtc_state))
-		transmission_line = crtc_state->vrr.vsync_start;
+		transmission_line = intel_dp_get_as_sdp_transmission_line(crtc_state);
 
 	intel_de_write(display,
 		       EMP_AS_SDP_TL(display, cpu_transcoder),
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3569e61e7fee..f54f7faf878f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7465,3 +7465,15 @@ void intel_dp_link_cleanup(struct intel_dp *intel_dp)
 {
 	intel_dp_link_training_cleanup(intel_dp->link.training);
 }
+
+int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
+	 * Transmission Line, which corresponds to the start of the
+	 * VSYNC pulse.
+	 *
+	 * Use the T1 position for now.
+	 */
+	return crtc_state->vrr.vsync_start;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 92ce04852326..fc80b5b64785 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -238,6 +238,7 @@ bool intel_dp_joiner_candidate_valid(struct intel_connector *connector,
 		for_each_if(intel_dp_joiner_candidate_valid(__connector, (__mode)->hdisplay, __num_joined_pipes))
 
 u8 intel_dp_as_sdp_transmission_time(void);
+int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state *crtc_state);
 
 int intel_dp_link_init(struct intel_dp *intel_dp);
 void intel_dp_link_cleanup(struct intel_dp *intel_dp);
-- 
2.45.2

[PATCH v4 05/12] drm/i915/display: Add crtc state for DIP transmission lines

[Ankit Nautiyal]

The Adaptive Sync SDP is currently the only packet with a programmable
transmission line.

Make a structure struct intel_dip for Data Island Packets. Add a member to
track Adaptive-Sync SDP transmission line. Include the new member in the
pipe configuration comparison.

This will pave the way for supporting more packets' programmable
transmission lines, including the common base SDP transmission line
introduced with Xe3p_lpd.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.h           | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_display.c       | 2 ++
 drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
 3 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
index 25bae4a04d6b..37507ac3e645 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.h
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -35,4 +35,12 @@ struct intel_crtc_state;
 u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 
+struct intel_dip {
+	/*
+	 * DIP Transmission line, relative to the Vtotal.
+	 * The programmed transmit line is (Vtotal - value)
+	 */
+	u16 emp_as_sdp_tl;
+};
+
 #endif /* __INTEL_DIP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bdf02b67c1d8..c84ee0e865ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5507,6 +5507,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 
 	PIPE_CONF_CHECK_I(set_context_latency);
 
+	PIPE_CONF_CHECK_I(dip.emp_as_sdp_tl);
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_LLI
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index aa4772a1c208..6cc3a4c2f17c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -46,6 +46,7 @@
 
 #include "i915_gtt_view_types.h"
 #include "intel_bios.h"
+#include "intel_dip.h"
 #include "intel_display.h"
 #include "intel_display_conversion.h"
 #include "intel_display_limits.h"
@@ -1301,6 +1302,8 @@ struct intel_crtc_state {
 		struct drm_dp_as_sdp as_sdp;
 	} infoframes;
 
+	struct intel_dip dip;
+
 	u8 eld[MAX_ELD_BYTES];
 
 	/* HDMI scrambling status */
-- 
2.45.2

[PATCH v4 06/12] drm/i915/dip: Store and use AS SDP transmission line from crtc state

[Ankit Nautiyal]

The driver currently computes the Adaptive Sync SDP transmission line
directly at programming time. Instead, compute and store the
AS SDP transmission line in the crtc state and use it when programming the
EMP_AS_SDP_TL register.

We get the clear picture about the SDPs and guardband only in
intel_dp_sdp_compute_config_late() therefore we must configure the
AS SDP transmission line at this point when AS SDP is enabled in
crtc_state.

This prepares the ground for supporting programmable transmission lines
for additional DP SDPs.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  2 ++
 drivers/gpu/drm/i915/display/intel_dip.c | 20 +++++++++++---------
 drivers/gpu/drm/i915/display/intel_dip.h |  3 +++
 drivers/gpu/drm/i915/display/intel_dp.c  | 11 +++++++++++
 4 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 6399b16405c8..d2edfad295d5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -49,6 +49,7 @@
 #include "intel_ddi.h"
 #include "intel_ddi_buf_trans.h"
 #include "intel_de.h"
+#include "intel_dip.h"
 #include "intel_display_power.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -4215,6 +4216,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
 	intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
 	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
 	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
+	intel_dip_sdp_transmission_line_get_config(pipe_config);
 
 	intel_audio_codec_get_config(encoder, pipe_config);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index 504a2edadd0e..333314637db5 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -27,19 +27,21 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	u32 transmission_line = 0;
 
 	if (!HAS_EMP_AS_SDP_TL(display))
 		return;
-	/*
-	 * Since currently we support VRR only for DP/eDP, program the register
-	 * for Adaptive Sync SDP. For non-DP encoders, the register is reset
-	 * to 0.
-	 */
-	if (intel_crtc_has_dp_encoder(crtc_state))
-		transmission_line = intel_dp_get_as_sdp_transmission_line(crtc_state);
 
 	intel_de_write(display,
 		       EMP_AS_SDP_TL(display, cpu_transcoder),
-		       EMP_AS_SDP_DB_TL(transmission_line));
+		       EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl));
+}
+
+void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->dip.emp_as_sdp_tl = intel_dp_get_as_sdp_transmission_line(crtc_state);
+}
+
+void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
+{
+	crtc_state->dip.emp_as_sdp_tl = intel_dip_read_emp_as_sdp_tl(crtc_state);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
index 37507ac3e645..600dabbf7372 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.h
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -43,4 +43,7 @@ struct intel_dip {
 	u16 emp_as_sdp_tl;
 };
 
+void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state);
+void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_DIP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index f54f7faf878f..e143ec1b76d0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -7356,6 +7356,8 @@ int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
 		return -EINVAL;
 	}
 
+	intel_dip_sdp_tl_compute_config_late(crtc_state);
+
 	return 0;
 }
 
@@ -7468,6 +7470,15 @@ void intel_dp_link_cleanup(struct intel_dp *intel_dp)
 
 int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (!HAS_EMP_AS_SDP_TL(display))
+		return 0;
+
+	if (!(crtc_state->infoframes.enable &
+	      intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)))
+		return 0;
+
 	/*
 	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
 	 * Transmission Line, which corresponds to the start of the
-- 
2.45.2

[PATCH v4 07/12] drm/i915/nvl: Add register definitions for common SDP Transmission Line

[Ankit Nautiyal]

From: Arun R Murthy <arun.r.murthy@intel.com>

Add registers definitions for common SDP transmission line CMN_SDP_TL
and CMN_SDP_TL_STGR_CTL.

v2: Move all registers to intel_dip_regs.h (Ankit)

Bspec: 74384
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip_regs.h | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dip_regs.h b/drivers/gpu/drm/i915/display/intel_dip_regs.h
index 85dcbf42e77d..7e69c5cf63da 100644
--- a/drivers/gpu/drm/i915/display/intel_dip_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dip_regs.h
@@ -14,4 +14,23 @@
 #define   EMP_AS_SDP_DB_TL_MASK			REG_GENMASK(12, 0)
 #define   EMP_AS_SDP_DB_TL(db_transmit_line)	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
 
+/* COMMON SDP TRANSMISSION LINE */
+#define _CMN_SDP_TL_A			0x6020c
+#define CMN_SDP_TL(display, trans)	_MMIO_TRANS2(display, (trans), _CMN_SDP_TL_A)
+#define  TRANSMISSION_LINE_ENABLE	REG_BIT(31)
+#define  BASE_TRANSMISSION_LINE_MASK	REG_GENMASK(12, 0)
+#define  BASE_TRANSMISSION_LINE(x)	REG_FIELD_PREP(BASE_TRANSMISSION_LINE_MASK, x)
+
+#define _CMN_SDP_TL_STGR_CTL_A			0x60214
+#define CMN_SDP_TL_STGR_CTL(display, trans)	_MMIO_TRANS2(display, (trans), _CMN_SDP_TL_STGR_CTL_A)
+#define  VSC_EXT_STAGGER_MASK			REG_GENMASK(11, 8)
+#define  VSC_EXT_STAGGER(x)			REG_FIELD_PREP(VSC_EXT_STAGGER_MASK, x)
+#define  VSC_EXT_STAGGER_DEFAULT		0x2
+#define  PPS_STAGGER_MASK			REG_GENMASK(7, 4)
+#define  PPS_STAGGER(x)				REG_FIELD_PREP(PPS_STAGGER_MASK, x)
+#define  PPS_STAGGER_DEFAULT			0x1
+#define  GMP_STAGGER_MASK			REG_GENMASK(3, 0)
+#define  GMP_STAGGER(x)				REG_FIELD_PREP(GMP_STAGGER_MASK, x)
+#define  GMP_STAGGER_DEFAULT			0x0
+
 #endif /* __INTEL_DIP_REGS_H__ */
-- 
2.45.2

[PATCH v4 08/12] drm/i915/display: Add HAS_COMMON_SDP_TL macro

[Ankit Nautiyal]

Add a helper macro to detect CMN SDP TL support on platforms with display
version 35 and above.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
index 600dabbf7372..e9959356226e 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.h
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -32,6 +32,16 @@ struct intel_crtc_state;
 #define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display) == 1401 || \
 					 DISPLAY_VER(__display) >= 20)
 
+/*
+ * CMN SDP TL: Common Secondary Data Packet Transmission Line.
+ *
+ * Xe3p_lpd introduces new register CMN_SDP_TL to program a common SDP
+ * Transmission line that will be used by the Hardware to position the
+ * SDPs. Along with this, another new register CMN_SDP_TL_STGR_CTL is
+ * also added to stagger the different SDPs.
+ */
+#define HAS_COMMON_SDP_TL(__display)      (DISPLAY_VER(__display) >= 35)
+
 u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
 
-- 
2.45.2

[PATCH v4 09/12] drm/i915/dp: Store SDP transmission lines in crtc_state

[Ankit Nautiyal]

Currently the driver only programs the transmission line for the
Adaptive-Sync SDP, while the hardware controls the transmission lines for
other SDPs.

Starting with Xe3p_lpd, the hardware allows the driver to program
transmission lines for additional DP SDPs. Prepare for this by adding
fields to struct intel_crtc_state to store SDP transmission lines, and
include them in pipe config comparison.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.h     | 6 ++++++
 drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
index e9959356226e..03ef749a79ca 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.h
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -51,6 +51,12 @@ struct intel_dip {
 	 * The programmed transmit line is (Vtotal - value)
 	 */
 	u16 emp_as_sdp_tl;
+	u16 gmp_sdp_tl;
+	u16 pps_sdp_tl;
+	u16 vsc_sdp_tl;
+	u16 vsc_ext_sdp_tl;
+	/* Common SDP Base transmission line (Xe3p_lpd+) */
+	u16 cmn_sdp_tl;
 };
 
 void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c84ee0e865ee..8807897538a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5508,6 +5508,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(set_context_latency);
 
 	PIPE_CONF_CHECK_I(dip.emp_as_sdp_tl);
+	PIPE_CONF_CHECK_I(dip.gmp_sdp_tl);
+	PIPE_CONF_CHECK_I(dip.pps_sdp_tl);
+	PIPE_CONF_CHECK_I(dip.vsc_sdp_tl);
+	PIPE_CONF_CHECK_I(dip.vsc_ext_sdp_tl);
+	PIPE_CONF_CHECK_I(dip.cmn_sdp_tl);
 
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
-- 
2.45.2

[PATCH v4 10/12] drm/i915/dp: Introduce helpers to enable/disable CMN SDP Transmission line

[Ankit Nautiyal]

Introduce helpers to program or disable CMN_SDP_TL and stagger registers
using the state stored in crtc_state.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dip.c | 56 ++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dip.h |  2 +
 2 files changed, 58 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index 333314637db5..5cda9792d593 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -4,6 +4,8 @@
  *
  */
 
+#include <drm/drm_print.h>
+
 #include "intel_de.h"
 #include "intel_dip.h"
 #include "intel_dip_regs.h"
@@ -45,3 +47,57 @@ void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_st
 {
 	crtc_state->dip.emp_as_sdp_tl = intel_dip_read_emp_as_sdp_tl(crtc_state);
 }
+
+static int intel_dip_sdp_tl_to_stagger(const struct intel_crtc_state *crtc_state,
+				       u16 sdp_transmission_line)
+{
+	return sdp_transmission_line - crtc_state->dip.cmn_sdp_tl;
+}
+
+void intel_dip_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	int gmp_stagger;
+	int pps_stagger;
+	int vsc_ext_stagger;
+
+	if (!crtc_state->dip.cmn_sdp_tl)
+		return;
+
+	gmp_stagger = intel_dip_sdp_tl_to_stagger(crtc_state,
+						  crtc_state->dip.gmp_sdp_tl);
+
+	pps_stagger = intel_dip_sdp_tl_to_stagger(crtc_state,
+						  crtc_state->dip.pps_sdp_tl);
+
+	vsc_ext_stagger = intel_dip_sdp_tl_to_stagger(crtc_state,
+						      crtc_state->dip.vsc_ext_sdp_tl);
+
+	if (drm_WARN_ON(display->drm, gmp_stagger < 0))
+		return;
+	if (drm_WARN_ON(display->drm, pps_stagger < 0))
+		return;
+	if (drm_WARN_ON(display->drm, vsc_ext_stagger < 0))
+		return;
+
+	intel_de_write(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder),
+		       GMP_STAGGER(gmp_stagger) |
+		       PPS_STAGGER(pps_stagger) |
+		       VSC_EXT_STAGGER(vsc_ext_stagger));
+
+	intel_de_write(display, CMN_SDP_TL(display, cpu_transcoder),
+		       TRANSMISSION_LINE_ENABLE |
+		       BASE_TRANSMISSION_LINE(crtc_state->dip.cmn_sdp_tl));
+}
+
+void intel_dip_cmn_sdp_transmission_line_disable(const struct intel_crtc_state *old_crtc_state)
+{
+	struct intel_display *display = to_intel_display(old_crtc_state);
+	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+
+	if (!old_crtc_state->dip.cmn_sdp_tl)
+		return;
+
+	intel_de_write(display, CMN_SDP_TL(display, cpu_transcoder), 0);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
index 03ef749a79ca..24d6228c2f8d 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.h
+++ b/drivers/gpu/drm/i915/display/intel_dip.h
@@ -61,5 +61,7 @@ struct intel_dip {
 
 void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state);
 void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state);
+void intel_dip_cmn_sdp_transmission_line_enable(const struct intel_crtc_state *crtc_state);
+void intel_dip_cmn_sdp_transmission_line_disable(const struct intel_crtc_state *old_crtc_state);
 
 #endif /* __INTEL_DIP_H__ */
-- 
2.45.2

[PATCH v4 11/12] drm/i915/dip: Enable Common SDP Transmission line

[Ankit Nautiyal]

Enable programming of the common SDP transmission line on platforms that
support it. Compute and program the common base transmission line and
per-SDP stagger values from the crtc state during modeset, and disable the
feature on pipe disable.

Currently, the stagger values are set as per the default policy of the
Hardware. This can be optimized later if we come up with a specific driver
policy to sequence the SDPs better.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  3 +
 drivers/gpu/drm/i915/display/intel_dip.c | 90 ++++++++++++++++++++++++
 2 files changed, 93 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d2edfad295d5..ca9144add691 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2727,6 +2727,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
 	/* 6.o Configure and enable FEC if needed */
 	intel_ddi_enable_fec(encoder, crtc_state);
 
+	intel_dip_cmn_sdp_transmission_line_enable(crtc_state);
+
 	/* 7.a 128b/132b SST. */
 	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
 		/* VCPID 1, start slot 0 for 128b/132b, tu slots */
@@ -3114,6 +3116,7 @@ static void intel_ddi_buf_disable(struct intel_encoder *encoder,
 			     DP_TP_CTL_ENABLE, 0);
 	}
 
+	intel_dip_cmn_sdp_transmission_line_disable(crtc_state);
 	intel_ddi_disable_fec(encoder, crtc_state);
 
 	if (DISPLAY_VER(display) < 14)
diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c
index 5cda9792d593..d60f9f8111b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dip.c
+++ b/drivers/gpu/drm/i915/display/intel_dip.c
@@ -11,6 +11,7 @@
 #include "intel_dip_regs.h"
 #include "intel_display_types.h"
 #include "intel_dp.h"
+#include "intel_hdmi.h"
 
 u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 {
@@ -38,14 +39,103 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)
 		       EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl));
 }
 
+static int intel_dip_sdp_stagger_to_tl(struct intel_crtc_state *crtc_state,
+				       int stagger)
+{
+	return crtc_state->dip.cmn_sdp_tl + stagger;
+}
+
+static
+void intel_dip_cmn_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	bool as_sdp;
+
+	if (!HAS_COMMON_SDP_TL(display))
+		return;
+
+	as_sdp = crtc_state->infoframes.enable &
+		 intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
+	/*
+	 * When AS SDP is enabled :
+	 *  - The common SDP Transmission Line matches the EMP SDP Transmission Line.
+	 *
+	 * When AS SDP is disabled:
+	 *  - Bspec mentions the positions as lines of delayed vblank.
+	 *  - Guardband = 1st line of delayed vblank
+	 *  - Common SDP Transmission line is set to 2nd line of delayed vblank.
+	 */
+
+	if (as_sdp)
+		crtc_state->dip.cmn_sdp_tl = crtc_state->dip.emp_as_sdp_tl;
+	else
+		crtc_state->dip.cmn_sdp_tl = crtc_state->vrr.guardband - 1;
+
+	/*
+	 * Currently we are programming the default stagger values, but these
+	 * can be optimized if required, based on number of SDPs enabled.
+	 *
+	 * Default values of the Transmission lines for SDPs other than AS SDP:
+	 * VSC : CMN SDP Transmission line
+	 * GMP : CMN SDP Transmission line
+	 * PPS : CMN SDP Transmission line + 1
+	 * VSC_EXT: CMN SDP Transmission line + 2
+	 */
+	crtc_state->dip.vsc_sdp_tl = crtc_state->dip.cmn_sdp_tl;
+	crtc_state->dip.gmp_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, GMP_STAGGER_DEFAULT);
+	crtc_state->dip.pps_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, PPS_STAGGER_DEFAULT);
+	crtc_state->dip.vsc_ext_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, VSC_EXT_STAGGER_DEFAULT);
+}
+
 void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state)
 {
 	crtc_state->dip.emp_as_sdp_tl = intel_dp_get_as_sdp_transmission_line(crtc_state);
+
+	intel_dip_cmn_sdp_tl_compute_config_late(crtc_state);
+}
+
+static
+void intel_dip_cmn_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	u16 vsc_ext_stagger, pps_stagger, gmp_stagger;
+	u32 val;
+
+	if (!HAS_COMMON_SDP_TL(display))
+		return;
+
+	val = intel_de_read(display, CMN_SDP_TL(display, cpu_transcoder));
+
+	if (!(val & TRANSMISSION_LINE_ENABLE))
+		return;
+
+	crtc_state->dip.cmn_sdp_tl = REG_FIELD_GET(BASE_TRANSMISSION_LINE_MASK, val);
+
+	/* SDP VSC uses same transmission line as CMN base transmission line */
+	crtc_state->dip.vsc_sdp_tl = crtc_state->dip.cmn_sdp_tl;
+
+	val = intel_de_read(display, CMN_SDP_TL_STGR_CTL(display, cpu_transcoder));
+
+	vsc_ext_stagger = REG_FIELD_GET(VSC_EXT_STAGGER_MASK, val);
+	pps_stagger = REG_FIELD_GET(PPS_STAGGER_MASK, val);
+	gmp_stagger = REG_FIELD_GET(GMP_STAGGER_MASK, val);
+
+	crtc_state->dip.vsc_ext_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, vsc_ext_stagger);
+	crtc_state->dip.pps_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, pps_stagger);
+	crtc_state->dip.gmp_sdp_tl =
+		intel_dip_sdp_stagger_to_tl(crtc_state, gmp_stagger);
 }
 
 void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state)
 {
 	crtc_state->dip.emp_as_sdp_tl = intel_dip_read_emp_as_sdp_tl(crtc_state);
+	intel_dip_cmn_sdp_transmission_line_get_config(crtc_state);
 }
 
 static int intel_dip_sdp_tl_to_stagger(const struct intel_crtc_state *crtc_state,
-- 
2.45.2

[PATCH v4 12/12] drm/i915/display: Dump DIP Transmission lines

[Ankit Nautiyal]

Add DIP transmission lines to the CRTC state dump.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 4493483f10a9..20d71b1c0509 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -251,6 +251,15 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 			   str_enabled_disabled(pipe_config->has_panel_replay),
 			   str_enabled_disabled(pipe_config->enable_psr2_sel_fetch));
 		drm_printf(&p, "minimum hblank: %d\n", pipe_config->min_hblank);
+
+		drm_printf(&p, "DIP Transmission Lines: EMP/AS SDP: %u\n",
+			   pipe_config->dip.emp_as_sdp_tl);
+		drm_printf(&p, "DIP Transmission Lines: Common Base SDP: %u, GMP SDP: %u, PPS SDP: %u, VSC SDP: %u, VSC_EXT SDP: %u\n",
+			   pipe_config->dip.cmn_sdp_tl,
+			   pipe_config->dip.gmp_sdp_tl,
+			   pipe_config->dip.pps_sdp_tl,
+			   pipe_config->dip.vsc_sdp_tl,
+			   pipe_config->dip.vsc_ext_sdp_tl);
 	}
 
 	drm_printf(&p, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
-- 
2.45.2

✓ i915.CI.BAT: success for Add support for Common SDP Transmission Line (rev4)

[Patchwork]

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== Series Details ==

Series: Add support for Common SDP Transmission Line (rev4)
URL   : https://patchwork.freedesktop.org/series/162622/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18660 -> Patchwork_162622v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 


Changes
-------

  No changes found


Build changes
-------------

  * Linux: CI_DRM_18660 -> Patchwork_162622v4

  CI-20190529: 20190529
  CI_DRM_18660: e9f46237d19eab8041730860e800d92007c3bc7b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8958: 8958
  Patchwork_162622v4: e9f46237d19eab8041730860e800d92007c3bc7b @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/index.html

[-- Attachment #2: Type: text/html, Size: 1575 bytes --]

✗ i915.CI.Full: failure for Add support for Common SDP Transmission Line (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 122695 bytes --]

== Series Details ==

Series: Add support for Common SDP Transmission Line (rev4)
URL   : https://patchwork.freedesktop.org/series/162622/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18660_full -> Patchwork_162622v4_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_162622v4_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_162622v4_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_162622v4_full:

### IGT changes ###

#### Possible regressions ####

  * igt@perf_pmu@rc6:
    - shard-dg2:          [PASS][1] -> [WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-7/igt@perf_pmu@rc6.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-6/igt@perf_pmu@rc6.html

  * igt@perf_pmu@rc6@runtime-pm-long-gt0:
    - shard-dg2:          [PASS][3] -> [SKIP][4] +1 other test skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-7/igt@perf_pmu@rc6@runtime-pm-long-gt0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-6/igt@perf_pmu@rc6@runtime-pm-long-gt0.html

  
Known issues
------------

  Here are the changes found in Patchwork_162622v4_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-dg2:          NOTRUN -> [SKIP][5] ([i915#8411])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@device_reset@cold-reset-bound:
    - shard-tglu:         NOTRUN -> [SKIP][6] ([i915#11078])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@device_reset@cold-reset-bound.html

  * igt@dmabuf@all-tests:
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#15931])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@dmabuf@all-tests.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          NOTRUN -> [INCOMPLETE][8] ([i915#13356] / [i915#16348])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-7/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_ctx_freq@sysfs@gt0:
    - shard-dg2:          [PASS][9] -> [FAIL][10] ([i915#9561]) +1 other test fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-6/igt@gem_ctx_freq@sysfs@gt0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@gem_ctx_freq@sysfs@gt0.html

  * igt@gem_ctx_sseu@engines:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#280])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-tglu-1:       NOTRUN -> [SKIP][12] ([i915#280])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_exec_balancer@bonded-dual:
    - shard-dg2:          NOTRUN -> [SKIP][13] ([i915#4771])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@gem_exec_balancer@bonded-dual.html

  * igt@gem_exec_balancer@parallel:
    - shard-tglu-1:       NOTRUN -> [SKIP][14] ([i915#4525]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          NOTRUN -> [SKIP][15] ([i915#6344])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_capture@capture@vecs0-lmem0:
    - shard-dg2:          NOTRUN -> [FAIL][16] ([i915#11965]) +4 other tests fail
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@gem_exec_capture@capture@vecs0-lmem0.html

  * igt@gem_exec_reloc@basic-write-read-active:
    - shard-dg1:          NOTRUN -> [SKIP][17] ([i915#3281])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@gem_exec_reloc@basic-write-read-active.html

  * igt@gem_exec_reloc@basic-write-read-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][18] ([i915#3281]) +6 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html

  * igt@gem_fenced_exec_thrash@no-spare-fences-busy:
    - shard-dg2:          NOTRUN -> [SKIP][19] ([i915#4860])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-3/igt@gem_fenced_exec_thrash@no-spare-fences-busy.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-glk:          NOTRUN -> [SKIP][20] ([i915#4613]) +2 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk1/igt@gem_lmem_evict@dontneed-evict-race.html
    - shard-rkl:          NOTRUN -> [SKIP][21] ([i915#4613] / [i915#7582])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][22] ([i915#4613]) +3 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
    - shard-tglu-1:       NOTRUN -> [SKIP][23] ([i915#4613]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-tglu:         NOTRUN -> [SKIP][24] ([i915#4613]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_mmap_gtt@cpuset-big-copy:
    - shard-dg2:          NOTRUN -> [SKIP][25] ([i915#4077])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@gem_mmap_gtt@cpuset-big-copy.html

  * igt@gem_mmap_gtt@hang-busy:
    - shard-dg1:          NOTRUN -> [SKIP][26] ([i915#4077])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@gem_mmap_gtt@hang-busy.html

  * igt@gem_mmap_wc@invalid-flags:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#4083])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@gem_mmap_wc@invalid-flags.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-dg2:          NOTRUN -> [SKIP][28] ([i915#3282]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_pread@exhaustion:
    - shard-glk10:        NOTRUN -> [WARN][29] ([i915#2658])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk10/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-dg1:          NOTRUN -> [SKIP][30] ([i915#3282])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@gem_pwrite@basic-exhaustion.html
    - shard-tglu:         NOTRUN -> [WARN][31] ([i915#2658])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#4270]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - shard-tglu-1:       NOTRUN -> [SKIP][33] ([i915#13398])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@gem_pxp@hw-rejects-pxp-buffer.html

  * igt@gem_readwrite@beyond-eob:
    - shard-rkl:          NOTRUN -> [SKIP][34] ([i915#3282]) +5 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@gem_readwrite@beyond-eob.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
    - shard-glk:          NOTRUN -> [SKIP][35] +279 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk5/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html

  * igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#5190] / [i915#8428])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html

  * igt@gem_set_tiling_vs_gtt:
    - shard-dg1:          NOTRUN -> [SKIP][37] ([i915#4079])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@gem_set_tiling_vs_gtt.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][38] ([i915#3297])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@gem_userptr_blits@coherency-unsync.html
    - shard-tglu-1:       NOTRUN -> [SKIP][39] ([i915#3297])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][40] ([i915#13356])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk11/igt@gem_workarounds@suspend-resume-context.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#2856])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          [PASS][42] -> [ABORT][43] ([i915#5566])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-glk5/igt@gen9_exec_parse@allowed-single.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk9/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-rkl:          NOTRUN -> [SKIP][44] ([i915#2527]) +4 other tests skip
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-tglu-1:       NOTRUN -> [SKIP][45] ([i915#2527] / [i915#2856]) +3 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_drm_fdinfo@virtual-busy-idle:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#14118]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@i915_drm_fdinfo@virtual-busy-idle.html

  * igt@i915_pm_freq_api@freq-reset:
    - shard-rkl:          NOTRUN -> [SKIP][47] ([i915#8399])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@i915_pm_freq_api@freq-reset.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][48] ([i915#8399]) +1 other test skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-rkl:          [PASS][49] -> [INCOMPLETE][50] ([i915#13356])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-3/igt@i915_pm_rpm@system-suspend-execbuf.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_pm_rps@min-max-config-idle:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#11681] / [i915#6621])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@i915_pm_rps@min-max-config-idle.html

  * igt@i915_suspend@forcewake:
    - shard-glk:          NOTRUN -> [INCOMPLETE][52] ([i915#16182] / [i915#4817])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk6/igt@i915_suspend@forcewake.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-1:
    - shard-glk:          [PASS][53] -> [FAIL][54] ([i915#14888])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-1.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk2/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-a-hdmi-a-1.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-rkl:          [PASS][55] -> [INCOMPLETE][56] ([i915#12761])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_async_flips@async-flip-suspend-resume.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][57] ([i915#12761])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          NOTRUN -> [SKIP][58] ([i915#9531])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-glk:          NOTRUN -> [SKIP][59] ([i915#1769])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-glk10:        NOTRUN -> [SKIP][60] ([i915#1769])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk10/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][61] -> [FAIL][62] ([i915#15662]) +1 other test fail
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-tglu-2/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-3/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-0:
    - shard-mtlp:         [PASS][63] -> [FAIL][64] ([i915#12469] / [i915#15733] / [i915#5138])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-mtlp-5/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-mtlp-8/igt@kms_big_fb@4-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-180:
    - shard-tglu:         NOTRUN -> [SKIP][65] ([i915#5286]) +1 other test skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][66] ([i915#5286]) +2 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][67] -> [FAIL][68] ([i915#15733] / [i915#5138])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-tglu-1:       NOTRUN -> [SKIP][69] ([i915#5286]) +3 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][70] ([i915#3638])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#3638]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][72] +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][73] ([i915#4538] / [i915#5190]) +2 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2:          NOTRUN -> [SKIP][74] ([i915#5190])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][75] ([i915#10307] / [i915#6095]) +56 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-5/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][76] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#14098] / [i915#14544] / [i915#6095]) +7 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#12313])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][79] ([i915#14544] / [i915#6095]) +14 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([i915#12805])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([i915#6095]) +15 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-3/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][82] ([i915#15582]) +1 other test incomplete
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk8/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][83] ([i915#14098] / [i915#6095]) +52 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][84] ([i915#6095]) +44 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][85] ([i915#12313])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][86] ([i915#6095]) +238 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-4.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][87] ([i915#6095]) +39 other tests skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][88] ([i915#12313])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
    - shard-tglu:         NOTRUN -> [SKIP][89] ([i915#12313])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#6095]) +92 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-4/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][91] ([i915#13781]) +4 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html

  * igt@kms_chamelium_edid@dp-mode-timings:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#11151] / [i915#7828]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_chamelium_edid@dp-mode-timings.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#11151] / [i915#7828]) +6 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-tglu-1:       NOTRUN -> [SKIP][94] ([i915#11151] / [i915#7828]) +4 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_chamelium_hpd@vga-hpd-without-ddc:
    - shard-tglu:         NOTRUN -> [SKIP][95] ([i915#11151] / [i915#7828]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html
    - shard-dg1:          NOTRUN -> [SKIP][96] ([i915#11151] / [i915#7828])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html

  * igt@kms_color@deep-color:
    - shard-rkl:          NOTRUN -> [SKIP][97] ([i915#12655] / [i915#3555])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_color@deep-color.html

  * igt@kms_content_protection@dp-mst-type-0-hdcp14:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#15330])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_content_protection@dp-mst-type-0-hdcp14.html

  * igt@kms_content_protection@dp-mst-type-0-suspend-resume:
    - shard-tglu-1:       NOTRUN -> [SKIP][99] ([i915#15330])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([i915#15330] / [i915#3299])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][101] ([i915#15330])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@legacy-hdcp14:
    - shard-tglu:         NOTRUN -> [SKIP][102] ([i915#15865])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_content_protection@legacy-hdcp14.html

  * igt@kms_content_protection@srm:
    - shard-tglu-1:       NOTRUN -> [SKIP][103] ([i915#15865]) +1 other test skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@suspend-resume:
    - shard-rkl:          NOTRUN -> [SKIP][104] ([i915#15865])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_content_protection@suspend-resume.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][105] ([i915#13049])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_cursor_crc@cursor-onscreen-512x512.html
    - shard-dg1:          NOTRUN -> [SKIP][106] ([i915#13049])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][107] ([i915#13566]) +3 other tests fail
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-rkl:          NOTRUN -> [SKIP][108] ([i915#3555]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [FAIL][109] ([i915#13566]) +1 other test fail
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-sliding-32x32:
    - shard-tglu:         NOTRUN -> [SKIP][110] ([i915#3555]) +2 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_cursor_crc@cursor-sliding-32x32.html
    - shard-dg1:          NOTRUN -> [SKIP][111] ([i915#3555]) +1 other test skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_cursor_crc@cursor-sliding-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-tglu-1:       NOTRUN -> [SKIP][112] ([i915#13049]) +2 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-dg2:          NOTRUN -> [SKIP][113] ([i915#3555]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#13046] / [i915#5354])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-dg1:          NOTRUN -> [SKIP][115] ([i915#4103])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
    - shard-tglu:         NOTRUN -> [SKIP][116] ([i915#4103]) +2 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#9067])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
    - shard-tglu-1:       NOTRUN -> [SKIP][118] ([i915#9067])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-tglu:         NOTRUN -> [SKIP][119] ([i915#9723])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#13691])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][121] ([i915#14544] / [i915#3804])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-dg2:          NOTRUN -> [SKIP][122] ([i915#13749])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-tglu-1:       NOTRUN -> [SKIP][123] ([i915#13749])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-tglu-1:       NOTRUN -> [SKIP][124] ([i915#13707])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-basic:
    - shard-dg2:          NOTRUN -> [SKIP][125] ([i915#16361])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp-bigjoiner:
    - shard-tglu:         NOTRUN -> [SKIP][126] ([i915#16361]) +1 other test skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_dsc@dsc-fractional-bpp-bigjoiner.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner:
    - shard-rkl:          NOTRUN -> [SKIP][127] ([i915#16361]) +4 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner.html
    - shard-tglu-1:       NOTRUN -> [SKIP][128] ([i915#16361]) +2 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          NOTRUN -> [SKIP][129] ([i915#3955])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_fbcon_fbt@psr.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][130] ([i915#3469])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-rkl:          NOTRUN -> [SKIP][131] ([i915#16081]) +1 other test skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-tglu-1:       NOTRUN -> [SKIP][132] ([i915#16081])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([i915#9934]) +2 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-3/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][134] ([i915#3637] / [i915#9934]) +3 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#9934]) +1 other test skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][136] ([i915#3637] / [i915#9934]) +3 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-rkl:          NOTRUN -> [FAIL][137] ([i915#13027]) +1 other test fail
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
    - shard-tglu:         [PASS][138] -> [FAIL][139] ([i915#13027]) +1 other test fail
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-tglu-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-7/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][140] ([i915#12314] / [i915#12745] / [i915#4839] / [i915#6113])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][141] ([i915#12314] / [i915#12745] / [i915#6113])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk5/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][142] ([i915#15643])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][143] ([i915#15643])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][144] ([i915#15643]) +2 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][145] ([i915#15643]) +4 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#15990] / [i915#8708]) +4 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][147] ([i915#1825]) +5 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-tglu:         NOTRUN -> [SKIP][148] ([i915#5439])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][149] ([i915#15990]) +3 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-indfb-draw-mmap-wc.html
    - shard-tglu:         NOTRUN -> [SKIP][150] ([i915#15989]) +10 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move:
    - shard-rkl:          [PASS][151] -> [SKIP][152] ([i915#15989]) +5 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg2:          [PASS][153] -> [SKIP][154] ([i915#15989]) +1 other test skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-10/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-pgflip-blt.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-3/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][155] ([i915#15989]) +20 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-tglu-1:       NOTRUN -> [SKIP][156] +82 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#15102]) +22 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][158] ([i915#15102]) +23 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#15102]) +5 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][160] +11 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][161] ([i915#15102]) +33 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][162] ([i915#5439])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-shrfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#15990]) +4 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-cur-indfb-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][164] +51 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][165] ([i915#15989]) +8 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-dg1:          NOTRUN -> [SKIP][166] ([i915#15989]) +1 other test skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-pri-indfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][167] ([i915#15991]) +10 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
    - shard-glk:          [PASS][168] -> [SKIP][169] +22 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-glk8/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk9/igt@kms_frontbuffer_tracking@hdr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-pwrite:
    - shard-tglu-1:       NOTRUN -> [SKIP][170] ([i915#15989]) +12 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-dg1:          NOTRUN -> [SKIP][171] ([i915#9766])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
    - shard-tglu:         NOTRUN -> [SKIP][172] ([i915#9766])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][173] ([i915#15102] / [i915#3023]) +10 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg1:          NOTRUN -> [SKIP][174] ([i915#15102]) +3 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][175] ([i915#15990] / [i915#8708]) +2 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][176] ([i915#15991] / [i915#5354]) +5 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-cur-indfb-move:
    - shard-rkl:          NOTRUN -> [SKIP][177] +88 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-cur-indfb-move.html

  * igt@kms_hdr@bpc-switch:
    - shard-rkl:          NOTRUN -> [SKIP][178] ([i915#16012] / [i915#3555] / [i915#8228]) +2 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-dpms@pipe-a-hdmi-a-2-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#16012]) +5 other tests skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_hdr@bpc-switch-dpms@pipe-a-hdmi-a-2-xrgb2101010.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][180] ([i915#16012] / [i915#3555] / [i915#8228])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-1-xrgb2101010:
    - shard-tglu-1:       NOTRUN -> [SKIP][181] ([i915#16012]) +1 other test skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-1-xrgb2101010.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-dg1:          NOTRUN -> [SKIP][182] ([i915#16012]) +5 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-12/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-1-xrgb2101010:
    - shard-tglu-1:       NOTRUN -> [SKIP][183] ([i915#16011]) +2 other tests skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_hdr@brightness-with-hdr@pipe-a-hdmi-a-1-xrgb2101010.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-2-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][184] ([i915#14544] / [i915#16025]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-2-xrgb2101010.html

  * igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-1-xrgb16161616f:
    - shard-dg1:          NOTRUN -> [SKIP][185] ([i915#16011]) +11 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-15/igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-1-xrgb16161616f.html

  * igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-2-xrgb2101010:
    - shard-rkl:          NOTRUN -> [SKIP][186] ([i915#16011]) +9 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_hdr@invalid-metadata-sizes@pipe-a-hdmi-a-2-xrgb2101010.html

  * igt@kms_hdr@static-toggle:
    - shard-tglu:         NOTRUN -> [SKIP][187] ([i915#16011] / [i915#3555] / [i915#8228])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-1-xrgb16161616f:
    - shard-tglu:         NOTRUN -> [SKIP][188] ([i915#16011]) +1 other test skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-1-xrgb16161616f.html

  * igt@kms_invalid_mode@bad-hsync-end:
    - shard-dg1:          [PASS][189] -> [DMESG-WARN][190] ([i915#4423])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-19/igt@kms_invalid_mode@bad-hsync-end.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-13/igt@kms_invalid_mode@bad-hsync-end.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([i915#15458])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_joiner@basic-ultra-joiner.html
    - shard-tglu-1:       NOTRUN -> [SKIP][192] ([i915#15458]) +1 other test skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][193] ([i915#12756] / [i915#13409] / [i915#13476]) +1 other test incomplete
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk1/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html

  * igt@kms_pipe_stress@stress-xrgb8888-4tiled:
    - shard-tglu:         NOTRUN -> [SKIP][194] ([i915#14712])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#15709])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
    - shard-tglu-1:       NOTRUN -> [SKIP][196] ([i915#15709]) +1 other test skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping:
    - shard-dg1:          NOTRUN -> [SKIP][197] ([i915#15709])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping.html
    - shard-tglu:         NOTRUN -> [SKIP][198] ([i915#15709]) +1 other test skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-a-plane-7:
    - shard-tglu-1:       NOTRUN -> [SKIP][199] ([i915#16386]) +3 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-a-plane-7.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-b-plane-5:
    - shard-rkl:          NOTRUN -> [SKIP][200] ([i915#16386]) +3 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-b-plane-5.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier:
    - shard-rkl:          NOTRUN -> [SKIP][201] ([i915#15709]) +4 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_plane@pixel-format-yf-tiled-modifier.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][202] ([i915#13026]) +1 other test incomplete
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk8/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk10:        NOTRUN -> [FAIL][203] ([i915#10647] / [i915#12169])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk10/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-c-hdmi-a-1:
    - shard-glk10:        NOTRUN -> [FAIL][204] ([i915#10647]) +1 other test fail
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk10/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-c-hdmi-a-1.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][205] ([i915#13958]) +1 other test skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-tglu-1:       NOTRUN -> [SKIP][206] ([i915#13958])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-tglu:         NOTRUN -> [SKIP][207] ([i915#13958])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2:          NOTRUN -> [SKIP][208] ([i915#6953] / [i915#9423])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b:
    - shard-rkl:          NOTRUN -> [SKIP][209] ([i915#15329]) +7 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-b.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][210] ([i915#12343])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-tglu:         NOTRUN -> [SKIP][211] ([i915#3828])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][212] ([i915#15739])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-glk11:        NOTRUN -> [SKIP][213] +26 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk11/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg1:          [PASS][214] -> [SKIP][215] ([i915#15073])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-15/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-18/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-rkl:          [PASS][216] -> [SKIP][217] ([i915#15073]) +1 other test skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-8/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [PASS][218] -> [SKIP][219] ([i915#14544] / [i915#15073])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][220] ([i915#15073])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
    - shard-tglu:         NOTRUN -> [SKIP][221] ([i915#11520]) +3 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-dg2:          NOTRUN -> [SKIP][222] ([i915#11520]) +1 other test skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-tglu-1:       NOTRUN -> [SKIP][223] ([i915#11520]) +4 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf:
    - shard-dg1:          NOTRUN -> [SKIP][224] ([i915#11520]) +1 other test skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-rkl:          NOTRUN -> [SKIP][225] ([i915#11520]) +4 other tests skip
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][226] ([i915#11520]) +3 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk5/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-glk10:        NOTRUN -> [SKIP][227] ([i915#11520]) +6 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk10/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-rkl:          NOTRUN -> [SKIP][228] ([i915#9683]) +1 other test skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-tglu-1:       NOTRUN -> [SKIP][229] ([i915#9683]) +1 other test skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-primary-render:
    - shard-glk10:        NOTRUN -> [SKIP][230] +233 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk10/igt@kms_psr@fbc-pr-primary-render.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          NOTRUN -> [SKIP][231] ([i915#1072] / [i915#9732]) +17 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr@pr-cursor-plane-onoff:
    - shard-tglu:         NOTRUN -> [SKIP][232] ([i915#9732]) +9 other tests skip
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_psr@pr-cursor-plane-onoff.html

  * igt@kms_psr@pr-primary-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][233] ([i915#1072] / [i915#9732]) +5 other tests skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_psr@pr-primary-mmap-gtt.html

  * igt@kms_psr@psr-sprite-plane-move:
    - shard-tglu-1:       NOTRUN -> [SKIP][234] ([i915#9732]) +13 other tests skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_psr@psr-sprite-plane-move.html

  * igt@kms_psr@psr2-cursor-plane-move:
    - shard-dg1:          NOTRUN -> [SKIP][235] ([i915#1072] / [i915#9732]) +2 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_psr@psr2-cursor-plane-move.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-dg2:          NOTRUN -> [SKIP][236] ([i915#4235])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-glk:          NOTRUN -> [INCOMPLETE][237] ([i915#15500] / [i915#16184])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk5/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2:          NOTRUN -> [SKIP][238] ([i915#12755] / [i915#15867])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-tglu-1:       NOTRUN -> [SKIP][239] ([i915#3555]) +1 other test skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][240] ([i915#12276]) +1 other test incomplete
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk5/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-tglu-1:       NOTRUN -> [SKIP][241] ([i915#9906])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-1/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@negative-basic:
    - shard-tglu:         NOTRUN -> [SKIP][242] ([i915#3555] / [i915#9906])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@kms_vrr@negative-basic.html
    - shard-mtlp:         [PASS][243] -> [FAIL][244] ([i915#15420]) +1 other test fail
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-mtlp-6/igt@kms_vrr@negative-basic.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-mtlp-1/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-dg2:          NOTRUN -> [SKIP][245] ([i915#9906])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-rkl:          NOTRUN -> [SKIP][246] ([i915#9906])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-rkl:          NOTRUN -> [SKIP][247] ([i915#2436])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf@unprivileged-single-ctx-counters:
    - shard-rkl:          NOTRUN -> [SKIP][248] ([i915#2433])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@perf@unprivileged-single-ctx-counters.html

  * igt@perf_pmu@module-unload:
    - shard-glk:          NOTRUN -> [ABORT][249] ([i915#15778])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk8/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-dg1:          NOTRUN -> [SKIP][250] ([i915#8516])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@perf_pmu@rc6@other-idle-gt0.html
    - shard-tglu:         NOTRUN -> [SKIP][251] ([i915#8516])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_vgem@fence-read-hang:
    - shard-dg1:          NOTRUN -> [SKIP][252] ([i915#3708])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@prime_vgem@fence-read-hang.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random:
    - shard-tglu:         NOTRUN -> [SKIP][253] ([i915#16066]) +8 other tests skip
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-tglu-4/igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random.html

  
#### Possible fixes ####

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0:
    - shard-dg2:          [INCOMPLETE][254] ([i915#13356] / [i915#16348]) -> [PASS][255]
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-3/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-7/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-smem-lmem0.html

  * igt@gem_eio@in-flight-suspend:
    - shard-rkl:          [INCOMPLETE][256] ([i915#13390]) -> [PASS][257]
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@gem_eio@in-flight-suspend.html
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@gem_eio@in-flight-suspend.html

  * igt@i915_module_load@fault-injection@uc_fw_rsa_data_create:
    - shard-mtlp:         [INCOMPLETE][258] ([i915#15895]) -> [PASS][259]
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-mtlp-2/igt@i915_module_load@fault-injection@uc_fw_rsa_data_create.html
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-mtlp-8/igt@i915_module_load@fault-injection@uc_fw_rsa_data_create.html

  * igt@i915_module_load@reload-no-display:
    - shard-dg1:          [DMESG-WARN][260] ([i915#13029] / [i915#14545]) -> [PASS][261]
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-12/igt@i915_module_load@reload-no-display.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-16/igt@i915_module_load@reload-no-display.html

  * igt@i915_selftest@live@gt_timelines:
    - shard-dg1:          [ABORT][262] -> [PASS][263] +1 other test pass
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-14/igt@i915_selftest@live@gt_timelines.html
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@i915_selftest@live@gt_timelines.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - shard-dg2:          [ABORT][264] ([i915#15131]) -> [PASS][265] +1 other test pass
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-10/igt@i915_suspend@basic-s2idle-without-i915.html
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-8/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@i915_suspend@debugfs-reader:
    - shard-rkl:          [INCOMPLETE][266] ([i915#4817]) -> [PASS][267] +2 other tests pass
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@i915_suspend@debugfs-reader.html
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@i915_suspend@debugfs-reader.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic:
    - shard-dg1:          [FAIL][268] ([i915#14888]) -> [PASS][269]
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-17/igt@kms_async_flips@alternate-sync-async-flip-atomic.html
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-12/igt@kms_async_flips@alternate-sync-async-flip-atomic.html

  * igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-hdmi-a-1:
    - shard-glk:          [FAIL][270] ([i915#14888]) -> [PASS][271]
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-hdmi-a-1.html
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk2/igt@kms_async_flips@alternate-sync-async-flip-atomic@pipe-b-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-rkl:          [FAIL][272] ([i915#13566]) -> [PASS][273]
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-dg1:          [FAIL][274] ([i915#13027]) -> [PASS][275] +1 other test pass
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-16/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-16/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling:
    - shard-dg1:          [DMESG-WARN][276] -> [PASS][277]
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-14/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-linear-to-64bpp-linear-downscaling.html

  * igt@kms_frontbuffer_tracking@fbchdr-rgb101010-draw-render:
    - shard-rkl:          [SKIP][278] ([i915#15989]) -> [PASS][279] +16 other tests pass
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-rgb101010-draw-render.html
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-rgb101010-draw-render.html

  * igt@kms_pm_rpm@i2c:
    - shard-dg1:          [DMESG-WARN][280] ([i915#4423]) -> [PASS][281]
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-19/igt@kms_pm_rpm@i2c.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-13/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-dg2:          [SKIP][282] ([i915#15073]) -> [PASS][283]
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp.html
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [SKIP][284] ([i915#15073]) -> [PASS][285]
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp.html

  
#### Warnings ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-rkl:          [SKIP][286] ([i915#14544] / [i915#8411]) -> [SKIP][287] ([i915#8411]) +1 other test skip
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@api_intel_bb@blit-reloc-purge-cache.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-rkl:          [SKIP][288] ([i915#8411]) -> [SKIP][289] ([i915#14544] / [i915#8411])
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@api_intel_bb@object-reloc-keep-cache.html
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@gem_bad_reloc@negative-reloc-lut:
    - shard-rkl:          [SKIP][290] ([i915#3281]) -> [SKIP][291] ([i915#14544] / [i915#3281]) +7 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@gem_bad_reloc@negative-reloc-lut.html
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gem_bad_reloc@negative-reloc-lut.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-rkl:          [SKIP][292] ([i915#9323]) -> [SKIP][293] ([i915#14544] / [i915#9323])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@gem_ccs@block-multicopy-compressed.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-rkl:          [SKIP][294] ([i915#14544] / [i915#3555] / [i915#9323]) -> [SKIP][295] ([i915#3555] / [i915#9323])
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@gem_ccs@block-multicopy-inplace.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          [SKIP][296] ([i915#7697]) -> [SKIP][297] ([i915#14544] / [i915#7697])
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@gem_close_race@multigpu-basic-threads.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-rkl:          [SKIP][298] ([i915#280]) -> [SKIP][299] ([i915#14544] / [i915#280])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@gem_ctx_sseu@invalid-sseu.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_exec_balancer@parallel-bb-first:
    - shard-rkl:          [SKIP][300] ([i915#4525]) -> [SKIP][301] ([i915#14544] / [i915#4525]) +2 other tests skip
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@gem_exec_balancer@parallel-bb-first.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gem_exec_balancer@parallel-bb-first.html

  * igt@gem_exec_reloc@basic-gtt-wc:
    - shard-rkl:          [SKIP][302] ([i915#14544] / [i915#3281]) -> [SKIP][303] ([i915#3281]) +4 other tests skip
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-wc.html
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-wc.html

  * igt@gem_lmem_swapping@verify-ccs:
    - shard-rkl:          [SKIP][304] ([i915#4613]) -> [SKIP][305] ([i915#14544] / [i915#4613])
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@gem_lmem_swapping@verify-ccs.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gem_lmem_swapping@verify-ccs.html

  * igt@gem_media_vme:
    - shard-rkl:          [SKIP][306] ([i915#284]) -> [SKIP][307] ([i915#14544] / [i915#284])
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@gem_media_vme.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gem_media_vme.html

  * igt@gem_partial_pwrite_pread@writes-after-reads:
    - shard-rkl:          [SKIP][308] ([i915#3282]) -> [SKIP][309] ([i915#14544] / [i915#3282]) +3 other tests skip
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_readwrite@new-obj:
    - shard-rkl:          [SKIP][310] ([i915#14544] / [i915#3282]) -> [SKIP][311] ([i915#3282])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@gem_readwrite@new-obj.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@gem_readwrite@new-obj.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-rkl:          [SKIP][312] ([i915#3297] / [i915#3323]) -> [SKIP][313] ([i915#14544] / [i915#3297] / [i915#3323])
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@gem_userptr_blits@dmabuf-sync.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-rkl:          [SKIP][314] ([i915#14544] / [i915#2527]) -> [SKIP][315] ([i915#2527]) +1 other test skip
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@gen9_exec_parse@bb-start-param.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@gen9_exec_parse@bb-start-param.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-rkl:          [SKIP][316] ([i915#2527]) -> [SKIP][317] ([i915#14544] / [i915#2527])
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@gen9_exec_parse@shadow-peek.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_module_load@fault-injection:
    - shard-mtlp:         [ABORT][318] ([i915#15342] / [i915#15481] / [i915#15895]) -> [ABORT][319] ([i915#15342] / [i915#15481])
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-mtlp-2/igt@i915_module_load@fault-injection.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-mtlp-8/igt@i915_module_load@fault-injection.html

  * igt@i915_module_load@fault-injection@__uc_init:
    - shard-rkl:          [SKIP][320] ([i915#15479]) -> [SKIP][321] ([i915#14544] / [i915#15479]) +4 other tests skip
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@i915_module_load@fault-injection@__uc_init.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@i915_module_load@fault-injection@__uc_init.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
    - shard-dg1:          [SKIP][322] ([i915#4212] / [i915#4423]) -> [SKIP][323] ([i915#4212])
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-17/igt@kms_addfb_basic@tile-pitch-mismatch.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-14/igt@kms_addfb_basic@tile-pitch-mismatch.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          [SKIP][324] ([i915#14544] / [i915#1769] / [i915#3555]) -> [SKIP][325] ([i915#1769] / [i915#3555])
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-rkl:          [SKIP][326] ([i915#1769] / [i915#3555]) -> [SKIP][327] ([i915#14544] / [i915#1769] / [i915#3555])
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-rkl:          [SKIP][328] ([i915#5286]) -> [SKIP][329] ([i915#14544] / [i915#5286]) +3 other tests skip
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-rkl:          [SKIP][330] ([i915#14544] / [i915#5286]) -> [SKIP][331] ([i915#5286]) +1 other test skip
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-rkl:          [SKIP][332] ([i915#3638]) -> [SKIP][333] ([i915#14544] / [i915#3638])
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-3/igt@kms_big_fb@linear-16bpp-rotate-90.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-rkl:          [SKIP][334] ([i915#14544] / [i915#3638]) -> [SKIP][335] ([i915#3638])
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_big_fb@linear-8bpp-rotate-270.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          [SKIP][336] ([i915#3828]) -> [SKIP][337] ([i915#14544] / [i915#3828])
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-rkl:          [SKIP][338] -> [SKIP][339] ([i915#14544]) +54 other tests skip
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][340] ([i915#6095]) -> [SKIP][341] ([i915#14544] / [i915#6095]) +1 other test skip
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-3/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
    - shard-rkl:          [SKIP][342] ([i915#14098] / [i915#6095]) -> [SKIP][343] ([i915#14098] / [i915#14544] / [i915#6095]) +9 other tests skip
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][344] ([i915#14544] / [i915#6095]) -> [SKIP][345] ([i915#6095]) +5 other tests skip
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][346] ([i915#12313]) -> [SKIP][347] ([i915#12313] / [i915#14544]) +1 other test skip
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs:
    - shard-rkl:          [SKIP][348] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][349] ([i915#14098] / [i915#6095]) +11 other tests skip
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - shard-rkl:          [SKIP][350] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][351] ([i915#11151] / [i915#7828]) +3 other tests skip
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_chamelium_frames@dp-crc-fast.html
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_chamelium_frames@dp-crc-fast.html

  * igt@kms_chamelium_hpd@vga-hpd-fast:
    - shard-rkl:          [SKIP][352] ([i915#11151] / [i915#7828]) -> [SKIP][353] ([i915#11151] / [i915#14544] / [i915#7828]) +6 other tests skip
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_chamelium_hpd@vga-hpd-fast.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_chamelium_hpd@vga-hpd-fast.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          [FAIL][354] ([i915#7173]) -> [SKIP][355] ([i915#15865])
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-10/igt@kms_content_protection@atomic-dpms.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-3/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@content-type-change:
    - shard-rkl:          [SKIP][356] ([i915#14544] / [i915#15865]) -> [SKIP][357] ([i915#15865])
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_content_protection@content-type-change.html
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@dp-mst-lic-type-0-hdcp14:
    - shard-rkl:          [SKIP][358] ([i915#15330]) -> [SKIP][359] ([i915#14544] / [i915#15330])
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_content_protection@dp-mst-lic-type-0-hdcp14.html

  * igt@kms_content_protection@uevent-hdcp14:
    - shard-rkl:          [SKIP][360] ([i915#15865]) -> [SKIP][361] ([i915#14544] / [i915#15865]) +1 other test skip
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_content_protection@uevent-hdcp14.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_content_protection@uevent-hdcp14.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-rkl:          [SKIP][362] ([i915#13049]) -> [SKIP][363] ([i915#13049] / [i915#14544])
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-dg2:          [SKIP][364] ([i915#13049] / [i915#3359]) -> [SKIP][365] ([i915#13049]) +1 other test skip
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-10/igt@kms_cursor_crc@cursor-random-512x170.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          [SKIP][366] ([i915#3555] / [i915#3804]) -> [SKIP][367] ([i915#14544] / [i915#3555] / [i915#3804])
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-rkl:          [SKIP][368] ([i915#13748]) -> [SKIP][369] ([i915#13748] / [i915#14544]) +1 other test skip
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_dp_link_training@uhbr-sst.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          [SKIP][370] ([i915#13707] / [i915#14544]) -> [SKIP][371] ([i915#13707])
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-ultrajoiner:
    - shard-rkl:          [SKIP][372] ([i915#16361]) -> [SKIP][373] ([i915#14544] / [i915#16361]) +1 other test skip
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_dsc@dsc-fractional-bpp-ultrajoiner.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp-ultrajoiner.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          [SKIP][374] ([i915#14544] / [i915#16361]) -> [SKIP][375] ([i915#16361]) +1 other test skip
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_dsc@dsc-with-output-formats.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-rkl:          [SKIP][376] ([i915#9337]) -> [SKIP][377] ([i915#14544] / [i915#9337])
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_feature_discovery@dp-mst.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-rkl:          [SKIP][378] ([i915#9934]) -> [SKIP][379] ([i915#14544] / [i915#9934]) +6 other tests skip
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_flip@2x-flip-vs-panning-vs-hang.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][380] ([i915#12745] / [i915#4839] / [i915#6113]) -> [INCOMPLETE][381] ([i915#12745] / [i915#4839])
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-glk1/igt@kms_flip@2x-flip-vs-suspend.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-glk4/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-rkl:          [SKIP][382] ([i915#14544] / [i915#9934]) -> [SKIP][383] ([i915#9934]) +4 other tests skip
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-rkl:          [SKIP][384] ([i915#15643]) -> [SKIP][385] ([i915#14544] / [i915#15643]) +1 other test skip
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][386] ([i915#1825]) -> [SKIP][387] ([i915#14544] / [i915#1825]) +8 other tests skip
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-rkl:          [SKIP][388] ([i915#14544]) -> [SKIP][389] +35 other tests skip
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary:
    - shard-dg2:          [SKIP][390] ([i915#15102]) -> [SKIP][391] ([i915#10433] / [i915#15102])
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-dg2:          [SKIP][392] ([i915#10433] / [i915#15102]) -> [SKIP][393] ([i915#15102])
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
    - shard-rkl:          [SKIP][394] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][395] ([i915#15102] / [i915#3023]) +10 other tests skip
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][396] ([i915#15102]) -> [SKIP][397] ([i915#14544] / [i915#15102]) +15 other tests skip
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-indfb-draw-mmap-cpu.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-offscreen-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-rte:
    - shard-rkl:          [SKIP][398] ([i915#15102] / [i915#3023]) -> [SKIP][399] ([i915#14544] / [i915#15102] / [i915#3023]) +9 other tests skip
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-rte.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-rte.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][400] ([i915#14544] / [i915#1825]) -> [SKIP][401] ([i915#1825]) +1 other test skip
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
    - shard-dg1:          [SKIP][402] ([i915#15990] / [i915#4423] / [i915#8708]) -> [SKIP][403] ([i915#15990] / [i915#8708]) +1 other test skip
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-17/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt:
    - shard-dg1:          [SKIP][404] ([i915#15990] / [i915#8708]) -> [SKIP][405] ([i915#15990] / [i915#4423] / [i915#8708])
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-19/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-farfromfence-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-dg1:          [SKIP][406] ([i915#4423]) -> [SKIP][407]
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg1-13/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-draw-pwrite.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg1-17/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psrhdr-rgb101010-draw-pwrite:
    - shard-rkl:          [SKIP][408] ([i915#14544] / [i915#15102]) -> [SKIP][409] ([i915#15102]) +9 other tests skip
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_frontbuffer_tracking@psrhdr-rgb101010-draw-pwrite.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_frontbuffer_tracking@psrhdr-rgb101010-draw-pwrite.html

  * igt@kms_hdr@invalid-hdr:
    - shard-rkl:          [SKIP][410] ([i915#16012] / [i915#3555] / [i915#8228]) -> [SKIP][411] ([i915#14544] / [i915#3555] / [i915#8228])
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_hdr@invalid-hdr.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-rkl:          [SKIP][412] ([i915#15460]) -> [SKIP][413] ([i915#14544] / [i915#15460])
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_joiner@basic-big-joiner.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-rkl:          [SKIP][414] ([i915#14544] / [i915#15638] / [i915#15722]) -> [SKIP][415] ([i915#15638] / [i915#15722])
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][416] ([i915#15815]) -> [SKIP][417] ([i915#14544] / [i915#15815])
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-rkl:          [SKIP][418] ([i915#6301]) -> [SKIP][419] ([i915#14544] / [i915#6301]) +1 other test skip
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_panel_fitting@atomic-fastset.html
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier:
    - shard-rkl:          [SKIP][420] ([i915#15709]) -> [SKIP][421] ([i915#14544] / [i915#15709]) +1 other test skip
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier.html
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-ccs-modifier:
    - shard-rkl:          [SKIP][422] ([i915#14544] / [i915#15709]) -> [SKIP][423] ([i915#15709]) +2 other tests skip
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier.html
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-rkl:          [SKIP][424] ([i915#14259]) -> [SKIP][425] ([i915#14259] / [i915#14544])
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_plane_multiple@tiling-yf.html
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-c:
    - shard-rkl:          [SKIP][426] ([i915#15329]) -> [SKIP][427] ([i915#14544] / [i915#15329]) +3 other tests skip
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-c.html
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-c.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          [SKIP][428] ([i915#12343] / [i915#5354]) -> [SKIP][429] ([i915#12343] / [i915#14544] / [i915#5354])
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_pm_backlight@basic-brightness.html
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-rkl:          [SKIP][430] ([i915#14544] / [i915#15948]) -> [SKIP][431] ([i915#15948])
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_pm_dc@dc5-psr.html
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          [SKIP][432] ([i915#9340]) -> [SKIP][433] ([i915#3828])
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-rkl:          [SKIP][434] ([i915#15073]) -> [SKIP][435] ([i915#14544] / [i915#15073])
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp.html
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][436] ([i915#11520] / [i915#14544]) -> [SKIP][437] ([i915#11520]) +2 other tests skip
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-rkl:          [SKIP][438] ([i915#11520]) -> [SKIP][439] ([i915#11520] / [i915#14544]) +2 other tests skip
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          [SKIP][440] ([i915#9683]) -> [SKIP][441] ([i915#14544] / [i915#9683])
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_psr2_su@page_flip-p010.html
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-rkl:          [SKIP][442] ([i915#1072] / [i915#9732]) -> [SKIP][443] ([i915#1072] / [i915#14544] / [i915#9732]) +13 other tests skip
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_psr@psr-sprite-plane-onoff.html
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_psr@psr2-sprite-mmap-cpu:
    - shard-rkl:          [SKIP][444] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][445] ([i915#1072] / [i915#9732]) +6 other tests skip
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_psr@psr2-sprite-mmap-cpu.html
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@kms_psr@psr2-sprite-mmap-cpu.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg2:          [SKIP][446] ([i915#15867] / [i915#5190]) -> [SKIP][447] ([i915#12755] / [i915#15867] / [i915#5190])
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-dg2-10/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-dg2-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-rkl:          [SKIP][448] ([i915#3555]) -> [SKIP][449] ([i915#14544] / [i915#3555]) +2 other tests skip
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_scaling_modes@scaling-mode-none.html
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-rkl:          [SKIP][450] ([i915#14544] / [i915#3555]) -> [SKIP][451] ([i915#3555]) +2 other tests skip
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_setmode@basic-clone-single-crtc.html
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-rkl:          [SKIP][452] ([i915#14544] / [i915#8623]) -> [SKIP][453] ([i915#8623])
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@kms_tiled_display@basic-test-pattern.html
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_vrr@lobf:
    - shard-rkl:          [SKIP][454] ([i915#11920]) -> [SKIP][455] ([i915#11920] / [i915#14544])
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@kms_vrr@lobf.html
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_vrr@lobf.html

  * igt@kms_vrr@max-min:
    - shard-rkl:          [SKIP][456] ([i915#9906]) -> [SKIP][457] ([i915#14544] / [i915#9906])
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@kms_vrr@max-min.html
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@kms_vrr@max-min.html

  * igt@perf@mi-rpc:
    - shard-rkl:          [SKIP][458] ([i915#2434]) -> [SKIP][459] ([i915#14544] / [i915#2434])
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-4/igt@perf@mi-rpc.html
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@perf@mi-rpc.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-rkl:          [SKIP][460] ([i915#14544] / [i915#2435]) -> [SKIP][461] ([i915#2435])
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@perf@per-context-mode-unprivileged.html
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-5/igt@perf@per-context-mode-unprivileged.html

  * igt@prime_vgem@basic-read:
    - shard-rkl:          [SKIP][462] ([i915#3291] / [i915#3708]) -> [SKIP][463] ([i915#14544] / [i915#3291] / [i915#3708])
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@prime_vgem@basic-read.html
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-write:
    - shard-rkl:          [SKIP][464] ([i915#14544] / [i915#3291] / [i915#3708]) -> [SKIP][465] ([i915#3291] / [i915#3708])
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@prime_vgem@basic-write.html
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-7/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@fence-write-hang:
    - shard-rkl:          [SKIP][466] ([i915#3708]) -> [SKIP][467] ([i915#14544] / [i915#3708])
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@prime_vgem@fence-write-hang.html
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@enable-vfs-autoprobe-off:
    - shard-rkl:          [SKIP][468] ([i915#14544] / [i915#9917]) -> [SKIP][469] ([i915#9917])
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-6/igt@sriov_basic@enable-vfs-autoprobe-off.html
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-2/igt@sriov_basic@enable-vfs-autoprobe-off.html

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - shard-rkl:          [SKIP][470] ([i915#9917]) -> [SKIP][471] ([i915#14544] / [i915#9917]) +1 other test skip
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18660/shard-rkl-2/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/shard-rkl-6/igt@sriov_basic@enable-vfs-autoprobe-on.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
  [i915#11965]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11965
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12469
  [i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12756]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12756
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
  [i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
  [i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
  [i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
  [i915#13409]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13409
  [i915#13476]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13476
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#14888]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14888
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15342
  [i915#15420]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15420
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15479]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15479
  [i915#15481]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15481
  [i915#15500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15500
  [i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
  [i915#15638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15638
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15662]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15662
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15722]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15722
  [i915#15733]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15733
  [i915#15739]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15739
  [i915#15778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15778
  [i915#15815]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15815
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15867
  [i915#15895]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15895
  [i915#15931]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15931
  [i915#15948]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15948
  [i915#15989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15989
  [i915#15990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15990
  [i915#15991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15991
  [i915#16011]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16011
  [i915#16012]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16012
  [i915#16025]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16025
  [i915#16066]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16066
  [i915#16081]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16081
  [i915#16182]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16182
  [i915#16184]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16184
  [i915#16348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16348
  [i915#16361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16361
  [i915#16386]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16386
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
  [i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
  [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9561
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_18660 -> Patchwork_162622v4

  CI-20190529: 20190529
  CI_DRM_18660: e9f46237d19eab8041730860e800d92007c3bc7b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8958: 8958
  Patchwork_162622v4: e9f46237d19eab8041730860e800d92007c3bc7b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_162622v4/index.html

[-- Attachment #2: Type: text/html, Size: 164101 bytes --]

RE: [PATCH v4 01/12] drm/i915/dip: Add new file to handle Data Island Packet hardware

[Kandpal, Suraj]

> Subject: [PATCH v4 01/12] drm/i915/dip: Add new file to handle Data Island
> Packet hardware
> 
> Add new files intel_dip.c, intel_dip.h, and intel_dip_regs.h to handle low level
> hardware programming related to Data Island Packets.
> 
> Currently only programming of the Transmission Line for HDMI 2.1 Extended
> Metadata Packet (EMP) and DP Adaptive-Sync Secondary Data Packet (SDP) is
> added (MMIO register EMP_AS_SDP_TL).
> 
> This will serve as a common place for DIP related code, which is currently
> scattered across DP and HDMI files. A TODO has been added for extracting the
> remaining DIP helpers.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/Makefile                 |  1 +
>  drivers/gpu/drm/i915/display/intel_dip.c      | 39 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dip.h      | 38 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_dip_regs.h | 17 ++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.c      |  1 +
>  drivers/gpu/drm/i915/display/intel_vrr_regs.h |  6 ---
>  drivers/gpu/drm/xe/Makefile                   |  1 +
>  7 files changed, 97 insertions(+), 6 deletions(-)  create mode 100644
> drivers/gpu/drm/i915/display/intel_dip.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_dip.h
>  create mode 100644 drivers/gpu/drm/i915/display/intel_dip_regs.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 07802a7f4ce5..04624d35447c 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -349,6 +349,7 @@ i915-y += \
>  	display/intel_cx0_phy.o \
>  	display/intel_ddi.o \
>  	display/intel_ddi_buf_trans.o \
> +	display/intel_dip.o \
>  	display/intel_display_device.o \
>  	display/intel_display_trace.o \
>  	display/intel_dkl_phy.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.c
> b/drivers/gpu/drm/i915/display/intel_dip.c
> new file mode 100644
> index 000000000000..2e2bdb2b199c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dip.c
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + *
> + */
> +
> +#include "intel_de.h"
> +#include "intel_dip.h"
> +#include "intel_dip_regs.h"
> +#include "intel_display_types.h"
> +
> +u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 val;
> +
> +	if (!HAS_EMP_AS_SDP_TL(display))
> +		return 0;
> +
> +	val = intel_de_read(display, EMP_AS_SDP_TL(display, cpu_transcoder));
> +	return REG_FIELD_GET(EMP_AS_SDP_DB_TL_MASK, val); }
> +
> +void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +
> +	if (!HAS_EMP_AS_SDP_TL(display))
> +		return;
> +	/*
> +	 * Since currently we support VRR only for DP/eDP, so this is
> programmed
> +	 * only for Adaptive Sync SDP to Vsync start.
> +	 */
> +	intel_de_write(display,
> +		       EMP_AS_SDP_TL(display, cpu_transcoder),
> +		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h
> b/drivers/gpu/drm/i915/display/intel_dip.h
> new file mode 100644
> index 000000000000..25bae4a04d6b
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dip.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DIP_H__
> +#define __INTEL_DIP_H__
> +
> +#include "intel_display_device.h"
> +
> +/*
> + * Video DIP (Data Island Packet) helpers.
> + *
> + * This file contains helpers for programming video DIP related hardware.
> + *
> + * TODO: Currently, this is only used for programming EMP_AS_SDP_TL
> +i.e. to
> + * program Transmission Line for HDMI 2.1 Extended Metadata Packet
> +(EMP) and
> + * DP Adaptive Sync (AS) Secondary Data Packet (SDP). However, all low
> +level
> + * DIP buffer read/write and related helpers should be extracted here later.
> + */
> +
> +struct intel_crtc_state;
> +
> +/*
> + * EMP AS SDP TL: Extended Metadata Packet (EMP) Adaptive Sync (AS)
> + * Secondary Data Packet (SDP) Transmission Line (TL).
> + *
> + * Starting with BMG (display ver 14.01) and LNL+ (display ver 20+),
> + * the AS SDP transmission line is programmable via the EMP AS SDP TL
> + * register.
> + */
> +#define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display)
> == 1401 || \
> +					 DISPLAY_VER(__display) >= 20)
> +
> +u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state
> +*crtc_state); void intel_dip_write_emp_as_sdp_tl(const struct
> +intel_crtc_state *crtc_state);
> +
> +#endif /* __INTEL_DIP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dip_regs.h
> b/drivers/gpu/drm/i915/display/intel_dip_regs.h
> new file mode 100644
> index 000000000000..85dcbf42e77d
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dip_regs.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DIP_REGS_H__
> +#define __INTEL_DIP_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +/* EMP (Extended Metadata Packet) AS (Adaptive Sync) SDP Transmission Line
> */
> +#define _EMP_AS_SDP_TL_A			0x60204
> +#define EMP_AS_SDP_TL(display, trans)
> 	_MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)
> +#define   EMP_AS_SDP_DB_TL_MASK			REG_GENMASK(12, 0)
> +#define   EMP_AS_SDP_DB_TL(db_transmit_line)
> 	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
> +
> +#endif /* __INTEL_DIP_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index e03b5daac5be..6130854a706c 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -9,6 +9,7 @@
>  #include "intel_alpm.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
> +#include "intel_dip_regs.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
>  #include "intel_dmc.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index 9d4d6573a149..ba8631cbc672 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -174,12 +174,6 @@
>  #define   VRR_VSYNC_START_MASK			REG_GENMASK(12, 0)
>  #define   VRR_VSYNC_START(vsync_start)
> 	REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
> 
> -/* Common register for HDMI EMP and DP AS SDP */
> -#define _EMP_AS_SDP_TL_A			0x60204
> -#define EMP_AS_SDP_TL(display, trans)
> 	_MMIO_TRANS2((display), (trans), _EMP_AS_SDP_TL_A)
> -#define   EMP_AS_SDP_DB_TL_MASK			REG_GENMASK(12, 0)
> -#define   EMP_AS_SDP_DB_TL(db_transmit_line)
> 	REG_FIELD_PREP(EMP_AS_SDP_DB_TL_MASK, (db_transmit_line))
> -
>  #define _TRANS_CMRR_M_LO_A			0x604F0
>  #define TRANS_CMRR_M_LO(display, trans)
> 	_MMIO_TRANS2((display), (trans), _TRANS_CMRR_M_LO_A)
> 
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index
> 09661f079d03..9e826d164951 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -256,6 +256,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>  	i915-display/intel_ddi.o \
>  	i915-display/intel_ddi_buf_trans.o \
>  	i915-display/intel_de.o \
> +	i915-display/intel_dip.o \
>  	i915-display/intel_display.o \
>  	i915-display/intel_display_conversion.o \
>  	i915-display/intel_display_device.o \
> --
> 2.45.2

RE: [PATCH v4 02/12] drm/i915/vrr: Use the helper to write EMP_AS_SDP_TL register

[Kandpal, Suraj]

> Subject: [PATCH v4 02/12] drm/i915/vrr: Use the helper to write
> EMP_AS_SDP_TL register
> 
> Now that intel_dip_write_emp_as_sdp_tl() exists, use it instead of the open-
> coded EMP_AS_SDP_TL programming sequence in
> intel_vrr_set_transcoder_timings().
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++------------
>  1 file changed, 2 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 6130854a706c..a3dfeaa12e8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -9,7 +9,7 @@
>  #include "intel_alpm.h"
>  #include "intel_crtc.h"
>  #include "intel_de.h"
> -#include "intel_dip_regs.h"
> +#include "intel_dip.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
>  #include "intel_dmc.h"
> @@ -658,17 +658,7 @@ void intel_vrr_set_transcoder_timings(const struct
> intel_crtc_state *crtc_state)
>  			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
>  			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
> 
> -	/*
> -	 * For BMG and LNL+ onwards the EMP_AS_SDP_TL is used for
> programming
> -	 * double buffering point and transmission line for VRR packets for
> -	 * HDMI2.1/DP/eDP/DP->HDMI2.1 PCON.
> -	 * Since currently we support VRR only for DP/eDP, so this is
> programmed
> -	 * to for Adaptive Sync SDP to Vsync start.
> -	 */
> -	if (DISPLAY_VERx100(display) == 1401 || DISPLAY_VER(display) >= 20)
> -		intel_de_write(display,
> -			       EMP_AS_SDP_TL(display, cpu_transcoder),
> -			       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> +	intel_dip_write_emp_as_sdp_tl(crtc_state);
>  }
> 
>  void
> --
> 2.45.2

RE: [PATCH v4 03/12] drm/i915/intel_dip: Add check for DP encoder

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ankit
> Nautiyal
> Sent: Thursday, June 11, 2026 1:03 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Murthy, Arun R <arun.r.murthy@intel.com>;
> jani.nikula@linux.intel.com; Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Subject: [PATCH v4 03/12] drm/i915/intel_dip: Add check for DP encoder
> 
> At the moment, the common register for programming Transmission line for
> Extended Metadata Packet and Adaptive-Sync Secondary Data Packet
> (EMP_AS_SDP_TL) is only used to program Adaptive-Sync SDP (AS SDP).
> 
> Since VRR and Video Timing Extended Metadat Packet (VTEMP) are not yet
> implemented for HDMI, add an explicit check to write the register only for DP
> encoders (that may use AS SDP) and reset the register for non-DP encoders.
> 
> In subsequent changes, instead of directly writing the value, appropriate helpers
> will be called, that will supply the transmission line for these packets.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dip.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.c
> b/drivers/gpu/drm/i915/display/intel_dip.c
> index 2e2bdb2b199c..450a599b5053 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.c
> +++ b/drivers/gpu/drm/i915/display/intel_dip.c
> @@ -26,14 +26,19 @@ void intel_dip_write_emp_as_sdp_tl(const struct
> intel_crtc_state *crtc_state)  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	u32 transmission_line = 0;
> 
>  	if (!HAS_EMP_AS_SDP_TL(display))
>  		return;
>  	/*
> -	 * Since currently we support VRR only for DP/eDP, so this is
> programmed
> -	 * only for Adaptive Sync SDP to Vsync start.
> +	 * Since currently we support VRR only for DP/eDP, program the register
> +	 * for Adaptive Sync SDP using vsync start. For non-DP encoders,
> +	 * the register is reset to 0.

Nit: Since we currently

Otherwise LGTM
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

  	 */
> +	if (intel_crtc_has_dp_encoder(crtc_state))
> +		transmission_line = crtc_state->vrr.vsync_start;
> +
>  	intel_de_write(display,
>  		       EMP_AS_SDP_TL(display, cpu_transcoder),
> -		       EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start));
> +		       EMP_AS_SDP_DB_TL(transmission_line));
>  }
> --
> 2.45.2

RE: [PATCH v4 04/12] drm/i915/dp: Add helper to get AS SDP Transmission Line

[Kandpal, Suraj]

> Subject: [PATCH v4 04/12] drm/i915/dp: Add helper to get AS SDP Transmission
> Line
> 
> Introduce a DP helper to compute the Adaptive Sync SDP transmission line and
> use it when programming the EMP_AS_SDP_TL register.
> 
> Currently the AS SDP transmission line is programmed to the T1 position.
> This can be extended in the future to support programming the T2 position as
> well.
> 
> While at it, improve the documentation: the AS SDP transmission line
> corresponds to the T1 position, which maps to the start of the VSYNC pulse.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dip.c |  7 ++++---
> drivers/gpu/drm/i915/display/intel_dp.c  | 12 ++++++++++++
> drivers/gpu/drm/i915/display/intel_dp.h  |  1 +
>  3 files changed, 17 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.c
> b/drivers/gpu/drm/i915/display/intel_dip.c
> index 450a599b5053..504a2edadd0e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.c
> +++ b/drivers/gpu/drm/i915/display/intel_dip.c
> @@ -8,6 +8,7 @@
>  #include "intel_dip.h"
>  #include "intel_dip_regs.h"
>  #include "intel_display_types.h"
> +#include "intel_dp.h"
> 
>  u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state)  {
> @@ -32,11 +33,11 @@ void intel_dip_write_emp_as_sdp_tl(const struct
> intel_crtc_state *crtc_state)
>  		return;
>  	/*
>  	 * Since currently we support VRR only for DP/eDP, program the register
> -	 * for Adaptive Sync SDP using vsync start. For non-DP encoders,
> -	 * the register is reset to 0.
> +	 * for Adaptive Sync SDP. For non-DP encoders, the register is reset
> +	 * to 0.
>  	 */
>  	if (intel_crtc_has_dp_encoder(crtc_state))
> -		transmission_line = crtc_state->vrr.vsync_start;
> +		transmission_line =
> +intel_dp_get_as_sdp_transmission_line(crtc_state);
> 
>  	intel_de_write(display,
>  		       EMP_AS_SDP_TL(display, cpu_transcoder), diff --git
> a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 3569e61e7fee..f54f7faf878f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7465,3 +7465,15 @@ void intel_dp_link_cleanup(struct intel_dp
> *intel_dp)  {
>  	intel_dp_link_training_cleanup(intel_dp->link.training);
>  }
> +
> +int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state
> +*crtc_state) {
> +	/*
> +	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
> +	 * Transmission Line, which corresponds to the start of the
> +	 * VSYNC pulse.
> +	 *
> +	 * Use the T1 position for now.
> +	 */
> +	return crtc_state->vrr.vsync_start;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index 92ce04852326..fc80b5b64785 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -238,6 +238,7 @@ bool intel_dp_joiner_candidate_valid(struct
> intel_connector *connector,
>  		for_each_if(intel_dp_joiner_candidate_valid(__connector,
> (__mode)->hdisplay, __num_joined_pipes))
> 
>  u8 intel_dp_as_sdp_transmission_time(void);
> +int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state
> +*crtc_state);
> 
>  int intel_dp_link_init(struct intel_dp *intel_dp);  void
> intel_dp_link_cleanup(struct intel_dp *intel_dp);
> --
> 2.45.2

RE: [PATCH v4 05/12] drm/i915/display: Add crtc state for DIP transmission lines

[Kandpal, Suraj]

> Subject: [PATCH v4 05/12] drm/i915/display: Add crtc state for DIP transmission
> lines
> 
> The Adaptive Sync SDP is currently the only packet with a programmable
> transmission line.
> 
> Make a structure struct intel_dip for Data Island Packets. Add a member to
> track Adaptive-Sync SDP transmission line. Include the new member in the pipe
> configuration comparison.
> 
> This will pave the way for supporting more packets' programmable transmission
> lines, including the common base SDP transmission line introduced with
> Xe3p_lpd.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dip.h           | 8 ++++++++
>  drivers/gpu/drm/i915/display/intel_display.c       | 2 ++
>  drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
>  3 files changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h
> b/drivers/gpu/drm/i915/display/intel_dip.h
> index 25bae4a04d6b..37507ac3e645 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.h
> +++ b/drivers/gpu/drm/i915/display/intel_dip.h
> @@ -35,4 +35,12 @@ struct intel_crtc_state;
>  u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
> void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
> 
> +struct intel_dip {
> +	/*
> +	 * DIP Transmission line, relative to the Vtotal.
> +	 * The programmed transmit line is (Vtotal - value)
> +	 */
> +	u16 emp_as_sdp_tl;
> +};
> +
>  #endif /* __INTEL_DIP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index bdf02b67c1d8..c84ee0e865ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5507,6 +5507,8 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
> 
>  	PIPE_CONF_CHECK_I(set_context_latency);
> 
> +	PIPE_CONF_CHECK_I(dip.emp_as_sdp_tl);
> +
>  #undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
>  #undef PIPE_CONF_CHECK_LLI
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index aa4772a1c208..6cc3a4c2f17c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -46,6 +46,7 @@
> 
>  #include "i915_gtt_view_types.h"
>  #include "intel_bios.h"
> +#include "intel_dip.h"
>  #include "intel_display.h"
>  #include "intel_display_conversion.h"
>  #include "intel_display_limits.h"
> @@ -1301,6 +1302,8 @@ struct intel_crtc_state {
>  		struct drm_dp_as_sdp as_sdp;
>  	} infoframes;
> 
> +	struct intel_dip dip;
> +
>  	u8 eld[MAX_ELD_BYTES];
> 
>  	/* HDMI scrambling status */
> --
> 2.45.2

RE: [PATCH v4 06/12] drm/i915/dip: Store and use AS SDP transmission line from crtc state

[Kandpal, Suraj]

> Subject: [PATCH v4 06/12] drm/i915/dip: Store and use AS SDP transmission line
> from crtc state
> 
> The driver currently computes the Adaptive Sync SDP transmission line directly
> at programming time. Instead, compute and store the AS SDP transmission line
> in the crtc state and use it when programming the EMP_AS_SDP_TL register.
> 
> We get the clear picture about the SDPs and guardband only in
> intel_dp_sdp_compute_config_late() therefore we must configure the AS SDP
> transmission line at this point when AS SDP is enabled in crtc_state.
> 
> This prepares the ground for supporting programmable transmission lines for
> additional DP SDPs.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |  2 ++
> drivers/gpu/drm/i915/display/intel_dip.c | 20 +++++++++++---------
> drivers/gpu/drm/i915/display/intel_dip.h |  3 +++
> drivers/gpu/drm/i915/display/intel_dp.c  | 11 +++++++++++
>  4 files changed, 27 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 6399b16405c8..d2edfad295d5 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -49,6 +49,7 @@
>  #include "intel_ddi.h"
>  #include "intel_ddi_buf_trans.h"
>  #include "intel_de.h"
> +#include "intel_dip.h"
>  #include "intel_display_power.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> @@ -4215,6 +4216,7 @@ static void intel_ddi_get_config(struct intel_encoder
> *encoder,
>  	intel_read_dp_sdp(encoder, pipe_config,
> HDMI_PACKET_TYPE_GAMUT_METADATA);
>  	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>  	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
> +	intel_dip_sdp_transmission_line_get_config(pipe_config);
> 
>  	intel_audio_codec_get_config(encoder, pipe_config);  } diff --git
> a/drivers/gpu/drm/i915/display/intel_dip.c
> b/drivers/gpu/drm/i915/display/intel_dip.c
> index 504a2edadd0e..333314637db5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.c
> +++ b/drivers/gpu/drm/i915/display/intel_dip.c
> @@ -27,19 +27,21 @@ void intel_dip_write_emp_as_sdp_tl(const struct
> intel_crtc_state *crtc_state)  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> -	u32 transmission_line = 0;
> 
>  	if (!HAS_EMP_AS_SDP_TL(display))
>  		return;
> -	/*
> -	 * Since currently we support VRR only for DP/eDP, program the register
> -	 * for Adaptive Sync SDP. For non-DP encoders, the register is reset
> -	 * to 0.
> -	 */
> -	if (intel_crtc_has_dp_encoder(crtc_state))
> -		transmission_line =
> intel_dp_get_as_sdp_transmission_line(crtc_state);
> 
>  	intel_de_write(display,
>  		       EMP_AS_SDP_TL(display, cpu_transcoder),
> -		       EMP_AS_SDP_DB_TL(transmission_line));
> +		       EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl));
> +}
> +
> +void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state
> +*crtc_state) {
> +	crtc_state->dip.emp_as_sdp_tl =
> +intel_dp_get_as_sdp_transmission_line(crtc_state);
> +}
> +
> +void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state
> +*crtc_state) {
> +	crtc_state->dip.emp_as_sdp_tl =
> +intel_dip_read_emp_as_sdp_tl(crtc_state);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h
> b/drivers/gpu/drm/i915/display/intel_dip.h
> index 37507ac3e645..600dabbf7372 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.h
> +++ b/drivers/gpu/drm/i915/display/intel_dip.h
> @@ -43,4 +43,7 @@ struct intel_dip {
>  	u16 emp_as_sdp_tl;
>  };
> 
> +void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state
> +*crtc_state); void intel_dip_sdp_transmission_line_get_config(struct
> +intel_crtc_state *crtc_state);
> +
>  #endif /* __INTEL_DIP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index f54f7faf878f..e143ec1b76d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -7356,6 +7356,8 @@ int intel_dp_sdp_compute_config_late(struct
> intel_crtc_state *crtc_state)
>  		return -EINVAL;
>  	}
> 
> +	intel_dip_sdp_tl_compute_config_late(crtc_state);
> +
>  	return 0;
>  }
> 
> @@ -7468,6 +7470,15 @@ void intel_dp_link_cleanup(struct intel_dp
> *intel_dp)
> 
>  int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state
> *crtc_state)  {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (!HAS_EMP_AS_SDP_TL(display))
> +		return 0;
> +
> +	if (!(crtc_state->infoframes.enable &
> +	      intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)))
> +		return 0;
> +

this part should not be a part of this maybe can be squashed with 4th patch where this function was introduced

Regards,
Suraj Kandpal

>  	/*
>  	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
>  	 * Transmission Line, which corresponds to the start of the
> --
> 2.45.2

RE: [PATCH v4 08/12] drm/i915/display: Add HAS_COMMON_SDP_TL macro

[Kandpal, Suraj]

> Subject: [PATCH v4 08/12] drm/i915/display: Add HAS_COMMON_SDP_TL
> macro
> 

Maybe drm/i915/dip

Otherwise LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> Add a helper macro to detect CMN SDP TL support on platforms with display
> version 35 and above.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dip.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h
> b/drivers/gpu/drm/i915/display/intel_dip.h
> index 600dabbf7372..e9959356226e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.h
> +++ b/drivers/gpu/drm/i915/display/intel_dip.h
> @@ -32,6 +32,16 @@ struct intel_crtc_state;
>  #define HAS_EMP_AS_SDP_TL(__display)	(DISPLAY_VERx100(__display)
> == 1401 || \
>  					 DISPLAY_VER(__display) >= 20)
> 
> +/*
> + * CMN SDP TL: Common Secondary Data Packet Transmission Line.
> + *
> + * Xe3p_lpd introduces new register CMN_SDP_TL to program a common SDP
> + * Transmission line that will be used by the Hardware to position the
> + * SDPs. Along with this, another new register CMN_SDP_TL_STGR_CTL is
> + * also added to stagger the different SDPs.
> + */
> +#define HAS_COMMON_SDP_TL(__display)      (DISPLAY_VER(__display) >= 35)
> +
>  u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
> void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
> 
> --
> 2.45.2

RE: [PATCH v4 09/12] drm/i915/dp: Store SDP transmission lines in crtc_state

[Kandpal, Suraj]

> Subject: [PATCH v4 09/12] drm/i915/dp: Store SDP transmission lines in
> crtc_state

This needs to be either drm/i915/dip or drm/i915/display

> 
> Currently the driver only programs the transmission line for the Adaptive-Sync
> SDP, while the hardware controls the transmission lines for other SDPs.
> 
> Starting with Xe3p_lpd, the hardware allows the driver to program transmission
> lines for additional DP SDPs. Prepare for this by adding fields to struct
> intel_crtc_state to store SDP transmission lines, and include them in pipe config
> comparison.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dip.h     | 6 ++++++
>  drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h
> b/drivers/gpu/drm/i915/display/intel_dip.h
> index e9959356226e..03ef749a79ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.h
> +++ b/drivers/gpu/drm/i915/display/intel_dip.h
> @@ -51,6 +51,12 @@ struct intel_dip {
>  	 * The programmed transmit line is (Vtotal - value)
>  	 */
>  	u16 emp_as_sdp_tl;
> +	u16 gmp_sdp_tl;
> +	u16 pps_sdp_tl;
> +	u16 vsc_sdp_tl;
> +	u16 vsc_ext_sdp_tl;
> +	/* Common SDP Base transmission line (Xe3p_lpd+) */
> +	u16 cmn_sdp_tl;
>  };
> 
>  void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index c84ee0e865ee..8807897538a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5508,6 +5508,11 @@ intel_pipe_config_compare(const struct
> intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_I(set_context_latency);
> 
>  	PIPE_CONF_CHECK_I(dip.emp_as_sdp_tl);
> +	PIPE_CONF_CHECK_I(dip.gmp_sdp_tl);
> +	PIPE_CONF_CHECK_I(dip.pps_sdp_tl);
> +	PIPE_CONF_CHECK_I(dip.vsc_sdp_tl);
> +	PIPE_CONF_CHECK_I(dip.vsc_ext_sdp_tl);
> +	PIPE_CONF_CHECK_I(dip.cmn_sdp_tl);

If you doing a compare in this patch itself should maybe assigning all these variables some values in comute config too in this patch too.

Regards,
Suraj Kandpal

> 
>  #undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
> --
> 2.45.2

Re: [PATCH v4 06/12] drm/i915/dip: Store and use AS SDP transmission line from crtc state

[Nautiyal, Ankit K]

On 9/1/2026 8:33 AM, Kandpal, Suraj wrote:
>> Subject: [PATCH v4 06/12] drm/i915/dip: Store and use AS SDP transmission line
>> from crtc state
>>
>> The driver currently computes the Adaptive Sync SDP transmission line directly
>> at programming time. Instead, compute and store the AS SDP transmission line
>> in the crtc state and use it when programming the EMP_AS_SDP_TL register.
>>
>> We get the clear picture about the SDPs and guardband only in
>> intel_dp_sdp_compute_config_late() therefore we must configure the AS SDP
>> transmission line at this point when AS SDP is enabled in crtc_state.
>>
>> This prepares the ground for supporting programmable transmission lines for
>> additional DP SDPs.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_ddi.c |  2 ++
>> drivers/gpu/drm/i915/display/intel_dip.c | 20 +++++++++++---------
>> drivers/gpu/drm/i915/display/intel_dip.h |  3 +++
>> drivers/gpu/drm/i915/display/intel_dp.c  | 11 +++++++++++
>>   4 files changed, 27 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 6399b16405c8..d2edfad295d5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -49,6 +49,7 @@
>>   #include "intel_ddi.h"
>>   #include "intel_ddi_buf_trans.h"
>>   #include "intel_de.h"
>> +#include "intel_dip.h"
>>   #include "intel_display_power.h"
>>   #include "intel_display_regs.h"
>>   #include "intel_display_types.h"
>> @@ -4215,6 +4216,7 @@ static void intel_ddi_get_config(struct intel_encoder
>> *encoder,
>>   	intel_read_dp_sdp(encoder, pipe_config,
>> HDMI_PACKET_TYPE_GAMUT_METADATA);
>>   	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
>>   	intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC);
>> +	intel_dip_sdp_transmission_line_get_config(pipe_config);
>>
>>   	intel_audio_codec_get_config(encoder, pipe_config);  } diff --git
>> a/drivers/gpu/drm/i915/display/intel_dip.c
>> b/drivers/gpu/drm/i915/display/intel_dip.c
>> index 504a2edadd0e..333314637db5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dip.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dip.c
>> @@ -27,19 +27,21 @@ void intel_dip_write_emp_as_sdp_tl(const struct
>> intel_crtc_state *crtc_state)  {
>>   	struct intel_display *display = to_intel_display(crtc_state);
>>   	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> -	u32 transmission_line = 0;
>>
>>   	if (!HAS_EMP_AS_SDP_TL(display))
>>   		return;
>> -	/*
>> -	 * Since currently we support VRR only for DP/eDP, program the register
>> -	 * for Adaptive Sync SDP. For non-DP encoders, the register is reset
>> -	 * to 0.
>> -	 */
>> -	if (intel_crtc_has_dp_encoder(crtc_state))
>> -		transmission_line =
>> intel_dp_get_as_sdp_transmission_line(crtc_state);
>>
>>   	intel_de_write(display,
>>   		       EMP_AS_SDP_TL(display, cpu_transcoder),
>> -		       EMP_AS_SDP_DB_TL(transmission_line));
>> +		       EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl));
>> +}
>> +
>> +void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state
>> +*crtc_state) {
>> +	crtc_state->dip.emp_as_sdp_tl =
>> +intel_dp_get_as_sdp_transmission_line(crtc_state);
>> +}
>> +
>> +void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state
>> +*crtc_state) {
>> +	crtc_state->dip.emp_as_sdp_tl =
>> +intel_dip_read_emp_as_sdp_tl(crtc_state);
>>   }
>> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h
>> b/drivers/gpu/drm/i915/display/intel_dip.h
>> index 37507ac3e645..600dabbf7372 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dip.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dip.h
>> @@ -43,4 +43,7 @@ struct intel_dip {
>>   	u16 emp_as_sdp_tl;
>>   };
>>
>> +void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state
>> +*crtc_state); void intel_dip_sdp_transmission_line_get_config(struct
>> +intel_crtc_state *crtc_state);
>> +
>>   #endif /* __INTEL_DIP_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index f54f7faf878f..e143ec1b76d0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -7356,6 +7356,8 @@ int intel_dp_sdp_compute_config_late(struct
>> intel_crtc_state *crtc_state)
>>   		return -EINVAL;
>>   	}
>>
>> +	intel_dip_sdp_tl_compute_config_late(crtc_state);
>> +
>>   	return 0;
>>   }
>>
>> @@ -7468,6 +7470,15 @@ void intel_dp_link_cleanup(struct intel_dp
>> *intel_dp)
>>
>>   int intel_dp_get_as_sdp_transmission_line(const struct intel_crtc_state
>> *crtc_state)  {
>> +	struct intel_display *display = to_intel_display(crtc_state);
>> +
>> +	if (!HAS_EMP_AS_SDP_TL(display))
>> +		return 0;
>> +
>> +	if (!(crtc_state->infoframes.enable &
>> +	      intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC)))
>> +		return 0;
>> +
> this part should not be a part of this maybe can be squashed with 4th patch where this function was introduced

Agreed. Actually infoframe.enable check is not needed since we are 
computing the transmission line even if the packet is not sent. Since 
this is called only from DP/eDP compute config path now, for non-DP 
encoders it will not be set.

I will remove the check and move the HAS_EMP_AS_SDP_TL() check in 
patch#4 where it belongs.


Regards,

Ankit

>
> Regards,
> Suraj Kandpal
>
>>   	/*
>>   	 * EMP_AS_SDP_TL defines the T1 position as the default AS SDP
>>   	 * Transmission Line, which corresponds to the start of the
>> --
>> 2.45.2

Re: [PATCH v4 09/12] drm/i915/dp: Store SDP transmission lines in crtc_state

[Nautiyal, Ankit K]

On 9/1/2026 9:00 AM, Kandpal, Suraj wrote:
>> Subject: [PATCH v4 09/12] drm/i915/dp: Store SDP transmission lines in
>> crtc_state
> This needs to be either drm/i915/dip or drm/i915/display
>
>> Currently the driver only programs the transmission line for the Adaptive-Sync
>> SDP, while the hardware controls the transmission lines for other SDPs.
>>
>> Starting with Xe3p_lpd, the hardware allows the driver to program transmission
>> lines for additional DP SDPs. Prepare for this by adding fields to struct
>> intel_crtc_state to store SDP transmission lines, and include them in pipe config
>> comparison.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dip.h     | 6 ++++++
>>   drivers/gpu/drm/i915/display/intel_display.c | 5 +++++
>>   2 files changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h
>> b/drivers/gpu/drm/i915/display/intel_dip.h
>> index e9959356226e..03ef749a79ca 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dip.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dip.h
>> @@ -51,6 +51,12 @@ struct intel_dip {
>>   	 * The programmed transmit line is (Vtotal - value)
>>   	 */
>>   	u16 emp_as_sdp_tl;
>> +	u16 gmp_sdp_tl;
>> +	u16 pps_sdp_tl;
>> +	u16 vsc_sdp_tl;
>> +	u16 vsc_ext_sdp_tl;
>> +	/* Common SDP Base transmission line (Xe3p_lpd+) */
>> +	u16 cmn_sdp_tl;
>>   };
>>
>>   void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> b/drivers/gpu/drm/i915/display/intel_display.c
>> index c84ee0e865ee..8807897538a4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5508,6 +5508,11 @@ intel_pipe_config_compare(const struct
>> intel_crtc_state *current_config,
>>   	PIPE_CONF_CHECK_I(set_context_latency);
>>
>>   	PIPE_CONF_CHECK_I(dip.emp_as_sdp_tl);
>> +	PIPE_CONF_CHECK_I(dip.gmp_sdp_tl);
>> +	PIPE_CONF_CHECK_I(dip.pps_sdp_tl);
>> +	PIPE_CONF_CHECK_I(dip.vsc_sdp_tl);
>> +	PIPE_CONF_CHECK_I(dip.vsc_ext_sdp_tl);
>> +	PIPE_CONF_CHECK_I(dip.cmn_sdp_tl);
> If you doing a compare in this patch itself should maybe assigning all these variables some values in comute config too in this patch too.


If we assign the values in compute config without readout, it will 
result is mismatches.

So I have introduced the new members and added them to PIPE_CONF_CHECK 
without compute config part or readout part here. Both of these are 
added together in Patch#11.

Regards,

Ankit

>
> Regards,
> Suraj Kandpal
>
>>   #undef PIPE_CONF_CHECK_X
>>   #undef PIPE_CONF_CHECK_I
>> --
>> 2.45.2

Re: [PATCH v4 05/12] drm/i915/display: Add crtc state for DIP transmission lines

[Jani Nikula]

On Thu, 11 Jun 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> The Adaptive Sync SDP is currently the only packet with a programmable
> transmission line.
>
> Make a structure struct intel_dip for Data Island Packets. Add a member to
> track Adaptive-Sync SDP transmission line. Include the new member in the
> pipe configuration comparison.
>
> This will pave the way for supporting more packets' programmable
> transmission lines, including the common base SDP transmission line
> introduced with Xe3p_lpd.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dip.h           | 8 ++++++++
>  drivers/gpu/drm/i915/display/intel_display.c       | 2 ++
>  drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
>  3 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
> index 25bae4a04d6b..37507ac3e645 100644
> --- a/drivers/gpu/drm/i915/display/intel_dip.h
> +++ b/drivers/gpu/drm/i915/display/intel_dip.h
> @@ -35,4 +35,12 @@ struct intel_crtc_state;
>  u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
>  void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
>  
> +struct intel_dip {
> +	/*
> +	 * DIP Transmission line, relative to the Vtotal.
> +	 * The programmed transmit line is (Vtotal - value)
> +	 */
> +	u16 emp_as_sdp_tl;
> +};
> +
>  #endif /* __INTEL_DIP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index bdf02b67c1d8..c84ee0e865ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5507,6 +5507,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  	PIPE_CONF_CHECK_I(set_context_latency);
>  
> +	PIPE_CONF_CHECK_I(dip.emp_as_sdp_tl);
> +
>  #undef PIPE_CONF_CHECK_X
>  #undef PIPE_CONF_CHECK_I
>  #undef PIPE_CONF_CHECK_LLI
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index aa4772a1c208..6cc3a4c2f17c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -46,6 +46,7 @@
>  
>  #include "i915_gtt_view_types.h"
>  #include "intel_bios.h"
> +#include "intel_dip.h"

I understand the motivation, but I'd rather keep the struct here in
intel_display_types.h than blow up the includes. There are already too
many includes *and* this file is included just about everywhere.

The point is, if you change anything unrelated to struct intel_dip in
intel_dip.h, you'll end up rebuilding pretty much all the display code,
and it'll slow everyone down.

C really sucks at this. And embedding a lot of structs makes it worse.


BR,
Jani.



>  #include "intel_display.h"
>  #include "intel_display_conversion.h"
>  #include "intel_display_limits.h"
> @@ -1301,6 +1302,8 @@ struct intel_crtc_state {
>  		struct drm_dp_as_sdp as_sdp;
>  	} infoframes;
>  
> +	struct intel_dip dip;
> +
>  	u8 eld[MAX_ELD_BYTES];
>  
>  	/* HDMI scrambling status */

-- 
Jani Nikula, Intel

Re: [PATCH v4 05/12] drm/i915/display: Add crtc state for DIP transmission lines

[Nautiyal, Ankit K]

On 9/8/2026 9:05 PM, Jani Nikula wrote:
> On Thu, 11 Jun 2026, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
>> The Adaptive Sync SDP is currently the only packet with a programmable
>> transmission line.
>>
>> Make a structure struct intel_dip for Data Island Packets. Add a member to
>> track Adaptive-Sync SDP transmission line. Include the new member in the
>> pipe configuration comparison.
>>
>> This will pave the way for supporting more packets' programmable
>> transmission lines, including the common base SDP transmission line
>> introduced with Xe3p_lpd.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dip.h           | 8 ++++++++
>>   drivers/gpu/drm/i915/display/intel_display.c       | 2 ++
>>   drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
>>   3 files changed, 13 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h
>> index 25bae4a04d6b..37507ac3e645 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dip.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dip.h
>> @@ -35,4 +35,12 @@ struct intel_crtc_state;
>>   u16 intel_dip_read_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
>>   void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state);
>>   
>> +struct intel_dip {
>> +	/*
>> +	 * DIP Transmission line, relative to the Vtotal.
>> +	 * The programmed transmit line is (Vtotal - value)
>> +	 */
>> +	u16 emp_as_sdp_tl;
>> +};
>> +
>>   #endif /* __INTEL_DIP_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index bdf02b67c1d8..c84ee0e865ee 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5507,6 +5507,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>>   
>>   	PIPE_CONF_CHECK_I(set_context_latency);
>>   
>> +	PIPE_CONF_CHECK_I(dip.emp_as_sdp_tl);
>> +
>>   #undef PIPE_CONF_CHECK_X
>>   #undef PIPE_CONF_CHECK_I
>>   #undef PIPE_CONF_CHECK_LLI
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index aa4772a1c208..6cc3a4c2f17c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -46,6 +46,7 @@
>>   
>>   #include "i915_gtt_view_types.h"
>>   #include "intel_bios.h"
>> +#include "intel_dip.h"
> I understand the motivation, but I'd rather keep the struct here in
> intel_display_types.h than blow up the includes. There are already too
> many includes *and* this file is included just about everywhere.
>
> The point is, if you change anything unrelated to struct intel_dip in
> intel_dip.h, you'll end up rebuilding pretty much all the display code,
> and it'll slow everyone down.
>
> C really sucks at this. And embedding a lot of structs makes it worse.


Good point. I had not thought about this, though the pattern was always 
there, but it became clearer to me now.

I will move the structs to intel_display_types.h, and keep this in mind.

Thanks & Regards,
Ankit

>
>
> BR,
> Jani.
>
>
>
>>   #include "intel_display.h"
>>   #include "intel_display_conversion.h"
>>   #include "intel_display_limits.h"
>> @@ -1301,6 +1302,8 @@ struct intel_crtc_state {
>>   		struct drm_dp_as_sdp as_sdp;
>>   	} infoframes;
>>   
>> +	struct intel_dip dip;
>> +
>>   	u8 eld[MAX_ELD_BYTES];
>>   
>>   	/* HDMI scrambling status */