Re: [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup

Re: [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Matt Roper <
> matthew.d.roper@intel.com
> >
> 
> DG1 does some additional pcode/uncore handshaking at
> boot time; this handshaking must complete before various other pcode
> commands are effective and before general work is submitted to the GPU.
> We need to poll a new pcode mailbox during startup until it reports that
> this handshaking is complete.
> 
> The bspec doesn't give guidance on how long we may need to wait for this
> handshaking to complete.  For now, let's just set a really long timeout;
> if we still don't get a completion status by the end of that timeout,
> we'll just continue on and hope for the best.
> 
> Bspec: 52065
> Cc: Clinton Taylor <
> Clinton.A.Taylor@intel.com
> >
> Cc: Ville Syrjälä <
> ville.syrjala@linux.intel.com
> >
> Cc: Radhakrishna Sripada <
> radhakrishna.sripada@intel.com
> >
> Signed-off-by: Matt Roper <
> matthew.d.roper@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/i915_drv.c       |  3 +++
>  drivers/gpu/drm/i915/i915_reg.h       |  3 +++
>  drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/intel_sideband.h |  2 ++
>  4 files changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5fd5af4bc855..5473bfe9126c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -85,6 +85,7 @@
>  #include "intel_gvt.h"
>  #include "intel_memory_region.h"
>  #include "intel_pm.h"
> +#include "intel_sideband.h"
>  #include "vlv_suspend.h"
>  
>  static struct drm_driver driver;
> @@ -737,6 +738,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
>  	 */
>  	intel_dram_detect(dev_priv);
>  
> +	intel_pcode_init(dev_priv);
> +
>  	intel_bw_init_hw(dev_priv);
>  
>  	return 0;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0d31f3bf634..3767b32127da 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9245,6 +9245,9 @@ enum {
>  #define     GEN9_SAGV_DISABLE			0x0
>  #define     GEN9_SAGV_IS_DISABLED		0x1
>  #define     GEN9_SAGV_ENABLE			0x3
> +#define   DG1_PCODE_STATUS			0x7E
> +#define     DG1_CHECK_UNCORE_INIT_STATUS	0x0
> +#define     DG1_UNCORE_INIT_COMPLETE		0x1

With s/DG1_CHECK_UNCORE_INIT_STATUS/DG1_CHECK_UNCORE_INIT_STATUS_COMPLETE or something similar that makes easy to understand that 0x1 is the response
of the DG1_CHECK_UNCORE_INIT_STATUS sub-command.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


>  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
>  #define GEN6_PCODE_DATA				_MMIO(0x138128)
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 916ccd1c0e96..8b093525240d 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
>  	return ret ? ret : status;
>  #undef COND
>  }
> +
> +void intel_pcode_init(struct drm_i915_private *i915)
> +{
> +	int ret;
> +
> +	if (!IS_DGFX(i915))
> +		return;
> +
> +	ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
> +				DG1_CHECK_UNCORE_INIT_STATUS,
> +				DG1_UNCORE_INIT_COMPLETE,
> +				DG1_UNCORE_INIT_COMPLETE, 50);
> +	if (ret)
> +		drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
> +}
> diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
> index 7fb95745a444..094c7b19c5d4 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.h
> +++ b/drivers/gpu/drm/i915/intel_sideband.h
> @@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
>  int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
>  		      u32 reply_mask, u32 reply, int timeout_base_ms);
>  
> +void intel_pcode_init(struct drm_i915_private *i915);
> +
>  #endif /* _INTEL_SIDEBAND_H */
> 
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Re: [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup

[Lucas De Marchi]

On Mon, Aug 03, 2020 at 04:24:17PM -0700, Jose Souza wrote:
>On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
>> From: Matt Roper <
>> matthew.d.roper@intel.com
>> >
>>
>> DG1 does some additional pcode/uncore handshaking at
>> boot time; this handshaking must complete before various other pcode
>> commands are effective and before general work is submitted to the GPU.
>> We need to poll a new pcode mailbox during startup until it reports that
>> this handshaking is complete.
>>
>> The bspec doesn't give guidance on how long we may need to wait for this
>> handshaking to complete.  For now, let's just set a really long timeout;
>> if we still don't get a completion status by the end of that timeout,
>> we'll just continue on and hope for the best.
>>
>> Bspec: 52065
>> Cc: Clinton Taylor <
>> Clinton.A.Taylor@intel.com
>> >
>> Cc: Ville Syrjälä <
>> ville.syrjala@linux.intel.com
>> >
>> Cc: Radhakrishna Sripada <
>> radhakrishna.sripada@intel.com
>> >
>> Signed-off-by: Matt Roper <
>> matthew.d.roper@intel.com
>> >
>> Signed-off-by: Lucas De Marchi <
>> lucas.demarchi@intel.com
>> >
>> ---
>>  drivers/gpu/drm/i915/i915_drv.c       |  3 +++
>>  drivers/gpu/drm/i915/i915_reg.h       |  3 +++
>>  drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
>>  drivers/gpu/drm/i915/intel_sideband.h |  2 ++
>>  4 files changed, 23 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 5fd5af4bc855..5473bfe9126c 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -85,6 +85,7 @@
>>  #include "intel_gvt.h"
>>  #include "intel_memory_region.h"
>>  #include "intel_pm.h"
>> +#include "intel_sideband.h"
>>  #include "vlv_suspend.h"
>>
>>  static struct drm_driver driver;
>> @@ -737,6 +738,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
>>  	 */
>>  	intel_dram_detect(dev_priv);
>>
>> +	intel_pcode_init(dev_priv);
>> +
>>  	intel_bw_init_hw(dev_priv);
>>
>>  	return 0;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index a0d31f3bf634..3767b32127da 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9245,6 +9245,9 @@ enum {
>>  #define     GEN9_SAGV_DISABLE			0x0
>>  #define     GEN9_SAGV_IS_DISABLED		0x1
>>  #define     GEN9_SAGV_ENABLE			0x3
>> +#define   DG1_PCODE_STATUS			0x7E
>> +#define     DG1_CHECK_UNCORE_INIT_STATUS	0x0
>> +#define     DG1_UNCORE_INIT_COMPLETE		0x1
>
>With s/DG1_CHECK_UNCORE_INIT_STATUS/DG1_CHECK_UNCORE_INIT_STATUS_COMPLETE or something similar that makes easy to understand that 0x1 is the response
>of the DG1_CHECK_UNCORE_INIT_STATUS sub-command.

checking all the other users of skl_pcode_request() I don't see a
pattern there. Examples:

ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
                         SKL_CDCLK_PREPARE_FOR_CHANGE,     
                         SKL_CDCLK_READY_FOR_CHANGE,       
                         SKL_CDCLK_READY_FOR_CHANGE, 3);   

ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,            
                         GEN9_SAGV_DISABLE,                            
                         GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 
                         1);                                           

Giveng the current uses, I'd rather rename like:

+#define   DG1_PCODE_STATUS			0x7E
+#define     DG1_UNCORE_GET_INIT_STATUS		0x0
+#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1


>Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

does that still stands with the rename above?

thanks
Lucas De Marchi

>
>
>>  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
>>  #define GEN6_PCODE_DATA				_MMIO(0x138128)
>>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
>> index 916ccd1c0e96..8b093525240d 100644
>> --- a/drivers/gpu/drm/i915/intel_sideband.c
>> +++ b/drivers/gpu/drm/i915/intel_sideband.c
>> @@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
>>  	return ret ? ret : status;
>>  #undef COND
>>  }
>> +
>> +void intel_pcode_init(struct drm_i915_private *i915)
>> +{
>> +	int ret;
>> +
>> +	if (!IS_DGFX(i915))
>> +		return;
>> +
>> +	ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
>> +				DG1_CHECK_UNCORE_INIT_STATUS,
>> +				DG1_UNCORE_INIT_COMPLETE,
>> +				DG1_UNCORE_INIT_COMPLETE, 50);
>> +	if (ret)
>> +		drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
>> index 7fb95745a444..094c7b19c5d4 100644
>> --- a/drivers/gpu/drm/i915/intel_sideband.h
>> +++ b/drivers/gpu/drm/i915/intel_sideband.h
>> @@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
>>  int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
>>  		      u32 reply_mask, u32 reply, int timeout_base_ms);
>>
>> +void intel_pcode_init(struct drm_i915_private *i915);
>> +
>>  #endif /* _INTEL_SIDEBAND_H */
>>
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Re: [Intel-gfx] [PATCH v5 05/22] drm/i915/dg1: Wait for pcode/uncore handshake at startup

[Souza, Jose]

On Mon, 2020-08-24 at 12:24 -0700, Lucas De Marchi wrote:
> On Mon, Aug 03, 2020 at 04:24:17PM -0700, Jose Souza wrote:
> > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > From: Matt Roper <
> > > matthew.d.roper@intel.com
> > > 
> > > 
> > > DG1 does some additional pcode/uncore handshaking at
> > > boot time; this handshaking must complete before various other pcode
> > > commands are effective and before general work is submitted to the GPU.
> > > We need to poll a new pcode mailbox during startup until it reports that
> > > this handshaking is complete.
> > > 
> > > The bspec doesn't give guidance on how long we may need to wait for this
> > > handshaking to complete.  For now, let's just set a really long timeout;
> > > if we still don't get a completion status by the end of that timeout,
> > > we'll just continue on and hope for the best.
> > > 
> > > Bspec: 52065
> > > Cc: Clinton Taylor <
> > > Clinton.A.Taylor@intel.com
> > > 
> > > 
> > > Cc: Ville Syrjälä <
> > > ville.syrjala@linux.intel.com
> > > 
> > > 
> > > Cc: Radhakrishna Sripada <
> > > radhakrishna.sripada@intel.com
> > > 
> > > 
> > > Signed-off-by: Matt Roper <
> > > matthew.d.roper@intel.com
> > > 
> > > 
> > > Signed-off-by: Lucas De Marchi <
> > > lucas.demarchi@intel.com
> > > 
> > > 
> > > ---
> > >  drivers/gpu/drm/i915/i915_drv.c       |  3 +++
> > >  drivers/gpu/drm/i915/i915_reg.h       |  3 +++
> > >  drivers/gpu/drm/i915/intel_sideband.c | 15 +++++++++++++++
> > >  drivers/gpu/drm/i915/intel_sideband.h |  2 ++
> > >  4 files changed, 23 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index 5fd5af4bc855..5473bfe9126c 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -85,6 +85,7 @@
> > >  #include "intel_gvt.h"
> > >  #include "intel_memory_region.h"
> > >  #include "intel_pm.h"
> > > +#include "intel_sideband.h"
> > >  #include "vlv_suspend.h"
> > > 
> > >  static struct drm_driver driver;
> > > @@ -737,6 +738,8 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> > >  	 */
> > >  	intel_dram_detect(dev_priv);
> > > 
> > > +	intel_pcode_init(dev_priv);
> > > +
> > >  	intel_bw_init_hw(dev_priv);
> > > 
> > >  	return 0;
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index a0d31f3bf634..3767b32127da 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -9245,6 +9245,9 @@ enum {
> > >  #define     GEN9_SAGV_DISABLE			0x0
> > >  #define     GEN9_SAGV_IS_DISABLED		0x1
> > >  #define     GEN9_SAGV_ENABLE			0x3
> > > +#define   DG1_PCODE_STATUS			0x7E
> > > +#define     DG1_CHECK_UNCORE_INIT_STATUS	0x0
> > > +#define     DG1_UNCORE_INIT_COMPLETE		0x1
> > 
> > With s/DG1_CHECK_UNCORE_INIT_STATUS/DG1_CHECK_UNCORE_INIT_STATUS_COMPLETE or something similar that makes easy to understand that 0x1 is the response
> > of the DG1_CHECK_UNCORE_INIT_STATUS sub-command.
> 
> checking all the other users of skl_pcode_request() I don't see a
> pattern there. Examples:
> 
> ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
>                          SKL_CDCLK_PREPARE_FOR_CHANGE,     
>                          SKL_CDCLK_READY_FOR_CHANGE,       
>                          SKL_CDCLK_READY_FOR_CHANGE, 3);   
> 
> ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,            
>                          GEN9_SAGV_DISABLE,                            
>                          GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 
>                          1);                                           
> 
> Giveng the current uses, I'd rather rename like:
> 
> +#define   DG1_PCODE_STATUS			0x7E
> +#define     DG1_UNCORE_GET_INIT_STATUS		0x0
> +#define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
> 
> 
> > Reviewed-by: José Roberto de Souza <
> > jose.souza@intel.com
> > >
> 
> does that still stands with the rename above?

LGTM, keep it please.

> 
> thanks
> Lucas De Marchi
> 
> > 
> > >  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> > >  #define GEN6_PCODE_DATA				_MMIO(0x138128)
> > >  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
> > > diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> > > index 916ccd1c0e96..8b093525240d 100644
> > > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > > @@ -543,3 +543,18 @@ int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> > >  	return ret ? ret : status;
> > >  #undef COND
> > >  }
> > > +
> > > +void intel_pcode_init(struct drm_i915_private *i915)
> > > +{
> > > +	int ret;
> > > +
> > > +	if (!IS_DGFX(i915))
> > > +		return;
> > > +
> > > +	ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
> > > +				DG1_CHECK_UNCORE_INIT_STATUS,
> > > +				DG1_UNCORE_INIT_COMPLETE,
> > > +				DG1_UNCORE_INIT_COMPLETE, 50);
> > > +	if (ret)
> > > +		drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
> > > index 7fb95745a444..094c7b19c5d4 100644
> > > --- a/drivers/gpu/drm/i915/intel_sideband.h
> > > +++ b/drivers/gpu/drm/i915/intel_sideband.h
> > > @@ -138,4 +138,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
> > >  int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> > >  		      u32 reply_mask, u32 reply, int timeout_base_ms);
> > > 
> > > +void intel_pcode_init(struct drm_i915_private *i915);
> > > +
> > >  #endif /* _INTEL_SIDEBAND_H */
> > > 
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Re: [Intel-gfx] [PATCH v5 19/22] drm/i915/dg1: Load DMC

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Matt Atwood <
> matthew.s.atwood@intel.com
> >
> 
> Add support to load DMC v2.0.2 on DG1
> 
> While we're at it, tweak the TGL and RKL firmware size definition to
> follow the convention used in previous platforms. Remove obsolete
> commenting.
> 
> Bpec: 49230
> 
> Cc: Matt Roper <
> matthew.d.roper@intel.com
> >
> Signed-off-by: Matt Atwood <
> matthew.s.atwood@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_csr.c | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
> index f22a7645c249..ccf13ea627d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_csr.c
> +++ b/drivers/gpu/drm/i915/display/intel_csr.c
> @@ -38,15 +38,19 @@
>   * low-power state and comes back to normal.
>   */
>  
> -#define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
> +#define DG1_CSR_PATH			"i915/dg1_dmc_ver2_02.bin"
> +#define DG1_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
> +#define DG1_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
> +MODULE_FIRMWARE(DG1_CSR_PATH);
>  
>  #define RKL_CSR_PATH			"i915/rkl_dmc_ver2_01.bin"
>  #define RKL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 1)
> +#define RKL_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
>  MODULE_FIRMWARE(RKL_CSR_PATH);
>  
>  #define TGL_CSR_PATH			"i915/tgl_dmc_ver2_06.bin"
>  #define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 6)
> -#define TGL_CSR_MAX_FW_SIZE		0x6000
> +#define TGL_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE

Until CSR_MAX_FW_SIZE of a GEN12 platform is different I don't see a reason why to define a per-platform CSR_MAX_FW_SIZE.

The rest looks good.

>  MODULE_FIRMWARE(TGL_CSR_PATH);
>  
>  #define ICL_CSR_PATH			"i915/icl_dmc_ver1_09.bin"
> @@ -686,15 +690,18 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
>  	 */
>  	intel_csr_runtime_pm_get(dev_priv);
>  
> -	if (IS_ROCKETLAKE(dev_priv)) {
> +	if (IS_DG1(dev_priv)) {
> +		csr->fw_path = DG1_CSR_PATH;
> +		csr->required_version = DG1_CSR_VERSION_REQUIRED;
> +		csr->max_fw_size = DG1_CSR_MAX_FW_SIZE;
> +	} else if (IS_ROCKETLAKE(dev_priv)) {
>  		csr->fw_path = RKL_CSR_PATH;
>  		csr->required_version = RKL_CSR_VERSION_REQUIRED;
> -		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> +		csr->max_fw_size = RKL_CSR_MAX_FW_SIZE;
>  	} else if (INTEL_GEN(dev_priv) >= 12) {
>  		csr->fw_path = TGL_CSR_PATH;
>  		csr->required_version = TGL_CSR_VERSION_REQUIRED;
> -		/* Allow to load fw via parameter using the last known size */
> -		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
> +		csr->max_fw_size = TGL_CSR_MAX_FW_SIZE;
>  	} else if (IS_GEN(dev_priv, 11)) {
>  		csr->fw_path = ICL_CSR_PATH;
>  		csr->required_version = ICL_CSR_VERSION_REQUIRED;
> 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> 
> DGFX devices have different DMC_DEBUG* counter MMIO address
> offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> counter and handle i915_dmc_info accordingly.
> 
> Cc: Uma Shankar <
> uma.shankar@intel.com
> >
> Signed-off-by: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
>  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
>  2 files changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 3644752cc5ec..e3536edcb394 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>  		   CSR_VERSION_MINOR(csr->version));
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> +		if (IS_DG1(dev_priv)) {
> +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> +		} else {
> +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> +		}
> +
>  		/*
>  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
>  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4e95312eba24..78bdce67da08 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7549,6 +7549,8 @@ enum {
>  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
>  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
>  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
> +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
> +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)

DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
Removing it:

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


>  
>  #define DMC_DEBUG3		_MMIO(0x101090)
>  
> 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Anshuman Gupta]

On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > From: Anshuman Gupta <
> > anshuman.gupta@intel.com
> > >
> > 
> > DGFX devices have different DMC_DEBUG* counter MMIO address
> > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > counter and handle i915_dmc_info accordingly.
> > 
> > Cc: Uma Shankar <
> > uma.shankar@intel.com
> > >
> > Signed-off-by: Anshuman Gupta <
> > anshuman.gupta@intel.com
> > >
> > Signed-off-by: Lucas De Marchi <
> > lucas.demarchi@intel.com
> > >
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
> >  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
> >  2 files changed, 9 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index 3644752cc5ec..e3536edcb394 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> >  		   CSR_VERSION_MINOR(csr->version));
> >  
> >  	if (INTEL_GEN(dev_priv) >= 12) {
> > -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > +		if (IS_DG1(dev_priv)) {
> > +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > +		} else {
> > +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > +		}
> > +
> >  		/*
> >  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
> >  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 4e95312eba24..78bdce67da08 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7549,6 +7549,8 @@ enum {
> >  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
> >  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
> >  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
> > +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
> > +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)
> 
> DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> Removing it:
DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
igfx platforms, considering name consistency it has been kept with name DG1_*
inline to B.Spec Index:49787.

Thanks,
Anshuman Gupta.
> 
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> 
> 
> >  
> >  #define DMC_DEBUG3		_MMIO(0x101090)
> >  
> > 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Souza, Jose]

On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
> On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > From: Anshuman Gupta <
> > > anshuman.gupta@intel.com
> > > 
> > > 
> > > DGFX devices have different DMC_DEBUG* counter MMIO address
> > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > > counter and handle i915_dmc_info accordingly.
> > > 
> > > Cc: Uma Shankar <
> > > uma.shankar@intel.com
> > > 
> > > 
> > > Signed-off-by: Anshuman Gupta <
> > > anshuman.gupta@intel.com
> > > 
> > > 
> > > Signed-off-by: Lucas De Marchi <
> > > lucas.demarchi@intel.com
> > > 
> > > 
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
> > >  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
> > >  2 files changed, 9 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > index 3644752cc5ec..e3536edcb394 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> > >  		   CSR_VERSION_MINOR(csr->version));
> > >  
> > >  	if (INTEL_GEN(dev_priv) >= 12) {
> > > -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > +		if (IS_DG1(dev_priv)) {
> > > +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > > +		} else {
> > > +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > +		}
> > > +
> > >  		/*
> > >  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
> > >  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 4e95312eba24..78bdce67da08 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -7549,6 +7549,8 @@ enum {
> > >  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
> > >  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
> > >  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
> > > +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
> > > +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)
> > 
> > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> > Removing it:
> 
> DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
> igfx platforms, considering name consistency it has been kept with name DG1_*
> inline to B.Spec Index:49787.

A discrete graphics card will never be able to reach DC6 as it is a SOC power saving feature.

> 
> Thanks,
> Anshuman Gupta.
> > Reviewed-by: José Roberto de Souza <
> > jose.souza@intel.com
> > >
> > 
> > 
> > >  
> > >  #define DMC_DEBUG3		_MMIO(0x101090)
> > >  
> > > 
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > 
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Anshuman Gupta]

On 2020-08-07 at 22:56:54 +0530, Souza, Jose wrote:
> On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
> > On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
> > > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> > > > From: Anshuman Gupta <
> > > > anshuman.gupta@intel.com
> > > > 
> > > > 
> > > > DGFX devices have different DMC_DEBUG* counter MMIO address
> > > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
> > > > counter and handle i915_dmc_info accordingly.
> > > > 
> > > > Cc: Uma Shankar <
> > > > uma.shankar@intel.com
> > > > 
> > > > 
> > > > Signed-off-by: Anshuman Gupta <
> > > > anshuman.gupta@intel.com
> > > > 
> > > > 
> > > > Signed-off-by: Lucas De Marchi <
> > > > lucas.demarchi@intel.com
> > > > 
> > > > 
> > > > ---
> > > >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
> > > >  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
> > > >  2 files changed, 9 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > index 3644752cc5ec..e3536edcb394 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
> > > >  		   CSR_VERSION_MINOR(csr->version));
> > > >  
> > > >  	if (INTEL_GEN(dev_priv) >= 12) {
> > > > -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > > -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > > +		if (IS_DG1(dev_priv)) {
> > > > +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> > > > +		} else {
> > > > +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> > > > +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
> > > > +		}
> > > > +
> > > >  		/*
> > > >  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
> > > >  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 4e95312eba24..78bdce67da08 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -7549,6 +7549,8 @@ enum {
> > > >  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
> > > >  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
> > > >  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
> > > > +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
> > > > +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)
> > > 
> > > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
> > > Removing it:
> > 
> > DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
> > igfx platforms, considering name consistency it has been kept with name DG1_*
> > inline to B.Spec Index:49787.
> 
> A discrete graphics card will never be able to reach DC6 as it is a SOC power saving feature.
Is it documented some where, AFAIK DC6 is still diplay C state where it power off its innermost power well,
with involvment of some non display third party f/w.
IMHO if any discrete-gfx would support DC6, it would be useful in the use cases where driver is yet to request runtime suspend (DC9)
but display is already being powered off.
Thanks,
Anshuman Gupta.
> 
> > 
> > Thanks,
> > Anshuman Gupta.
> > > Reviewed-by: José Roberto de Souza <
> > > jose.souza@intel.com
> > > >
> > > 
> > > 
> > > >  
> > > >  #define DMC_DEBUG3		_MMIO(0x101090)
> > > >  
> > > > 
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > 
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > 
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Re: [Intel-gfx] [PATCH v5 22/22] drm/i915/dg1: Change DMC_DEBUG{1, 2} registers

[Lucas De Marchi]

On Mon, Aug 10, 2020 at 11:18:11AM +0530, Anshuman Gupta wrote:
>On 2020-08-07 at 22:56:54 +0530, Souza, Jose wrote:
>> On Fri, 2020-08-07 at 18:44 +0530, Anshuman Gupta wrote:
>> > On 2020-08-04 at 05:01:37 +0530, Souza, Jose wrote:
>> > > On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
>> > > > From: Anshuman Gupta <
>> > > > anshuman.gupta@intel.com
>> > > >
>> > > >
>> > > > DGFX devices have different DMC_DEBUG* counter MMIO address
>> > > > offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
>> > > > counter and handle i915_dmc_info accordingly.
>> > > >
>> > > > Cc: Uma Shankar <
>> > > > uma.shankar@intel.com
>> > > >
>> > > >
>> > > > Signed-off-by: Anshuman Gupta <
>> > > > anshuman.gupta@intel.com
>> > > >
>> > > >
>> > > > Signed-off-by: Lucas De Marchi <
>> > > > lucas.demarchi@intel.com
>> > > >
>> > > >
>> > > > ---
>> > > >  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
>> > > >  drivers/gpu/drm/i915/i915_reg.h                      | 2 ++
>> > > >  2 files changed, 9 insertions(+), 2 deletions(-)
>> > > >
>> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> > > > index 3644752cc5ec..e3536edcb394 100644
>> > > > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> > > > @@ -515,8 +515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
>> > > >  		   CSR_VERSION_MINOR(csr->version));
>> > > >
>> > > >  	if (INTEL_GEN(dev_priv) >= 12) {
>> > > > -		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
>> > > > -		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
>> > > > +		if (IS_DG1(dev_priv)) {
>> > > > +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
>> > > > +		} else {
>> > > > +			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
>> > > > +			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
>> > > > +		}
>> > > > +
>> > > >  		/*
>> > > >  		 * NOTE: DMC_DEBUG3 is a general purpose reg.
>> > > >  		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
>> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > > > index 4e95312eba24..78bdce67da08 100644
>> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > > > @@ -7549,6 +7549,8 @@ enum {
>> > > >  #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
>> > > >  #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
>> > > >  #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
>> > > > +#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
>> > > > +#define DG1_DMC_DEBUG_DC6_COUNT	_MMIO(0x134158)
>> > >
>> > > DG1_DMC_DEBUG_DC6_COUNT is not used as DG1 do not support DC6.
>> > > Removing it:
>> >
>> > DG1_DMC_DEBUG_DC6_COUNT is still valid DMC_DEBUG counter for future
>> > igfx platforms, considering name consistency it has been kept with name DG1_*
>> > inline to B.Spec Index:49787.
>>
>> A discrete graphics card will never be able to reach DC6 as it is a SOC power saving feature.
>Is it documented some where, AFAIK DC6 is still diplay C state where it power off its innermost power well,
>with involvment of some non display third party f/w.
>IMHO if any discrete-gfx would support DC6, it would be useful in the use cases where driver is yet to request runtime suspend (DC9)
>but display is already being powered off.

Correct, but I think the more relevant argument here is that it is _not
used_. If it was a bitfield, then ok. But it is a register. I don't think
we want to add all the unused registers. Chances are a new platform that
supports it will already have it in another address already.

I will remove it in the next version. And this is also 

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>


Lucas De Marchi
>Thanks,
>Anshuman Gupta.
>>
>> >
>> > Thanks,
>> > Anshuman Gupta.
>> > > Reviewed-by: José Roberto de Souza <
>> > > jose.souza@intel.com
>> > > >
>> > >
>> > >
>> > > >
>> > > >  #define DMC_DEBUG3		_MMIO(0x101090)
>> > > >
>> > > >
>> > >
>> > > _______________________________________________
>> > > Intel-gfx mailing list
>> > > Intel-gfx@lists.freedesktop.org
>> > >
>> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>> > >
>_______________________________________________
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Re: [Intel-gfx] [PATCH v5 21/22] drm/i915/dg1: DG1 does not support DC6

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> 
> DC6 is not supported on DG1, so change the allowed DC mask for DG1.
> 
> Cc: Uma Shankar <
> uma.shankar@intel.com
> >
> Signed-off-by: Anshuman Gupta <
> anshuman.gupta@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 21f39c94056e..389a0f2d3a14 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
>  	int max_dc;
>  
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		max_dc = 4;
> +		if (IS_DG1(dev_priv))

Better change to IS_DGFX() as DC6 is a SOC power-saving state, no discrete card will enter it.
With this change:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> +			max_dc = 3;
> +		else
> +			max_dc = 4;
>  		/*
>  		 * DC9 has a separate HW flow from the rest of the DC states,
>  		 * not depending on the DMC firmware. It's needed by system
> 
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Re: [Intel-gfx] [PATCH v5 21/22] drm/i915/dg1: DG1 does not support DC6

[Lucas De Marchi]

On Mon, Aug 03, 2020 at 04:33:45PM -0700, Jose Souza wrote:
>On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
>> From: Anshuman Gupta <
>> anshuman.gupta@intel.com
>> >
>>
>> DC6 is not supported on DG1, so change the allowed DC mask for DG1.
>>
>> Cc: Uma Shankar <
>> uma.shankar@intel.com
>> >
>> Signed-off-by: Anshuman Gupta <
>> anshuman.gupta@intel.com
>> >
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 21f39c94056e..389a0f2d3a14 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
>>  	int max_dc;
>>
>>  	if (INTEL_GEN(dev_priv) >= 12) {
>> -		max_dc = 4;
>> +		if (IS_DG1(dev_priv))
>
>Better change to IS_DGFX() as DC6 is a SOC power-saving state, no discrete card will enter it.
>With this change:

that doesn't seem true... it's more a dg1 thing than general dgfx

Lucas De Marchi

>Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
>> +			max_dc = 3;
>> +		else
>> +			max_dc = 4;
>>  		/*
>>  		 * DC9 has a separate HW flow from the rest of the DC states,
>>  		 * not depending on the DMC firmware. It's needed by system
>>
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Re: [Intel-gfx] [PATCH v5 15/22] drm/i915/dg1: Update voltage swing tables for DP

[Souza, Jose]

On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Matt Roper <
> matthew.d.roper@intel.com
> >
> 
> DG1's vswing tables are the same for eDP and HDMI but have slight
> differences from ICL/TGL for DP.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Bspec: 49291
> Cc: Clinton Taylor <
> Clinton.A.Taylor@intel.com
> >
> Cc: José Roberto de Souza <
> jose.souza@intel.com
> >
> Cc: Radhakrishna Sripada <
> radhakrishna.sripada@intel.com
> >
> Signed-off-by: Matt Roper <
> matthew.d.roper@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demarchi@intel.com
> >
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 714b2bc96f23..c19d5a375eba 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
>  	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
>  };
>  
> +static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x32, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +	{ 0xA, 0x48, 0x35, 0x00, 0x0A },	/* 350   500      3.1   */
> +	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
> +	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 350   900      8.2   */
> +	{ 0xA, 0x43, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
> +	{ 0xC, 0x60, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
> +	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
> +	{ 0xC, 0x60, 0x3F, 0x00, 0x00 },	/* 650   700      0.6   */
> +	{ 0x6, 0x7F, 0x37, 0x00, 0x08 },	/* 600   900      3.5   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> +};
> +
> +static const struct cnl_ddi_buf_trans dg1_combo_phy_ddi_translations_dp_hbr2[] = {
> +						/* NT mV Trans mV db    */
> +	{ 0xA, 0x32, 0x3F, 0x00, 0x00 },	/* 350   350      0.0   */
> +	{ 0xA, 0x48, 0x35, 0x00, 0x0A },	/* 350   500      3.1   */
> +	{ 0xC, 0x63, 0x2F, 0x00, 0x10 },	/* 350   700      6.0   */
> +	{ 0x6, 0x7F, 0x2C, 0x00, 0x13 },	/* 350   900      8.2   */
> +	{ 0xA, 0x43, 0x3F, 0x00, 0x00 },	/* 500   500      0.0   */
> +	{ 0xC, 0x60, 0x36, 0x00, 0x09 },	/* 500   700      2.9   */
> +	{ 0x6, 0x7F, 0x30, 0x00, 0x0F },	/* 500   900      5.1   */
> +	{ 0xC, 0x58, 0x3F, 0x00, 0x00 },	/* 650   700      0.6   */
> +	{ 0x6, 0x7F, 0x35, 0x00, 0x0A },	/* 600   900      3.5   */
> +	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
> +};
> +
>  struct icl_mg_phy_ddi_buf_trans {
>  	u32 cri_txdeemph_override_11_6;
>  	u32 cri_txdeemph_override_5_0;
> @@ -1034,6 +1062,12 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
>  	} else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
>  		*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
>  		return icl_combo_phy_ddi_translations_edp_hbr2;
> +	} else if (IS_DG1(dev_priv) && rate > 270000) {
> +		*n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
> +		return dg1_combo_phy_ddi_translations_dp_hbr2;
> +	} else if (IS_DG1(dev_priv)) {
> +		*n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
> +		return dg1_combo_phy_ddi_translations_dp_hbr;
>  	}
>  
>  	*n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
> 
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Re: [Intel-gfx] [PATCH v5 03/22] drm/i915/dg1: Add DG1 power wells

[Lucas De Marchi]

On Tue, Jul 28, 2020 at 01:51:53PM -0700, Matt Roper wrote:
>On Fri, Jul 24, 2020 at 02:38:59PM -0700, Lucas De Marchi wrote:
>> From: Uma Shankar <uma.shankar@intel.com>
>>
>> Most of TGL power wells are re-used for DG1. However, AUDIO Power
>> Domain is moved from PG3 to PG0. Handle the change and initialize
>> power wells with the new power well structure.
>>
>> Some of the Audio Streaming logic still remains in PW3 so still
>> it needs to be enabled.
>>
>> DDIA, DDIB, TC1 and TC2 are the active ports on DG1.
>>
>> Need to keep Transcoder C and D to Pipe Power wells, this is against
>> the spec but else hitting unclaimed register warnings (kept the logic
>> same as TGL)
>
>I think this paragraph is old; the bspec shows transcoders C and D in
>the same power wells as pipes C and D now so this is no longer a spec
>violation.
>
>Although the bspec went through a few revisions early on, it looks like
>DG1 is just a strict subset of the TGL power wells now, so there
>probably isn't a need to duplicate it as a whole new table here; I think
>the only thing keeping us from re-using TGL's table as-is for DG1 is the
>fake "TC COLD" well that blindly makes assumptions about which outputs
>are TC rather than paying attention to the real output type.  I think
>Aditya has some code that would fix the TCCOLD's assumptions and then we
>can just point DG1 to the TGL table.

Aditya, are you going to submit this soon?


>
>
>Matt
>
>>
>> Bspec: 49182
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  .../drm/i915/display/intel_display_power.c    | 201 +++++++++++++++++-
>>  1 file changed, 200 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 0c713e83274d..b51b82cb2398 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -2970,6 +2970,44 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
>>  	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
>>  	BIT_ULL(POWER_DOMAIN_INIT))
>>
>> +#define DG1_PW_5_POWER_DOMAINS (			\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_D) |			\
>> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_D) |		\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) |     \
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>> +#define DG1_PW_4_POWER_DOMAINS (			\
>> +	DG1_PW_5_POWER_DOMAINS |			\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_C) |			\
>> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_C) |		\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |	\
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>> +#define DG1_PW_3_POWER_DOMAINS (			\
>> +	DG1_PW_4_POWER_DOMAINS |			\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_B) |			\
>> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_B) |		\
>> +	BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |	\
>> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) |	\
>> +	BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) |	\
>> +	BIT_ULL(POWER_DOMAIN_AUX_D) |		\
>> +	BIT_ULL(POWER_DOMAIN_AUX_E) |		\
>> +	BIT_ULL(POWER_DOMAIN_VGA) |			\
>> +	BIT_ULL(POWER_DOMAIN_AUDIO) |			\
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>> +#define DG1_PW_2_POWER_DOMAINS (			\
>> +	DG1_PW_3_POWER_DOMAINS |			\
>> +	BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) |	\
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>> +#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS (		\
>> +	DG1_PW_3_POWER_DOMAINS |			\
>> +	BIT_ULL(POWER_DOMAIN_MODESET) |			\
>> +	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
>> +	BIT_ULL(POWER_DOMAIN_AUX_B) |			\
>> +	BIT_ULL(POWER_DOMAIN_INIT))
>> +
>>  static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
>>  	.sync_hw = i9xx_power_well_sync_hw_noop,
>>  	.enable = i9xx_always_on_power_well_noop,
>> @@ -4474,6 +4512,165 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
>>  	},
>>  };
>>
>> +static const struct i915_power_well_desc dg1_power_wells[] = {
>> +	{
>> +		.name = "always-on",
>> +		.always_on = true,
>> +		.domains = POWER_DOMAIN_MASK,
>> +		.ops = &i9xx_always_on_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +	},
>> +	{
>> +		.name = "power well 1",
>> +		/* Handled by the DMC firmware */
>> +		.always_on = true,
>> +		.domains = 0,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = SKL_DISP_PW_1,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_PW_1,
>> +			.hsw.has_fuses = true,
>> +		},
>> +	},
>> +	{
>> +		.name = "DC off",
>> +		.domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
>> +		.ops = &gen9_dc_off_power_well_ops,
>> +		.id = SKL_DISP_DC_OFF,
>> +	},
>> +	{
>> +		.name = "power well 2",
>> +		.domains = DG1_PW_2_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = SKL_DISP_PW_2,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_PW_2,
>> +			.hsw.has_fuses = true,
>> +		},
>> +	},
>> +	{
>> +		.name = "power well 3",
>> +		.domains = DG1_PW_3_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = ICL_DISP_PW_3,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_PW_3,
>> +			.hsw.irq_pipe_mask = BIT(PIPE_B),
>> +			.hsw.has_vga = true,
>> +			.hsw.has_fuses = true,
>> +		},
>> +	},
>> +	{
>> +		.name = "DDI A IO",
>> +		.domains = ICL_DDI_IO_A_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_ddi_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
>> +		}
>> +	},
>> +	{
>> +		.name = "DDI B IO",
>> +		.domains = ICL_DDI_IO_B_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_ddi_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
>> +		}
>> +	},
>> +	{
>> +		.name = "DDI D TC1 IO",
>> +		.domains = TGL_DDI_IO_D_TC1_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_ddi_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
>> +		},
>> +	},
>> +	{
>> +		.name = "DDI E TC2 IO",
>> +		.domains = TGL_DDI_IO_E_TC2_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_ddi_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
>> +		},
>> +	},
>> +	{
>> +		.name = "AUX A",
>> +		.domains = ICL_AUX_A_IO_POWER_DOMAINS,
>> +		.ops = &icl_aux_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_aux_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
>> +		},
>> +	},
>> +	{
>> +		.name = "AUX B",
>> +		.domains = ICL_AUX_B_IO_POWER_DOMAINS,
>> +		.ops = &icl_aux_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_aux_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
>> +		},
>> +	},
>> +	{
>> +		.name = "AUX D TC1",
>> +		.domains = TGL_AUX_D_TC1_IO_POWER_DOMAINS,
>> +		.ops = &icl_aux_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_aux_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
>> +			.hsw.is_tc_tbt = false,
>> +		},
>> +	},
>> +	{
>> +		.name = "AUX E TC2",
>> +		.domains = TGL_AUX_E_TC2_IO_POWER_DOMAINS,
>> +		.ops = &icl_aux_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &icl_aux_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
>> +			.hsw.is_tc_tbt = false,
>> +		},
>> +	},
>> +	{
>> +		.name = "power well 4",
>> +		.domains = DG1_PW_4_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = ICL_PW_CTL_IDX_PW_4,
>> +			.hsw.has_fuses = true,
>> +			.hsw.irq_pipe_mask = BIT(PIPE_C),
>> +		}
>> +	},
>> +	{
>> +		.name = "power well 5",
>> +		.domains = DG1_PW_5_POWER_DOMAINS,
>> +		.ops = &hsw_power_well_ops,
>> +		.id = DISP_PW_ID_NONE,
>> +		{
>> +			.hsw.regs = &hsw_power_well_regs,
>> +			.hsw.idx = TGL_PW_CTL_IDX_PW_5,
>> +			.hsw.has_fuses = true,
>> +			.hsw.irq_pipe_mask = BIT(PIPE_D),
>> +		},
>> +	},
>> +};
>> +
>>  static int
>>  sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
>>  				   int disable_power_well)
>> @@ -4622,7 +4819,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
>>  	 * The enabling order will be from lower to higher indexed wells,
>>  	 * the disabling order is reversed.
>>  	 */
>> -	if (IS_ROCKETLAKE(dev_priv)) {
>> +	if (IS_DG1(dev_priv)) {
>> +		err = set_power_wells(power_domains, dg1_power_wells);
>> +	} else if (IS_ROCKETLAKE(dev_priv)) {
>>  		err = set_power_wells(power_domains, rkl_power_wells);
>>  	} else if (IS_GEN(dev_priv, 12)) {
>>  		err = set_power_wells(power_domains, tgl_power_wells);
>> --
>> 2.26.2
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
>_______________________________________________
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Re: [Intel-gfx] [PATCH v5 06/22] drm/i915/dg1: Add DPLL macros for DG1

[Lucas De Marchi]

On Tue, Jul 28, 2020 at 02:54:18PM -0700, Matt Roper wrote:
>On Fri, Jul 24, 2020 at 02:39:02PM -0700, Lucas De Marchi wrote:
>> From: Aditya Swarup <aditya.swarup@intel.com>
>>
>> DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
>> DPLL2 and DPLL3 drive DDIC/DDID.
>
>Since this is a DG1-specific commit with DG1-specific macros, we should
>also use the DG1-specific terminology in the commit message to avoid
>confusion (i.e., DDI-TC1 and DDI-TC2 instead of DDIC/DDID).
>

ok, re-reading  bspec 49182 now I agree, although I find this naming
more confusing as it doesn't use TC phy

thanks
Lucas De Marchi

>Aside from that,
>
>Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>>
>> Introduce DG1_DPLL_CFCRx() helper macros to configure
>> DPLL registers.
>>
>> Bspec: 50288, 50299
>>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++++++++++++++++
>>  drivers/gpu/drm/i915/i915_reg.h               | 17 ++++++++++++++++-
>>  2 files changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> index 5d9a2bc371e7..205542fb8dc7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
>> @@ -154,6 +154,23 @@ enum intel_dpll_id {
>>  	 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
>>  	 */
>>  	DPLL_ID_TGL_MGPLL6 = 8,
>> +
>> +	/**
>> +	 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
>> +	 */
>> +	DPLL_ID_DG1_DPLL0 = 0,
>> +	/**
>> +	 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
>> +	 */
>> +	DPLL_ID_DG1_DPLL1 = 1,
>> +	/**
>> +	 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
>> +	 */
>> +	DPLL_ID_DG1_DPLL2 = 2,
>> +	/**
>> +	 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
>> +	 */
>> +	DPLL_ID_DG1_DPLL3 = 3,
>>  };
>>
>>  #define I915_NUM_PLLS 9
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 3767b32127da..986e31af7763 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>>  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
>>  #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
>> -#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
>> +#define _MMIO_PLL3(pll, ...)		_MMIO(_PICK(pll, __VA_ARGS__))
>> +
>>
>>  /*
>>   * Device info offset array based helpers for groups of registers with unevenly
>> @@ -10547,6 +10548,20 @@ enum skl_power_gate {
>>  #define RKL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
>>  						  _TGL_DPLL1_CFGCR1)
>>
>> +#define _DG1_DPLL2_CFGCR0		0x16C284
>> +#define _DG1_DPLL3_CFGCR0		0x16C28C
>> +#define DG1_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
>> +						   _TGL_DPLL1_CFGCR0, \
>> +						   _DG1_DPLL2_CFGCR0, \
>> +						   _DG1_DPLL3_CFGCR0)
>> +
>> +#define _DG1_DPLL2_CFGCR1               0x16C288
>> +#define _DG1_DPLL3_CFGCR1               0x16C290
>> +#define DG1_DPLL_CFGCR1(pll)            _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
>> +						   _TGL_DPLL1_CFGCR1, \
>> +						   _DG1_DPLL2_CFGCR1, \
>> +						   _DG1_DPLL3_CFGCR1)
>> +
>>  #define _DKL_PHY1_BASE			0x168000
>>  #define _DKL_PHY2_BASE			0x169000
>>  #define _DKL_PHY3_BASE			0x16A000
>> --
>> 2.26.2
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>VTT-OSGC Platform Enablement
>Intel Corporation
>(916) 356-2795
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
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