* [Intel-gfx] [PATCH 1/8] drm/i915: Consolidate condition for Wa_22011802037
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
@ 2023-07-18 22:27 ` Matt Roper
2023-07-19 17:22 ` Gustavo Sousa
2023-07-18 22:27 ` [Intel-gfx] [PATCH 2/8] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version Matt Roper
` (10 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Matt Roper @ 2023-07-18 22:27 UTC (permalink / raw)
To: intel-gfx; +Cc: matthew.d.roper
The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code. Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +---
.../drm/i915/gt/intel_execlists_submission.c | 4 +---
drivers/gpu/drm/i915/gt/intel_reset.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_reset.h | 2 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +---
6 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0aff5bb13c53..0d095337b350 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1616,9 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
* Wa_22011802037: Prior to doing a reset, ensure CS is
* stopped, set ring stop bit and prefetch disable bit to halt CS
*/
- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(engine->i915) >= 11 &&
- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+ if (intel_engine_reset_needs_wa_22011802037(engine->gt))
intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
_MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index d85b5a6d981f..b9f297c546fb 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,9 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
* Wa_22011802037: In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(engine->i915) >= 11 &&
- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+ if (intel_engine_reset_needs_wa_22011802037(engine->gt))
intel_engine_wait_for_pending_mi_fw(engine);
engine->execlists.reset_ccid = active_ccid(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index cc6bd21a3e51..1ff7b42521c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1632,6 +1632,24 @@ void __intel_fini_wedge(struct intel_wedge_me *w)
w->gt = NULL;
}
+/*
+ * Wa_22011802037 requires that we (or the GuC) ensure that no command
+ * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
+ */
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
+{
+ if (GRAPHICS_VER(gt->i915) < 11)
+ return false;
+
+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
+ return true;
+
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
+ return false;
+
+ return true;
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_reset.c"
#include "selftest_hangcheck.c"
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index 25c975b6e8fc..f615b30b81c5 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -78,4 +78,6 @@ void __intel_fini_wedge(struct intel_wedge_me *w);
bool intel_has_gpu_reset(const struct intel_gt *gt);
bool intel_has_reset_engine(const struct intel_gt *gt);
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt);
+
#endif /* I915_RESET_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2eb891b270ae..1e532981f74e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -292,9 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
flags |= GUC_WA_DUAL_QUEUE;
/* Wa_22011802037: graphics version 11/12 */
- if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(gt->i915) >= 11 &&
- GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
+ if (intel_engine_reset_needs_wa_22011802037(gt))
flags |= GUC_WA_PRE_PARSER;
/* Wa_16011777198:dg2 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d2..1bd5d8f7c40b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,9 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
* Wa_22011802037: In addition to stopping the cs, we need
* to wait for any pending mi force wakeups
*/
- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
- (GRAPHICS_VER(engine->i915) >= 11 &&
- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
+ if (intel_engine_reset_needs_wa_22011802037(engine->gt)) {
intel_engine_stop_cs(engine);
intel_engine_wait_for_pending_mi_fw(engine);
}
--
2.41.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 1/8] drm/i915: Consolidate condition for Wa_22011802037
2023-07-18 22:27 ` [Intel-gfx] [PATCH 1/8] drm/i915: Consolidate condition for Wa_22011802037 Matt Roper
@ 2023-07-19 17:22 ` Gustavo Sousa
0 siblings, 0 replies; 30+ messages in thread
From: Gustavo Sousa @ 2023-07-19 17:22 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: matthew.d.roper
Quoting Matt Roper (2023-07-18 19:27:55-03:00)
>The workaround bounds for Wa_22011802037 are somewhat complex and are
>replicated in several places throughout the code. Pull the condition
>out to a helper function to prevent mistakes if this condition needs to
>change again in the future.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +---
> .../drm/i915/gt/intel_execlists_submission.c | 4 +---
> drivers/gpu/drm/i915/gt/intel_reset.c | 18 ++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_reset.h | 2 ++
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 +---
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 4 +---
> 6 files changed, 24 insertions(+), 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>index 0aff5bb13c53..0d095337b350 100644
>--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
>@@ -1616,9 +1616,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
> * Wa_22011802037: Prior to doing a reset, ensure CS is
> * stopped, set ring stop bit and prefetch disable bit to halt CS
> */
>- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>- (GRAPHICS_VER(engine->i915) >= 11 &&
>- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>+ if (intel_engine_reset_needs_wa_22011802037(engine->gt))
> intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
> _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>index d85b5a6d981f..b9f297c546fb 100644
>--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>@@ -3001,9 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
> * Wa_22011802037: In addition to stopping the cs, we need
> * to wait for any pending mi force wakeups
> */
>- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>- (GRAPHICS_VER(engine->i915) >= 11 &&
>- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
>+ if (intel_engine_reset_needs_wa_22011802037(engine->gt))
> intel_engine_wait_for_pending_mi_fw(engine);
>
> engine->execlists.reset_ccid = active_ccid(engine);
>diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>index cc6bd21a3e51..1ff7b42521c9 100644
>--- a/drivers/gpu/drm/i915/gt/intel_reset.c
>+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>@@ -1632,6 +1632,24 @@ void __intel_fini_wedge(struct intel_wedge_me *w)
> w->gt = NULL;
> }
>
>+/*
>+ * Wa_22011802037 requires that we (or the GuC) ensure that no command
>+ * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
>+ */
>+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
>+{
>+ if (GRAPHICS_VER(gt->i915) < 11)
>+ return false;
>+
>+ if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
>+ return true;
>+
>+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
>+ return false;
>+
>+ return true;
>+}
>+
> #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
> #include "selftest_reset.c"
> #include "selftest_hangcheck.c"
>diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
>index 25c975b6e8fc..f615b30b81c5 100644
>--- a/drivers/gpu/drm/i915/gt/intel_reset.h
>+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
>@@ -78,4 +78,6 @@ void __intel_fini_wedge(struct intel_wedge_me *w);
> bool intel_has_gpu_reset(const struct intel_gt *gt);
> bool intel_has_reset_engine(const struct intel_gt *gt);
>
>+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt);
>+
> #endif /* I915_RESET_H */
>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>index 2eb891b270ae..1e532981f74e 100644
>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>@@ -292,9 +292,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> flags |= GUC_WA_DUAL_QUEUE;
>
> /* Wa_22011802037: graphics version 11/12 */
>- if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>- (GRAPHICS_VER(gt->i915) >= 11 &&
>- GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
>+ if (intel_engine_reset_needs_wa_22011802037(gt))
> flags |= GUC_WA_PRE_PARSER;
>
> /* Wa_16011777198:dg2 */
>diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>index a0e3ef1c65d2..1bd5d8f7c40b 100644
>--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>@@ -1658,9 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
> * Wa_22011802037: In addition to stopping the cs, we need
> * to wait for any pending mi force wakeups
> */
>- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>- (GRAPHICS_VER(engine->i915) >= 11 &&
>- GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
>+ if (intel_engine_reset_needs_wa_22011802037(engine->gt)) {
> intel_engine_stop_cs(engine);
> intel_engine_wait_for_pending_mi_fw(engine);
> }
>--
>2.41.0
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH 2/8] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
2023-07-18 22:27 ` [Intel-gfx] [PATCH 1/8] drm/i915: Consolidate condition for Wa_22011802037 Matt Roper
@ 2023-07-18 22:27 ` Matt Roper
2023-07-19 18:30 ` Gustavo Sousa
2023-07-18 22:27 ` [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP Matt Roper
` (9 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Matt Roper @ 2023-07-18 22:27 UTC (permalink / raw)
To: intel-gfx; +Cc: matthew.d.roper
Although some of our Xe_LPG workarounds were already being applied based
on IP version correctly, others were matching on MTL as a base platform,
which is incorrect. Although MTL is the only platform right now that
uses Xe_LPG IP, this may not always be the case. If a future platform
re-uses this graphics IP, the same workarounds should be applied, even
if it isn't a "MTL" platform.
We were also incorrectly applying Xe_LPG workarounds/tuning to the
Xe_LPM+ media IP in one or two places; we should make sure that we don't
try to apply graphics workarounds to the media GT and vice versa where
they don't belong. A new helper macro GT_GRAPHICS_RANGE() is added to
help ensure this is handled properly -- it checks both the graphics
version range and that the code isn't operating on a media GT.
Note that many of the stepping-based workarounds are still incorrectly
checking for a MTL base platform; that will be remedied in a later
patch.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 5 +++
2 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b177c588698b..2a5bf50962ad 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
}
-static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
- struct i915_wa_list *wal)
+static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
@@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
}
-static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
- struct i915_wa_list *wal)
+static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
+ struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
- mtl_ctx_gt_tuning_init(engine, wal);
+ xelpg_ctx_gt_tuning_init(engine, wal);
if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
@@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
if (engine->class != RENDER_CLASS)
goto done;
- if (IS_METEORLAKE(i915))
- mtl_ctx_workarounds_init(engine, wal);
+ if (GT_GRAPHICS_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+ xelpg_ctx_workarounds_init(engine, wal);
else if (IS_PONTEVECCHIO(i915))
; /* noop; none at this time */
else if (IS_DG2(i915))
@@ -1790,10 +1790,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
*/
static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
{
- if (IS_METEORLAKE(gt->i915)) {
- if (gt->type != GT_MEDIA)
- wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
-
+ if (GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
+ wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
}
@@ -1817,7 +1815,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
gt_tuning_settings(gt, wal);
if (gt->type == GT_MEDIA) {
- if (MEDIA_VER(i915) >= 13)
+ if (MEDIA_VER(i915) == 13)
xelpmp_gt_workarounds_init(gt, wal);
else
MISSING_CASE(MEDIA_VER(i915));
@@ -1825,7 +1823,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
return;
}
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+ if (GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
xelpg_gt_workarounds_init(gt, wal);
else if (IS_PONTEVECCHIO(i915))
pvc_gt_workarounds_init(gt, wal);
@@ -2293,7 +2291,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
blacklist_trtt(engine);
}
-static void mtl_whitelist_build(struct intel_engine_cs *engine)
+static void xelpg_whitelist_build(struct intel_engine_cs *engine)
{
struct i915_wa_list *w = &engine->whitelist;
@@ -2315,8 +2313,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
wa_init_start(w, engine->gt, "whitelist", engine->name);
- if (IS_METEORLAKE(i915))
- mtl_whitelist_build(engine);
+ if (engine->gt->type == GT_MEDIA)
+ ; /* none yet */
+ else if (GT_GRAPHICS_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
+ xelpg_whitelist_build(engine);
else if (IS_PONTEVECCHIO(i915))
pvc_whitelist_build(engine);
else if (IS_DG2(i915))
@@ -2974,10 +2974,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* function invoked by __intel_engine_init_ctx_wa().
*/
static void
-add_render_compute_tuning_settings(struct drm_i915_private *i915,
+add_render_compute_tuning_settings(struct intel_gt *gt,
struct i915_wa_list *wal)
{
- if (IS_METEORLAKE(i915) || IS_DG2(i915))
+ struct drm_i915_private *i915 = gt->i915;
+
+ if (GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
/*
@@ -3007,7 +3009,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
{
struct drm_i915_private *i915 = engine->i915;
- add_render_compute_tuning_settings(i915, wal);
+ add_render_compute_tuning_settings(engine->gt, wal);
if (GRAPHICS_VER(i915) >= 11) {
/* This is not a Wa (although referred to as
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 682ef2b5c7d5..f38c93d82c56 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -431,6 +431,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
#define IS_GRAPHICS_VER(i915, from, until) \
(GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
+#define GT_GRAPHICS_RANGE(gt, from, until) \
+ (BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+ ((gt)->type != GT_MEDIA && \
+ (GRAPHICS_VER_FULL((gt)->i915) >= (from) && GRAPHICS_VER_FULL((gt)->i915) <= (until))))
+
#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
RUNTIME_INFO(i915)->media.ip.rel)
--
2.41.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 2/8] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
2023-07-18 22:27 ` [Intel-gfx] [PATCH 2/8] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version Matt Roper
@ 2023-07-19 18:30 ` Gustavo Sousa
0 siblings, 0 replies; 30+ messages in thread
From: Gustavo Sousa @ 2023-07-19 18:30 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: matthew.d.roper
Quoting Matt Roper (2023-07-18 19:27:56-03:00)
>Although some of our Xe_LPG workarounds were already being applied based
>on IP version correctly, others were matching on MTL as a base platform,
>which is incorrect. Although MTL is the only platform right now that
>uses Xe_LPG IP, this may not always be the case. If a future platform
>re-uses this graphics IP, the same workarounds should be applied, even
>if it isn't a "MTL" platform.
>
>We were also incorrectly applying Xe_LPG workarounds/tuning to the
>Xe_LPM+ media IP in one or two places; we should make sure that we don't
>try to apply graphics workarounds to the media GT and vice versa where
>they don't belong. A new helper macro GT_GRAPHICS_RANGE() is added to
>help ensure this is handled properly -- it checks both the graphics
>version range and that the code isn't operating on a media GT.
>
>Note that many of the stepping-based workarounds are still incorrectly
>checking for a MTL base platform; that will be remedied in a later
>patch.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++----------
> drivers/gpu/drm/i915/i915_drv.h | 5 +++
> 2 files changed, 26 insertions(+), 19 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index b177c588698b..2a5bf50962ad 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -805,8 +805,8 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
> }
>
>-static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>- struct i915_wa_list *wal)
>+static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>+ struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
>@@ -817,12 +817,12 @@ static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> }
>
>-static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
>- struct i915_wa_list *wal)
>+static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
>+ struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
>
>- mtl_ctx_gt_tuning_init(engine, wal);
>+ xelpg_ctx_gt_tuning_init(engine, wal);
>
> if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>@@ -931,8 +931,8 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
> if (engine->class != RENDER_CLASS)
> goto done;
>
>- if (IS_METEORLAKE(i915))
>- mtl_ctx_workarounds_init(engine, wal);
>+ if (GT_GRAPHICS_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
>+ xelpg_ctx_workarounds_init(engine, wal);
> else if (IS_PONTEVECCHIO(i915))
> ; /* noop; none at this time */
> else if (IS_DG2(i915))
>@@ -1790,10 +1790,8 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> */
> static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
> {
>- if (IS_METEORLAKE(gt->i915)) {
>- if (gt->type != GT_MEDIA)
>- wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
>-
>+ if (GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
>+ wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
> wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
> }
>
>@@ -1817,7 +1815,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> gt_tuning_settings(gt, wal);
>
> if (gt->type == GT_MEDIA) {
>- if (MEDIA_VER(i915) >= 13)
>+ if (MEDIA_VER(i915) == 13)
This looks a bit unrelated to the commit message. I would add a short note for
this or make it a different patch.
> xelpmp_gt_workarounds_init(gt, wal);
> else
> MISSING_CASE(MEDIA_VER(i915));
>@@ -1825,7 +1823,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
> return;
> }
>
>- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>+ if (GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))
> xelpg_gt_workarounds_init(gt, wal);
> else if (IS_PONTEVECCHIO(i915))
> pvc_gt_workarounds_init(gt, wal);
>@@ -2293,7 +2291,7 @@ static void pvc_whitelist_build(struct intel_engine_cs *engine)
> blacklist_trtt(engine);
> }
>
>-static void mtl_whitelist_build(struct intel_engine_cs *engine)
>+static void xelpg_whitelist_build(struct intel_engine_cs *engine)
> {
> struct i915_wa_list *w = &engine->whitelist;
>
>@@ -2315,8 +2313,10 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>
> wa_init_start(w, engine->gt, "whitelist", engine->name);
>
>- if (IS_METEORLAKE(i915))
>- mtl_whitelist_build(engine);
>+ if (engine->gt->type == GT_MEDIA)
>+ ; /* none yet */
>+ else if (GT_GRAPHICS_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))
>+ xelpg_whitelist_build(engine);
> else if (IS_PONTEVECCHIO(i915))
> pvc_whitelist_build(engine);
> else if (IS_DG2(i915))
>@@ -2974,10 +2974,12 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> * function invoked by __intel_engine_init_ctx_wa().
> */
> static void
>-add_render_compute_tuning_settings(struct drm_i915_private *i915,
>+add_render_compute_tuning_settings(struct intel_gt *gt,
> struct i915_wa_list *wal)
> {
>- if (IS_METEORLAKE(i915) || IS_DG2(i915))
>+ struct drm_i915_private *i915 = gt->i915;
>+
>+ if (GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))
> wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
>
> /*
>@@ -3007,7 +3009,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> {
> struct drm_i915_private *i915 = engine->i915;
>
>- add_render_compute_tuning_settings(i915, wal);
>+ add_render_compute_tuning_settings(engine->gt, wal);
>
> if (GRAPHICS_VER(i915) >= 11) {
> /* This is not a Wa (although referred to as
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 682ef2b5c7d5..f38c93d82c56 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -431,6 +431,11 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> #define IS_GRAPHICS_VER(i915, from, until) \
> (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
>
>+#define GT_GRAPHICS_RANGE(gt, from, until) \
>+ (BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
>+ ((gt)->type != GT_MEDIA && \
>+ (GRAPHICS_VER_FULL((gt)->i915) >= (from) && GRAPHICS_VER_FULL((gt)->i915) <= (until))))
>+
I know the macro's name is already a bit long, but maybe
s/GT_GRAPHICS_RANGE/IS_GT_GRAPHICS_RANGE/ for consistency?
Considering current discussions on disaggregating macros, wouldn't having macros
IS_GRAPHICS_GT() and IS_GRAPHICS_RANGE() macro be more suitable here?
By the way, I also noticed that the proposed macro uses full versions while
others (e.g. IS_MEDIA_VER) use only the major part. I wonder if we could have a
single way to specify version boundaries so we could reduce the number of
variants. For example, we could have a single IS_GRAPHICS_RANGE() (or
IS_GFX_RANGE?) instead of another one (i.e. IS_GRAPHICS_VER) for comparing only
major ranges. Anyways, this somewhat is out of the scope of this patch, but I
just thought I would mention it.
--
Gustavo Sousa
> #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
> #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
> RUNTIME_INFO(i915)->media.ip.rel)
>--
>2.41.0
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
2023-07-18 22:27 ` [Intel-gfx] [PATCH 1/8] drm/i915: Consolidate condition for Wa_22011802037 Matt Roper
2023-07-18 22:27 ` [Intel-gfx] [PATCH 2/8] drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version Matt Roper
@ 2023-07-18 22:27 ` Matt Roper
2023-07-19 8:01 ` Tvrtko Ursulin
2023-07-18 22:27 ` [Intel-gfx] [PATCH 4/8] drm/i915: Eliminate IS_MTL_MEDIA_STEP Matt Roper
` (8 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Matt Roper @ 2023-07-18 22:27 UTC (permalink / raw)
To: intel-gfx; +Cc: matthew.d.roper
Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
of these workarounds are actually tied to MTL as a platform; they only
relate to the Xe_LPG graphics IP, regardless of what platform it appears
in. At the moment MTL is the only platform that uses Xe_LPG with IP
versions 12.70 and 12.71, but we can't count on this being true in the
future. Switch these to use a new IS_GFX_IPVER_STEP() macro instead
that is purely based on IP version. IS_GFX_IPVER_STEP() is also
GT-based rather than device-based, which will help prevent mistakes
where we accidentally try to apply Xe_LPG graphics workarounds to the
Xe_LPM+ media GT.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 4 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 9 ++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 8 +--
9 files changed, 46 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6b01a0b68b97..c13e64faaaad 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
enum pipe pipe, enum plane_id plane_id)
{
/* Wa_14017240301 */
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ if (IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
return false;
/* Wa_22011186057 */
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 23857cc08eca..c1af91d908e5 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
static int mtl_dummy_pipe_control(struct i915_request *rq)
{
/* Wa_14016712196 */
- if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+ if (IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
u32 *cs;
/* dummy PIPE_CONTROL + depth flush */
@@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
struct drm_i915_private *i915 = rq->engine->i915;
+ struct intel_gt *gt = rq->engine->gt;
u32 flags = (PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TLB_INVALIDATE |
PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
PIPE_CONTROL_FLUSH_ENABLE);
/* Wa_14016712196 */
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
/* dummy PIPE_CONTROL + depth flush */
cs = gen12_emit_pipe_control(cs, 0,
PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 0b414eae1683..41140eb86051 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
} else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
/* Wa_14016747170 */
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
intel_uncore_read(gt->uncore,
MTL_GT_ACTIVITY_FACTOR));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 1b710102390b..4fefa67d285f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
cs, GEN12_GFX_CCS_AUX_NV);
/* Wa_16014892111 */
- if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
+ if (IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
IS_DG2(ce->engine->i915))
cs = dg2_emit_draw_watermark_setting(cs);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 1ff7b42521c9..403f0d9caadf 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
if (GRAPHICS_VER(gt->i915) < 11)
return false;
- if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
return true;
if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2a5bf50962ad..785453b2e95e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
- struct drm_i915_private *i915 = engine->i915;
+ struct intel_gt *gt = engine->gt;
dg2_ctx_gt_tuning_init(engine, wal);
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
}
static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
- struct drm_i915_private *i915 = engine->i915;
+ struct intel_gt *gt = engine->gt;
xelpg_ctx_gt_tuning_init(engine, wal);
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
/* Wa_14014947963 */
wa_masked_field_set(wal, VF_PREEMPTION,
PREEMPTION_VERTEX_COUNT, 0x4000);
@@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_22016670082 */
wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
- if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
/* Wa_14014830051 */
wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
@@ -2424,16 +2424,17 @@ static void
rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ struct intel_gt *gt = engine->gt;
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
/* Wa_22014600077 */
wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
ENABLE_EU_COUNT_FOR_TDL_FLUSH);
}
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
/* Wa_1509727124 */
@@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
- IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) {
/* Wa_22012856258 */
wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
GEN12_DISABLE_READ_SUPPRESSION);
@@ -3008,8 +3009,9 @@ static void
general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = engine->i915;
+ struct intel_gt *gt = engine->gt;
- add_render_compute_tuning_settings(engine->gt, wal);
+ add_render_compute_tuning_settings(gt, wal);
if (GRAPHICS_VER(i915) >= 11) {
/* This is not a Wa (although referred to as
@@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
}
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
/* Wa_14017856879 */
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
/*
* Wa_14017066071
* Wa_14017654203
@@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
MTL_DISABLE_SAMPLER_SC_OOO);
- if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
/* Wa_22015279794 */
wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
DISABLE_PREFETCH_INTO_IC);
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
/* Wa_22013037850 */
@@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
DISABLE_128B_EVICTION_COMMAND_UDW);
}
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
IS_PONTEVECCHIO(i915) ||
IS_DG2(i915)) {
/* Wa_22014226127 */
wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
}
- if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
+ IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
IS_DG2(i915)) {
/* Wa_18017747507 */
wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 1e532981f74e..300b968e6de8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
flags |= GUC_WA_GAM_CREDITS;
/* Wa_14014475959 */
- if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
+ if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
IS_DG2(gt->i915))
flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1bd5d8f7c40b..3b159069dbc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
/* Wa_14014475959:dg2 */
if (engine->class == COMPUTE_CLASS)
- if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
+ if (IS_GFX_IPVER_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
IS_DG2(engine->i915))
engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f38c93d82c56..d03710c923c8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -692,9 +692,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
-#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
- (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
- IS_GRAPHICS_STEP(__i915, since, until))
+#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+ (__gt->type != GT_MEDIA && \
+ GRAPHICS_VER_FULL(__gt->i915) == ipver && \
+ IS_GRAPHICS_STEP(__gt->i915, since, until)))
#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
(IS_METEORLAKE(__i915) && \
--
2.41.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
2023-07-18 22:27 ` [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP Matt Roper
@ 2023-07-19 8:01 ` Tvrtko Ursulin
2023-07-19 15:28 ` Matt Roper
0 siblings, 1 reply; 30+ messages in thread
From: Tvrtko Ursulin @ 2023-07-19 8:01 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On 18/07/2023 23:27, Matt Roper wrote:
> Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> of these workarounds are actually tied to MTL as a platform; they only
> relate to the Xe_LPG graphics IP, regardless of what platform it appears
> in. At the moment MTL is the only platform that uses Xe_LPG with IP
> versions 12.70 and 12.71, but we can't count on this being true in the
> future. Switch these to use a new IS_GFX_IPVER_STEP() macro instead
> that is purely based on IP version. IS_GFX_IPVER_STEP() is also
> GT-based rather than device-based, which will help prevent mistakes
> where we accidentally try to apply Xe_LPG graphics workarounds to the
> Xe_LPM+ media GT.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../drm/i915/display/skl_universal_plane.c | 4 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 9 ++--
> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++++++++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 8 +--
> 9 files changed, 46 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 6b01a0b68b97..c13e64faaaad 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> enum pipe pipe, enum plane_id plane_id)
> {
> /* Wa_14017240301 */
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + if (IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
Do we really need/want a combined/long macro like this and not split it
out to something like a more readable IS_GFX_IPVER && IS_<...>_STEP?
Adding Jani since we were discussing this direction over the past few weeks.
Hm.. macro trickery for stepping ranges to make it more compact? Like
making the STEP_ prefix be prepended by the macro. Don't know..
Regards,
Tvrtko
> return false;
>
> /* Wa_22011186057 */
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 23857cc08eca..c1af91d908e5 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> static int mtl_dummy_pipe_control(struct i915_request *rq)
> {
> /* Wa_14016712196 */
> - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> + if (IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> u32 *cs;
>
> /* dummy PIPE_CONTROL + depth flush */
> @@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> {
> struct drm_i915_private *i915 = rq->engine->i915;
> + struct intel_gt *gt = rq->engine->gt;
> u32 flags = (PIPE_CONTROL_CS_STALL |
> PIPE_CONTROL_TLB_INVALIDATE |
> PIPE_CONTROL_TILE_CACHE_FLUSH |
> @@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> PIPE_CONTROL_FLUSH_ENABLE);
>
> /* Wa_14016712196 */
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> /* dummy PIPE_CONTROL + depth flush */
> cs = gen12_emit_pipe_control(cs, 0,
> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> index 0b414eae1683..41140eb86051 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> /* Wa_14016747170 */
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> intel_uncore_read(gt->uncore,
> MTL_GT_ACTIVITY_FACTOR));
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 1b710102390b..4fefa67d285f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> cs, GEN12_GFX_CCS_AUX_NV);
>
> /* Wa_16014892111 */
> - if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> + if (IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> IS_DG2(ce->engine->i915))
> cs = dg2_emit_draw_watermark_setting(cs);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 1ff7b42521c9..403f0d9caadf 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
> if (GRAPHICS_VER(gt->i915) < 11)
> return false;
>
> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
> return true;
>
> if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 2a5bf50962ad..785453b2e95e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> - struct drm_i915_private *i915 = engine->i915;
> + struct intel_gt *gt = engine->gt;
>
> dg2_ctx_gt_tuning_init(engine, wal);
>
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> }
>
> static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> - struct drm_i915_private *i915 = engine->i915;
> + struct intel_gt *gt = engine->gt;
>
> xelpg_ctx_gt_tuning_init(engine, wal);
>
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> /* Wa_14014947963 */
> wa_masked_field_set(wal, VF_PREEMPTION,
> PREEMPTION_VERTEX_COUNT, 0x4000);
> @@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_22016670082 */
> wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>
> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> /* Wa_14014830051 */
> wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>
> @@ -2424,16 +2424,17 @@ static void
> rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
> + struct intel_gt *gt = engine->gt;
>
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> /* Wa_22014600077 */
> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> }
>
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> /* Wa_1509727124 */
> @@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> - IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) {
> /* Wa_22012856258 */
> wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_DISABLE_READ_SUPPRESSION);
> @@ -3008,8 +3009,9 @@ static void
> general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> {
> struct drm_i915_private *i915 = engine->i915;
> + struct intel_gt *gt = engine->gt;
>
> - add_render_compute_tuning_settings(engine->gt, wal);
> + add_render_compute_tuning_settings(gt, wal);
>
> if (GRAPHICS_VER(i915) >= 11) {
> /* This is not a Wa (although referred to as
> @@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> }
>
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> /* Wa_14017856879 */
> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> /*
> * Wa_14017066071
> * Wa_14017654203
> @@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> MTL_DISABLE_SAMPLER_SC_OOO);
>
> - if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> /* Wa_22015279794 */
> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> DISABLE_PREFETCH_INTO_IC);
>
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> /* Wa_22013037850 */
> @@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> DISABLE_128B_EVICTION_COMMAND_UDW);
> }
>
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> IS_PONTEVECCHIO(i915) ||
> IS_DG2(i915)) {
> /* Wa_22014226127 */
> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> }
>
> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> IS_DG2(i915)) {
> /* Wa_18017747507 */
> wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 1e532981f74e..300b968e6de8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> flags |= GUC_WA_GAM_CREDITS;
>
> /* Wa_14014475959 */
> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> IS_DG2(gt->i915))
> flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 1bd5d8f7c40b..3b159069dbc4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>
> /* Wa_14014475959:dg2 */
> if (engine->class == COMPUTE_CLASS)
> - if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> + if (IS_GFX_IPVER_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> IS_DG2(engine->i915))
> engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f38c93d82c56..d03710c923c8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -692,9 +692,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>
> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> - (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> - IS_GRAPHICS_STEP(__i915, since, until))
> +#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
> + (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
> + (__gt->type != GT_MEDIA && \
> + GRAPHICS_VER_FULL(__gt->i915) == ipver && \
> + IS_GRAPHICS_STEP(__gt->i915, since, until)))
>
> #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> (IS_METEORLAKE(__i915) && \
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
2023-07-19 8:01 ` Tvrtko Ursulin
@ 2023-07-19 15:28 ` Matt Roper
2023-07-19 22:54 ` Matt Roper
2023-07-20 9:23 ` Tvrtko Ursulin
0 siblings, 2 replies; 30+ messages in thread
From: Matt Roper @ 2023-07-19 15:28 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
>
> On 18/07/2023 23:27, Matt Roper wrote:
> > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > of these workarounds are actually tied to MTL as a platform; they only
> > relate to the Xe_LPG graphics IP, regardless of what platform it appears
> > in. At the moment MTL is the only platform that uses Xe_LPG with IP
> > versions 12.70 and 12.71, but we can't count on this being true in the
> > future. Switch these to use a new IS_GFX_IPVER_STEP() macro instead
> > that is purely based on IP version. IS_GFX_IPVER_STEP() is also
> > GT-based rather than device-based, which will help prevent mistakes
> > where we accidentally try to apply Xe_LPG graphics workarounds to the
> > Xe_LPM+ media GT.
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > .../drm/i915/display/skl_universal_plane.c | 4 +-
> > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 9 ++--
> > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 +-
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
> > drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++++++++++---------
> > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
> > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 8 +--
> > 9 files changed, 46 insertions(+), 41 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 6b01a0b68b97..c13e64faaaad 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> > enum pipe pipe, enum plane_id plane_id)
> > {
> > /* Wa_14017240301 */
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > + if (IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
>
> Do we really need/want a combined/long macro like this and not split it out
> to something like a more readable IS_GFX_IPVER && IS_<...>_STEP?
>
> Adding Jani since we were discussing this direction over the past few weeks.
>
> Hm.. macro trickery for stepping ranges to make it more compact? Like making
> the STEP_ prefix be prepended by the macro. Don't know..
One other thing that we could consider if some of these things are
getting too long is eliminating IP_VER() and using the "versionx100"
scheme that Xe and Mesa use. On one hand that makes me a bit nervous
since GMD_ID's release number is 8 bits and could go past 100 on future
platforms, which would break the scheme (and we're already up to .71 on
MTL). But on the other hand it does make the code simpler and shorter
and we can always wait and see if we ever actually get a platform with
version X.100 or something before we really worry about what to do
there.
The other point in favor of switching to versionx100 is that we wouldn't
have an inconsistent mix of both IP_VER() and verx100 in the Xe driver
where the display code comes from i915 but the non-display code is
separate.
Matt
>
> Regards,
>
> Tvrtko
>
> > return false;
> > /* Wa_22011186057 */
> > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > index 23857cc08eca..c1af91d908e5 100644
> > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> > static int mtl_dummy_pipe_control(struct i915_request *rq)
> > {
> > /* Wa_14016712196 */
> > - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> > + if (IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > u32 *cs;
> > /* dummy PIPE_CONTROL + depth flush */
> > @@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
> > u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> > {
> > struct drm_i915_private *i915 = rq->engine->i915;
> > + struct intel_gt *gt = rq->engine->gt;
> > u32 flags = (PIPE_CONTROL_CS_STALL |
> > PIPE_CONTROL_TLB_INVALIDATE |
> > PIPE_CONTROL_TILE_CACHE_FLUSH |
> > @@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> > PIPE_CONTROL_FLUSH_ENABLE);
> > /* Wa_14016712196 */
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > /* dummy PIPE_CONTROL + depth flush */
> > cs = gen12_emit_pipe_control(cs, 0,
> > PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > index 0b414eae1683..41140eb86051 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> > gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> > } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> > /* Wa_14016747170 */
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> > intel_uncore_read(gt->uncore,
> > MTL_GT_ACTIVITY_FACTOR));
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 1b710102390b..4fefa67d285f 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> > cs, GEN12_GFX_CCS_AUX_NV);
> > /* Wa_16014892111 */
> > - if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> > + if (IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > IS_DG2(ce->engine->i915))
> > cs = dg2_emit_draw_watermark_setting(cs);
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index 1ff7b42521c9..403f0d9caadf 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
> > if (GRAPHICS_VER(gt->i915) < 11)
> > return false;
> > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
> > return true;
> > if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 2a5bf50962ad..785453b2e95e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > struct i915_wa_list *wal)
> > {
> > - struct drm_i915_private *i915 = engine->i915;
> > + struct intel_gt *gt = engine->gt;
> > dg2_ctx_gt_tuning_init(engine, wal);
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> > wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> > }
> > static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
> > struct i915_wa_list *wal)
> > {
> > - struct drm_i915_private *i915 = engine->i915;
> > + struct intel_gt *gt = engine->gt;
> > xelpg_ctx_gt_tuning_init(engine, wal);
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > /* Wa_14014947963 */
> > wa_masked_field_set(wal, VF_PREEMPTION,
> > PREEMPTION_VERTEX_COUNT, 0x4000);
> > @@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > /* Wa_22016670082 */
> > wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > /* Wa_14014830051 */
> > wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> > @@ -2424,16 +2424,17 @@ static void
> > rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > {
> > struct drm_i915_private *i915 = engine->i915;
> > + struct intel_gt *gt = engine->gt;
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > /* Wa_22014600077 */
> > wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> > ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> > }
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > /* Wa_1509727124 */
> > @@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> > - IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) {
> > /* Wa_22012856258 */
> > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> > GEN12_DISABLE_READ_SUPPRESSION);
> > @@ -3008,8 +3009,9 @@ static void
> > general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > {
> > struct drm_i915_private *i915 = engine->i915;
> > + struct intel_gt *gt = engine->gt;
> > - add_render_compute_tuning_settings(engine->gt, wal);
> > + add_render_compute_tuning_settings(gt, wal);
> > if (GRAPHICS_VER(i915) >= 11) {
> > /* This is not a Wa (although referred to as
> > @@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> > }
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> > /* Wa_14017856879 */
> > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > /*
> > * Wa_14017066071
> > * Wa_14017654203
> > @@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> > MTL_DISABLE_SAMPLER_SC_OOO);
> > - if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > /* Wa_22015279794 */
> > wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> > DISABLE_PREFETCH_INTO_IC);
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > /* Wa_22013037850 */
> > @@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > DISABLE_128B_EVICTION_COMMAND_UDW);
> > }
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > IS_PONTEVECCHIO(i915) ||
> > IS_DG2(i915)) {
> > /* Wa_22014226127 */
> > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> > }
> > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > IS_DG2(i915)) {
> > /* Wa_18017747507 */
> > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > index 1e532981f74e..300b968e6de8 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> > flags |= GUC_WA_GAM_CREDITS;
> > /* Wa_14014475959 */
> > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > IS_DG2(gt->i915))
> > flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > index 1bd5d8f7c40b..3b159069dbc4 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > @@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > /* Wa_14014475959:dg2 */
> > if (engine->class == COMPUTE_CLASS)
> > - if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > + if (IS_GFX_IPVER_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > IS_DG2(engine->i915))
> > engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index f38c93d82c56..d03710c923c8 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -692,9 +692,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> > (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> > -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > - (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> > - IS_GRAPHICS_STEP(__i915, since, until))
> > +#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
> > + (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
> > + (__gt->type != GT_MEDIA && \
> > + GRAPHICS_VER_FULL(__gt->i915) == ipver && \
> > + IS_GRAPHICS_STEP(__gt->i915, since, until)))
> > #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> > (IS_METEORLAKE(__i915) && \
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
2023-07-19 15:28 ` Matt Roper
@ 2023-07-19 22:54 ` Matt Roper
2023-07-20 9:36 ` Tvrtko Ursulin
2023-07-20 9:23 ` Tvrtko Ursulin
1 sibling, 1 reply; 30+ messages in thread
From: Matt Roper @ 2023-07-19 22:54 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Wed, Jul 19, 2023 at 08:28:12AM -0700, Matt Roper wrote:
> On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
> >
> > On 18/07/2023 23:27, Matt Roper wrote:
> > > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > > of these workarounds are actually tied to MTL as a platform; they only
> > > relate to the Xe_LPG graphics IP, regardless of what platform it appears
> > > in. At the moment MTL is the only platform that uses Xe_LPG with IP
> > > versions 12.70 and 12.71, but we can't count on this being true in the
> > > future. Switch these to use a new IS_GFX_IPVER_STEP() macro instead
> > > that is purely based on IP version. IS_GFX_IPVER_STEP() is also
> > > GT-based rather than device-based, which will help prevent mistakes
> > > where we accidentally try to apply Xe_LPG graphics workarounds to the
> > > Xe_LPM+ media GT.
> > >
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > > .../drm/i915/display/skl_universal_plane.c | 4 +-
> > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 9 ++--
> > > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 +-
> > > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
> > > drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++++++++++---------
> > > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
> > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> > > drivers/gpu/drm/i915/i915_drv.h | 8 +--
> > > 9 files changed, 46 insertions(+), 41 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index 6b01a0b68b97..c13e64faaaad 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> > > enum pipe pipe, enum plane_id plane_id)
> > > {
> > > /* Wa_14017240301 */
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > + if (IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
> >
> > Do we really need/want a combined/long macro like this and not split it out
> > to something like a more readable IS_GFX_IPVER && IS_<...>_STEP?
On this part, wouldn't that make it less readable? Right now these
conditions are an ||'d list of cases for which the workaround should
apply (relating to various entries in the workaround database). If we
split the version, stepping, and GT checks out into separate macros
we'll get more complex conditions that are a mix of && and ||. We can
try that, but my gut feeling is that it's going to be more error-prone
since we'll have to be really careful to always get the parenentheses in
the right places. Also many people (myself included) are already having
some trouble adjusting to the new idea of GT (primary vs media) being an
important factor that needs to be considered in the workaround
condition; one of the goals with these new macros was to make sure that
got included in the macro so that it couldn't be omitted by accident.
Matt
> >
> > Adding Jani since we were discussing this direction over the past few weeks.
> >
> > Hm.. macro trickery for stepping ranges to make it more compact? Like making
> > the STEP_ prefix be prepended by the macro. Don't know..
>
> One other thing that we could consider if some of these things are
> getting too long is eliminating IP_VER() and using the "versionx100"
> scheme that Xe and Mesa use. On one hand that makes me a bit nervous
> since GMD_ID's release number is 8 bits and could go past 100 on future
> platforms, which would break the scheme (and we're already up to .71 on
> MTL). But on the other hand it does make the code simpler and shorter
> and we can always wait and see if we ever actually get a platform with
> version X.100 or something before we really worry about what to do
> there.
>
> The other point in favor of switching to versionx100 is that we wouldn't
> have an inconsistent mix of both IP_VER() and verx100 in the Xe driver
> where the display code comes from i915 but the non-display code is
> separate.
>
>
> Matt
>
> >
> > Regards,
> >
> > Tvrtko
> >
> > > return false;
> > > /* Wa_22011186057 */
> > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > index 23857cc08eca..c1af91d908e5 100644
> > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> > > static int mtl_dummy_pipe_control(struct i915_request *rq)
> > > {
> > > /* Wa_14016712196 */
> > > - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> > > + if (IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > > u32 *cs;
> > > /* dummy PIPE_CONTROL + depth flush */
> > > @@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
> > > u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> > > {
> > > struct drm_i915_private *i915 = rq->engine->i915;
> > > + struct intel_gt *gt = rq->engine->gt;
> > > u32 flags = (PIPE_CONTROL_CS_STALL |
> > > PIPE_CONTROL_TLB_INVALIDATE |
> > > PIPE_CONTROL_TILE_CACHE_FLUSH |
> > > @@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> > > PIPE_CONTROL_FLUSH_ENABLE);
> > > /* Wa_14016712196 */
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > > /* dummy PIPE_CONTROL + depth flush */
> > > cs = gen12_emit_pipe_control(cs, 0,
> > > PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > > index 0b414eae1683..41140eb86051 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > > @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> > > gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> > > } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> > > /* Wa_14016747170 */
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > > fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> > > intel_uncore_read(gt->uncore,
> > > MTL_GT_ACTIVITY_FACTOR));
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > index 1b710102390b..4fefa67d285f 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > @@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
> > > cs, GEN12_GFX_CCS_AUX_NV);
> > > /* Wa_16014892111 */
> > > - if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
> > > + if (IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > > IS_DG2(ce->engine->i915))
> > > cs = dg2_emit_draw_watermark_setting(cs);
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > index 1ff7b42521c9..403f0d9caadf 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > @@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
> > > if (GRAPHICS_VER(gt->i915) < 11)
> > > return false;
> > > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
> > > return true;
> > > if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > index 2a5bf50962ad..785453b2e95e 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > @@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > > struct i915_wa_list *wal)
> > > {
> > > - struct drm_i915_private *i915 = engine->i915;
> > > + struct intel_gt *gt = engine->gt;
> > > dg2_ctx_gt_tuning_init(engine, wal);
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> > > wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> > > }
> > > static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > struct i915_wa_list *wal)
> > > {
> > > - struct drm_i915_private *i915 = engine->i915;
> > > + struct intel_gt *gt = engine->gt;
> > > xelpg_ctx_gt_tuning_init(engine, wal);
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > > /* Wa_14014947963 */
> > > wa_masked_field_set(wal, VF_PREEMPTION,
> > > PREEMPTION_VERTEX_COUNT, 0x4000);
> > > @@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > > /* Wa_22016670082 */
> > > wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> > > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > > /* Wa_14014830051 */
> > > wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> > > @@ -2424,16 +2424,17 @@ static void
> > > rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > {
> > > struct drm_i915_private *i915 = engine->i915;
> > > + struct intel_gt *gt = engine->gt;
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > > /* Wa_22014600077 */
> > > wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> > > ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> > > }
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > > IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > > IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > > /* Wa_1509727124 */
> > > @@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > > IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) {
> > > /* Wa_22012856258 */
> > > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> > > GEN12_DISABLE_READ_SUPPRESSION);
> > > @@ -3008,8 +3009,9 @@ static void
> > > general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> > > {
> > > struct drm_i915_private *i915 = engine->i915;
> > > + struct intel_gt *gt = engine->gt;
> > > - add_render_compute_tuning_settings(engine->gt, wal);
> > > + add_render_compute_tuning_settings(gt, wal);
> > > if (GRAPHICS_VER(i915) >= 11) {
> > > /* This is not a Wa (although referred to as
> > > @@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > > GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> > > }
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> > > /* Wa_14017856879 */
> > > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > > /*
> > > * Wa_14017066071
> > > * Wa_14017654203
> > > @@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> > > MTL_DISABLE_SAMPLER_SC_OOO);
> > > - if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > > /* Wa_22015279794 */
> > > wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> > > DISABLE_PREFETCH_INTO_IC);
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > > IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > > IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > > /* Wa_22013037850 */
> > > @@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> > > DISABLE_128B_EVICTION_COMMAND_UDW);
> > > }
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > > IS_PONTEVECCHIO(i915) ||
> > > IS_DG2(i915)) {
> > > /* Wa_22014226127 */
> > > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
> > > }
> > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > > IS_DG2(i915)) {
> > > /* Wa_18017747507 */
> > > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > index 1e532981f74e..300b968e6de8 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> > > flags |= GUC_WA_GAM_CREDITS;
> > > /* Wa_14014475959 */
> > > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > IS_DG2(gt->i915))
> > > flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > index 1bd5d8f7c40b..3b159069dbc4 100644
> > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > @@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
> > > /* Wa_14014475959:dg2 */
> > > if (engine->class == COMPUTE_CLASS)
> > > - if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
> > > + if (IS_GFX_IPVER_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > IS_DG2(engine->i915))
> > > engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index f38c93d82c56..d03710c923c8 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -692,9 +692,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> > > #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> > > (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> > > -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > > - (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
> > > - IS_GRAPHICS_STEP(__i915, since, until))
> > > +#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
> > > + (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
> > > + (__gt->type != GT_MEDIA && \
> > > + GRAPHICS_VER_FULL(__gt->i915) == ipver && \
> > > + IS_GRAPHICS_STEP(__gt->i915, since, until)))
> > > #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> > > (IS_METEORLAKE(__i915) && \
>
> --
> Matt Roper
> Graphics Software Engineer
> Linux GPU Platform Enablement
> Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
2023-07-19 22:54 ` Matt Roper
@ 2023-07-20 9:36 ` Tvrtko Ursulin
2023-07-20 13:10 ` Andrzej Hajda
0 siblings, 1 reply; 30+ messages in thread
From: Tvrtko Ursulin @ 2023-07-20 9:36 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On 19/07/2023 23:54, Matt Roper wrote:
> On Wed, Jul 19, 2023 at 08:28:12AM -0700, Matt Roper wrote:
>> On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
>>>
>>> On 18/07/2023 23:27, Matt Roper wrote:
>>>> Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
>>>> of these workarounds are actually tied to MTL as a platform; they only
>>>> relate to the Xe_LPG graphics IP, regardless of what platform it appears
>>>> in. At the moment MTL is the only platform that uses Xe_LPG with IP
>>>> versions 12.70 and 12.71, but we can't count on this being true in the
>>>> future. Switch these to use a new IS_GFX_IPVER_STEP() macro instead
>>>> that is purely based on IP version. IS_GFX_IPVER_STEP() is also
>>>> GT-based rather than device-based, which will help prevent mistakes
>>>> where we accidentally try to apply Xe_LPG graphics workarounds to the
>>>> Xe_LPM+ media GT.
>>>>
>>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>>> ---
>>>> .../drm/i915/display/skl_universal_plane.c | 4 +-
>>>> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 9 ++--
>>>> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 +-
>>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
>>>> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
>>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++++++++++---------
>>>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
>>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>>>> drivers/gpu/drm/i915/i915_drv.h | 8 +--
>>>> 9 files changed, 46 insertions(+), 41 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> index 6b01a0b68b97..c13e64faaaad 100644
>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
>>>> enum pipe pipe, enum plane_id plane_id)
>>>> {
>>>> /* Wa_14017240301 */
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> + if (IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
>>>
>>> Do we really need/want a combined/long macro like this and not split it out
>>> to something like a more readable IS_GFX_IPVER && IS_<...>_STEP?
>
> On this part, wouldn't that make it less readable? Right now these
> conditions are an ||'d list of cases for which the workaround should
> apply (relating to various entries in the workaround database). If we
> split the version, stepping, and GT checks out into separate macros
> we'll get more complex conditions that are a mix of && and ||. We can
> try that, but my gut feeling is that it's going to be more error-prone
> since we'll have to be really careful to always get the parenentheses in
> the right places. Also many people (myself included) are already having
> some trouble adjusting to the new idea of GT (primary vs media) being an
> important factor that needs to be considered in the workaround
> condition; one of the goals with these new macros was to make sure that
> got included in the macro so that it couldn't be omitted by accident.
Oh well I don't know.. maybe. It's just that I find that as amount of
all uppercase blocks grows over a certain limit things become quite an
eyesore and hard to read. One line of:
if (IS_GFX_IPVER_STEP(i915, IP_VER(12,70), STEP_A0, STEP_B0))
Is already borderline. A few of those on the same line is just hard to
parse. But your argument also has merit so again, don't know.
What I was suggesting is to maybe have:
IS_GFX_IPVER_STEP(i915, IP_VER(12,70), IP_STEP(A0, B0))
Marginally shorter.
Maybe find a shorted name for IS_GFX_IPVER_STEP?
IS_GFX_IP(i915, IP_VER(12,70), IP_STEP(A0, B0))
?
Too bad we can't have that macro take the stepping argument as optional.
Or maybe it is possible, I don't know C macro magic that well.
Also, if we added GT based macros we could get away with encoding the GT
type in the macro name. Asking the GT/tile directrly about their IP_VER.
Not sure how widely applicable tha would be so just a thought.
IS_IP(gt, IP_VER(12, 70))
GT_VER_FULL(gt) == IP_VER(13, 0)
Unless that falls apart with that GT is not a tile story.
Regards,
Tvrtko
>
>
> Matt
>
>>>
>>> Adding Jani since we were discussing this direction over the past few weeks.
>>>
>>> Hm.. macro trickery for stepping ranges to make it more compact? Like making
>>> the STEP_ prefix be prepended by the macro. Don't know..
>>
>> One other thing that we could consider if some of these things are
>> getting too long is eliminating IP_VER() and using the "versionx100"
>> scheme that Xe and Mesa use. On one hand that makes me a bit nervous
>> since GMD_ID's release number is 8 bits and could go past 100 on future
>> platforms, which would break the scheme (and we're already up to .71 on
>> MTL). But on the other hand it does make the code simpler and shorter
>> and we can always wait and see if we ever actually get a platform with
>> version X.100 or something before we really worry about what to do
>> there.
>>
>> The other point in favor of switching to versionx100 is that we wouldn't
>> have an inconsistent mix of both IP_VER() and verx100 in the Xe driver
>> where the display code comes from i915 but the non-display code is
>> separate.
>>
>>
>> Matt
>>
>>>
>>> Regards,
>>>
>>> Tvrtko
>>>
>>>> return false;
>>>> /* Wa_22011186057 */
>>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>> index 23857cc08eca..c1af91d908e5 100644
>>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
>>>> static int mtl_dummy_pipe_control(struct i915_request *rq)
>>>> {
>>>> /* Wa_14016712196 */
>>>> - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>>>> + if (IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>>> u32 *cs;
>>>> /* dummy PIPE_CONTROL + depth flush */
>>>> @@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>>>> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>>> {
>>>> struct drm_i915_private *i915 = rq->engine->i915;
>>>> + struct intel_gt *gt = rq->engine->gt;
>>>> u32 flags = (PIPE_CONTROL_CS_STALL |
>>>> PIPE_CONTROL_TLB_INVALIDATE |
>>>> PIPE_CONTROL_TILE_CACHE_FLUSH |
>>>> @@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>>> PIPE_CONTROL_FLUSH_ENABLE);
>>>> /* Wa_14016712196 */
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>>> /* dummy PIPE_CONTROL + depth flush */
>>>> cs = gen12_emit_pipe_control(cs, 0,
>>>> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>> index 0b414eae1683..41140eb86051 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>>>> gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
>>>> } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>>>> /* Wa_14016747170 */
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>>> fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>>>> intel_uncore_read(gt->uncore,
>>>> MTL_GT_ACTIVITY_FACTOR));
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>> index 1b710102390b..4fefa67d285f 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>> @@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
>>>> cs, GEN12_GFX_CCS_AUX_NV);
>>>> /* Wa_16014892111 */
>>>> - if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>>>> + if (IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>>> IS_DG2(ce->engine->i915))
>>>> cs = dg2_emit_draw_watermark_setting(cs);
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>>>> index 1ff7b42521c9..403f0d9caadf 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>>>> @@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
>>>> if (GRAPHICS_VER(gt->i915) < 11)
>>>> return false;
>>>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
>>>> return true;
>>>> if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> index 2a5bf50962ad..785453b2e95e 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> @@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>>>> static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>>>> struct i915_wa_list *wal)
>>>> {
>>>> - struct drm_i915_private *i915 = engine->i915;
>>>> + struct intel_gt *gt = engine->gt;
>>>> dg2_ctx_gt_tuning_init(engine, wal);
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
>>>> wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>>>> }
>>>> static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
>>>> struct i915_wa_list *wal)
>>>> {
>>>> - struct drm_i915_private *i915 = engine->i915;
>>>> + struct intel_gt *gt = engine->gt;
>>>> xelpg_ctx_gt_tuning_init(engine, wal);
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>>> /* Wa_14014947963 */
>>>> wa_masked_field_set(wal, VF_PREEMPTION,
>>>> PREEMPTION_VERTEX_COUNT, 0x4000);
>>>> @@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>>>> /* Wa_22016670082 */
>>>> wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>>>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>>> /* Wa_14014830051 */
>>>> wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>>>> @@ -2424,16 +2424,17 @@ static void
>>>> rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>> {
>>>> struct drm_i915_private *i915 = engine->i915;
>>>> + struct intel_gt *gt = engine->gt;
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>>> /* Wa_22014600077 */
>>>> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>> ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>>>> }
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>>> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>> /* Wa_1509727124 */
>>>> @@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>> IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) {
>>>> /* Wa_22012856258 */
>>>> wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>>>> GEN12_DISABLE_READ_SUPPRESSION);
>>>> @@ -3008,8 +3009,9 @@ static void
>>>> general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>>> {
>>>> struct drm_i915_private *i915 = engine->i915;
>>>> + struct intel_gt *gt = engine->gt;
>>>> - add_render_compute_tuning_settings(engine->gt, wal);
>>>> + add_render_compute_tuning_settings(gt, wal);
>>>> if (GRAPHICS_VER(i915) >= 11) {
>>>> /* This is not a Wa (although referred to as
>>>> @@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>>> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>> }
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
>>>> /* Wa_14017856879 */
>>>> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>>> /*
>>>> * Wa_14017066071
>>>> * Wa_14017654203
>>>> @@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>>> wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>>>> MTL_DISABLE_SAMPLER_SC_OOO);
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>>> /* Wa_22015279794 */
>>>> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>> DISABLE_PREFETCH_INTO_IC);
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>>> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>> /* Wa_22013037850 */
>>>> @@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>>> DISABLE_128B_EVICTION_COMMAND_UDW);
>>>> }
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>>> IS_PONTEVECCHIO(i915) ||
>>>> IS_DG2(i915)) {
>>>> /* Wa_22014226127 */
>>>> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
>>>> }
>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>>> IS_DG2(i915)) {
>>>> /* Wa_18017747507 */
>>>> wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>> index 1e532981f74e..300b968e6de8 100644
>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>>> flags |= GUC_WA_GAM_CREDITS;
>>>> /* Wa_14014475959 */
>>>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> IS_DG2(gt->i915))
>>>> flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>> index 1bd5d8f7c40b..3b159069dbc4 100644
>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>> @@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>>>> /* Wa_14014475959:dg2 */
>>>> if (engine->class == COMPUTE_CLASS)
>>>> - if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>>> + if (IS_GFX_IPVER_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>> IS_DG2(engine->i915))
>>>> engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>>> index f38c93d82c56..d03710c923c8 100644
>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>> @@ -692,9 +692,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>>> #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>>>> (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>>>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>>>> - (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
>>>> - IS_GRAPHICS_STEP(__i915, since, until))
>>>> +#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
>>>> + (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
>>>> + (__gt->type != GT_MEDIA && \
>>>> + GRAPHICS_VER_FULL(__gt->i915) == ipver && \
>>>> + IS_GRAPHICS_STEP(__gt->i915, since, until)))
>>>> #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>>>> (IS_METEORLAKE(__i915) && \
>>
>> --
>> Matt Roper
>> Graphics Software Engineer
>> Linux GPU Platform Enablement
>> Intel Corporation
>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
2023-07-20 9:36 ` Tvrtko Ursulin
@ 2023-07-20 13:10 ` Andrzej Hajda
2023-07-25 0:12 ` Matt Roper
0 siblings, 1 reply; 30+ messages in thread
From: Andrzej Hajda @ 2023-07-20 13:10 UTC (permalink / raw)
To: Tvrtko Ursulin, Matt Roper; +Cc: intel-gfx
On 20.07.2023 11:36, Tvrtko Ursulin wrote:
>
> On 19/07/2023 23:54, Matt Roper wrote:
>> On Wed, Jul 19, 2023 at 08:28:12AM -0700, Matt Roper wrote:
>>> On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
>>>>
>>>> On 18/07/2023 23:27, Matt Roper wrote:
>>>>> Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
>>>>> of these workarounds are actually tied to MTL as a platform; they only
>>>>> relate to the Xe_LPG graphics IP, regardless of what platform it
>>>>> appears
>>>>> in. At the moment MTL is the only platform that uses Xe_LPG with IP
>>>>> versions 12.70 and 12.71, but we can't count on this being true in the
>>>>> future. Switch these to use a new IS_GFX_IPVER_STEP() macro instead
>>>>> that is purely based on IP version. IS_GFX_IPVER_STEP() is also
>>>>> GT-based rather than device-based, which will help prevent mistakes
>>>>> where we accidentally try to apply Xe_LPG graphics workarounds to the
>>>>> Xe_LPM+ media GT.
>>>>>
>>>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>>>> ---
>>>>> .../drm/i915/display/skl_universal_plane.c | 4 +-
>>>>> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 9 ++--
>>>>> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 +-
>>>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
>>>>> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
>>>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 52
>>>>> ++++++++++---------
>>>>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
>>>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>>>>> drivers/gpu/drm/i915/i915_drv.h | 8 +--
>>>>> 9 files changed, 46 insertions(+), 41 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>> index 6b01a0b68b97..c13e64faaaad 100644
>>>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>>>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct
>>>>> drm_i915_private *i915,
>>>>> enum pipe pipe, enum plane_id plane_id)
>>>>> {
>>>>> /* Wa_14017240301 */
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>> + if (IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0,
>>>>> STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0,
>>>>> STEP_B0))
>>>>
>>>> Do we really need/want a combined/long macro like this and not split
>>>> it out
>>>> to something like a more readable IS_GFX_IPVER && IS_<...>_STEP?
>>
>> On this part, wouldn't that make it less readable? Right now these
>> conditions are an ||'d list of cases for which the workaround should
>> apply (relating to various entries in the workaround database). If we
>> split the version, stepping, and GT checks out into separate macros
>> we'll get more complex conditions that are a mix of && and ||. We can
>> try that, but my gut feeling is that it's going to be more error-prone
>> since we'll have to be really careful to always get the parenentheses in
>> the right places. Also many people (myself included) are already having
>> some trouble adjusting to the new idea of GT (primary vs media) being an
>> important factor that needs to be considered in the workaround
>> condition; one of the goals with these new macros was to make sure that
>> got included in the macro so that it couldn't be omitted by accident.
>
> Oh well I don't know.. maybe. It's just that I find that as amount of
> all uppercase blocks grows over a certain limit things become quite an
> eyesore and hard to read. One line of:
>
> if (IS_GFX_IPVER_STEP(i915, IP_VER(12,70), STEP_A0, STEP_B0))
>
> Is already borderline. A few of those on the same line is just hard to
> parse. But your argument also has merit so again, don't know.
>
> What I was suggesting is to maybe have:
>
> IS_GFX_IPVER_STEP(i915, IP_VER(12,70), IP_STEP(A0, B0))
>
> Marginally shorter.
>
> Maybe find a shorted name for IS_GFX_IPVER_STEP?
>
> IS_GFX_IP(i915, IP_VER(12,70), IP_STEP(A0, B0))
>
> ?
>
> Too bad we can't have that macro take the stepping argument as optional.
> Or maybe it is possible, I don't know C macro magic that well.
It is possible:
#define IS_GFX_IP(i915, ver, args...) IS_GFX_IP_STEP(i915, ver, args,
default_step)
#define IS_GFX_IP_STEP(i915, ver, step, ...) definition_ignoring_elipsis
Assuming IP_STEP is just single value.
I am not sure about meaning of steppings in i915, it looks somehow
special. If it is just another dot in version MAJOR.MINOR.STEP, why not
extend IP_VER with stepping (ver << 16 & rel << 8 & step):
IP_VER(12)
IP_VER(12,70)
IP_VER(12, 70, A0)
then for example:
IS_IP_VER(gt, IP_VER(12))
IS_IP_VER(gt, IP_VER(12), IP_VER(13))
IS_IP_REL(gt, IP_VER(12, 70))
IS_IP_REL(gt, IP_VER(12, 70), IP_VER(12, 71))
IS_IP_STEP(gt, IP_VER(12, 70, A0))
IS_IP_STEP(gt, IP_VER(12, 70, A0), IP_VER(12, 70, B0))
Regards
Andrzej
>
> Also, if we added GT based macros we could get away with encoding the GT
> type in the macro name. Asking the GT/tile directrly about their IP_VER.
> Not sure how widely applicable tha would be so just a thought.
>
> IS_IP(gt, IP_VER(12, 70))
>
> GT_VER_FULL(gt) == IP_VER(13, 0)
>
> Unless that falls apart with that GT is not a tile story.
>
> Regards,
>
> Tvrtko
>
>>
>>
>> Matt
>>
>>>>
>>>> Adding Jani since we were discussing this direction over the past
>>>> few weeks.
>>>>
>>>> Hm.. macro trickery for stepping ranges to make it more compact?
>>>> Like making
>>>> the STEP_ prefix be prepended by the macro. Don't know..
>>>
>>> One other thing that we could consider if some of these things are
>>> getting too long is eliminating IP_VER() and using the "versionx100"
>>> scheme that Xe and Mesa use. On one hand that makes me a bit nervous
>>> since GMD_ID's release number is 8 bits and could go past 100 on future
>>> platforms, which would break the scheme (and we're already up to .71 on
>>> MTL). But on the other hand it does make the code simpler and shorter
>>> and we can always wait and see if we ever actually get a platform with
>>> version X.100 or something before we really worry about what to do
>>> there.
>>>
>>> The other point in favor of switching to versionx100 is that we wouldn't
>>> have an inconsistent mix of both IP_VER() and verx100 in the Xe driver
>>> where the display code comes from i915 but the non-display code is
>>> separate.
>>>
>>>
>>> Matt
>>>
>>>>
>>>> Regards,
>>>>
>>>> Tvrtko
>>>>
>>>>> return false;
>>>>> /* Wa_22011186057 */
>>>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>>> index 23857cc08eca..c1af91d908e5 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt
>>>>> *gt, u32 *cs, const i915_reg_t inv
>>>>> static int mtl_dummy_pipe_control(struct i915_request *rq)
>>>>> {
>>>>> /* Wa_14016712196 */
>>>>> - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0,
>>>>> STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0,
>>>>> STEP_B0)) {
>>>>> + if (IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0,
>>>>> STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0,
>>>>> STEP_B0)) {
>>>>> u32 *cs;
>>>>> /* dummy PIPE_CONTROL + depth flush */
>>>>> @@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct
>>>>> i915_request *rq, u32 *cs)
>>>>> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32
>>>>> *cs)
>>>>> {
>>>>> struct drm_i915_private *i915 = rq->engine->i915;
>>>>> + struct intel_gt *gt = rq->engine->gt;
>>>>> u32 flags = (PIPE_CONTROL_CS_STALL |
>>>>> PIPE_CONTROL_TLB_INVALIDATE |
>>>>> PIPE_CONTROL_TILE_CACHE_FLUSH |
>>>>> @@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct
>>>>> i915_request *rq, u32 *cs)
>>>>> PIPE_CONTROL_FLUSH_ENABLE);
>>>>> /* Wa_14016712196 */
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>>>> /* dummy PIPE_CONTROL + depth flush */
>>>>> cs = gen12_emit_pipe_control(cs, 0,
>>>>> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>>> b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>>> index 0b414eae1683..41140eb86051 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>>>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>>>>> gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
>>>>> } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>>>>> /* Wa_14016747170 */
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0,
>>>>> STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>>>> fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>>>>> intel_uncore_read(gt->uncore,
>>>>> MTL_GT_ACTIVITY_FACTOR));
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>> b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>> index 1b710102390b..4fefa67d285f 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>> @@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct
>>>>> intel_context *ce, u32 *cs)
>>>>> cs, GEN12_GFX_CCS_AUX_NV);
>>>>> /* Wa_16014892111 */
>>>>> - if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0,
>>>>> STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0,
>>>>> STEP_B0) ||
>>>>> + if (IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0,
>>>>> STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0,
>>>>> STEP_B0) ||
>>>>> IS_DG2(ce->engine->i915))
>>>>> cs = dg2_emit_draw_watermark_setting(cs);
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
>>>>> b/drivers/gpu/drm/i915/gt/intel_reset.c
>>>>> index 1ff7b42521c9..403f0d9caadf 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>>>>> @@ -1641,7 +1641,7 @@ bool
>>>>> intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
>>>>> if (GRAPHICS_VER(gt->i915) < 11)
>>>>> return false;
>>>>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
>>>>> return true;
>>>>> if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> index 2a5bf50962ad..785453b2e95e 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>>> @@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct
>>>>> intel_engine_cs *engine,
>>>>> static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs
>>>>> *engine,
>>>>> struct i915_wa_list *wal)
>>>>> {
>>>>> - struct drm_i915_private *i915 = engine->i915;
>>>>> + struct intel_gt *gt = engine->gt;
>>>>> dg2_ctx_gt_tuning_init(engine, wal);
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0,
>>>>> STEP_FOREVER) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
>>>>> wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>>>>> }
>>>>> static void xelpg_ctx_workarounds_init(struct intel_engine_cs
>>>>> *engine,
>>>>> struct i915_wa_list *wal)
>>>>> {
>>>>> - struct drm_i915_private *i915 = engine->i915;
>>>>> + struct intel_gt *gt = engine->gt;
>>>>> xelpg_ctx_gt_tuning_init(engine, wal);
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>>>> /* Wa_14014947963 */
>>>>> wa_masked_field_set(wal, VF_PREEMPTION,
>>>>> PREEMPTION_VERTEX_COUNT, 0x4000);
>>>>> @@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt
>>>>> *gt, struct i915_wa_list *wal)
>>>>> /* Wa_22016670082 */
>>>>> wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>>>>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>>>> /* Wa_14014830051 */
>>>>> wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>>>>> @@ -2424,16 +2424,17 @@ static void
>>>>> rcs_engine_wa_init(struct intel_engine_cs *engine, struct
>>>>> i915_wa_list *wal)
>>>>> {
>>>>> struct drm_i915_private *i915 = engine->i915;
>>>>> + struct intel_gt *gt = engine->gt;
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>>>> /* Wa_22014600077 */
>>>>> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>>> ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>>>>> }
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>>>> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>>> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>>> /* Wa_1509727124 */
>>>>> @@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs
>>>>> *engine, struct i915_wa_list *wal)
>>>>> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>>> IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) {
>>>>> /* Wa_22012856258 */
>>>>> wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>>>>> GEN12_DISABLE_READ_SUPPRESSION);
>>>>> @@ -3008,8 +3009,9 @@ static void
>>>>> general_render_compute_wa_init(struct intel_engine_cs *engine,
>>>>> struct i915_wa_list *wal)
>>>>> {
>>>>> struct drm_i915_private *i915 = engine->i915;
>>>>> + struct intel_gt *gt = engine->gt;
>>>>> - add_render_compute_tuning_settings(engine->gt, wal);
>>>>> + add_render_compute_tuning_settings(gt, wal);
>>>>> if (GRAPHICS_VER(i915) >= 11) {
>>>>> /* This is not a Wa (although referred to as
>>>>> @@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct
>>>>> intel_engine_cs *engine, struct i915_wa_li
>>>>> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>>>> }
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0,
>>>>> STEP_FOREVER) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
>>>>> /* Wa_14017856879 */
>>>>> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
>>>>> MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>>>> /*
>>>>> * Wa_14017066071
>>>>> * Wa_14017654203
>>>>> @@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct
>>>>> intel_engine_cs *engine, struct i915_wa_li
>>>>> wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>>>>> MTL_DISABLE_SAMPLER_SC_OOO);
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>>>> /* Wa_22015279794 */
>>>>> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>>>> DISABLE_PREFETCH_INTO_IC);
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>>>> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>>>> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>>>> /* Wa_22013037850 */
>>>>> @@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct
>>>>> intel_engine_cs *engine, struct i915_wa_li
>>>>> DISABLE_128B_EVICTION_COMMAND_UDW);
>>>>> }
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>>>> IS_PONTEVECCHIO(i915) ||
>>>>> IS_DG2(i915)) {
>>>>> /* Wa_22014226127 */
>>>>> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
>>>>> DISABLE_D8_D16_COASLESCE);
>>>>> }
>>>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>>>> IS_DG2(i915)) {
>>>>> /* Wa_18017747507 */
>>>>> wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
>>>>> POLYGON_TRIFAN_LINELOOP_DISABLE);
>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>>> index 1e532981f74e..300b968e6de8 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>>>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>>>> flags |= GUC_WA_GAM_CREDITS;
>>>>> /* Wa_14014475959 */
>>>>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>>>> IS_DG2(gt->i915))
>>>>> flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>>>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>> index 1bd5d8f7c40b..3b159069dbc4 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>>>> @@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct
>>>>> intel_engine_cs *engine)
>>>>> /* Wa_14014475959:dg2 */
>>>>> if (engine->class == COMPUTE_CLASS)
>>>>> - if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0,
>>>>> STEP_B0) ||
>>>>> + if (IS_GFX_IPVER_STEP(engine->gt, IP_VER(12, 70), STEP_A0,
>>>>> STEP_B0) ||
>>>>> IS_DG2(engine->i915))
>>>>> engine->flags |=
>>>>> I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>>>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>>>>> b/drivers/gpu/drm/i915/i915_drv.h
>>>>> index f38c93d82c56..d03710c923c8 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>>>> @@ -692,9 +692,11 @@ IS_SUBPLATFORM(const struct drm_i915_private
>>>>> *i915,
>>>>> #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>>>>> (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>>>>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>>>>> - (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
>>>>> INTEL_SUBPLATFORM_##variant) && \
>>>>> - IS_GRAPHICS_STEP(__i915, since, until))
>>>>> +#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
>>>>> + (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
>>>>> + (__gt->type != GT_MEDIA && \
>>>>> + GRAPHICS_VER_FULL(__gt->i915) == ipver && \
>>>>> + IS_GRAPHICS_STEP(__gt->i915, since, until)))
>>>>> #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>>>>> (IS_METEORLAKE(__i915) && \
>>>
>>> --
>>> Matt Roper
>>> Graphics Software Engineer
>>> Linux GPU Platform Enablement
>>> Intel Corporation
>>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
2023-07-20 13:10 ` Andrzej Hajda
@ 2023-07-25 0:12 ` Matt Roper
0 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2023-07-25 0:12 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
On Thu, Jul 20, 2023 at 03:10:21PM +0200, Andrzej Hajda wrote:
> On 20.07.2023 11:36, Tvrtko Ursulin wrote:
> >
> > On 19/07/2023 23:54, Matt Roper wrote:
> > > On Wed, Jul 19, 2023 at 08:28:12AM -0700, Matt Roper wrote:
> > > > On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
> > > > >
> > > > > On 18/07/2023 23:27, Matt Roper wrote:
> > > > > > Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
> > > > > > of these workarounds are actually tied to MTL as a platform; they only
> > > > > > relate to the Xe_LPG graphics IP, regardless of what
> > > > > > platform it appears
> > > > > > in. At the moment MTL is the only platform that uses Xe_LPG with IP
> > > > > > versions 12.70 and 12.71, but we can't count on this being true in the
> > > > > > future. Switch these to use a new IS_GFX_IPVER_STEP() macro instead
> > > > > > that is purely based on IP version. IS_GFX_IPVER_STEP() is also
> > > > > > GT-based rather than device-based, which will help prevent mistakes
> > > > > > where we accidentally try to apply Xe_LPG graphics workarounds to the
> > > > > > Xe_LPM+ media GT.
> > > > > >
> > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > > ---
> > > > > > .../drm/i915/display/skl_universal_plane.c | 4 +-
> > > > > > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 9 ++--
> > > > > > drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 +-
> > > > > > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
> > > > > > drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> > > > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 52
> > > > > > ++++++++++---------
> > > > > > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
> > > > > > .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
> > > > > > drivers/gpu/drm/i915/i915_drv.h | 8 +--
> > > > > > 9 files changed, 46 insertions(+), 41 deletions(-)
> > > > > >
> > > > > > diff --git
> > > > > > a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > index 6b01a0b68b97..c13e64faaaad 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > > > > @@ -2169,8 +2169,8 @@ static bool
> > > > > > skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> > > > > > enum pipe pipe, enum plane_id plane_id)
> > > > > > {
> > > > > > /* Wa_14017240301 */
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > > > > + if (IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 70),
> > > > > > STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 71),
> > > > > > STEP_A0, STEP_B0))
> > > > >
> > > > > Do we really need/want a combined/long macro like this and
> > > > > not split it out
> > > > > to something like a more readable IS_GFX_IPVER && IS_<...>_STEP?
> > >
> > > On this part, wouldn't that make it less readable? Right now these
> > > conditions are an ||'d list of cases for which the workaround should
> > > apply (relating to various entries in the workaround database). If we
> > > split the version, stepping, and GT checks out into separate macros
> > > we'll get more complex conditions that are a mix of && and ||. We can
> > > try that, but my gut feeling is that it's going to be more error-prone
> > > since we'll have to be really careful to always get the parenentheses in
> > > the right places. Also many people (myself included) are already having
> > > some trouble adjusting to the new idea of GT (primary vs media) being an
> > > important factor that needs to be considered in the workaround
> > > condition; one of the goals with these new macros was to make sure that
> > > got included in the macro so that it couldn't be omitted by accident.
> >
> > Oh well I don't know.. maybe. It's just that I find that as amount of
> > all uppercase blocks grows over a certain limit things become quite an
> > eyesore and hard to read. One line of:
> >
> > if (IS_GFX_IPVER_STEP(i915, IP_VER(12,70), STEP_A0, STEP_B0))
> >
> > Is already borderline. A few of those on the same line is just hard to
> > parse. But your argument also has merit so again, don't know.
> >
> > What I was suggesting is to maybe have:
> >
> > IS_GFX_IPVER_STEP(i915, IP_VER(12,70), IP_STEP(A0, B0))
> >
> > Marginally shorter.
> >
> > Maybe find a shorted name for IS_GFX_IPVER_STEP?
> >
> > IS_GFX_IP(i915, IP_VER(12,70), IP_STEP(A0, B0))
> >
> > ?
> >
> > Too bad we can't have that macro take the stepping argument as optional.
> > Or maybe it is possible, I don't know C macro magic that well.
>
> It is possible:
>
> #define IS_GFX_IP(i915, ver, args...) IS_GFX_IP_STEP(i915, ver, args,
> default_step)
> #define IS_GFX_IP_STEP(i915, ver, step, ...) definition_ignoring_elipsis
>
> Assuming IP_STEP is just single value.
>
> I am not sure about meaning of steppings in i915, it looks somehow special.
> If it is just another dot in version MAJOR.MINOR.STEP, why not extend IP_VER
> with stepping (ver << 16 & rel << 8 & step):
> IP_VER(12)
> IP_VER(12,70)
> IP_VER(12, 70, A0)
>
> then for example:
> IS_IP_VER(gt, IP_VER(12))
> IS_IP_VER(gt, IP_VER(12), IP_VER(13))
> IS_IP_REL(gt, IP_VER(12, 70))
> IS_IP_REL(gt, IP_VER(12, 70), IP_VER(12, 71))
> IS_IP_STEP(gt, IP_VER(12, 70, A0))
> IS_IP_STEP(gt, IP_VER(12, 70, A0), IP_VER(12, 70, B0))
I'm not sure it's a good idea to include stepping in the general IP_VER
value because the version and stepping information are used in very
different ways in the driver.
- If we're checking a range of versions, it's an inclusive range of IP
versions that the behavior applies to.
- If we're checking a range of steppings, it's always within one
specific IP version (it's not possible to compare steppings in a
sensible way cross-version) and the comparison is expected to match
an entry in the workaround database. Because the workaround database
is based on "hardware fix" version numbers, the range always has an
exclusive upper bound (since that's the "fix version" at which the
workaround should no longer be applied.
Even if we use CPP trickery to create macros that take default values, I
don't see how we'd use that effectively since the appropriate default
value would change depending on which type of comparison we were doing
(and also whether it was an upper or lower bound for a range).
Matt
>
> Regards
> Andrzej
>
>
> >
> > Also, if we added GT based macros we could get away with encoding the GT
> > type in the macro name. Asking the GT/tile directrly about their IP_VER.
> > Not sure how widely applicable tha would be so just a thought.
> >
> > IS_IP(gt, IP_VER(12, 70))
> >
> > GT_VER_FULL(gt) == IP_VER(13, 0)
> >
> > Unless that falls apart with that GT is not a tile story.
> >
> > Regards,
> >
> > Tvrtko
> >
> > >
> > >
> > > Matt
> > >
> > > > >
> > > > > Adding Jani since we were discussing this direction over the
> > > > > past few weeks.
> > > > >
> > > > > Hm.. macro trickery for stepping ranges to make it more
> > > > > compact? Like making
> > > > > the STEP_ prefix be prepended by the macro. Don't know..
> > > >
> > > > One other thing that we could consider if some of these things are
> > > > getting too long is eliminating IP_VER() and using the "versionx100"
> > > > scheme that Xe and Mesa use. On one hand that makes me a bit nervous
> > > > since GMD_ID's release number is 8 bits and could go past 100 on future
> > > > platforms, which would break the scheme (and we're already up to .71 on
> > > > MTL). But on the other hand it does make the code simpler and shorter
> > > > and we can always wait and see if we ever actually get a platform with
> > > > version X.100 or something before we really worry about what to do
> > > > there.
> > > >
> > > > The other point in favor of switching to versionx100 is that we wouldn't
> > > > have an inconsistent mix of both IP_VER() and verx100 in the Xe driver
> > > > where the display code comes from i915 but the non-display code is
> > > > separate.
> > > >
> > > >
> > > > Matt
> > > >
> > > > >
> > > > > Regards,
> > > > >
> > > > > Tvrtko
> > > > >
> > > > > > return false;
> > > > > > /* Wa_22011186057 */
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > > > > b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > > > > index 23857cc08eca..c1af91d908e5 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> > > > > > @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct
> > > > > > intel_gt *gt, u32 *cs, const i915_reg_t inv
> > > > > > static int mtl_dummy_pipe_control(struct i915_request *rq)
> > > > > > {
> > > > > > /* Wa_14016712196 */
> > > > > > - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M,
> > > > > > STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P,
> > > > > > STEP_A0, STEP_B0)) {
> > > > > > + if (IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12,
> > > > > > 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12,
> > > > > > 71), STEP_A0, STEP_B0)) {
> > > > > > u32 *cs;
> > > > > > /* dummy PIPE_CONTROL + depth flush */
> > > > > > @@ -755,6 +755,7 @@ u32
> > > > > > *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq,
> > > > > > u32 *cs)
> > > > > > u32 *gen12_emit_fini_breadcrumb_rcs(struct
> > > > > > i915_request *rq, u32 *cs)
> > > > > > {
> > > > > > struct drm_i915_private *i915 = rq->engine->i915;
> > > > > > + struct intel_gt *gt = rq->engine->gt;
> > > > > > u32 flags = (PIPE_CONTROL_CS_STALL |
> > > > > > PIPE_CONTROL_TLB_INVALIDATE |
> > > > > > PIPE_CONTROL_TILE_CACHE_FLUSH |
> > > > > > @@ -765,8 +766,8 @@ u32
> > > > > > *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq,
> > > > > > u32 *cs)
> > > > > > PIPE_CONTROL_FLUSH_ENABLE);
> > > > > > /* Wa_14016712196 */
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > > > > > /* dummy PIPE_CONTROL + depth flush */
> > > > > > cs = gen12_emit_pipe_control(cs, 0,
> > > > > > PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > > > > > b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > > > > > index 0b414eae1683..41140eb86051 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
> > > > > > @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
> > > > > > gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
> > > > > > } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
> > > > > > /* Wa_14016747170 */
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70),
> > > > > > STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > > > > > fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
> > > > > > intel_uncore_read(gt->uncore,
> > > > > > MTL_GT_ACTIVITY_FACTOR));
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > > > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > > > index 1b710102390b..4fefa67d285f 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > > > > @@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const
> > > > > > struct intel_context *ce, u32 *cs)
> > > > > > cs, GEN12_GFX_CCS_AUX_NV);
> > > > > > /* Wa_16014892111 */
> > > > > > - if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M,
> > > > > > STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(ce->engine->i915, P,
> > > > > > STEP_A0, STEP_B0) ||
> > > > > > + if (IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12,
> > > > > > 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12,
> > > > > > 71), STEP_A0, STEP_B0) ||
> > > > > > IS_DG2(ce->engine->i915))
> > > > > > cs = dg2_emit_draw_watermark_setting(cs);
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > > b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > > index 1ff7b42521c9..403f0d9caadf 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > > > > > @@ -1641,7 +1641,7 @@ bool
> > > > > > intel_engine_reset_needs_wa_22011802037(struct intel_gt
> > > > > > *gt)
> > > > > > if (GRAPHICS_VER(gt->i915) < 11)
> > > > > > return false;
> > > > > > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
> > > > > > return true;
> > > > > > if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > > b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > > index 2a5bf50962ad..785453b2e95e 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > > > > > @@ -808,24 +808,24 @@ static void
> > > > > > dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > > > > > static void xelpg_ctx_gt_tuning_init(struct
> > > > > > intel_engine_cs *engine,
> > > > > > struct i915_wa_list *wal)
> > > > > > {
> > > > > > - struct drm_i915_private *i915 = engine->i915;
> > > > > > + struct intel_gt *gt = engine->gt;
> > > > > > dg2_ctx_gt_tuning_init(engine, wal);
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0,
> > > > > > STEP_FOREVER) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> > > > > > wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
> > > > > > }
> > > > > > static void xelpg_ctx_workarounds_init(struct
> > > > > > intel_engine_cs *engine,
> > > > > > struct i915_wa_list *wal)
> > > > > > {
> > > > > > - struct drm_i915_private *i915 = engine->i915;
> > > > > > + struct intel_gt *gt = engine->gt;
> > > > > > xelpg_ctx_gt_tuning_init(engine, wal);
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > > > > > /* Wa_14014947963 */
> > > > > > wa_masked_field_set(wal, VF_PREEMPTION,
> > > > > > PREEMPTION_VERTEX_COUNT, 0x4000);
> > > > > > @@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct
> > > > > > intel_gt *gt, struct i915_wa_list *wal)
> > > > > > /* Wa_22016670082 */
> > > > > > wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
> > > > > > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > > > > > /* Wa_14014830051 */
> > > > > > wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
> > > > > > @@ -2424,16 +2424,17 @@ static void
> > > > > > rcs_engine_wa_init(struct intel_engine_cs *engine,
> > > > > > struct i915_wa_list *wal)
> > > > > > {
> > > > > > struct drm_i915_private *i915 = engine->i915;
> > > > > > + struct intel_gt *gt = engine->gt;
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
> > > > > > /* Wa_22014600077 */
> > > > > > wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> > > > > > ENABLE_EU_COUNT_FOR_TDL_FLUSH);
> > > > > > }
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > > > > > IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > > > > > IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > > > > > /* Wa_1509727124 */
> > > > > > @@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct
> > > > > > intel_engine_cs *engine, struct i915_wa_list *wal)
> > > > > > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > > > > > IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) {
> > > > > > /* Wa_22012856258 */
> > > > > > wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
> > > > > > GEN12_DISABLE_READ_SUPPRESSION);
> > > > > > @@ -3008,8 +3009,9 @@ static void
> > > > > > general_render_compute_wa_init(struct intel_engine_cs
> > > > > > *engine, struct i915_wa_list *wal)
> > > > > > {
> > > > > > struct drm_i915_private *i915 = engine->i915;
> > > > > > + struct intel_gt *gt = engine->gt;
> > > > > > - add_render_compute_tuning_settings(engine->gt, wal);
> > > > > > + add_render_compute_tuning_settings(gt, wal);
> > > > > > if (GRAPHICS_VER(i915) >= 11) {
> > > > > > /* This is not a Wa (although referred to as
> > > > > > @@ -3030,13 +3032,13 @@
> > > > > > general_render_compute_wa_init(struct intel_engine_cs
> > > > > > *engine, struct i915_wa_li
> > > > > > GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
> > > > > > }
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0,
> > > > > > STEP_FOREVER) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
> > > > > > /* Wa_14017856879 */
> > > > > > wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3,
> > > > > > MTL_DISABLE_FIX_FOR_EOT_FLUSH);
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > > > > > /*
> > > > > > * Wa_14017066071
> > > > > > * Wa_14017654203
> > > > > > @@ -3044,13 +3046,13 @@
> > > > > > general_render_compute_wa_init(struct intel_engine_cs
> > > > > > *engine, struct i915_wa_li
> > > > > > wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
> > > > > > MTL_DISABLE_SAMPLER_SC_OOO);
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
> > > > > > /* Wa_22015279794 */
> > > > > > wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
> > > > > > DISABLE_PREFETCH_INTO_IC);
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > > > > > IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
> > > > > > IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
> > > > > > /* Wa_22013037850 */
> > > > > > @@ -3058,16 +3060,16 @@
> > > > > > general_render_compute_wa_init(struct intel_engine_cs
> > > > > > *engine, struct i915_wa_li
> > > > > > DISABLE_128B_EVICTION_COMMAND_UDW);
> > > > > > }
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > > > > > IS_PONTEVECCHIO(i915) ||
> > > > > > IS_DG2(i915)) {
> > > > > > /* Wa_22014226127 */
> > > > > > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
> > > > > > DISABLE_D8_D16_COASLESCE);
> > > > > > }
> > > > > > - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
> > > > > > - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
> > > > > > IS_DG2(i915)) {
> > > > > > /* Wa_18017747507 */
> > > > > > wa_masked_en(wal, VFG_PREEMPTION_CHICKEN,
> > > > > > POLYGON_TRIFAN_LINELOOP_DISABLE);
> > > > > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > > > b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > > > index 1e532981f74e..300b968e6de8 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > > > > > @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
> > > > > > flags |= GUC_WA_GAM_CREDITS;
> > > > > > /* Wa_14014475959 */
> > > > > > - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
> > > > > > + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
> > > > > > IS_DG2(gt->i915))
> > > > > > flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
> > > > > > diff --git
> > > > > > a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > > > b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > > > index 1bd5d8f7c40b..3b159069dbc4 100644
> > > > > > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > > > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> > > > > > @@ -4265,7 +4265,7 @@ static void
> > > > > > guc_default_vfuncs(struct intel_engine_cs *engine)
> > > > > > /* Wa_14014475959:dg2 */
> > > > > > if (engine->class == COMPUTE_CLASS)
> > > > > > - if (IS_MTL_GRAPHICS_STEP(engine->i915, M,
> > > > > > STEP_A0, STEP_B0) ||
> > > > > > + if (IS_GFX_IPVER_STEP(engine->gt, IP_VER(12,
> > > > > > 70), STEP_A0, STEP_B0) ||
> > > > > > IS_DG2(engine->i915))
> > > > > > engine->flags |=
> > > > > > I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
> > > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > index f38c93d82c56..d03710c923c8 100644
> > > > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > > > @@ -692,9 +692,11 @@ IS_SUBPLATFORM(const struct
> > > > > > drm_i915_private *i915,
> > > > > > #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
> > > > > > (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
> > > > > > -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
> > > > > > - (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE,
> > > > > > INTEL_SUBPLATFORM_##variant) && \
> > > > > > - IS_GRAPHICS_STEP(__i915, since, until))
> > > > > > +#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
> > > > > > + (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
> > > > > > + (__gt->type != GT_MEDIA && \
> > > > > > + GRAPHICS_VER_FULL(__gt->i915) == ipver && \
> > > > > > + IS_GRAPHICS_STEP(__gt->i915, since, until)))
> > > > > > #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
> > > > > > (IS_METEORLAKE(__i915) && \
> > > >
> > > > --
> > > > Matt Roper
> > > > Graphics Software Engineer
> > > > Linux GPU Platform Enablement
> > > > Intel Corporation
> > >
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
2023-07-19 15:28 ` Matt Roper
2023-07-19 22:54 ` Matt Roper
@ 2023-07-20 9:23 ` Tvrtko Ursulin
1 sibling, 0 replies; 30+ messages in thread
From: Tvrtko Ursulin @ 2023-07-20 9:23 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On 19/07/2023 16:28, Matt Roper wrote:
> On Wed, Jul 19, 2023 at 09:01:58AM +0100, Tvrtko Ursulin wrote:
>>
>> On 18/07/2023 23:27, Matt Roper wrote:
>>> Several workarounds are guarded by IS_MTL_GRAPHICS_STEP. However none
>>> of these workarounds are actually tied to MTL as a platform; they only
>>> relate to the Xe_LPG graphics IP, regardless of what platform it appears
>>> in. At the moment MTL is the only platform that uses Xe_LPG with IP
>>> versions 12.70 and 12.71, but we can't count on this being true in the
>>> future. Switch these to use a new IS_GFX_IPVER_STEP() macro instead
>>> that is purely based on IP version. IS_GFX_IPVER_STEP() is also
>>> GT-based rather than device-based, which will help prevent mistakes
>>> where we accidentally try to apply Xe_LPG graphics workarounds to the
>>> Xe_LPM+ media GT.
>>>
>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>> ---
>>> .../drm/i915/display/skl_universal_plane.c | 4 +-
>>> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 9 ++--
>>> drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 4 +-
>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 +-
>>> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 ++++++++++---------
>>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
>>> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 2 +-
>>> drivers/gpu/drm/i915/i915_drv.h | 8 +--
>>> 9 files changed, 46 insertions(+), 41 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> index 6b01a0b68b97..c13e64faaaad 100644
>>> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
>>> @@ -2169,8 +2169,8 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
>>> enum pipe pipe, enum plane_id plane_id)
>>> {
>>> /* Wa_14017240301 */
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> + if (IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
>>
>> Do we really need/want a combined/long macro like this and not split it out
>> to something like a more readable IS_GFX_IPVER && IS_<...>_STEP?
>>
>> Adding Jani since we were discussing this direction over the past few weeks.
>>
>> Hm.. macro trickery for stepping ranges to make it more compact? Like making
>> the STEP_ prefix be prepended by the macro. Don't know..
>
> One other thing that we could consider if some of these things are
> getting too long is eliminating IP_VER() and using the "versionx100"
> scheme that Xe and Mesa use. On one hand that makes me a bit nervous
> since GMD_ID's release number is 8 bits and could go past 100 on future
> platforms, which would break the scheme (and we're already up to .71 on
> MTL). But on the other hand it does make the code simpler and shorter
> and we can always wait and see if we ever actually get a platform with
> version X.100 or something before we really worry about what to do
> there.
>
> The other point in favor of switching to versionx100 is that we wouldn't
> have an inconsistent mix of both IP_VER() and verx100 in the Xe driver
> where the display code comes from i915 but the non-display code is
> separate.
I don't think IP_VER is a problem for readability, the opposite. And it
nicely enables do to stuff under the hood without churn. So maybe go
IP_VER in Xe? Best to settle on these small details as much as possible
before first release.
Regards,
Tvrtko
>
>
> Matt
>
>>
>> Regards,
>>
>> Tvrtko
>>
>>> return false;
>>> /* Wa_22011186057 */
>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> index 23857cc08eca..c1af91d908e5 100644
>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
>>> static int mtl_dummy_pipe_control(struct i915_request *rq)
>>> {
>>> /* Wa_14016712196 */
>>> - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>>> + if (IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(rq->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>> u32 *cs;
>>> /* dummy PIPE_CONTROL + depth flush */
>>> @@ -755,6 +755,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>>> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>> {
>>> struct drm_i915_private *i915 = rq->engine->i915;
>>> + struct intel_gt *gt = rq->engine->gt;
>>> u32 flags = (PIPE_CONTROL_CS_STALL |
>>> PIPE_CONTROL_TLB_INVALIDATE |
>>> PIPE_CONTROL_TILE_CACHE_FLUSH |
>>> @@ -765,8 +766,8 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>> PIPE_CONTROL_FLUSH_ENABLE);
>>> /* Wa_14016712196 */
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>> /* dummy PIPE_CONTROL + depth flush */
>>> cs = gen12_emit_pipe_control(cs, 0,
>>> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> index 0b414eae1683..41140eb86051 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
>>> @@ -166,8 +166,8 @@ void intel_gt_mcr_init(struct intel_gt *gt)
>>> gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
>>> } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
>>> /* Wa_14016747170 */
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>> fuse = REG_FIELD_GET(MTL_GT_L3_EXC_MASK,
>>> intel_uncore_read(gt->uncore,
>>> MTL_GT_ACTIVITY_FACTOR));
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> index 1b710102390b..4fefa67d285f 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> @@ -1377,8 +1377,8 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
>>> cs, GEN12_GFX_CCS_AUX_NV);
>>> /* Wa_16014892111 */
>>> - if (IS_MTL_GRAPHICS_STEP(ce->engine->i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(ce->engine->i915, P, STEP_A0, STEP_B0) ||
>>> + if (IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(ce->engine->gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>> IS_DG2(ce->engine->i915))
>>> cs = dg2_emit_draw_watermark_setting(cs);
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>>> index 1ff7b42521c9..403f0d9caadf 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>>> @@ -1641,7 +1641,7 @@ bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
>>> if (GRAPHICS_VER(gt->i915) < 11)
>>> return false;
>>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0))
>>> return true;
>>> if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index 2a5bf50962ad..785453b2e95e 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -808,24 +808,24 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>>> static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine,
>>> struct i915_wa_list *wal)
>>> {
>>> - struct drm_i915_private *i915 = engine->i915;
>>> + struct intel_gt *gt = engine->gt;
>>> dg2_ctx_gt_tuning_init(engine, wal);
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
>>> wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
>>> }
>>> static void xelpg_ctx_workarounds_init(struct intel_engine_cs *engine,
>>> struct i915_wa_list *wal)
>>> {
>>> - struct drm_i915_private *i915 = engine->i915;
>>> + struct intel_gt *gt = engine->gt;
>>> xelpg_ctx_gt_tuning_init(engine, wal);
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>> /* Wa_14014947963 */
>>> wa_masked_field_set(wal, VF_PREEMPTION,
>>> PREEMPTION_VERTEX_COUNT, 0x4000);
>>> @@ -1746,8 +1746,8 @@ xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>>> /* Wa_22016670082 */
>>> wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE);
>>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(gt->i915, P, STEP_A0, STEP_B0)) {
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>> /* Wa_14014830051 */
>>> wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
>>> @@ -2424,16 +2424,17 @@ static void
>>> rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>> {
>>> struct drm_i915_private *i915 = engine->i915;
>>> + struct intel_gt *gt = engine->gt;
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) {
>>> /* Wa_22014600077 */
>>> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>> ENABLE_EU_COUNT_FOR_TDL_FLUSH);
>>> }
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>> /* Wa_1509727124 */
>>> @@ -2443,7 +2444,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>> if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>> IS_DG2_G11(i915) || IS_DG2_G12(i915) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0)) {
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)) {
>>> /* Wa_22012856258 */
>>> wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
>>> GEN12_DISABLE_READ_SUPPRESSION);
>>> @@ -3008,8 +3009,9 @@ static void
>>> general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>> {
>>> struct drm_i915_private *i915 = engine->i915;
>>> + struct intel_gt *gt = engine->gt;
>>> - add_render_compute_tuning_settings(engine->gt, wal);
>>> + add_render_compute_tuning_settings(gt, wal);
>>> if (GRAPHICS_VER(i915) >= 11) {
>>> /* This is not a Wa (although referred to as
>>> @@ -3030,13 +3032,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>> GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE);
>>> }
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))
>>> /* Wa_14017856879 */
>>> wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>> /*
>>> * Wa_14017066071
>>> * Wa_14017654203
>>> @@ -3044,13 +3046,13 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>> wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
>>> MTL_DISABLE_SAMPLER_SC_OOO);
>>> - if (IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0))
>>> /* Wa_22015279794 */
>>> wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
>>> DISABLE_PREFETCH_INTO_IC);
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>> IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
>>> IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
>>> /* Wa_22013037850 */
>>> @@ -3058,16 +3060,16 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
>>> DISABLE_128B_EVICTION_COMMAND_UDW);
>>> }
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>> IS_PONTEVECCHIO(i915) ||
>>> IS_DG2(i915)) {
>>> /* Wa_22014226127 */
>>> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
>>> }
>>> - if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> + IS_GFX_IPVER_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) ||
>>> IS_DG2(i915)) {
>>> /* Wa_18017747507 */
>>> wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE);
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> index 1e532981f74e..300b968e6de8 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> @@ -277,7 +277,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
>>> flags |= GUC_WA_GAM_CREDITS;
>>> /* Wa_14014475959 */
>>> - if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
>>> + if (IS_GFX_IPVER_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> IS_DG2(gt->i915))
>>> flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> index 1bd5d8f7c40b..3b159069dbc4 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
>>> @@ -4265,7 +4265,7 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine)
>>> /* Wa_14014475959:dg2 */
>>> if (engine->class == COMPUTE_CLASS)
>>> - if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
>>> + if (IS_GFX_IPVER_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||
>>> IS_DG2(engine->i915))
>>> engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index f38c93d82c56..d03710c923c8 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -692,9 +692,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>> #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
>>> (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
>>> -#define IS_MTL_GRAPHICS_STEP(__i915, variant, since, until) \
>>> - (IS_SUBPLATFORM(__i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_##variant) && \
>>> - IS_GRAPHICS_STEP(__i915, since, until))
>>> +#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
>>> + (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
>>> + (__gt->type != GT_MEDIA && \
>>> + GRAPHICS_VER_FULL(__gt->i915) == ipver && \
>>> + IS_GRAPHICS_STEP(__gt->i915, since, until)))
>>> #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>>> (IS_METEORLAKE(__i915) && \
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH 4/8] drm/i915: Eliminate IS_MTL_MEDIA_STEP
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
` (2 preceding siblings ...)
2023-07-18 22:27 ` [Intel-gfx] [PATCH 3/8] drm/i915: Eliminate IS_MTL_GRAPHICS_STEP Matt Roper
@ 2023-07-18 22:27 ` Matt Roper
2023-07-18 22:27 ` [Intel-gfx] [PATCH 5/8] drm/i915: Eliminate IS_MTL_DISPLAY_STEP Matt Roper
` (7 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Matt Roper @ 2023-07-18 22:27 UTC (permalink / raw)
To: intel-gfx; +Cc: matthew.d.roper
Stepping-specific media behavior shouldn't be tied to MTL as a platform,
but rather specifically to the Xe_LPM+ IP. Future non-MTL platforms may
re-use this IP and will need to follow the exact same logic and apply
the same workarounds. IS_MTL_MEDIA_STEP() is dropped in favor of a new
macro IS_MEDIA_IPVER_STEP() that checks the media IP version associated
with a specific IP and also ensures that we're operating on the media
GT, not the primary GT.
This new macro will return false if the GT is NULL (so it's safe to pass
i915->media_gt as a parameter, even though that will be NULL on
platforms without standalone media). We don't expect this macro to used
to match media versions earlier than 13 (when media became a standalone
GT), so a build error will be raised if this macro is used to match on a
pre-13 version of media. That restriction can be adjusted in the future
if we find a use for this macro on earlier platforms.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +--
drivers/gpu/drm/i915/i915_drv.h | 10 ++++++----
drivers/gpu/drm/i915/i915_perf.c | 15 ++++-----------
3 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 58bb1c55294c..91c68c0ec32d 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -526,8 +526,7 @@ static bool rc6_supported(struct intel_rc6 *rc6)
return false;
}
- if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
- gt->type == GT_MEDIA) {
+ if (IS_MEDIA_IPVER_STEP(gt, IP_VER(13, 0), STEP_A0, STEP_B0)) {
drm_notice(&i915->drm,
"Media RC6 disabled on A step\n");
return false;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d03710c923c8..10741177b654 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -698,14 +698,16 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
GRAPHICS_VER_FULL(__gt->i915) == ipver && \
IS_GRAPHICS_STEP(__gt->i915, since, until)))
+#define IS_MEDIA_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(13, 0)) + \
+ (__gt && __gt->type == GT_MEDIA && \
+ MEDIA_VER_FULL(__gt->i915) == ipver && \
+ IS_MEDIA_STEP(__gt->i915, since, until)))
+
#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
(IS_METEORLAKE(__i915) && \
IS_DISPLAY_STEP(__i915, since, until))
-#define IS_MTL_MEDIA_STEP(__i915, since, until) \
- (IS_METEORLAKE(__i915) && \
- IS_MEDIA_STEP(__i915, since, until))
-
/*
* DG2 hardware steppings are a bit unusual. The hardware design was forked to
* create three variants (G10, G11, and G12) which each have distinct
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 49c6f1ff1128..ff95f2cdf2b0 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -4223,7 +4223,7 @@ static int read_properties_unlocked(struct i915_perf *perf,
* C6 disable in BIOS. Fail if Media C6 is enabled on steppings where OAM
* does not work as expected.
*/
- if (IS_MTL_MEDIA_STEP(props->engine->i915, STEP_A0, STEP_C0) &&
+ if (IS_MEDIA_IPVER_STEP(props->engine->gt, IP_VER(13, 0), STEP_A0, STEP_C0) &&
props->engine->oa_group->type == TYPE_OAM &&
intel_check_bios_c6_setup(&props->engine->gt->rc6)) {
drm_dbg(&perf->i915->drm,
@@ -5332,16 +5332,9 @@ int i915_perf_ioctl_version(struct drm_i915_private *i915)
* C6 disable in BIOS. If Media C6 is enabled in BIOS, return version 6
* to indicate that OA media is not supported.
*/
- if (IS_MTL_MEDIA_STEP(i915, STEP_A0, STEP_C0)) {
- struct intel_gt *gt;
- int i;
-
- for_each_gt(gt, i915, i) {
- if (gt->type == GT_MEDIA &&
- intel_check_bios_c6_setup(>->rc6))
- return 6;
- }
- }
+ if (IS_MEDIA_IPVER_STEP(i915->media_gt, IP_VER(13, 0), STEP_A0, STEP_C0) &&
+ intel_check_bios_c6_setup(&i915->media_gt->rc6))
+ return 6;
return 7;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH 5/8] drm/i915: Eliminate IS_MTL_DISPLAY_STEP
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
` (3 preceding siblings ...)
2023-07-18 22:27 ` [Intel-gfx] [PATCH 4/8] drm/i915: Eliminate IS_MTL_MEDIA_STEP Matt Roper
@ 2023-07-18 22:27 ` Matt Roper
2023-07-19 19:22 ` Gustavo Sousa
2023-07-18 22:28 ` [Intel-gfx] [PATCH 6/8] drm/i915/mtl: Eliminate subplatforms Matt Roper
` (6 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Matt Roper @ 2023-07-18 22:27 UTC (permalink / raw)
To: intel-gfx; +Cc: matthew.d.roper
Stepping-specific display behavior shouldn't be tied to MTL as a
platform, but rather specifically to the Xe_LPM+ IP. Future non-MTL
platforms may re-use this IP and will need to follow the exact same
logic and apply the same workarounds. IS_MTL_DISPLAY_STEP() is dropped
in favor of a new macro IS_DISPLAY_IPVER_STEP() that only checks the
display IP version.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.h | 5 +++++
drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 6 ++----
5 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 3324bd453ca7..d8dccf7f1b5f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -71,6 +71,11 @@ struct drm_printer;
#define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
#define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
+#define IS_DISPLAY_IPVER_STEP(__i915, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+ DISPLAY_VER_FULL(__i915) == ipver && \
+ IS_DISPLAY_STEP(__i915, since, until))
+
struct intel_display_runtime_info {
struct {
u16 ver;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7f8b2d7713c7..a3a42e29b766 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -49,6 +49,7 @@
#include "i915_vgpu.h"
#include "intel_cdclk.h"
#include "intel_de.h"
+#include "intel_display_device.h"
#include "intel_display_trace.h"
#include "intel_display_types.h"
#include "intel_fbc.h"
@@ -1093,7 +1094,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
/* Wa_14016291713 */
if ((IS_DISPLAY_VER(i915, 12, 13) ||
- IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
+ IS_DISPLAY_IPVER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
crtc_state->has_psr) {
plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index f7608d363634..3b37beedc95c 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
&pmdemand_state->base,
&intel_pmdemand_funcs);
- if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+ if (IS_DISPLAY_IPVER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
/* Wa_14016740474 */
intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 04ab034a8d57..5770cbfef435 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1360,7 +1360,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
bool set_wa_bit = false;
/* Wa_14015648006 */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ if (IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
IS_DISPLAY_VER(dev_priv, 11, 13))
set_wa_bit |= crtc_state->wm_level_disabled;
@@ -1447,7 +1447,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
* All supported adlp panels have 1-based X granularity, this may
* cause issues if non-supported panels are used.
*/
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
ADLP_1_BASED_X_GRANULARITY);
else if (IS_ALDERLAKE_P(dev_priv))
@@ -1455,7 +1455,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
ADLP_1_BASED_X_GRANULARITY);
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
@@ -1613,7 +1613,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
if (intel_dp->psr.psr2_enabled) {
/* Wa_16012604467:adlp,mtl[a0,b0] */
- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
+ if (IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
@@ -2087,7 +2087,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
goto skip_sel_fetch_set_loop;
/* Wa_14014971492 */
- if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
+ if ((IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
crtc_state->splitter.enable)
pipe_clip.y1 = 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 10741177b654..cf72c34bca10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -443,6 +443,8 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
(MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
#define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
+#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
+ DISPLAY_RUNTIME_INFO(i915)->ip.rel)
#define IS_DISPLAY_VER(i915, from, until) \
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
@@ -704,10 +706,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
MEDIA_VER_FULL(__gt->i915) == ipver && \
IS_MEDIA_STEP(__gt->i915, since, until)))
-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
- (IS_METEORLAKE(__i915) && \
- IS_DISPLAY_STEP(__i915, since, until))
-
/*
* DG2 hardware steppings are a bit unusual. The hardware design was forked to
* create three variants (G10, G11, and G12) which each have distinct
--
2.41.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 5/8] drm/i915: Eliminate IS_MTL_DISPLAY_STEP
2023-07-18 22:27 ` [Intel-gfx] [PATCH 5/8] drm/i915: Eliminate IS_MTL_DISPLAY_STEP Matt Roper
@ 2023-07-19 19:22 ` Gustavo Sousa
0 siblings, 0 replies; 30+ messages in thread
From: Gustavo Sousa @ 2023-07-19 19:22 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: matthew.d.roper
Quoting Matt Roper (2023-07-18 19:27:59-03:00)
>Stepping-specific display behavior shouldn't be tied to MTL as a
>platform, but rather specifically to the Xe_LPM+ IP. Future non-MTL
s/Xe_LPD+/Xe_LPDM+/ ?
The changes for this and the previous two patches look correct to me,
but I would also be more leaning toward having IP version and stepping
boundary checks as separated macros.
--
Gustavo Sousa
>platforms may re-use this IP and will need to follow the exact same
>logic and apply the same workarounds. IS_MTL_DISPLAY_STEP() is dropped
>in favor of a new macro IS_DISPLAY_IPVER_STEP() that only checks the
>display IP version.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display_device.h | 5 +++++
> drivers/gpu/drm/i915/display/intel_fbc.c | 3 ++-
> drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++-----
> drivers/gpu/drm/i915/i915_drv.h | 6 ++----
> 5 files changed, 15 insertions(+), 11 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
>index 3324bd453ca7..d8dccf7f1b5f 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_device.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>@@ -71,6 +71,11 @@ struct drm_printer;
> #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical)
> #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv)
>
>+#define IS_DISPLAY_IPVER_STEP(__i915, ipver, since, until) \
>+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
>+ DISPLAY_VER_FULL(__i915) == ipver && \
>+ IS_DISPLAY_STEP(__i915, since, until))
>+
> struct intel_display_runtime_info {
> struct {
> u16 ver;
>diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
>index 7f8b2d7713c7..a3a42e29b766 100644
>--- a/drivers/gpu/drm/i915/display/intel_fbc.c
>+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>@@ -49,6 +49,7 @@
> #include "i915_vgpu.h"
> #include "intel_cdclk.h"
> #include "intel_de.h"
>+#include "intel_display_device.h"
> #include "intel_display_trace.h"
> #include "intel_display_types.h"
> #include "intel_fbc.h"
>@@ -1093,7 +1094,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
>
> /* Wa_14016291713 */
> if ((IS_DISPLAY_VER(i915, 12, 13) ||
>- IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0)) &&
>+ IS_DISPLAY_IPVER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) &&
> crtc_state->has_psr) {
> plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)";
> return 0;
>diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>index f7608d363634..3b37beedc95c 100644
>--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>@@ -92,7 +92,7 @@ int intel_pmdemand_init(struct drm_i915_private *i915)
> &pmdemand_state->base,
> &intel_pmdemand_funcs);
>
>- if (IS_MTL_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
>+ if (IS_DISPLAY_IPVER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0))
> /* Wa_14016740474 */
> intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE);
>
>diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>index 04ab034a8d57..5770cbfef435 100644
>--- a/drivers/gpu/drm/i915/display/intel_psr.c
>+++ b/drivers/gpu/drm/i915/display/intel_psr.c
>@@ -1360,7 +1360,7 @@ static void wm_optimization_wa(struct intel_dp *intel_dp,
> bool set_wa_bit = false;
>
> /* Wa_14015648006 */
>- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>+ if (IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
> IS_DISPLAY_VER(dev_priv, 11, 13))
> set_wa_bit |= crtc_state->wm_level_disabled;
>
>@@ -1447,7 +1447,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> * All supported adlp panels have 1-based X granularity, this may
> * cause issues if non-supported panels are used.
> */
>- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>+ if (IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
> intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), 0,
> ADLP_1_BASED_X_GRANULARITY);
> else if (IS_ALDERLAKE_P(dev_priv))
>@@ -1455,7 +1455,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
> ADLP_1_BASED_X_GRANULARITY);
>
> /* Wa_16012604467:adlp,mtl[a0,b0] */
>- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>+ if (IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
> intel_de_rmw(dev_priv,
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0,
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS);
>@@ -1613,7 +1613,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>
> if (intel_dp->psr.psr2_enabled) {
> /* Wa_16012604467:adlp,mtl[a0,b0] */
>- if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
>+ if (IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0))
> intel_de_rmw(dev_priv,
> MTL_CLKGATE_DIS_TRANS(cpu_transcoder),
> MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0);
>@@ -2087,7 +2087,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
> goto skip_sel_fetch_set_loop;
>
> /* Wa_14014971492 */
>- if ((IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0) ||
>+ if ((IS_DISPLAY_IPVER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) ||
> IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
> crtc_state->splitter.enable)
> pipe_clip.y1 = 0;
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 10741177b654..cf72c34bca10 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -443,6 +443,8 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
> (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
>
> #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
>+#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
>+ DISPLAY_RUNTIME_INFO(i915)->ip.rel)
> #define IS_DISPLAY_VER(i915, from, until) \
> (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
>
>@@ -704,10 +706,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> MEDIA_VER_FULL(__gt->i915) == ipver && \
> IS_MEDIA_STEP(__gt->i915, since, until)))
>
>-#define IS_MTL_DISPLAY_STEP(__i915, since, until) \
>- (IS_METEORLAKE(__i915) && \
>- IS_DISPLAY_STEP(__i915, since, until))
>-
> /*
> * DG2 hardware steppings are a bit unusual. The hardware design was forked to
> * create three variants (G10, G11, and G12) which each have distinct
>--
>2.41.0
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH 6/8] drm/i915/mtl: Eliminate subplatforms
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
` (4 preceding siblings ...)
2023-07-18 22:27 ` [Intel-gfx] [PATCH 5/8] drm/i915: Eliminate IS_MTL_DISPLAY_STEP Matt Roper
@ 2023-07-18 22:28 ` Matt Roper
2023-07-19 18:13 ` Garg, Nemesa
2023-07-19 19:27 ` Gustavo Sousa
2023-07-18 22:28 ` [Intel-gfx] [PATCH 7/8] drm/i915/display: Eliminate IS_METEORLAKE checks Matt Roper
` (5 subsequent siblings)
11 siblings, 2 replies; 30+ messages in thread
From: Matt Roper @ 2023-07-18 22:28 UTC (permalink / raw)
To: intel-gfx; +Cc: matthew.d.roper
Now that we properly match the Xe_LPG IP versions associated with
various workarounds, there's no longer any need to define separate MTL
subplatform in the driver. Nothing in the code is conditional on MTL-M
or MTL-P base platforms. Furthermore, I'm not sure the "M" and "P"
designations are even an accurate representation of which specific
platforms would have which IP versions; those were mostly just
placeholders from a long time ago. The reality is that the IP version
present on a platform gets read from a fuse register at driver init; we
shouldn't be trying to guess which IP is present based on PCI ID
anymore.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ----
drivers/gpu/drm/i915/intel_device_info.c | 14 --------------
drivers/gpu/drm/i915/intel_device_info.h | 4 ----
include/drm/i915_pciids.h | 11 +++--------
4 files changed, 3 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index cf72c34bca10..67cd9914bf33 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -581,10 +581,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
-#define IS_METEORLAKE_M(i915) \
- IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
-#define IS_METEORLAKE_P(i915) \
- IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
#define IS_DG2_G10(i915) \
IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(i915) \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index ea0ec6174ce5..9dfa680a4c62 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -206,14 +206,6 @@ static const u16 subplatform_g12_ids[] = {
INTEL_DG2_G12_IDS(0),
};
-static const u16 subplatform_m_ids[] = {
- INTEL_MTL_M_IDS(0),
-};
-
-static const u16 subplatform_p_ids[] = {
- INTEL_MTL_P_IDS(0),
-};
-
static bool find_devid(u16 id, const u16 *p, unsigned int num)
{
for (; num; num--, p++) {
@@ -275,12 +267,6 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
} else if (find_devid(devid, subplatform_g12_ids,
ARRAY_SIZE(subplatform_g12_ids))) {
mask = BIT(INTEL_SUBPLATFORM_G12);
- } else if (find_devid(devid, subplatform_m_ids,
- ARRAY_SIZE(subplatform_m_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_M);
- } else if (find_devid(devid, subplatform_p_ids,
- ARRAY_SIZE(subplatform_p_ids))) {
- mask = BIT(INTEL_SUBPLATFORM_P);
}
GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index dbfe6443457b..2ca54417d19b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -129,10 +129,6 @@ enum intel_platform {
#define INTEL_SUBPLATFORM_N 1
#define INTEL_SUBPLATFORM_RPLU 2
-/* MTL */
-#define INTEL_SUBPLATFORM_M 0
-#define INTEL_SUBPLATFORM_P 1
-
enum intel_ppgtt_type {
INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index e1e10dfbb661..38dae757d1a8 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -738,18 +738,13 @@
#define INTEL_ATS_M_IDS(info) \
INTEL_ATS_M150_IDS(info), \
INTEL_ATS_M75_IDS(info)
+
/* MTL */
-#define INTEL_MTL_M_IDS(info) \
+#define INTEL_MTL_IDS(info) \
INTEL_VGA_DEVICE(0x7D40, info), \
- INTEL_VGA_DEVICE(0x7D60, info)
-
-#define INTEL_MTL_P_IDS(info) \
INTEL_VGA_DEVICE(0x7D45, info), \
INTEL_VGA_DEVICE(0x7D55, info), \
+ INTEL_VGA_DEVICE(0x7D60, info), \
INTEL_VGA_DEVICE(0x7DD5, info)
-#define INTEL_MTL_IDS(info) \
- INTEL_MTL_M_IDS(info), \
- INTEL_MTL_P_IDS(info)
-
#endif /* _I915_PCIIDS_H */
--
2.41.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 6/8] drm/i915/mtl: Eliminate subplatforms
2023-07-18 22:28 ` [Intel-gfx] [PATCH 6/8] drm/i915/mtl: Eliminate subplatforms Matt Roper
@ 2023-07-19 18:13 ` Garg, Nemesa
2023-07-19 19:27 ` Gustavo Sousa
1 sibling, 0 replies; 30+ messages in thread
From: Garg, Nemesa @ 2023-07-19 18:13 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx@lists.freedesktop.org
> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Wednesday, July 19, 2023 3:58 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Roper, Matthew D <matthew.d.roper@intel.com>
> Subject: [Intel-gfx] [PATCH 6/8] drm/i915/mtl: Eliminate subplatforms
>
> Now that we properly match the Xe_LPG IP versions associated with various
> workarounds, there's no longer any need to define separate MTL
> subplatform in the driver. Nothing in the code is conditional on MTL-M or
> MTL-P base platforms. Furthermore, I'm not sure the "M" and "P"
> designations are even an accurate representation of which specific platforms
> would have which IP versions; those were mostly just placeholders from a
> long time ago. The reality is that the IP version present on a platform gets
> read from a fuse register at driver init; we shouldn't be trying to guess which
> IP is present based on PCI ID anymore.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Garg, Nemesa <nemesa.garg@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 ----
> drivers/gpu/drm/i915/intel_device_info.c | 14 --------------
> drivers/gpu/drm/i915/intel_device_info.h | 4 ----
> include/drm/i915_pciids.h | 11 +++--------
> 4 files changed, 3 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index cf72c34bca10..67cd9914bf33
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -581,10 +581,6 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915, #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915,
> INTEL_PONTEVECCHIO) #define IS_METEORLAKE(i915) IS_PLATFORM(i915,
> INTEL_METEORLAKE)
>
> -#define IS_METEORLAKE_M(i915) \
> - IS_SUBPLATFORM(i915, INTEL_METEORLAKE,
> INTEL_SUBPLATFORM_M)
> -#define IS_METEORLAKE_P(i915) \
> - IS_SUBPLATFORM(i915, INTEL_METEORLAKE,
> INTEL_SUBPLATFORM_P)
> #define IS_DG2_G10(i915) \
> IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
> #define IS_DG2_G11(i915) \ diff --git
> a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index ea0ec6174ce5..9dfa680a4c62 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -206,14 +206,6 @@ static const u16 subplatform_g12_ids[] = {
> INTEL_DG2_G12_IDS(0),
> };
>
> -static const u16 subplatform_m_ids[] = {
> - INTEL_MTL_M_IDS(0),
> -};
> -
> -static const u16 subplatform_p_ids[] = {
> - INTEL_MTL_P_IDS(0),
> -};
> -
> static bool find_devid(u16 id, const u16 *p, unsigned int num) {
> for (; num; num--, p++) {
> @@ -275,12 +267,6 @@ static void intel_device_info_subplatform_init(struct
> drm_i915_private *i915)
> } else if (find_devid(devid, subplatform_g12_ids,
> ARRAY_SIZE(subplatform_g12_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_G12);
> - } else if (find_devid(devid, subplatform_m_ids,
> - ARRAY_SIZE(subplatform_m_ids))) {
> - mask = BIT(INTEL_SUBPLATFORM_M);
> - } else if (find_devid(devid, subplatform_p_ids,
> - ARRAY_SIZE(subplatform_p_ids))) {
> - mask = BIT(INTEL_SUBPLATFORM_P);
> }
>
> GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); diff --git
> a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index dbfe6443457b..2ca54417d19b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -129,10 +129,6 @@ enum intel_platform {
> #define INTEL_SUBPLATFORM_N 1
> #define INTEL_SUBPLATFORM_RPLU 2
>
> -/* MTL */
> -#define INTEL_SUBPLATFORM_M 0
> -#define INTEL_SUBPLATFORM_P 1
> -
> enum intel_ppgtt_type {
> INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
> INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, diff --git
> a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index
> e1e10dfbb661..38dae757d1a8 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -738,18 +738,13 @@
> #define INTEL_ATS_M_IDS(info) \
> INTEL_ATS_M150_IDS(info), \
> INTEL_ATS_M75_IDS(info)
> +
> /* MTL */
> -#define INTEL_MTL_M_IDS(info) \
> +#define INTEL_MTL_IDS(info) \
> INTEL_VGA_DEVICE(0x7D40, info), \
> - INTEL_VGA_DEVICE(0x7D60, info)
> -
> -#define INTEL_MTL_P_IDS(info) \
> INTEL_VGA_DEVICE(0x7D45, info), \
> INTEL_VGA_DEVICE(0x7D55, info), \
> + INTEL_VGA_DEVICE(0x7D60, info), \
> INTEL_VGA_DEVICE(0x7DD5, info)
>
> -#define INTEL_MTL_IDS(info) \
> - INTEL_MTL_M_IDS(info), \
> - INTEL_MTL_P_IDS(info)
> -
> #endif /* _I915_PCIIDS_H */
> --
> 2.41.0
>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 6/8] drm/i915/mtl: Eliminate subplatforms
2023-07-18 22:28 ` [Intel-gfx] [PATCH 6/8] drm/i915/mtl: Eliminate subplatforms Matt Roper
2023-07-19 18:13 ` Garg, Nemesa
@ 2023-07-19 19:27 ` Gustavo Sousa
1 sibling, 0 replies; 30+ messages in thread
From: Gustavo Sousa @ 2023-07-19 19:27 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: matthew.d.roper
Quoting Matt Roper (2023-07-18 19:28:00-03:00)
>Now that we properly match the Xe_LPG IP versions associated with
>various workarounds, there's no longer any need to define separate MTL
>subplatform in the driver. Nothing in the code is conditional on MTL-M
>or MTL-P base platforms. Furthermore, I'm not sure the "M" and "P"
>designations are even an accurate representation of which specific
>platforms would have which IP versions; those were mostly just
>placeholders from a long time ago. The reality is that the IP version
>present on a platform gets read from a fuse register at driver init; we
>shouldn't be trying to guess which IP is present based on PCI ID
>anymore.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.h | 4 ----
> drivers/gpu/drm/i915/intel_device_info.c | 14 --------------
> drivers/gpu/drm/i915/intel_device_info.h | 4 ----
> include/drm/i915_pciids.h | 11 +++--------
> 4 files changed, 3 insertions(+), 30 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index cf72c34bca10..67cd9914bf33 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -581,10 +581,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
> #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
>
>-#define IS_METEORLAKE_M(i915) \
>- IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
>-#define IS_METEORLAKE_P(i915) \
>- IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
> #define IS_DG2_G10(i915) \
> IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
> #define IS_DG2_G11(i915) \
>diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
>index ea0ec6174ce5..9dfa680a4c62 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.c
>+++ b/drivers/gpu/drm/i915/intel_device_info.c
>@@ -206,14 +206,6 @@ static const u16 subplatform_g12_ids[] = {
> INTEL_DG2_G12_IDS(0),
> };
>
>-static const u16 subplatform_m_ids[] = {
>- INTEL_MTL_M_IDS(0),
>-};
>-
>-static const u16 subplatform_p_ids[] = {
>- INTEL_MTL_P_IDS(0),
>-};
>-
> static bool find_devid(u16 id, const u16 *p, unsigned int num)
> {
> for (; num; num--, p++) {
>@@ -275,12 +267,6 @@ static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
> } else if (find_devid(devid, subplatform_g12_ids,
> ARRAY_SIZE(subplatform_g12_ids))) {
> mask = BIT(INTEL_SUBPLATFORM_G12);
>- } else if (find_devid(devid, subplatform_m_ids,
>- ARRAY_SIZE(subplatform_m_ids))) {
>- mask = BIT(INTEL_SUBPLATFORM_M);
>- } else if (find_devid(devid, subplatform_p_ids,
>- ARRAY_SIZE(subplatform_p_ids))) {
>- mask = BIT(INTEL_SUBPLATFORM_P);
> }
>
> GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
>diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
>index dbfe6443457b..2ca54417d19b 100644
>--- a/drivers/gpu/drm/i915/intel_device_info.h
>+++ b/drivers/gpu/drm/i915/intel_device_info.h
>@@ -129,10 +129,6 @@ enum intel_platform {
> #define INTEL_SUBPLATFORM_N 1
> #define INTEL_SUBPLATFORM_RPLU 2
>
>-/* MTL */
>-#define INTEL_SUBPLATFORM_M 0
>-#define INTEL_SUBPLATFORM_P 1
>-
> enum intel_ppgtt_type {
> INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
> INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
>diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
>index e1e10dfbb661..38dae757d1a8 100644
>--- a/include/drm/i915_pciids.h
>+++ b/include/drm/i915_pciids.h
>@@ -738,18 +738,13 @@
> #define INTEL_ATS_M_IDS(info) \
> INTEL_ATS_M150_IDS(info), \
> INTEL_ATS_M75_IDS(info)
>+
> /* MTL */
>-#define INTEL_MTL_M_IDS(info) \
>+#define INTEL_MTL_IDS(info) \
> INTEL_VGA_DEVICE(0x7D40, info), \
>- INTEL_VGA_DEVICE(0x7D60, info)
>-
>-#define INTEL_MTL_P_IDS(info) \
> INTEL_VGA_DEVICE(0x7D45, info), \
> INTEL_VGA_DEVICE(0x7D55, info), \
>+ INTEL_VGA_DEVICE(0x7D60, info), \
> INTEL_VGA_DEVICE(0x7DD5, info)
>
>-#define INTEL_MTL_IDS(info) \
>- INTEL_MTL_M_IDS(info), \
>- INTEL_MTL_P_IDS(info)
>-
> #endif /* _I915_PCIIDS_H */
>--
>2.41.0
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH 7/8] drm/i915/display: Eliminate IS_METEORLAKE checks
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
` (5 preceding siblings ...)
2023-07-18 22:28 ` [Intel-gfx] [PATCH 6/8] drm/i915/mtl: Eliminate subplatforms Matt Roper
@ 2023-07-18 22:28 ` Matt Roper
2023-07-19 19:39 ` Gustavo Sousa
2023-07-18 22:28 ` [Intel-gfx] [PATCH 8/8] drm/i915: Replace several IS_METEORLAKE with proper IP version checks Matt Roper
` (4 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Matt Roper @ 2023-07-18 22:28 UTC (permalink / raw)
To: intel-gfx; +Cc: matthew.d.roper
Most of the IS_METEORLAKE checks in the display code shouldn't actually
be tied to MTL as a platform, but rather to the Xe_LPD+ display IP
(which is used in MTL, but may show up again in future platforms). In
cases where we're trying to match that specific IP, use a version check
against IP_VER(14, 0). For cases where we're just handling new behavior
introduced by this IP (but which may also be inherited by future IP as
well), use a ver >= 14 check.
The one exception here is the stolen memory workaround Wa_13010847436
(which is mislabelled as "Wa_22018444074" in the code). That's truly a
MTL-specific issue rather than being tied to any of the IP blocks, so
leaving the condition as IS_METEORLAKE is correct there.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index dcc1f6941b60..4cb1dc397b62 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1840,7 +1840,7 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
{
- return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
+ return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0)) &&
dev_priv->display.cdclk.hw.vco > 0 &&
HAS_CDCLK_SQUASH(dev_priv));
}
@@ -3559,7 +3559,7 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (IS_METEORLAKE(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) > 14) {
dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
} else if (IS_DG2(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 1b00ef2c6185..025c80b9fece 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -31,7 +31,7 @@
bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
{
- if (IS_METEORLAKE(i915) && (phy < PHY_C))
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && (phy < PHY_C))
return true;
return false;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 43cba98f7753..85efd77f491b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1767,7 +1767,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
if (IS_DG2(dev_priv))
/* DG2's "TC1" output uses a SNPS PHY */
return false;
- else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
+ else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0))
return phy >= PHY_F && phy <= PHY_I;
else if (IS_TIGERLAKE(dev_priv))
return phy >= PHY_D && phy <= PHY_I;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 5f479f3828bb..1623c0c5e8a1 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -998,7 +998,7 @@ void intel_dmc_init(struct drm_i915_private *i915)
INIT_WORK(&dmc->work, dmc_load_work_fn);
- if (IS_METEORLAKE(i915)) {
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
dmc->fw_path = MTL_DMC_PATH;
dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
} else if (IS_DG2(i915)) {
--
2.41.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display: Eliminate IS_METEORLAKE checks
2023-07-18 22:28 ` [Intel-gfx] [PATCH 7/8] drm/i915/display: Eliminate IS_METEORLAKE checks Matt Roper
@ 2023-07-19 19:39 ` Gustavo Sousa
2023-07-19 19:43 ` Gustavo Sousa
0 siblings, 1 reply; 30+ messages in thread
From: Gustavo Sousa @ 2023-07-19 19:39 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: matthew.d.roper
Quoting Matt Roper (2023-07-18 19:28:01-03:00)
>Most of the IS_METEORLAKE checks in the display code shouldn't actually
>be tied to MTL as a platform, but rather to the Xe_LPD+ display IP
>(which is used in MTL, but may show up again in future platforms). In
>cases where we're trying to match that specific IP, use a version check
>against IP_VER(14, 0). For cases where we're just handling new behavior
>introduced by this IP (but which may also be inherited by future IP as
>well), use a ver >= 14 check.
>
>The one exception here is the stolen memory workaround Wa_13010847436
>(which is mislabelled as "Wa_22018444074" in the code). That's truly a
>MTL-specific issue rather than being tied to any of the IP blocks, so
>leaving the condition as IS_METEORLAKE is correct there.
I grepped and also saw usage for IS_METEORLAKE() for RC6-related code
and around clock gating as well. I'm yet not familiar with those to be
able to tell if they are platform-specific or rather specific to sub
IP(s). Just thought it would be worth noting here, just in case.
>
>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
> drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
> 4 files changed, 5 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index dcc1f6941b60..4cb1dc397b62 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -1840,7 +1840,7 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
>
> static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
> {
>- return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
>+ return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0)) &&
> dev_priv->display.cdclk.hw.vco > 0 &&
> HAS_CDCLK_SQUASH(dev_priv));
> }
>@@ -3559,7 +3559,7 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
> */
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
> {
>- if (IS_METEORLAKE(dev_priv)) {
>+ if (DISPLAY_VER(dev_priv) > 14) {
I think you missed the equality part here, should be DISPLAY_VER(dev_priv) >=
14, right?
--
Gustavo Sousa
> dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
> dev_priv->display.cdclk.table = mtl_cdclk_table;
> } else if (IS_DG2(dev_priv)) {
>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>index 1b00ef2c6185..025c80b9fece 100644
>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>@@ -31,7 +31,7 @@
>
> bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
> {
>- if (IS_METEORLAKE(i915) && (phy < PHY_C))
>+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && (phy < PHY_C))
> return true;
>
> return false;
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 43cba98f7753..85efd77f491b 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -1767,7 +1767,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> if (IS_DG2(dev_priv))
> /* DG2's "TC1" output uses a SNPS PHY */
> return false;
>- else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
>+ else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0))
> return phy >= PHY_F && phy <= PHY_I;
> else if (IS_TIGERLAKE(dev_priv))
> return phy >= PHY_D && phy <= PHY_I;
>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>index 5f479f3828bb..1623c0c5e8a1 100644
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -998,7 +998,7 @@ void intel_dmc_init(struct drm_i915_private *i915)
>
> INIT_WORK(&dmc->work, dmc_load_work_fn);
>
>- if (IS_METEORLAKE(i915)) {
>+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
> dmc->fw_path = MTL_DMC_PATH;
> dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
> } else if (IS_DG2(i915)) {
>--
>2.41.0
>
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 7/8] drm/i915/display: Eliminate IS_METEORLAKE checks
2023-07-19 19:39 ` Gustavo Sousa
@ 2023-07-19 19:43 ` Gustavo Sousa
0 siblings, 0 replies; 30+ messages in thread
From: Gustavo Sousa @ 2023-07-19 19:43 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: matthew.d.roper
Quoting Gustavo Sousa (2023-07-19 16:39:25-03:00)
>Quoting Matt Roper (2023-07-18 19:28:01-03:00)
>>Most of the IS_METEORLAKE checks in the display code shouldn't actually
>>be tied to MTL as a platform, but rather to the Xe_LPD+ display IP
>>(which is used in MTL, but may show up again in future platforms). In
>>cases where we're trying to match that specific IP, use a version check
>>against IP_VER(14, 0). For cases where we're just handling new behavior
>>introduced by this IP (but which may also be inherited by future IP as
>>well), use a ver >= 14 check.
>>
>>The one exception here is the stolen memory workaround Wa_13010847436
>>(which is mislabelled as "Wa_22018444074" in the code). That's truly a
>>MTL-specific issue rather than being tied to any of the IP blocks, so
>>leaving the condition as IS_METEORLAKE is correct there.
>
>I grepped and also saw usage for IS_METEORLAKE() for RC6-related code
>and around clock gating as well. I'm yet not familiar with those to be
>able to tell if they are platform-specific or rather specific to sub
>IP(s). Just thought it would be worth noting here, just in case.
Oops. I was too quick on sending this without realizing that this patch is
specific to display...
>
>>
>>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>---
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 4 ++--
>> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_display.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_dmc.c | 2 +-
>> 4 files changed, 5 insertions(+), 5 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>index dcc1f6941b60..4cb1dc397b62 100644
>>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>>@@ -1840,7 +1840,7 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
>>
>> static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
>> {
>>- return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
>>+ return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0)) &&
>> dev_priv->display.cdclk.hw.vco > 0 &&
>> HAS_CDCLK_SQUASH(dev_priv));
>> }
>>@@ -3559,7 +3559,7 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
>> */
>> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
>> {
>>- if (IS_METEORLAKE(dev_priv)) {
>>+ if (DISPLAY_VER(dev_priv) > 14) {
>
>I think you missed the equality part here, should be DISPLAY_VER(dev_priv) >=
>14, right?
...so, with this fix,
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
>
>--
>Gustavo Sousa
>
>> dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
>> dev_priv->display.cdclk.table = mtl_cdclk_table;
>> } else if (IS_DG2(dev_priv)) {
>>diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>index 1b00ef2c6185..025c80b9fece 100644
>>--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
>>@@ -31,7 +31,7 @@
>>
>> bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
>> {
>>- if (IS_METEORLAKE(i915) && (phy < PHY_C))
>>+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && (phy < PHY_C))
>> return true;
>>
>> return false;
>>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>index 43cba98f7753..85efd77f491b 100644
>>--- a/drivers/gpu/drm/i915/display/intel_display.c
>>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>>@@ -1767,7 +1767,7 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>> if (IS_DG2(dev_priv))
>> /* DG2's "TC1" output uses a SNPS PHY */
>> return false;
>>- else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
>>+ else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0))
>> return phy >= PHY_F && phy <= PHY_I;
>> else if (IS_TIGERLAKE(dev_priv))
>> return phy >= PHY_D && phy <= PHY_I;
>>diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>>index 5f479f3828bb..1623c0c5e8a1 100644
>>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>>@@ -998,7 +998,7 @@ void intel_dmc_init(struct drm_i915_private *i915)
>>
>> INIT_WORK(&dmc->work, dmc_load_work_fn);
>>
>>- if (IS_METEORLAKE(i915)) {
>>+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) {
>> dmc->fw_path = MTL_DMC_PATH;
>> dmc->max_fw_size = XELPDP_DMC_MAX_FW_SIZE;
>> } else if (IS_DG2(i915)) {
>>--
>>2.41.0
>>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] [PATCH 8/8] drm/i915: Replace several IS_METEORLAKE with proper IP version checks
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
` (6 preceding siblings ...)
2023-07-18 22:28 ` [Intel-gfx] [PATCH 7/8] drm/i915/display: Eliminate IS_METEORLAKE checks Matt Roper
@ 2023-07-18 22:28 ` Matt Roper
2023-07-19 7:57 ` Tvrtko Ursulin
2023-07-18 23:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Reduce MTL-specific platform checks Patchwork
` (3 subsequent siblings)
11 siblings, 1 reply; 30+ messages in thread
From: Matt Roper @ 2023-07-18 22:28 UTC (permalink / raw)
To: intel-gfx; +Cc: matthew.d.roper
Many of the IS_METEORLAKE conditions throughout the driver are supposed
to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
specifically. Update those checks to ensure that the code will still
operate properly if/when these IP versions show up on future platforms.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 ++--
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 8 +++++---
10 files changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index d24c0ce8805c..19156ba4b9ef 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data)
BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
- /* Limiting the extension only to Meteor Lake */
- if (!IS_METEORLAKE(i915))
+ /* Limiting the extension only to Xe_LPG and beyond */
+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
return -ENODEV;
if (copy_from_user(&ext, base, sizeof(ext)))
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 89fc8ea6bcfc..4b003925cc3e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -470,9 +470,9 @@ enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
bool always_coherent)
{
/*
- * Wa_22016122933: always return I915_MAP_WC for MTL
+ * Wa_22016122933: always return I915_MAP_WC for Xe_LPM+
*/
- if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
+ if (i915_gem_object_is_lmem(obj) || MEDIA_VER_FULL(i915) == IP_VER(13, 0))
return I915_MAP_WC;
if (HAS_LLC(i915) || always_coherent)
return I915_MAP_WB;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 21af0ec52223..24060278e7a2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
{
struct drm_i915_private *i915 = engine->i915;
- if (IS_METEORLAKE(i915) && engine->id == GSC0) {
+ if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
intel_uncore_write(engine->gt->uncore,
RC_PSMI_CTRL_GSCCS,
_MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4fefa67d285f..a125c3284bab 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1095,10 +1095,10 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
if (IS_ERR(obj)) {
obj = i915_gem_object_create_shmem(engine->i915, context_size);
/*
- * Wa_22016122933: For MTL the shared memory needs to be mapped
+ * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
* as WC on CPU side and UC (PAT index 2) on GPU side
*/
- if (IS_METEORLAKE(engine->i915))
+ if (MEDIA_VER_FULL(engine->i915) == IP_VER(13, 0))
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
}
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 2c014407225c..830ad2c10761 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -507,7 +507,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
memset(table, 0, sizeof(struct drm_i915_mocs_table));
table->unused_entries_index = I915_MOCS_PTE;
- if (IS_METEORLAKE(i915)) {
+ if (GT_GRAPHICS_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) {
table->size = ARRAY_SIZE(mtl_mocs_table);
table->table = mtl_mocs_table;
table->n_entries = MTL_NUM_MOCS_ENTRIES;
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 403f0d9caadf..0714584dd83d 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
{
- if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
+ if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
return false;
if (!__HAS_ENGINE(engine_mask, GSC0))
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index e92e626d4994..89775328440e 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1160,7 +1160,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c
{
struct drm_i915_private *i915 = rps_to_i915(rps);
- if (IS_METEORLAKE(i915))
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
return mtl_get_freq_caps(rps, caps);
else
return __gen6_rps_get_freq_caps(rps, caps);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 300b968e6de8..310d12dc7077 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -743,10 +743,10 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
return ERR_CAST(obj);
/*
- * Wa_22016122933: For MTL the shared memory needs to be mapped
+ * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
* as WC on CPU side and UC (PAT index 2) on GPU side
*/
- if (IS_METEORLAKE(gt->i915))
+ if (MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0))
i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4de44cf1026d..0a0217271b76 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
{
struct drm_i915_private *i915 = obj_to_i915(obj);
- if (IS_METEORLAKE(i915)) {
+ if (GT_GRAPHICS_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
switch (obj->pat_index) {
case 0: return " WB";
case 1: return " WT";
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index ff95f2cdf2b0..cc9592d4de23 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3227,11 +3227,13 @@ get_sseu_config(struct intel_sseu *out_sseu,
*/
u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
{
+ struct intel_gt *gt = to_gt(i915);
+
/*
* Wa_18013179988:dg2
- * Wa_14015846243:mtl
+ * Wa_14015846243:xelpg
*/
- if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
+ if (IS_DG2(i915) || GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
intel_wakeref_t wakeref;
u32 reg, shift;
@@ -4539,7 +4541,7 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
{
- if (IS_METEORLAKE(perf->i915))
+ if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
return reg_in_range_table(addr, mtl_oa_mux_regs);
else
return reg_in_range_table(addr, gen12_oa_mux_regs);
--
2.41.0
^ permalink raw reply related [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 8/8] drm/i915: Replace several IS_METEORLAKE with proper IP version checks
2023-07-18 22:28 ` [Intel-gfx] [PATCH 8/8] drm/i915: Replace several IS_METEORLAKE with proper IP version checks Matt Roper
@ 2023-07-19 7:57 ` Tvrtko Ursulin
2023-07-19 15:22 ` Matt Roper
0 siblings, 1 reply; 30+ messages in thread
From: Tvrtko Ursulin @ 2023-07-19 7:57 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On 18/07/2023 23:28, Matt Roper wrote:
> Many of the IS_METEORLAKE conditions throughout the driver are supposed
> to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
> specifically. Update those checks to ensure that the code will still
> operate properly if/when these IP versions show up on future platforms.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
> drivers/gpu/drm/i915/gem/i915_gem_pages.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 ++--
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 8 +++++---
> 10 files changed, 18 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> index d24c0ce8805c..19156ba4b9ef 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> @@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data)
> BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
> offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
>
> - /* Limiting the extension only to Meteor Lake */
> - if (!IS_METEORLAKE(i915))
> + /* Limiting the extension only to Xe_LPG and beyond */
> + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
> return -ENODEV;
>
> if (copy_from_user(&ext, base, sizeof(ext)))
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> index 89fc8ea6bcfc..4b003925cc3e 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -470,9 +470,9 @@ enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
> bool always_coherent)
> {
> /*
> - * Wa_22016122933: always return I915_MAP_WC for MTL
> + * Wa_22016122933: always return I915_MAP_WC for Xe_LPM+
> */
> - if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
> + if (i915_gem_object_is_lmem(obj) || MEDIA_VER_FULL(i915) == IP_VER(13, 0))
The helper is global for the driver/device but this makes the response
based on just one part of the driver which reads dodgy. There is another
one in __lrc_alloc_state.
For instance, do these workarounds need to be applied to an object used
from the render tile? Yes it also was before these change, but now it is
not obvious to me if and how the ipver of the media tile affects the
other tile.
Regards,
Tvrtko
> return I915_MAP_WC;
> if (HAS_LLC(i915) || always_coherent)
> return I915_MAP_WB;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> index 21af0ec52223..24060278e7a2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> @@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *i915 = engine->i915;
>
> - if (IS_METEORLAKE(i915) && engine->id == GSC0) {
> + if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
> intel_uncore_write(engine->gt->uncore,
> RC_PSMI_CTRL_GSCCS,
> _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 4fefa67d285f..a125c3284bab 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1095,10 +1095,10 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
> if (IS_ERR(obj)) {
> obj = i915_gem_object_create_shmem(engine->i915, context_size);
> /*
> - * Wa_22016122933: For MTL the shared memory needs to be mapped
> + * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
> * as WC on CPU side and UC (PAT index 2) on GPU side
> */
> - if (IS_METEORLAKE(engine->i915))
> + if (MEDIA_VER_FULL(engine->i915) == IP_VER(13, 0))
> i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
> }
> if (IS_ERR(obj))
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 2c014407225c..830ad2c10761 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -507,7 +507,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> memset(table, 0, sizeof(struct drm_i915_mocs_table));
>
> table->unused_entries_index = I915_MOCS_PTE;
> - if (IS_METEORLAKE(i915)) {
> + if (GT_GRAPHICS_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) {
> table->size = ARRAY_SIZE(mtl_mocs_table);
> table->table = mtl_mocs_table;
> table->n_entries = MTL_NUM_MOCS_ENTRIES;
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 403f0d9caadf..0714584dd83d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
>
> static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
> {
> - if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
> + if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
> return false;
>
> if (!__HAS_ENGINE(engine_mask, GSC0))
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index e92e626d4994..89775328440e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1160,7 +1160,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c
> {
> struct drm_i915_private *i915 = rps_to_i915(rps);
>
> - if (IS_METEORLAKE(i915))
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> return mtl_get_freq_caps(rps, caps);
> else
> return __gen6_rps_get_freq_caps(rps, caps);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 300b968e6de8..310d12dc7077 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -743,10 +743,10 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
> return ERR_CAST(obj);
>
> /*
> - * Wa_22016122933: For MTL the shared memory needs to be mapped
> + * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
> * as WC on CPU side and UC (PAT index 2) on GPU side
> */
> - if (IS_METEORLAKE(gt->i915))
> + if (MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0))
> i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
>
> vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 4de44cf1026d..0a0217271b76 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
> {
> struct drm_i915_private *i915 = obj_to_i915(obj);
>
> - if (IS_METEORLAKE(i915)) {
> + if (GT_GRAPHICS_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
> switch (obj->pat_index) {
> case 0: return " WB";
> case 1: return " WT";
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index ff95f2cdf2b0..cc9592d4de23 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -3227,11 +3227,13 @@ get_sseu_config(struct intel_sseu *out_sseu,
> */
> u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt = to_gt(i915);
> +
> /*
> * Wa_18013179988:dg2
> - * Wa_14015846243:mtl
> + * Wa_14015846243:xelpg
> */
> - if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
> + if (IS_DG2(i915) || GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
> intel_wakeref_t wakeref;
> u32 reg, shift;
>
> @@ -4539,7 +4541,7 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
>
> static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
> {
> - if (IS_METEORLAKE(perf->i915))
> + if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
> return reg_in_range_table(addr, mtl_oa_mux_regs);
> else
> return reg_in_range_table(addr, gen12_oa_mux_regs);
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 8/8] drm/i915: Replace several IS_METEORLAKE with proper IP version checks
2023-07-19 7:57 ` Tvrtko Ursulin
@ 2023-07-19 15:22 ` Matt Roper
2023-07-20 9:19 ` Tvrtko Ursulin
0 siblings, 1 reply; 30+ messages in thread
From: Matt Roper @ 2023-07-19 15:22 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Wed, Jul 19, 2023 at 08:57:15AM +0100, Tvrtko Ursulin wrote:
>
> On 18/07/2023 23:28, Matt Roper wrote:
> > Many of the IS_METEORLAKE conditions throughout the driver are supposed
> > to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
> > specifically. Update those checks to ensure that the code will still
> > operate properly if/when these IP versions show up on future platforms.
> >
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
> > drivers/gpu/drm/i915/gem/i915_gem_pages.c | 4 ++--
> > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
> > drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
> > drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
> > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 ++--
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/i915_perf.c | 8 +++++---
> > 10 files changed, 18 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > index d24c0ce8805c..19156ba4b9ef 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
> > @@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data)
> > BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
> > offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
> > - /* Limiting the extension only to Meteor Lake */
> > - if (!IS_METEORLAKE(i915))
> > + /* Limiting the extension only to Xe_LPG and beyond */
> > + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
> > return -ENODEV;
> > if (copy_from_user(&ext, base, sizeof(ext)))
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > index 89fc8ea6bcfc..4b003925cc3e 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> > @@ -470,9 +470,9 @@ enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
> > bool always_coherent)
> > {
> > /*
> > - * Wa_22016122933: always return I915_MAP_WC for MTL
> > + * Wa_22016122933: always return I915_MAP_WC for Xe_LPM+
> > */
> > - if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
> > + if (i915_gem_object_is_lmem(obj) || MEDIA_VER_FULL(i915) == IP_VER(13, 0))
>
> The helper is global for the driver/device but this makes the response based
> on just one part of the driver which reads dodgy. There is another one in
> __lrc_alloc_state.
>
> For instance, do these workarounds need to be applied to an object used from
> the render tile? Yes it also was before these change, but now it is not
> obvious to me if and how the ipver of the media tile affects the other tile.
The current driver implementation is a bit overkill and goes beyond
what's actually requested by the workaround. There are only coherency
issues between the CPU and media, so if an object is only used on the
primary GT (which would be the case for a lot of stuff like GuC0 CTBs
and such), the workaround is not necessary.
The workaround database marks this one as relevant to Xe_LPM+ and _not_
relevant to Xe_LPG. Also, the hardware team's description even
explicitly notes that this is only necessary for media and that the
primary GT is not impacted.
I pointed this out recently in one of the internal reviews for some of
this code, so I think there may be some optimizations to the
implementation of this workaround coming soon.
Matt
>
> Regards,
>
> Tvrtko
>
> > return I915_MAP_WC;
> > if (HAS_LLC(i915) || always_coherent)
> > return I915_MAP_WB;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > index 21af0ec52223..24060278e7a2 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
> > @@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
> > {
> > struct drm_i915_private *i915 = engine->i915;
> > - if (IS_METEORLAKE(i915) && engine->id == GSC0) {
> > + if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
> > intel_uncore_write(engine->gt->uncore,
> > RC_PSMI_CTRL_GSCCS,
> > _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 4fefa67d285f..a125c3284bab 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1095,10 +1095,10 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
> > if (IS_ERR(obj)) {
> > obj = i915_gem_object_create_shmem(engine->i915, context_size);
> > /*
> > - * Wa_22016122933: For MTL the shared memory needs to be mapped
> > + * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
> > * as WC on CPU side and UC (PAT index 2) on GPU side
> > */
> > - if (IS_METEORLAKE(engine->i915))
> > + if (MEDIA_VER_FULL(engine->i915) == IP_VER(13, 0))
> > i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
> > }
> > if (IS_ERR(obj))
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index 2c014407225c..830ad2c10761 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -507,7 +507,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
> > memset(table, 0, sizeof(struct drm_i915_mocs_table));
> > table->unused_entries_index = I915_MOCS_PTE;
> > - if (IS_METEORLAKE(i915)) {
> > + if (GT_GRAPHICS_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) {
> > table->size = ARRAY_SIZE(mtl_mocs_table);
> > table->table = mtl_mocs_table;
> > table->n_entries = MTL_NUM_MOCS_ENTRIES;
> > diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
> > index 403f0d9caadf..0714584dd83d 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> > @@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
> > static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
> > {
> > - if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
> > + if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
> > return false;
> > if (!__HAS_ENGINE(engine_mask, GSC0))
> > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> > index e92e626d4994..89775328440e 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> > @@ -1160,7 +1160,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c
> > {
> > struct drm_i915_private *i915 = rps_to_i915(rps);
> > - if (IS_METEORLAKE(i915))
> > + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
> > return mtl_get_freq_caps(rps, caps);
> > else
> > return __gen6_rps_get_freq_caps(rps, caps);
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > index 300b968e6de8..310d12dc7077 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> > @@ -743,10 +743,10 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
> > return ERR_CAST(obj);
> > /*
> > - * Wa_22016122933: For MTL the shared memory needs to be mapped
> > + * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
> > * as WC on CPU side and UC (PAT index 2) on GPU side
> > */
> > - if (IS_METEORLAKE(gt->i915))
> > + if (MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0))
> > i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
> > vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 4de44cf1026d..0a0217271b76 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
> > {
> > struct drm_i915_private *i915 = obj_to_i915(obj);
> > - if (IS_METEORLAKE(i915)) {
> > + if (GT_GRAPHICS_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
> > switch (obj->pat_index) {
> > case 0: return " WB";
> > case 1: return " WT";
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> > index ff95f2cdf2b0..cc9592d4de23 100644
> > --- a/drivers/gpu/drm/i915/i915_perf.c
> > +++ b/drivers/gpu/drm/i915/i915_perf.c
> > @@ -3227,11 +3227,13 @@ get_sseu_config(struct intel_sseu *out_sseu,
> > */
> > u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
> > {
> > + struct intel_gt *gt = to_gt(i915);
> > +
> > /*
> > * Wa_18013179988:dg2
> > - * Wa_14015846243:mtl
> > + * Wa_14015846243:xelpg
> > */
> > - if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
> > + if (IS_DG2(i915) || GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
> > intel_wakeref_t wakeref;
> > u32 reg, shift;
> > @@ -4539,7 +4541,7 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
> > static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
> > {
> > - if (IS_METEORLAKE(perf->i915))
> > + if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
> > return reg_in_range_table(addr, mtl_oa_mux_regs);
> > else
> > return reg_in_range_table(addr, gen12_oa_mux_regs);
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: [Intel-gfx] [PATCH 8/8] drm/i915: Replace several IS_METEORLAKE with proper IP version checks
2023-07-19 15:22 ` Matt Roper
@ 2023-07-20 9:19 ` Tvrtko Ursulin
0 siblings, 0 replies; 30+ messages in thread
From: Tvrtko Ursulin @ 2023-07-20 9:19 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On 19/07/2023 16:22, Matt Roper wrote:
> On Wed, Jul 19, 2023 at 08:57:15AM +0100, Tvrtko Ursulin wrote:
>>
>> On 18/07/2023 23:28, Matt Roper wrote:
>>> Many of the IS_METEORLAKE conditions throughout the driver are supposed
>>> to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform
>>> specifically. Update those checks to ensure that the code will still
>>> operate properly if/when these IP versions show up on future platforms.
>>>
>>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++--
>>> drivers/gpu/drm/i915/gem/i915_gem_pages.c | 4 ++--
>>> drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 4 ++--
>>> drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_rps.c | 2 +-
>>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 4 ++--
>>> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
>>> drivers/gpu/drm/i915/i915_perf.c | 8 +++++---
>>> 10 files changed, 18 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>>> index d24c0ce8805c..19156ba4b9ef 100644
>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
>>> @@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data)
>>> BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) !=
>>> offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd));
>>> - /* Limiting the extension only to Meteor Lake */
>>> - if (!IS_METEORLAKE(i915))
>>> + /* Limiting the extension only to Xe_LPG and beyond */
>>> + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70))
>>> return -ENODEV;
>>> if (copy_from_user(&ext, base, sizeof(ext)))
>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
>>> index 89fc8ea6bcfc..4b003925cc3e 100644
>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
>>> @@ -470,9 +470,9 @@ enum i915_map_type i915_coherent_map_type(struct drm_i915_private *i915,
>>> bool always_coherent)
>>> {
>>> /*
>>> - * Wa_22016122933: always return I915_MAP_WC for MTL
>>> + * Wa_22016122933: always return I915_MAP_WC for Xe_LPM+
>>> */
>>> - if (i915_gem_object_is_lmem(obj) || IS_METEORLAKE(i915))
>>> + if (i915_gem_object_is_lmem(obj) || MEDIA_VER_FULL(i915) == IP_VER(13, 0))
>>
>> The helper is global for the driver/device but this makes the response based
>> on just one part of the driver which reads dodgy. There is another one in
>> __lrc_alloc_state.
>>
>> For instance, do these workarounds need to be applied to an object used from
>> the render tile? Yes it also was before these change, but now it is not
>> obvious to me if and how the ipver of the media tile affects the other tile.
>
> The current driver implementation is a bit overkill and goes beyond
> what's actually requested by the workaround. There are only coherency
> issues between the CPU and media, so if an object is only used on the
> primary GT (which would be the case for a lot of stuff like GuC0 CTBs
> and such), the workaround is not necessary.
>
> The workaround database marks this one as relevant to Xe_LPM+ and _not_
> relevant to Xe_LPG. Also, the hardware team's description even
> explicitly notes that this is only necessary for media and that the
> primary GT is not impacted.
>
> I pointed this out recently in one of the internal reviews for some of
> this code, so I think there may be some optimizations to the
> implementation of this workaround coming soon.
Okay, good to know improvements are on the radar. Would it make sense to
put a comment in i915_coherent_map_type, explaining the scope is
currently too wide, I mean in this patch when you replace the check with
MEDIA_VER_FULL?
Regards,
Tvrtko
>
>
> Matt
>
>>
>> Regards,
>>
>> Tvrtko
>>
>>> return I915_MAP_WC;
>>> if (HAS_LLC(i915) || always_coherent)
>>> return I915_MAP_WB;
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>>> index 21af0ec52223..24060278e7a2 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
>>> @@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine)
>>> {
>>> struct drm_i915_private *i915 = engine->i915;
>>> - if (IS_METEORLAKE(i915) && engine->id == GSC0) {
>>> + if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) {
>>> intel_uncore_write(engine->gt->uncore,
>>> RC_PSMI_CTRL_GSCCS,
>>> _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE));
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> index 4fefa67d285f..a125c3284bab 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> @@ -1095,10 +1095,10 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
>>> if (IS_ERR(obj)) {
>>> obj = i915_gem_object_create_shmem(engine->i915, context_size);
>>> /*
>>> - * Wa_22016122933: For MTL the shared memory needs to be mapped
>>> + * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
>>> * as WC on CPU side and UC (PAT index 2) on GPU side
>>> */
>>> - if (IS_METEORLAKE(engine->i915))
>>> + if (MEDIA_VER_FULL(engine->i915) == IP_VER(13, 0))
>>> i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
>>> }
>>> if (IS_ERR(obj))
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>>> index 2c014407225c..830ad2c10761 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>>> @@ -507,7 +507,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
>>> memset(table, 0, sizeof(struct drm_i915_mocs_table));
>>> table->unused_entries_index = I915_MOCS_PTE;
>>> - if (IS_METEORLAKE(i915)) {
>>> + if (GT_GRAPHICS_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) {
>>> table->size = ARRAY_SIZE(mtl_mocs_table);
>>> table->table = mtl_mocs_table;
>>> table->n_entries = MTL_NUM_MOCS_ENTRIES;
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
>>> index 403f0d9caadf..0714584dd83d 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>>> @@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt)
>>> static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
>>> {
>>> - if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
>>> + if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0))
>>> return false;
>>> if (!__HAS_ENGINE(engine_mask, GSC0))
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
>>> index e92e626d4994..89775328440e 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>>> @@ -1160,7 +1160,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c
>>> {
>>> struct drm_i915_private *i915 = rps_to_i915(rps);
>>> - if (IS_METEORLAKE(i915))
>>> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
>>> return mtl_get_freq_caps(rps, caps);
>>> else
>>> return __gen6_rps_get_freq_caps(rps, caps);
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> index 300b968e6de8..310d12dc7077 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
>>> @@ -743,10 +743,10 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
>>> return ERR_CAST(obj);
>>> /*
>>> - * Wa_22016122933: For MTL the shared memory needs to be mapped
>>> + * Wa_22016122933: For Xe_LPM+ the shared memory needs to be mapped
>>> * as WC on CPU side and UC (PAT index 2) on GPU side
>>> */
>>> - if (IS_METEORLAKE(gt->i915))
>>> + if (MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0))
>>> i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
>>> vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
>>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>>> index 4de44cf1026d..0a0217271b76 100644
>>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>>> @@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
>>> {
>>> struct drm_i915_private *i915 = obj_to_i915(obj);
>>> - if (IS_METEORLAKE(i915)) {
>>> + if (GT_GRAPHICS_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) {
>>> switch (obj->pat_index) {
>>> case 0: return " WB";
>>> case 1: return " WT";
>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>>> index ff95f2cdf2b0..cc9592d4de23 100644
>>> --- a/drivers/gpu/drm/i915/i915_perf.c
>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>>> @@ -3227,11 +3227,13 @@ get_sseu_config(struct intel_sseu *out_sseu,
>>> */
>>> u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915)
>>> {
>>> + struct intel_gt *gt = to_gt(i915);
>>> +
>>> /*
>>> * Wa_18013179988:dg2
>>> - * Wa_14015846243:mtl
>>> + * Wa_14015846243:xelpg
>>> */
>>> - if (IS_DG2(i915) || IS_METEORLAKE(i915)) {
>>> + if (IS_DG2(i915) || GT_GRAPHICS_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {
>>> intel_wakeref_t wakeref;
>>> u32 reg, shift;
>>> @@ -4539,7 +4541,7 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
>>> static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
>>> {
>>> - if (IS_METEORLAKE(perf->i915))
>>> + if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
>>> return reg_in_range_table(addr, mtl_oa_mux_regs);
>>> else
>>> return reg_in_range_table(addr, gen12_oa_mux_regs);
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Reduce MTL-specific platform checks
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
` (7 preceding siblings ...)
2023-07-18 22:28 ` [Intel-gfx] [PATCH 8/8] drm/i915: Replace several IS_METEORLAKE with proper IP version checks Matt Roper
@ 2023-07-18 23:37 ` Patchwork
2023-07-18 23:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2023-07-18 23:37 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Reduce MTL-specific platform checks
URL : https://patchwork.freedesktop.org/series/120943/
State : warning
== Summary ==
Error: dim checkpatch failed
c3afd0a4c654 drm/i915: Consolidate condition for Wa_22011802037
448c3a48c6f6 drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
-:154: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'gt' - possible side-effects?
#154: FILE: drivers/gpu/drm/i915/i915_drv.h:434:
+#define GT_GRAPHICS_RANGE(gt, from, until) \
+ (BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+ ((gt)->type != GT_MEDIA && \
+ (GRAPHICS_VER_FULL((gt)->i915) >= (from) && GRAPHICS_VER_FULL((gt)->i915) <= (until))))
-:154: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'from' - possible side-effects?
#154: FILE: drivers/gpu/drm/i915/i915_drv.h:434:
+#define GT_GRAPHICS_RANGE(gt, from, until) \
+ (BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+ ((gt)->type != GT_MEDIA && \
+ (GRAPHICS_VER_FULL((gt)->i915) >= (from) && GRAPHICS_VER_FULL((gt)->i915) <= (until))))
-:154: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'from' may be better as '(from)' to avoid precedence issues
#154: FILE: drivers/gpu/drm/i915/i915_drv.h:434:
+#define GT_GRAPHICS_RANGE(gt, from, until) \
+ (BUILD_BUG_ON_ZERO(from < IP_VER(2, 0)) + \
+ ((gt)->type != GT_MEDIA && \
+ (GRAPHICS_VER_FULL((gt)->i915) >= (from) && GRAPHICS_VER_FULL((gt)->i915) <= (until))))
total: 0 errors, 0 warnings, 3 checks, 116 lines checked
e99db64725a5 drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
-:292: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__gt' - possible side-effects?
#292: FILE: drivers/gpu/drm/i915/i915_drv.h:695:
+#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+ (__gt->type != GT_MEDIA && \
+ GRAPHICS_VER_FULL(__gt->i915) == ipver && \
+ IS_GRAPHICS_STEP(__gt->i915, since, until)))
-:292: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__gt' may be better as '(__gt)' to avoid precedence issues
#292: FILE: drivers/gpu/drm/i915/i915_drv.h:695:
+#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+ (__gt->type != GT_MEDIA && \
+ GRAPHICS_VER_FULL(__gt->i915) == ipver && \
+ IS_GRAPHICS_STEP(__gt->i915, since, until)))
-:292: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ipver' - possible side-effects?
#292: FILE: drivers/gpu/drm/i915/i915_drv.h:695:
+#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+ (__gt->type != GT_MEDIA && \
+ GRAPHICS_VER_FULL(__gt->i915) == ipver && \
+ IS_GRAPHICS_STEP(__gt->i915, since, until)))
-:292: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'ipver' may be better as '(ipver)' to avoid precedence issues
#292: FILE: drivers/gpu/drm/i915/i915_drv.h:695:
+#define IS_GFX_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+ (__gt->type != GT_MEDIA && \
+ GRAPHICS_VER_FULL(__gt->i915) == ipver && \
+ IS_GRAPHICS_STEP(__gt->i915, since, until)))
total: 0 errors, 0 warnings, 4 checks, 227 lines checked
57e068abc2d6 drm/i915: Eliminate IS_MTL_MEDIA_STEP
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__gt' - possible side-effects?
#46: FILE: drivers/gpu/drm/i915/i915_drv.h:701:
+#define IS_MEDIA_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(13, 0)) + \
+ (__gt && __gt->type == GT_MEDIA && \
+ MEDIA_VER_FULL(__gt->i915) == ipver && \
+ IS_MEDIA_STEP(__gt->i915, since, until)))
-:46: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__gt' may be better as '(__gt)' to avoid precedence issues
#46: FILE: drivers/gpu/drm/i915/i915_drv.h:701:
+#define IS_MEDIA_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(13, 0)) + \
+ (__gt && __gt->type == GT_MEDIA && \
+ MEDIA_VER_FULL(__gt->i915) == ipver && \
+ IS_MEDIA_STEP(__gt->i915, since, until)))
-:46: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ipver' - possible side-effects?
#46: FILE: drivers/gpu/drm/i915/i915_drv.h:701:
+#define IS_MEDIA_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(13, 0)) + \
+ (__gt && __gt->type == GT_MEDIA && \
+ MEDIA_VER_FULL(__gt->i915) == ipver && \
+ IS_MEDIA_STEP(__gt->i915, since, until)))
-:46: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'ipver' may be better as '(ipver)' to avoid precedence issues
#46: FILE: drivers/gpu/drm/i915/i915_drv.h:701:
+#define IS_MEDIA_IPVER_STEP(__gt, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(13, 0)) + \
+ (__gt && __gt->type == GT_MEDIA && \
+ MEDIA_VER_FULL(__gt->i915) == ipver && \
+ IS_MEDIA_STEP(__gt->i915, since, until)))
total: 0 errors, 0 warnings, 4 checks, 56 lines checked
5fbebe56cfed drm/i915: Eliminate IS_MTL_DISPLAY_STEP
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i915' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:74:
+#define IS_DISPLAY_IPVER_STEP(__i915, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+ DISPLAY_VER_FULL(__i915) == ipver && \
+ IS_DISPLAY_STEP(__i915, since, until))
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ipver' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:74:
+#define IS_DISPLAY_IPVER_STEP(__i915, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+ DISPLAY_VER_FULL(__i915) == ipver && \
+ IS_DISPLAY_STEP(__i915, since, until))
-:23: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'ipver' may be better as '(ipver)' to avoid precedence issues
#23: FILE: drivers/gpu/drm/i915/display/intel_display_device.h:74:
+#define IS_DISPLAY_IPVER_STEP(__i915, ipver, since, until) \
+ (BUILD_BUG_ON_ZERO(ipver < IP_VER(2, 0)) + \
+ DISPLAY_VER_FULL(__i915) == ipver && \
+ IS_DISPLAY_STEP(__i915, since, until))
-:122: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#122: FILE: drivers/gpu/drm/i915/i915_drv.h:446:
+#define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
+ DISPLAY_RUNTIME_INFO(i915)->ip.rel)
total: 0 errors, 0 warnings, 4 checks, 92 lines checked
d5a4c97b8df3 drm/i915/mtl: Eliminate subplatforms
-:92: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#92: FILE: include/drm/i915_pciids.h:743:
+#define INTEL_MTL_IDS(info) \
INTEL_VGA_DEVICE(0x7D40, info), \
INTEL_VGA_DEVICE(0x7D45, info), \
INTEL_VGA_DEVICE(0x7D55, info), \
+ INTEL_VGA_DEVICE(0x7D60, info), \
INTEL_VGA_DEVICE(0x7DD5, info)
-:92: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects?
#92: FILE: include/drm/i915_pciids.h:743:
+#define INTEL_MTL_IDS(info) \
INTEL_VGA_DEVICE(0x7D40, info), \
INTEL_VGA_DEVICE(0x7D45, info), \
INTEL_VGA_DEVICE(0x7D55, info), \
+ INTEL_VGA_DEVICE(0x7D60, info), \
INTEL_VGA_DEVICE(0x7DD5, info)
total: 1 errors, 0 warnings, 1 checks, 67 lines checked
42b7ddbd88d6 drm/i915/display: Eliminate IS_METEORLAKE checks
-:52: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'phy < PHY_C'
#52: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:34:
+ if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0) && (phy < PHY_C))
total: 0 errors, 0 warnings, 1 checks, 40 lines checked
eca499562098 drm/i915: Replace several IS_METEORLAKE with proper IP version checks
^ permalink raw reply [flat|nested] 30+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Reduce MTL-specific platform checks
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
` (8 preceding siblings ...)
2023-07-18 23:37 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Reduce MTL-specific platform checks Patchwork
@ 2023-07-18 23:37 ` Patchwork
2023-07-19 0:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-19 1:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2023-07-18 23:37 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Reduce MTL-specific platform checks
URL : https://patchwork.freedesktop.org/series/120943/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 30+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Reduce MTL-specific platform checks
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
` (9 preceding siblings ...)
2023-07-18 23:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-07-19 0:00 ` Patchwork
2023-07-19 1:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
11 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2023-07-19 0:00 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8136 bytes --]
== Series Details ==
Series: Reduce MTL-specific platform checks
URL : https://patchwork.freedesktop.org/series/120943/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13394 -> Patchwork_120943v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/index.html
Participating hosts (44 -> 43)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_120943v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@debugfs_test@read_all_entries:
- {bat-dg2-13}: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/bat-dg2-13/igt@debugfs_test@read_all_entries.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/bat-dg2-13/igt@debugfs_test@read_all_entries.html
Known issues
------------
Here are the changes found in Patchwork_120943v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-rte:
- fi-cfl-8109u: [PASS][3] -> [FAIL][4] ([i915#7940])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/fi-cfl-8109u/igt@i915_pm_rpm@basic-rte.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/fi-cfl-8109u/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@requests:
- bat-dg2-11: [PASS][5] -> [ABORT][6] ([i915#7913])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/bat-dg2-11/igt@i915_selftest@live@requests.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/bat-dg2-11/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- bat-mtlp-6: [PASS][7] -> [DMESG-WARN][8] ([i915#6367])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/bat-mtlp-6/igt@i915_selftest@live@slpc.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/bat-mtlp-6/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-kbl-7567u: [PASS][9] -> [INCOMPLETE][10] ([i915#4817])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/fi-kbl-7567u/igt@i915_suspend@basic-s3-without-i915.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/fi-kbl-7567u/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][11] ([i915#7828])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- fi-bsw-n3050: NOTRUN -> [SKIP][12] ([fdo#109271])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/fi-bsw-n3050/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-2: NOTRUN -> [SKIP][13] ([i915#1845])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-cfl-8700k: [FAIL][14] ([i915#7940]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
- fi-skl-guc: [FAIL][16] ([i915#7940]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/fi-skl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/fi-skl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
- fi-kbl-x1275: [SKIP][18] ([fdo#109271]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_pm_rpm@basic-rte:
- fi-tgl-1115g4: [FAIL][20] ([i915#7940]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/fi-tgl-1115g4/igt@i915_pm_rpm@basic-rte.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/fi-tgl-1115g4/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][22] ([i915#7911] / [i915#7913]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [DMESG-FAIL][24] ([i915#5334] / [i915#7872]) -> [PASS][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [DMESG-FAIL][26] ([i915#8497]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/bat-mtlp-8/igt@i915_selftest@live@requests.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/bat-mtlp-8/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@reset:
- bat-rpls-2: [ABORT][28] ([i915#4983] / [i915#7461] / [i915#7913] / [i915#8347]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/bat-rpls-2/igt@i915_selftest@live@reset.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/bat-rpls-2/igt@i915_selftest@live@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
Build changes
-------------
* Linux: CI_DRM_13394 -> Patchwork_120943v1
CI-20190529: 20190529
CI_DRM_13394: 4fab7ebb2e3675cb9fcd7a94a7b34caa0ea855cf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7392: 1e7c1d677d7ba57f342486bc522ed1bb6c19bf5e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_120943v1: 4fab7ebb2e3675cb9fcd7a94a7b34caa0ea855cf @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
5f91bf2dcc20 drm/i915: Replace several IS_METEORLAKE with proper IP version checks
bdb741c60bb5 drm/i915/display: Eliminate IS_METEORLAKE checks
afe3e7bd97da drm/i915/mtl: Eliminate subplatforms
60db5aab68eb drm/i915: Eliminate IS_MTL_DISPLAY_STEP
995078021b14 drm/i915: Eliminate IS_MTL_MEDIA_STEP
0d5c8060bebd drm/i915: Eliminate IS_MTL_GRAPHICS_STEP
9f0d9b7c52a9 drm/i915/xelpg: Call Xe_LPG workaround functions based on IP version
8532117254ce drm/i915: Consolidate condition for Wa_22011802037
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/index.html
[-- Attachment #2: Type: text/html, Size: 9556 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Reduce MTL-specific platform checks
2023-07-18 22:27 [Intel-gfx] [PATCH 0/8] Reduce MTL-specific platform checks Matt Roper
` (10 preceding siblings ...)
2023-07-19 0:00 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-07-19 1:53 ` Patchwork
11 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2023-07-19 1:53 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 32571 bytes --]
== Series Details ==
Series: Reduce MTL-specific platform checks
URL : https://patchwork.freedesktop.org/series/120943/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13394_full -> Patchwork_120943v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_120943v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_120943v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_120943v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-rkl-1/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-2.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-1/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-2.html
Known issues
------------
Here are the changes found in Patchwork_120943v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-snb5/igt@gem_ctx_persistence@idempotent.html
* igt@gem_exec_capture@pi@ccs0:
- shard-mtlp: [PASS][4] -> [FAIL][5] ([i915#7765])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-2/igt@gem_exec_capture@pi@ccs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-3/igt@gem_exec_capture@pi@ccs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][6] -> [FAIL][7] ([i915#2846])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-rkl: NOTRUN -> [FAIL][8] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-rkl-2/igt@gem_exec_fair@basic-pace@vecs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-6/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_params@secure-non-master:
- shard-rkl: NOTRUN -> [SKIP][11] ([fdo#112283])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@gem_exec_params@secure-non-master.html
* igt@gem_exec_reloc@basic-gtt-read:
- shard-rkl: NOTRUN -> [SKIP][12] ([i915#3281]) +2 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@gem_exec_reloc@basic-gtt-read.html
* igt@gem_exec_whisper@basic-contexts-forked-all:
- shard-mtlp: [PASS][13] -> [ABORT][14] ([i915#8131])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-1/igt@gem_exec_whisper@basic-contexts-forked-all.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-1/igt@gem_exec_whisper@basic-contexts-forked-all.html
* igt@gem_lmem_swapping@basic:
- shard-rkl: NOTRUN -> [SKIP][15] ([i915#4613])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-apl6/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][17] -> [TIMEOUT][18] ([i915#5493])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_pwrite@basic-exhaustion:
- shard-apl: NOTRUN -> [WARN][19] ([i915#2658])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-apl6/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_set_tiling_vs_pwrite:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#3282]) +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_userptr_blits@coherency-sync:
- shard-rkl: NOTRUN -> [SKIP][21] ([fdo#110542])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@gem_userptr_blits@coherency-sync.html
* igt@i915_pm_rpm@cursor-dpms:
- shard-tglu: [PASS][22] -> [FAIL][23] ([i915#7940]) +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-tglu-3/igt@i915_pm_rpm@cursor-dpms.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-tglu-3/igt@i915_pm_rpm@cursor-dpms.html
* igt@i915_pm_rpm@modeset-lpsp:
- shard-dg2: [PASS][24] -> [SKIP][25] ([i915#1397])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-dg2-10/igt@i915_pm_rpm@modeset-lpsp.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-1/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-rkl: [PASS][26] -> [SKIP][27] ([i915#1397]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-rkl-2/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_selftest@live@requests:
- shard-mtlp: [PASS][28] -> [DMESG-FAIL][29] ([i915#7269])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-5/igt@i915_selftest@live@requests.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-4/igt@i915_selftest@live@requests.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-mtlp: [PASS][30] -> [FAIL][31] ([i915#2521]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-6/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-1/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][32] ([i915#8502]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [FAIL][33] ([i915#8247]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-1/igt@kms_async_flips@crc@pipe-a-hdmi-a-3.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][34] ([i915#5286])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_big_fb@4-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-mtlp: [PASS][35] -> [FAIL][36] ([i915#3743])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-mtlp: [PASS][37] -> [FAIL][38] ([i915#5138])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][39] ([fdo#110723]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][40] ([i915#3734] / [i915#5354] / [i915#6095]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_ccs@pipe-a-missing-ccs-buffer-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-apl6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][42] ([i915#5354]) +5 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-snb: NOTRUN -> [SKIP][43] ([fdo#109271]) +189 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-snb2/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cdclk@mode-transition@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#4087] / [i915#7213]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-12/igt@kms_cdclk@mode-transition@pipe-a-dp-2.html
* igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#7828]) +1 similar issue
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
* igt@kms_content_protection@legacy@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [TIMEOUT][46] ([i915#7173])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-12/igt@kms_content_protection@legacy@pipe-a-dp-2.html
* igt@kms_content_protection@srm:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#7118])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-8/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [FAIL][48] ([i915#1339])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-12/igt@kms_content_protection@uevent@pipe-a-dp-2.html
* igt@kms_cursor_crc@cursor-rapid-movement-max-size:
- shard-rkl: NOTRUN -> [SKIP][49] ([i915#3555])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
* igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
- shard-mtlp: NOTRUN -> [SKIP][50] ([i915#3546])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-4/igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [PASS][51] -> [FAIL][52] ([i915#2346])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#3555])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-rkl: NOTRUN -> [SKIP][54] ([fdo#111825])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
- shard-snb: NOTRUN -> [DMESG-WARN][55] ([i915#8841]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-snb1/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#2672])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render:
- shard-rkl: NOTRUN -> [SKIP][57] ([fdo#111825] / [i915#1825]) +6 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][58] ([i915#3023]) +5 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_hdr@static-toggle:
- shard-rkl: NOTRUN -> [SKIP][59] ([i915#3555] / [i915#8228])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#3555] / [i915#8228])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-8/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c:
- shard-rkl: NOTRUN -> [SKIP][61] ([fdo#109289])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_pipe_b_c_ivb@pipe-b-double-modeset-then-modeset-pipe-c.html
* igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1:
- shard-apl: NOTRUN -> [FAIL][62] ([i915#4573]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-apl6/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-dp-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][63] ([i915#8292])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][64] ([i915#5176]) +5 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#5176]) +7 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-dp-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#5235]) +5 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#5235]) +19 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-3.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-rkl: NOTRUN -> [SKIP][68] ([fdo#111068] / [i915#658])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#658])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-apl6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@primary_page_flip:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271]) +38 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-apl6/igt@kms_psr@primary_page_flip.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-apl6/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-rkl: NOTRUN -> [SKIP][72] ([i915#2437])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_writeback@writeback-check-output.html
* igt@tools_test@sysfs_l3_parity:
- shard-rkl: NOTRUN -> [SKIP][73] ([fdo#109307])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@tools_test@sysfs_l3_parity.html
* igt@v3d/v3d_submit_csd@job-perfmon:
- shard-rkl: NOTRUN -> [SKIP][74] ([fdo#109315]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@v3d/v3d_submit_csd@job-perfmon.html
* igt@vc4/vc4_tiling@get-bad-flags:
- shard-rkl: NOTRUN -> [SKIP][75] ([i915#7711]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@vc4/vc4_tiling@get-bad-flags.html
#### Possible fixes ####
* igt@gem_eio@kms:
- shard-dg2: [INCOMPLETE][76] ([i915#7892]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-dg2-3/igt@gem_eio@kms.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-7/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [FAIL][78] ([i915#2842]) -> [PASS][79] +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-rkl-1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- {shard-dg1}: [FAIL][80] ([i915#3591]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-dg1-16/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
- shard-tglu: [FAIL][82] ([i915#3591]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-tglu-4/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- {shard-dg1}: [SKIP][84] ([i915#1397]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-dg1-14/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg1-19/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][86] ([i915#1397]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-4/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@gem-execbuf-stress@smem0:
- shard-tglu: [FAIL][88] ([i915#7940]) -> [PASS][89] +3 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-tglu-7/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-tglu-3/igt@i915_pm_rpm@gem-execbuf-stress@smem0.html
* igt@i915_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [SKIP][90] ([i915#1397]) -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-dg2-8/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-12/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-mtlp: [FAIL][92] ([i915#3743]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-5/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-4/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][94] ([i915#2346]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-mtlp: [FAIL][96] ([i915#2346]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [ABORT][98] ([i915#180]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-apl7/igt@kms_fbcon_fbt@fbc-suspend.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-rkl: [ABORT][100] ([i915#7461]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-rkl-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-7/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
#### Warnings ####
* igt@kms_async_flips@crc@pipe-a-edp-1:
- shard-mtlp: [DMESG-FAIL][102] ([i915#1982] / [i915#8561]) -> [DMESG-FAIL][103] ([i915#8561])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-5/igt@kms_async_flips@crc@pipe-a-edp-1.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-7/igt@kms_async_flips@crc@pipe-a-edp-1.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][104] ([i915#7118]) -> [SKIP][105] ([i915#7118] / [i915#7162]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-dg2-2/igt@kms_content_protection@type1.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-12/igt@kms_content_protection@type1.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: [DMESG-FAIL][106] ([i915#2017] / [i915#5954]) -> [FAIL][107] ([i915#2346])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][108] ([i915#3955]) -> [SKIP][109] ([fdo#110189] / [i915#3955])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-rkl-4/igt@kms_fbcon_fbt@psr-suspend.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][110] ([i915#4816]) -> [SKIP][111] ([i915#4070] / [i915#4816])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-rkl-7/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-rkl-2/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [CRASH][112] ([i915#7331]) -> [INCOMPLETE][113] ([i915#5493])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-dg2-12/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-dg2-8/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-mtlp: [TIMEOUT][114] ([i915#6950]) -> [ABORT][115] ([i915#8521])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13394/shard-mtlp-4/igt@sysfs_timeslice_duration@timeout@vecs0.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/shard-mtlp-2/igt@sysfs_timeslice_duration@timeout@vecs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1339]: https://gitlab.freedesktop.org/drm/intel/issues/1339
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6950]: https://gitlab.freedesktop.org/drm/intel/issues/6950
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7269]: https://gitlab.freedesktop.org/drm/intel/issues/7269
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7765]: https://gitlab.freedesktop.org/drm/intel/issues/7765
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7892]: https://gitlab.freedesktop.org/drm/intel/issues/7892
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8131]: https://gitlab.freedesktop.org/drm/intel/issues/8131
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8889]: https://gitlab.freedesktop.org/drm/intel/issues/8889
Build changes
-------------
* Linux: CI_DRM_13394 -> Patchwork_120943v1
CI-20190529: 20190529
CI_DRM_13394: 4fab7ebb2e3675cb9fcd7a94a7b34caa0ea855cf @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7392: 1e7c1d677d7ba57f342486bc522ed1bb6c19bf5e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_120943v1: 4fab7ebb2e3675cb9fcd7a94a7b34caa0ea855cf @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120943v1/index.html
[-- Attachment #2: Type: text/html, Size: 36766 bytes --]
^ permalink raw reply [flat|nested] 30+ messages in thread