From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
To: "Swarup, Aditya" <aditya.swarup@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Nikula, Jani" <jani.nikula@intel.com>,
"De Marchi, Lucas" <lucas.demarchi@intel.com>
Subject: Re: [Intel-gfx] [PATCH 19/21] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION
Date: Tue, 1 Dec 2020 18:35:01 +0000 [thread overview]
Message-ID: <f05e0f0810ce4646924acecf23858036@intel.com> (raw)
In-Reply-To: <20201117185029.22078-20-aditya.swarup@intel.com>
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Aditya Swarup
> Sent: Tuesday, November 17, 2020 10:50 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 19/21] drm/i915/display: Add
> HAS_D12_PLANE_MINIMIZATION
>
> From: José Roberto de Souza <jose.souza@intel.com>
>
> - As RKL and ADL-S only have 5 planes, primary and 4 sprites and
> the cursor plane, let's group the handling together under
> HAS_D12_PLANE_MINIMIZATION.
> - Also use macro to select pipe irq fault error mask.
>
> BSpec: 49251
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Imre Deak <imre.deak@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 +++
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> 4 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 1e954e2928fe..f65fd937bc55 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -351,7 +351,7 @@ int intel_plane_check_src_coordinates(struct
> intel_plane_state *plane_state)
>
> static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) {
> - if (IS_ROCKETLAKE(i915))
> + if (HAS_D12_PLANE_MINIMIZATION(i915))
> return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
> else
> return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); diff --git
> a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 817a5102b94f..f8d61785600d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1770,6 +1770,9 @@ extern const struct i915_rev_steppings
> adls_revids[]; #define INTEL_DISPLAY_ENABLED(dev_priv) \
> (drm_WARN_ON(&(dev_priv)->drm, !HAS_DISPLAY(dev_priv)),
> !(dev_priv)->params.disable_display)
>
> +#define HAS_D12_PLANE_MINIMIZATION(dev_priv)
> (IS_ROCKETLAKE(dev_priv) || \
> + IS_ALDERLAKE_S(dev_priv))
> +
> static inline bool intel_vtd_active(void) { #ifdef CONFIG_INTEL_IOMMU
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c index 758ed4f6c9f3..e39db39cd796
> 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2246,7 +2246,7 @@ static u32 gen8_de_port_aux_mask(struct
> drm_i915_private *dev_priv)
>
> static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv) {
> - if (IS_ROCKETLAKE(dev_priv))
> + if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
> return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
> else if (INTEL_GEN(dev_priv) >= 11)
> return GEN11_DE_PIPE_IRQ_FAULT_ERRORS; diff --git
> a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 64a09954fd54..49d5dac34d51 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -409,7 +409,7 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>
> BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) <
> I915_NUM_ENGINES);
>
> - if (IS_ROCKETLAKE(dev_priv))
> + if (HAS_D12_PLANE_MINIMIZATION(dev_priv))
> for_each_pipe(dev_priv, pipe)
> runtime->num_sprites[pipe] = 4;
> else if (INTEL_GEN(dev_priv) >= 11)
> --
> 2.27.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2020-12-01 18:35 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-17 18:50 [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 01/21] drm/i915/dg1: Enable ports Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 02/21] drm/i915/tgl: Fix macros for TGL SOC based WA Aditya Swarup
2020-11-17 19:03 ` Souza, Jose
2020-11-17 19:28 ` Lucas De Marchi
2020-11-17 19:33 ` Souza, Jose
2020-11-18 7:56 ` Lucas De Marchi
2020-11-17 19:31 ` Lucas De Marchi
2020-11-18 9:18 ` Jani Nikula
2020-11-24 1:32 ` Aditya Swarup
2020-11-24 13:14 ` Lucas De Marchi
2020-11-24 14:20 ` Jani Nikula
2020-11-24 20:11 ` Lucas De Marchi
2020-11-25 0:48 ` Aditya Swarup
2020-11-25 8:36 ` Jani Nikula
2020-11-17 18:50 ` [Intel-gfx] [PATCH 03/21] drm/i915/adl_s: Add ADL-S platform info and PCI ids Aditya Swarup
2020-11-17 19:17 ` Jani Nikula
2020-11-24 1:50 ` Aditya Swarup
2020-11-24 9:28 ` Jani Nikula
2020-11-17 18:50 ` [Intel-gfx] [PATCH 04/21] x86/gpu: add ADL_S stolen memory support Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 05/21] drm/i915/adl_s: Add PCH support Aditya Swarup
2020-11-20 0:09 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 06/21] drm/i915/adl_s: Add Interrupt Support Aditya Swarup
2020-11-20 0:12 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 07/21] drm/i915/adl_s: Add PHYs for Alderlake S Aditya Swarup
2020-11-20 0:20 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 08/21] drm/i915/adl_s: Configure DPLL for ADL-S Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 09/21] drm/i915/adl_s: Configure Port clock registers " Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 10/21] drm/i915/adl_s: Add HTI support and initialize display " Aditya Swarup
2020-11-20 0:27 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 11/21] drm/i915/adl_s: Add adl-s ddc pin mapping Aditya Swarup
2020-11-20 0:33 ` Matt Roper
2020-11-17 18:50 ` [Intel-gfx] [PATCH 12/21] drm/i915/adl_s: Add vbt port and aux channel settings for adls Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 13/21] drm/i915/adl_s: Update combo PHY master/slave relationships Aditya Swarup
2020-11-25 23:38 ` Srivatsa, Anusha
2020-11-17 18:50 ` [Intel-gfx] [PATCH 14/21] drm/i915/adl_s: Update PHY_MISC programming Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 15/21] drm/i915/adl_s: Add display, gt, ctx and ADL-S Aditya Swarup
2020-12-01 18:46 ` Srivatsa, Anusha
2020-12-01 20:51 ` Lucas De Marchi
2020-11-17 18:50 ` [Intel-gfx] [PATCH 16/21] drm/i915/adl_s: MCHBAR memory info registers are moved Aditya Swarup
2020-11-20 20:18 ` Lucas De Marchi
2020-11-20 20:39 ` Caz Yokoyama
2020-11-25 0:11 ` Lucas De Marchi
2020-11-17 18:50 ` [Intel-gfx] [PATCH 17/21] drm/i915/adl_s: Add power wells Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 18/21] drm/i915/adl_s: Re-use TGL GuC/HuC firmware Aditya Swarup
2020-11-25 22:52 ` Srivatsa, Anusha
2020-11-17 18:50 ` [Intel-gfx] [PATCH 19/21] drm/i915/display: Add HAS_D12_PLANE_MINIMIZATION Aditya Swarup
2020-12-01 18:35 ` Srivatsa, Anusha [this message]
2020-11-17 18:50 ` [Intel-gfx] [PATCH 20/21] drm/i915/adl_s: Load DMC Aditya Swarup
2020-11-17 18:50 ` [Intel-gfx] [PATCH 21/21] drm/i915/adl_s: Update memory bandwidth parameters Aditya Swarup
2020-11-25 22:46 ` Srivatsa, Anusha
2020-11-18 1:28 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alderlake-S (rev2) Patchwork
2020-11-18 1:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-11-18 1:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-11-18 7:53 ` [Intel-gfx] [PATCH 00/21] Introduce Alderlake-S Lucas De Marchi
2020-11-18 15:14 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce Alderlake-S (rev2) Patchwork
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