* [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup @ 2015-01-13 9:32 Mika Kuoppala 2015-01-13 9:32 ` [PATCH 2/2] drm/i915: Rename unpin_count to pin_count Mika Kuoppala 2015-01-20 16:14 ` [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup Daniel, Thomas 0 siblings, 2 replies; 6+ messages in thread From: Mika Kuoppala @ 2015-01-13 9:32 UTC (permalink / raw) To: intel-gfx We pin when we submit to execlist queue. Balance the pinning when the submitted queue is cleaned on reset. Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_gem.c | 4 ++++ drivers/gpu/drm/i915/intel_lrc.c | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 6c40365..68ea67d 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2657,6 +2657,10 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, execlist_link); list_del(&submit_req->execlist_link); intel_runtime_pm_put(dev_priv); + + if (submit_req->ctx != ring->default_context) + intel_lr_context_unpin(ring, submit_req->ctx); + i915_gem_context_unreference(submit_req->ctx); kfree(submit_req); } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 7670a0f..56a3625 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1774,6 +1774,7 @@ void intel_lr_context_free(struct intel_context *ctx) intel_unpin_ringbuffer_obj(ringbuf); i915_gem_object_ggtt_unpin(ctx_obj); } + WARN_ON(ctx->engine[ring->id].unpin_count); intel_destroy_ringbuffer_obj(ringbuf); kfree(ringbuf); drm_gem_object_unreference(&ctx_obj->base); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915: Rename unpin_count to pin_count 2015-01-13 9:32 [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup Mika Kuoppala @ 2015-01-13 9:32 ` Mika Kuoppala 2015-01-13 15:12 ` shuang.he 2015-01-20 16:16 ` Daniel, Thomas 2015-01-20 16:14 ` [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup Daniel, Thomas 1 sibling, 2 replies; 6+ messages in thread From: Mika Kuoppala @ 2015-01-13 9:32 UTC (permalink / raw) To: intel-gfx We increase it when we pin, so for the casual reader rename it to cause less confusion. Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e008fa0..b9bec97 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -725,7 +725,7 @@ struct intel_context { struct { struct drm_i915_gem_object *state; struct intel_ringbuffer *ringbuf; - int unpin_count; + int pin_count; } engine[I915_NUM_RINGS]; struct list_head link; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 56a3625..fbe59c1 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -839,11 +839,11 @@ static int intel_lr_context_pin(struct intel_engine_cs *ring, int ret = 0; WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); - if (ctx->engine[ring->id].unpin_count++ == 0) { + if (ctx->engine[ring->id].pin_count++ == 0) { ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); if (ret) - goto reset_unpin_count; + goto reset_pin_count; ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); if (ret) @@ -854,8 +854,8 @@ static int intel_lr_context_pin(struct intel_engine_cs *ring, unpin_ctx_obj: i915_gem_object_ggtt_unpin(ctx_obj); -reset_unpin_count: - ctx->engine[ring->id].unpin_count = 0; +reset_pin_count: + ctx->engine[ring->id].pin_count = 0; return ret; } @@ -868,7 +868,7 @@ void intel_lr_context_unpin(struct intel_engine_cs *ring, if (ctx_obj) { WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); - if (--ctx->engine[ring->id].unpin_count == 0) { + if (--ctx->engine[ring->id].pin_count == 0) { intel_unpin_ringbuffer_obj(ringbuf); i915_gem_object_ggtt_unpin(ctx_obj); } @@ -1774,7 +1774,7 @@ void intel_lr_context_free(struct intel_context *ctx) intel_unpin_ringbuffer_obj(ringbuf); i915_gem_object_ggtt_unpin(ctx_obj); } - WARN_ON(ctx->engine[ring->id].unpin_count); + WARN_ON(ctx->engine[ring->id].pin_count); intel_destroy_ringbuffer_obj(ringbuf); kfree(ringbuf); drm_gem_object_unreference(&ctx_obj->base); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Rename unpin_count to pin_count 2015-01-13 9:32 ` [PATCH 2/2] drm/i915: Rename unpin_count to pin_count Mika Kuoppala @ 2015-01-13 15:12 ` shuang.he 2015-01-20 16:16 ` Daniel, Thomas 1 sibling, 0 replies; 6+ messages in thread From: shuang.he @ 2015-01-13 15:12 UTC (permalink / raw) To: shuang.he, ethan.gao, intel-gfx, mika.kuoppala Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) -------------------------------------Summary------------------------------------- Platform Delta drm-intel-nightly Series Applied PNV -1 354/354 353/354 ILK 354/354 354/354 SNB +1-1 401/424 401/424 IVB 488/488 488/488 BYT 278/278 278/278 HSW -40 529/529 489/529 BDW -1 405/405 404/405 -------------------------------------Detailed------------------------------------- Platform Test drm-intel-nightly Series Applied *PNV igt_gen3_mixed_blits PASS(3, M7M23) CRASH(1, M23) SNB igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible NSPT(1, M35)PASS(9, M35M22) PASS(1, M22) *SNB igt_gem_concurrent_blit_gtt-rcs-early-read-interruptible PASS(10, M35M22) DMESG_WARN(1, M22) HSW igt_kms_cursor_crc_cursor-size-change NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_kms_fence_pin_leak NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_lpsp_non-edp NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_cursor NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_cursor-dpms NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_dpms-non-lpsp NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_drm-resources-equal NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_fences NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_fences-dpms NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_gem-execbuf NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_gem-mmap-cpu NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_gem-mmap-gtt NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_gem-pread NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_i2c NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_modeset-non-lpsp NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_pci-d3-state NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_pm_rpm_rte NSPT(5, M40M19)PASS(1, M20) NSPT(1, M40) HSW igt_gem_concurrent_blit_gtt-bcs-early-read-forked DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-bcs-early-read-interruptible DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-forked DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-interruptible DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-bcs-overwrite-source-forked DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-rcs-early-read-forked DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-rcs-early-read-interruptible DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-rcs-gpu-read-after-write-forked DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-rcs-gpu-read-after-write-interruptible DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-rcs-overwrite-source-forked DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gtt-rcs-overwrite-source-interruptible DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gttX-bcs-early-read-interruptible DMESG_WARN(4, M40)PASS(2, M20M19) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gttX-bcs-gpu-read-after-write-interruptible DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gttX-bcs-overwrite-source-forked DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gttX-bcs-overwrite-source-interruptible DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gttX-rcs-early-read-interruptible DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gttX-rcs-gpu-read-after-write-interruptible DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gttX-rcs-overwrite-source-forked DMESG_WARN(5, M40M19)PASS(1, M20) DMESG_WARN(1, M40) HSW igt_gem_concurrent_blit_gttX-rcs-overwrite-source-interruptible DMESG_WARN(2, M40M19)PASS(2, M20M40) DMESG_WARN(1, M40) *BDW igt_gem_concurrent_blit_gtt-bcs-gpu-read-after-write-interruptible PASS(9, M30M28) DMESG_WARN(1, M28) Note: You need to pay more attention to line start with '*' _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915: Rename unpin_count to pin_count 2015-01-13 9:32 ` [PATCH 2/2] drm/i915: Rename unpin_count to pin_count Mika Kuoppala 2015-01-13 15:12 ` shuang.he @ 2015-01-20 16:16 ` Daniel, Thomas 1 sibling, 0 replies; 6+ messages in thread From: Daniel, Thomas @ 2015-01-20 16:16 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf > Of Mika Kuoppala > Sent: Tuesday, January 13, 2015 9:32 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 2/2] drm/i915: Rename unpin_count to pin_count > > We increase it when we pin, so for the casual reader rename it to cause less > confusion. > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_lrc.c | > 12 ++++++------ > 2 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h > b/drivers/gpu/drm/i915/i915_drv.h index e008fa0..b9bec97 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -725,7 +725,7 @@ struct intel_context { > struct { > struct drm_i915_gem_object *state; > struct intel_ringbuffer *ringbuf; > - int unpin_count; > + int pin_count; > } engine[I915_NUM_RINGS]; > > struct list_head link; > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > b/drivers/gpu/drm/i915/intel_lrc.c > index 56a3625..fbe59c1 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -839,11 +839,11 @@ static int intel_lr_context_pin(struct > intel_engine_cs *ring, > int ret = 0; > > WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); > - if (ctx->engine[ring->id].unpin_count++ == 0) { > + if (ctx->engine[ring->id].pin_count++ == 0) { > ret = i915_gem_obj_ggtt_pin(ctx_obj, > GEN8_LR_CONTEXT_ALIGN, 0); > if (ret) > - goto reset_unpin_count; > + goto reset_pin_count; > > ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); > if (ret) > @@ -854,8 +854,8 @@ static int intel_lr_context_pin(struct intel_engine_cs > *ring, > > unpin_ctx_obj: > i915_gem_object_ggtt_unpin(ctx_obj); > -reset_unpin_count: > - ctx->engine[ring->id].unpin_count = 0; > +reset_pin_count: > + ctx->engine[ring->id].pin_count = 0; > > return ret; > } > @@ -868,7 +868,7 @@ void intel_lr_context_unpin(struct intel_engine_cs > *ring, > > if (ctx_obj) { > WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); > - if (--ctx->engine[ring->id].unpin_count == 0) { > + if (--ctx->engine[ring->id].pin_count == 0) { > intel_unpin_ringbuffer_obj(ringbuf); > i915_gem_object_ggtt_unpin(ctx_obj); > } > @@ -1774,7 +1774,7 @@ void intel_lr_context_free(struct intel_context > *ctx) > intel_unpin_ringbuffer_obj(ringbuf); > i915_gem_object_ggtt_unpin(ctx_obj); > } > - WARN_ON(ctx->engine[ring->id].unpin_count); > + WARN_ON(ctx->engine[ring->id].pin_count); > intel_destroy_ringbuffer_obj(ringbuf); > kfree(ringbuf); > drm_gem_object_unreference(&ctx_obj->base); Reviewed-by: Thomas Daniel <thomas.daniel@intel.com> Although this counter should go away once I get a chance to finish the reworking of the dynamic pinning. Thomas. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup 2015-01-13 9:32 [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup Mika Kuoppala 2015-01-13 9:32 ` [PATCH 2/2] drm/i915: Rename unpin_count to pin_count Mika Kuoppala @ 2015-01-20 16:14 ` Daniel, Thomas 2015-01-21 8:31 ` Daniel Vetter 1 sibling, 1 reply; 6+ messages in thread From: Daniel, Thomas @ 2015-01-20 16:14 UTC (permalink / raw) To: Mika Kuoppala, intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf > Of Mika Kuoppala > Sent: Tuesday, January 13, 2015 9:32 AM > To: intel-gfx@lists.freedesktop.org > Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Balance context pinning on reset > cleanup > > We pin when we submit to execlist queue. Balance the pinning when the > submitted queue is cleaned on reset. > > Cc: Dave Gordon <david.s.gordon@intel.com> > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_gem.c | 4 ++++ > drivers/gpu/drm/i915/intel_lrc.c | 1 + > 2 files changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c > b/drivers/gpu/drm/i915/i915_gem.c index 6c40365..68ea67d 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -2657,6 +2657,10 @@ static void i915_gem_reset_ring_cleanup(struct > drm_i915_private *dev_priv, > execlist_link); > list_del(&submit_req->execlist_link); > intel_runtime_pm_put(dev_priv); > + > + if (submit_req->ctx != ring->default_context) > + intel_lr_context_unpin(ring, submit_req->ctx); > + > i915_gem_context_unreference(submit_req->ctx); > kfree(submit_req); > } > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > b/drivers/gpu/drm/i915/intel_lrc.c > index 7670a0f..56a3625 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1774,6 +1774,7 @@ void intel_lr_context_free(struct intel_context > *ctx) > intel_unpin_ringbuffer_obj(ringbuf); > i915_gem_object_ggtt_unpin(ctx_obj); > } > + WARN_ON(ctx->engine[ring->id].unpin_count); > intel_destroy_ringbuffer_obj(ringbuf); > kfree(ringbuf); > drm_gem_object_unreference(&ctx_obj->base); Assuming this still patch still applies after Nick Hoath's recent changes, Reviewed-by: Thomas Daniel <thomas.daniel@intel.com> Note that there is still a bug in reset_ring_cleanup where neither the ring buffers nor the contexts head and tail are updated in execlists mode but the requests are cleaned out. I will post a separate patch for that soon. Thomas. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup 2015-01-20 16:14 ` [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup Daniel, Thomas @ 2015-01-21 8:31 ` Daniel Vetter 0 siblings, 0 replies; 6+ messages in thread From: Daniel Vetter @ 2015-01-21 8:31 UTC (permalink / raw) To: Daniel, Thomas; +Cc: intel-gfx@lists.freedesktop.org On Tue, Jan 20, 2015 at 04:14:58PM +0000, Daniel, Thomas wrote: > > -----Original Message----- > > From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf > > Of Mika Kuoppala > > Sent: Tuesday, January 13, 2015 9:32 AM > > To: intel-gfx@lists.freedesktop.org > > Subject: [Intel-gfx] [PATCH 1/2] drm/i915: Balance context pinning on reset > > cleanup > > > > We pin when we submit to execlist queue. Balance the pinning when the > > submitted queue is cleaned on reset. > > > > Cc: Dave Gordon <david.s.gordon@intel.com> > > Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> > > --- > > drivers/gpu/drm/i915/i915_gem.c | 4 ++++ > > drivers/gpu/drm/i915/intel_lrc.c | 1 + > > 2 files changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem.c > > b/drivers/gpu/drm/i915/i915_gem.c index 6c40365..68ea67d 100644 > > --- a/drivers/gpu/drm/i915/i915_gem.c > > +++ b/drivers/gpu/drm/i915/i915_gem.c > > @@ -2657,6 +2657,10 @@ static void i915_gem_reset_ring_cleanup(struct > > drm_i915_private *dev_priv, > > execlist_link); > > list_del(&submit_req->execlist_link); > > intel_runtime_pm_put(dev_priv); > > + > > + if (submit_req->ctx != ring->default_context) > > + intel_lr_context_unpin(ring, submit_req->ctx); > > + > > i915_gem_context_unreference(submit_req->ctx); > > kfree(submit_req); > > } > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > > b/drivers/gpu/drm/i915/intel_lrc.c > > index 7670a0f..56a3625 100644 > > --- a/drivers/gpu/drm/i915/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/intel_lrc.c > > @@ -1774,6 +1774,7 @@ void intel_lr_context_free(struct intel_context > > *ctx) > > intel_unpin_ringbuffer_obj(ringbuf); > > i915_gem_object_ggtt_unpin(ctx_obj); > > } > > + WARN_ON(ctx->engine[ring->id].unpin_count); > > intel_destroy_ringbuffer_obj(ringbuf); > > kfree(ringbuf); > > drm_gem_object_unreference(&ctx_obj->base); > > Assuming this still patch still applies after Nick Hoath's recent changes, > Reviewed-by: Thomas Daniel <thomas.daniel@intel.com> Both merged, thanks for patches&review. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-01-21 8:31 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-01-13 9:32 [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup Mika Kuoppala 2015-01-13 9:32 ` [PATCH 2/2] drm/i915: Rename unpin_count to pin_count Mika Kuoppala 2015-01-13 15:12 ` shuang.he 2015-01-20 16:16 ` Daniel, Thomas 2015-01-20 16:14 ` [PATCH 1/2] drm/i915: Balance context pinning on reset cleanup Daniel, Thomas 2015-01-21 8:31 ` Daniel Vetter
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