From: Chris Wilson <chris@chris-wilson.co.uk>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+.
Date: Mon, 26 Sep 2011 20:43:50 +0100 [thread overview]
Message-ID: <f80fcd$20ga0a@fmsmga001.fm.intel.com> (raw)
In-Reply-To: <20110926192302.GC2804@phenom.ffwll.local>
On Mon, 26 Sep 2011 21:23:02 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Sep 26, 2011 at 08:16:04PM +0100, Chris Wilson wrote:
> > On Mon, 26 Sep 2011 11:59:23 -0700, Kenneth Graunke <kenneth@whitecape.org> wrote:
> > > From: Jesse Barnes <jbarnes@virtuousgeek.org>
> >
> > From the school of "If ain't broke, don't fix it" there needs to be a real
> > explanation of why this change is required here.
> >
> > PIPE_CONTROL and its workarounds is a very bitter pill to swallow if
> > MI_FLUSH continues to function.
>
> Lazy tlb flush, gfdt flush, seperate depth cache flush. In short, I want
> this ;-)
I feel jaded, I could have swore you just said "bug, bugs, bugs." ;-)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2011-09-26 19:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-26 18:59 [PATCH] drm/i915: Use PIPE_CONTROL for flushing on gen6+ Kenneth Graunke
2011-09-26 19:16 ` Chris Wilson
2011-09-26 19:23 ` Daniel Vetter
2011-09-26 19:43 ` Chris Wilson [this message]
2011-09-26 20:15 ` Keith Packard
2011-09-26 20:21 ` Kenneth Graunke
2011-09-26 20:31 ` Daniel Vetter
2011-09-26 20:38 ` Kenneth Graunke
2011-09-26 22:25 ` Eric Anholt
2011-10-03 20:00 ` Jesse Barnes
2011-10-03 21:14 ` Keith Packard
2011-10-03 21:21 ` Jesse Barnes
2011-10-03 22:59 ` Eric Anholt
2011-10-03 23:16 ` Jesse Barnes
-- strict thread matches above, loose matches on Subject: below --
2011-10-11 21:41 [PATCH 3/3] " Daniel Vetter
2011-10-16 8:23 ` [PATCH] " Daniel Vetter
2011-10-17 1:27 ` Ben Widawsky
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