Re: [PATCH v2 21/56] drm/i915/ltphy: Calculate port clock for HDMI FRL

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915/ltphy: Fragile FRL mode check misidentifies 300MHz/600MHz TMDS as FRL
--

commit c8e5d35c7adb72d4a07659a9da4c78974ed1e816
Author: Suraj Kandpal <suraj.kandpal@intel.com>

drm/i915/ltphy: Calculate port clock for HDMI FRL

Define function to get the port clock after we read VDR0_CONFIG.
This helps us determine the port clock for HDMI FRL use case in LT
PHY.

> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 0e2ebd550bc5e..7ac0888cdf452 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -2000,6 +2019,10 @@ intel_lt_phy_calc_port_clock(struct intel_display *display,
>  		rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK,
>  				      lt_state->config[0]);
>  		clk = intel_lt_phy_get_dp_clock(rate);
> +	} else if (mode == MODE_HDMI_FRL) {
> +		rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK,
> +				      lt_state->config[0]);
> +		clk = intel_lt_phy_get_hdmi_frl_clock(rate);

[Severity: High]
Does returning valid FRL clocks from readout here expose an issue where 300MHz
and 600MHz TMDS modes are misidentified as FRL?

The driver relies on clock value guessing via intel_hdmi_is_frl(port_clock)
instead of checking protocol state (like crtc_state->frl.enable or
ltpll->config[0]) to distinguish FRL modes from TMDS.

Because 300MHz and 600MHz are both valid TMDS character rates and FRL link
rates, a TMDS mode running at exactly 300MHz or 600MHz (such as custom 4K or
1440p timings) will be misidentified as FRL.

This leads to incorrect PHY PLL state calculation and wrong port clock
programming in intel_lt_phy_program_port_clock_ctl():

	if (intel_lt_phy_is_hdmi(ltpll) && intel_hdmi_is_frl(port_clock))
		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
	else
		val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK);

Programming DIV18CLK instead of MAXPCLK will cause display failure for these
TMDS modes.

>  	} else if (mode == MODE_HDMI_20) {
>  		clk = intel_lt_phy_calc_hdmi_port_clock(display, lt_state);
>  	} else {

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261012035806.3361439-1-ankit.k.nautiyal@intel.com?part=21