* [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency
2025-10-09 7:17 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
@ 2025-10-09 7:17 ` Ankit Nautiyal
0 siblings, 0 replies; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 7:17 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: ville.syrjala, Ankit Nautiyal, Animesh Manna, Jouni Högander
Panel Replay and PSR2 selective update require sufficient vblank duration
to accommodate wake latencies. However, the current
wake_lines_fit_into_vblank() logic does not account for the minimum
Set Context Latency (SCL) lines.
Separate out _intel_psr_min_set_context_latency() to compute the minimum
SCL requirement based on platform and feature usage.
The alpm_config_valid() helper is updated to pass the necessary context for
determining whether Panel Replay or PSR2 selective update is enabled.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 102 ++++++++++++++---------
1 file changed, 61 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f7115969b4c5..295ce6e15ab2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1360,14 +1360,64 @@ static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
return entry_setup_frames;
}
+static
+int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state,
+ bool needs_panel_replay,
+ bool needs_sel_update)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (!crtc_state->has_psr)
+ return 0;
+
+ /* Wa_14015401596 */
+ if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
+ return 1;
+
+ /* Rest is for SRD_STATUS needed on LunarLake and onwards */
+ if (DISPLAY_VER(display) < 20)
+ return 0;
+
+ /*
+ * Comment on SRD_STATUS register in Bspec for LunarLake and onwards:
+ *
+ * To deterministically capture the transition of the state machine
+ * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
+ * one line after the non-delayed V. Blank.
+ *
+ * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
+ * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
+ * - TRANS_VTOTAL[ Vertical Active ])
+ *
+ * SRD_STATUS is used only by PSR1 on PantherLake.
+ * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
+ */
+
+ if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||
+ needs_sel_update))
+ return 0;
+ else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||
+ intel_crtc_has_type(crtc_state,
+ INTEL_OUTPUT_EDP)))
+ return 0;
+ else
+ return 1;
+}
+
static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
- bool aux_less)
+ bool aux_less,
+ bool needs_sel_update,
+ bool needs_panel_replay)
{
struct intel_display *display = to_intel_display(intel_dp);
int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
crtc_state->hw.adjusted_mode.crtc_vblank_start;
int wake_lines;
+ int scl = _intel_psr_min_set_context_latency(crtc_state,
+ needs_sel_update,
+ needs_panel_replay);
+ vblank -= scl;
if (aux_less)
wake_lines = intel_dp->alpm_parameters.aux_less_wake_lines;
@@ -1388,7 +1438,9 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
static bool alpm_config_valid(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
- bool aux_less)
+ bool aux_less,
+ bool needs_sel_update,
+ bool needs_panel_replay)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1398,7 +1450,8 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less)) {
+ if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less,
+ needs_sel_update, needs_panel_replay)) {
drm_dbg_kms(display->drm,
"PSR2/Panel Replay not enabled, too short vblank time\n");
return false;
@@ -1490,7 +1543,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (!alpm_config_valid(intel_dp, crtc_state, false))
+ if (!alpm_config_valid(intel_dp, crtc_state, false, true, crtc_state->has_panel_replay))
return false;
if (!crtc_state->enable_psr2_sel_fetch &&
@@ -1641,7 +1694,7 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
return false;
}
- if (!alpm_config_valid(intel_dp, crtc_state, true))
+ if (!alpm_config_valid(intel_dp, crtc_state, true, false, true))
return false;
return true;
@@ -2367,43 +2420,10 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
*/
int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
-
- if (!crtc_state->has_psr)
- return 0;
-
- /* Wa_14015401596 */
- if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
- return 1;
-
- /* Rest is for SRD_STATUS needed on LunarLake and onwards */
- if (DISPLAY_VER(display) < 20)
- return 0;
- /*
- * Comment on SRD_STATUS register in Bspec for LunarLake and onwards:
- *
- * To deterministically capture the transition of the state machine
- * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
- * one line after the non-delayed V. Blank.
- *
- * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
- * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
- * - TRANS_VTOTAL[ Vertical Active ])
- *
- * SRD_STATUS is used only by PSR1 on PantherLake.
- * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
- */
-
- if (DISPLAY_VER(display) >= 30 && (crtc_state->has_panel_replay ||
- crtc_state->has_sel_update))
- return 0;
- else if (DISPLAY_VER(display) < 30 && (crtc_state->has_sel_update ||
- intel_crtc_has_type(crtc_state,
- INTEL_OUTPUT_EDP)))
- return 0;
- else
- return 1;
+ return _intel_psr_min_set_context_latency(crtc_state,
+ crtc_state->has_panel_replay,
+ crtc_state->has_sel_update);
}
static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 0/8] Preparatory patches for guardband optimization
@ 2025-10-09 9:00 Ankit Nautiyal
2025-10-09 9:00 ` [PATCH 1/8] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
` (11 more replies)
0 siblings, 12 replies; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 9:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
Handle few cases which will need changes when guardband will no longer
be matched to vblank length.
- Fix the vblank_start evaluation.
- Fix PSR wake latency checks wrt to guradband.
Rev 2: PSR went through some changes recently, rebase the patches on latest
PSR changes.
Ankit Nautiyal (8):
drm/i915/vrr: Use crtc_vsync_start/end for computing
vrr.vsync_start/end
drm/i915/vrr:
s/intel_vrr_compute_config_late/intel_vrr_compute_guardband
drm/i915/vblank: Add helper to get correct vblank length
drm/i915/psr: Consider SCL lines when validating vblank for wake
latency
drm/i915/display: Check if final vblank is sufficient for PSR features
drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR
TG
drm/i915/display: Add vblank_start adjustment logic for always-on VRR
TG
drm/i915/display: Prepare for vblank_delay for LRR
drivers/gpu/drm/i915/display/intel_ddi.c | 3 +
drivers/gpu/drm/i915/display/intel_display.c | 14 +-
drivers/gpu/drm/i915/display/intel_dp.c | 9 ++
drivers/gpu/drm/i915/display/intel_dp.h | 3 +
drivers/gpu/drm/i915/display/intel_psr.c | 153 +++++++++++++------
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
drivers/gpu/drm/i915/display/intel_vblank.c | 10 ++
drivers/gpu/drm/i915/display/intel_vblank.h | 2 +
drivers/gpu/drm/i915/display/intel_vrr.c | 26 +++-
drivers/gpu/drm/i915/display/intel_vrr.h | 2 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 3 +-
11 files changed, 168 insertions(+), 59 deletions(-)
--
2.45.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH 1/8] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
@ 2025-10-09 9:00 ` Ankit Nautiyal
2025-10-09 9:00 ` [PATCH 2/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband Ankit Nautiyal
` (10 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 9:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal, Uma Shankar
Use adjusted_mode->crtc_vsync_start/end instead of
adjusted_mode->vsync_start while computing vrr.vsync_start/end.
For most modes, these are same but for 3D/stereo modes the
crtc_vsync_start is different than vsync_start.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 190c51be5cbc..4bc14b5e685f 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -394,10 +394,10 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
if (HAS_AS_SDP(display)) {
crtc_state->vrr.vsync_start =
(crtc_state->hw.adjusted_mode.crtc_vtotal -
- crtc_state->hw.adjusted_mode.vsync_start);
+ crtc_state->hw.adjusted_mode.crtc_vsync_start);
crtc_state->vrr.vsync_end =
(crtc_state->hw.adjusted_mode.crtc_vtotal -
- crtc_state->hw.adjusted_mode.vsync_end);
+ crtc_state->hw.adjusted_mode.crtc_vsync_end);
}
}
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 2/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-09 9:00 ` [PATCH 1/8] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
@ 2025-10-09 9:00 ` Ankit Nautiyal
2025-10-10 14:53 ` Ville Syrjälä
2025-10-09 9:00 ` [PATCH 3/8] drm/i915/vblank: Add helper to get correct vblank length Ankit Nautiyal
` (9 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 9:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
The helper intel_vrr_compute_config_late() practically just computes the
guardband. Rename intel_vrr_compute_config_late() to
intel_vrr_compute_guardband().
Since we are going to compute the guardband and then move the
vblank_start for optmizing guardband move it to
intel_crtc_compute_config() which handles such changes.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
drivers/gpu/drm/i915/display/intel_vrr.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b57efd870774..cd499e58bed3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2414,6 +2414,8 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
if (ret)
return ret;
+ intel_vrr_compute_guardband(crtc_state);
+
ret = intel_dpll_crtc_compute_clock(state, crtc);
if (ret)
return ret;
@@ -4722,8 +4724,6 @@ intel_modeset_pipe_config_late(struct intel_atomic_state *state,
struct drm_connector *connector;
int i;
- intel_vrr_compute_config_late(crtc_state);
-
for_each_new_connector_in_state(&state->base, connector,
conn_state, i) {
struct intel_encoder *encoder =
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 4bc14b5e685f..8d71d7dc9d12 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -433,7 +433,7 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
intel_vrr_max_vblank_guardband(crtc_state));
}
-void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
index 7317f8730089..bc9044621635 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr.h
@@ -21,7 +21,7 @@ bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
void intel_vrr_check_modeset(struct intel_atomic_state *state);
void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
-void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state);
+void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state);
void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
void intel_vrr_send_push(struct intel_dsb *dsb,
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 3/8] drm/i915/vblank: Add helper to get correct vblank length
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-09 9:00 ` [PATCH 1/8] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
2025-10-09 9:00 ` [PATCH 2/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband Ankit Nautiyal
@ 2025-10-09 9:00 ` Ankit Nautiyal
2025-10-10 14:54 ` Ville Syrjälä
2025-10-09 9:00 ` [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency Ankit Nautiyal
` (8 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 9:00 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
Currently crtc_vblank_start is assumed to be the vblank_start for the fixed
refresh rate case. That value can be different from the variable refresh
rate case whenever always_use_vrr_tg()==false. On icl/tgl it's always
different due to the extra vblank delay, and also on adl+ it could be
different if we were to use an optimized guardband.
So places where crtc_vblank_start is used to compute vblank length needs
change so as to account for cases where vrr is enabled. Specifically
with vrr.enable the effective vblank length is actually guardband.
Add a helper to get the correct vblank length for both vrr and fixed
refresh rate cases. Use this helper where vblank_start is used to
compute the vblank length.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vblank.c | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_vblank.h | 2 ++
drivers/gpu/drm/i915/display/skl_watermark.c | 3 ++-
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 0b7fcc05e64c..2fc0c1c0bb87 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -767,3 +767,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
return scanline;
}
+
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ if (crtc_state->vrr.enable)
+ return crtc_state->vrr.guardband;
+ else
+ return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
index 21fbb08d61d5..98d04cacd65f 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -48,4 +48,6 @@ const struct intel_crtc_state *
intel_pre_commit_crtc_state(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);
+
#endif /* __INTEL_VBLANK_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9df9ee137bf9..06e5e6c77d2e 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,6 +28,7 @@
#include "intel_flipq.h"
#include "intel_pcode.h"
#include "intel_plane.h"
+#include "intel_vblank.h"
#include "intel_wm.h"
#include "skl_universal_plane_regs.h"
#include "skl_watermark.h"
@@ -2241,7 +2242,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
scaler_prefill_latency(crtc_state) +
dsc_prefill_latency(crtc_state) +
wm0_lines >
- adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+ intel_crtc_vblank_length(crtc_state);
}
static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
` (2 preceding siblings ...)
2025-10-09 9:00 ` [PATCH 3/8] drm/i915/vblank: Add helper to get correct vblank length Ankit Nautiyal
@ 2025-10-09 9:00 ` Ankit Nautiyal
2025-10-10 6:40 ` Hogander, Jouni
2025-10-09 9:00 ` [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features Ankit Nautiyal
` (7 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 9:00 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: ville.syrjala, Ankit Nautiyal, Animesh Manna, Jouni Högander
Panel Replay and PSR2 selective update require sufficient vblank duration
to accommodate wake latencies. However, the current
wake_lines_fit_into_vblank() logic does not account for the minimum
Set Context Latency (SCL) lines.
Separate out _intel_psr_min_set_context_latency() to compute the minimum
SCL requirement based on platform and feature usage.
The alpm_config_valid() helper is updated to pass the necessary context for
determining whether Panel Replay or PSR2 selective update is enabled.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 102 ++++++++++++++---------
1 file changed, 61 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2131473cead6..212bd244beed 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1361,14 +1361,64 @@ static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
return entry_setup_frames;
}
+static
+int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state,
+ bool needs_panel_replay,
+ bool needs_sel_update)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (!crtc_state->has_psr)
+ return 0;
+
+ /* Wa_14015401596 */
+ if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
+ return 1;
+
+ /* Rest is for SRD_STATUS needed on LunarLake and onwards */
+ if (DISPLAY_VER(display) < 20)
+ return 0;
+
+ /*
+ * Comment on SRD_STATUS register in Bspec for LunarLake and onwards:
+ *
+ * To deterministically capture the transition of the state machine
+ * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
+ * one line after the non-delayed V. Blank.
+ *
+ * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
+ * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
+ * - TRANS_VTOTAL[ Vertical Active ])
+ *
+ * SRD_STATUS is used only by PSR1 on PantherLake.
+ * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
+ */
+
+ if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||
+ needs_sel_update))
+ return 0;
+ else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||
+ intel_crtc_has_type(crtc_state,
+ INTEL_OUTPUT_EDP)))
+ return 0;
+ else
+ return 1;
+}
+
static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
- bool aux_less)
+ bool aux_less,
+ bool needs_sel_update,
+ bool needs_panel_replay)
{
struct intel_display *display = to_intel_display(intel_dp);
int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
crtc_state->hw.adjusted_mode.crtc_vblank_start;
int wake_lines;
+ int scl = _intel_psr_min_set_context_latency(crtc_state,
+ needs_sel_update,
+ needs_panel_replay);
+ vblank -= scl;
if (aux_less)
wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
@@ -1390,7 +1440,9 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
static bool alpm_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
- bool aux_less)
+ bool aux_less,
+ bool needs_sel_update,
+ bool needs_panel_replay)
{
struct intel_display *display = to_intel_display(intel_dp);
@@ -1400,7 +1452,8 @@ static bool alpm_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less)) {
+ if (!wake_lines_fit_into_vblank(intel_dp, crtc_state, aux_less,
+ needs_sel_update, needs_panel_replay)) {
drm_dbg_kms(display->drm,
"PSR2/Panel Replay not enabled, too short vblank time\n");
return false;
@@ -1492,7 +1545,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return false;
}
- if (!alpm_config_valid(intel_dp, crtc_state, false))
+ if (!alpm_config_valid(intel_dp, crtc_state, false, true, crtc_state->has_panel_replay))
return false;
if (!crtc_state->enable_psr2_sel_fetch &&
@@ -1643,7 +1696,7 @@ _panel_replay_compute_config(struct intel_dp *intel_dp,
return false;
}
- if (!alpm_config_valid(intel_dp, crtc_state, true))
+ if (!alpm_config_valid(intel_dp, crtc_state, true, false, true))
return false;
return true;
@@ -2371,43 +2424,10 @@ void intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
*/
int intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state)
{
- struct intel_display *display = to_intel_display(crtc_state);
-
- if (!crtc_state->has_psr)
- return 0;
-
- /* Wa_14015401596 */
- if (intel_vrr_possible(crtc_state) && IS_DISPLAY_VER(display, 13, 14))
- return 1;
-
- /* Rest is for SRD_STATUS needed on LunarLake and onwards */
- if (DISPLAY_VER(display) < 20)
- return 0;
- /*
- * Comment on SRD_STATUS register in Bspec for LunarLake and onwards:
- *
- * To deterministically capture the transition of the state machine
- * going from SRDOFFACK to IDLE, the delayed V. Blank should be at least
- * one line after the non-delayed V. Blank.
- *
- * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
- * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[ VRR Vmax ]
- * - TRANS_VTOTAL[ Vertical Active ])
- *
- * SRD_STATUS is used only by PSR1 on PantherLake.
- * SRD_STATUS is used by PSR1 and Panel Replay DP on LunarLake.
- */
-
- if (DISPLAY_VER(display) >= 30 && (crtc_state->has_panel_replay ||
- crtc_state->has_sel_update))
- return 0;
- else if (DISPLAY_VER(display) < 30 && (crtc_state->has_sel_update ||
- intel_crtc_has_type(crtc_state,
- INTEL_OUTPUT_EDP)))
- return 0;
- else
- return 1;
+ return _intel_psr_min_set_context_latency(crtc_state,
+ crtc_state->has_panel_replay,
+ crtc_state->has_sel_update);
}
static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
` (3 preceding siblings ...)
2025-10-09 9:00 ` [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency Ankit Nautiyal
@ 2025-10-09 9:00 ` Ankit Nautiyal
2025-10-10 6:53 ` Hogander, Jouni
2025-10-09 9:01 ` [PATCH 6/8] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG Ankit Nautiyal
` (6 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 9:00 UTC (permalink / raw)
To: intel-gfx, intel-xe
Cc: ville.syrjala, Ankit Nautiyal, Animesh Manna, Jouni Högander
Currently, wake line latency checks rely on the vblank length,
which does not account for either the extra vblank delay for icl/tgl or for
the optimized guardband which will come into picture later at some point.
Introduce intel_dp_compute_config_late() to handle late-stage
configuration checks for DP/eDP features. For now, it validates whether the
final vblank (with extra vblank delay) or guardband is sufficient to
support wake line latencies required by Panel Replay and PSR2 selective
update.
Check if vblank is sufficient for PSR features, and disable them if their
wake requirements cannot be accomodated.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++
drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++
drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
drivers/gpu/drm/i915/display/intel_psr.c | 51 ++++++++++++++++++++----
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
5 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c09aa759f4d4..94c593bbedf4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4560,6 +4560,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
struct drm_connector *connector = conn_state->connector;
u8 port_sync_transcoders = 0;
+ if (intel_crtc_has_dp_encoder(crtc_state))
+ intel_dp_compute_config_late(encoder, crtc_state, conn_state);
+
drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
encoder->base.base.id, encoder->base.name,
crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a723e846321f..e481ff4c4959 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6979,3 +6979,12 @@ void intel_dp_mst_resume(struct intel_display *display)
}
}
}
+
+void intel_dp_compute_config_late(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+
+ intel_psr_compute_config_late(intel_dp, crtc_state);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index b379443e0211..0d9573ca44cb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -218,5 +218,8 @@ int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector);
void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external);
bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state);
+void intel_dp_compute_config_late(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state);
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 212bd244beed..dcab4127b399 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1405,6 +1405,20 @@ int _intel_psr_min_set_context_latency(const struct intel_crtc_state *crtc_state
return 1;
}
+static bool _wake_lines_fit_into_vblank(const struct intel_crtc_state *crtc_state,
+ int vblank,
+ int wake_lines)
+{
+ if (crtc_state->req_psr2_sdp_prior_scanline)
+ vblank -= 1;
+
+ /* Vblank >= PSR2_CTL Block Count Number maximum line count */
+ if (vblank < wake_lines)
+ return false;
+
+ return true;
+}
+
static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state,
bool aux_less,
@@ -1428,14 +1442,7 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
crtc_state->alpm_state.fast_wake_lines) :
crtc_state->alpm_state.io_wake_lines;
- if (crtc_state->req_psr2_sdp_prior_scanline)
- vblank -= 1;
-
- /* Vblank >= PSR2_CTL Block Count Number maximum line count */
- if (vblank < wake_lines)
- return false;
-
- return true;
+ return _wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines);
}
static bool alpm_config_valid(struct intel_dp *intel_dp,
@@ -4346,3 +4353,31 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
{
return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
}
+
+void intel_psr_compute_config_late(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(intel_dp);
+ int vblank = intel_crtc_vblank_length(crtc_state);
+ int aux_less_wake_lines = crtc_state->alpm_state.aux_less_wake_lines;
+ int wake_lines = DISPLAY_VER(display) < 20 ?
+ psr2_block_count_lines(crtc_state->alpm_state.io_wake_lines,
+ crtc_state->alpm_state.fast_wake_lines) :
+ crtc_state->alpm_state.io_wake_lines;
+
+ if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
+ !_wake_lines_fit_into_vblank(crtc_state, vblank, aux_less_wake_lines)) {
+ drm_dbg_kms(display->drm,
+ "Disabling Panel replay: vblank insufficient for wakelines = %d\n",
+ aux_less_wake_lines);
+ crtc_state->has_panel_replay = false;
+ }
+
+ if (crtc_state->has_sel_update &&
+ !_wake_lines_fit_into_vblank(crtc_state, vblank, wake_lines)) {
+ drm_dbg_kms(display->drm,
+ "Disabling Selective Update: vblank insufficient for wakelines = %d\n",
+ wake_lines);
+ crtc_state->has_sel_update = false;
+ }
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 9147996d6c9e..b17ce312dc37 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -83,5 +83,7 @@ void intel_psr_debugfs_register(struct intel_display *display);
bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state);
bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+void intel_psr_compute_config_late(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PSR_H__ */
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 6/8] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
` (4 preceding siblings ...)
2025-10-09 9:00 ` [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features Ankit Nautiyal
@ 2025-10-09 9:01 ` Ankit Nautiyal
2025-10-09 9:01 ` [PATCH 7/8] drm/i915/display: Add vblank_start adjustment logic for " Ankit Nautiyal
` (5 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 9:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
Currently, crtc_vblank_start is read from either the VBLANK_START register
(on pre-ADL platforms) or computed as vdisplay + set_context_latency in
intel_get_transcoder_timings().
This works when the entire vblank region after vdisplay is treated as
guardband, i.e.:
delayed vblank start = vdisplay + SCL = vtotal - guardband.
However, with optimized guardband, the guardband becomes shorter, and the
delayed vblank_start moves further away from vdisplay.
For platforms where intel_vrr_always_use_vrr_tg == false, the delayed
vblank start is only relevant in VRR mode. We retain the original
crtc_vblank_start and apply adjustments in VRR-specific paths. Evasion
logic, push clear already use vtotal - guardband directly for VRR case.
On platforms where intel_vrr_always_use_vrr_tg == true, the delayed
vblank_start is used in both fixed and VRR modes. So we need to change the
crtc_vblank_start so that fixed rr case works properly.
Therefore for the readout, we need to overwrite crtc_vblank_start
with vtotal - guardband to ensure correct behavior across both modes.
This change prepares the pipeline for optimized guardband usage by ensuring
crtc_vblank_start reflects the correct timing on platforms with always-on
VRR TG.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 8d71d7dc9d12..221b25832e56 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -821,6 +821,20 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
*/
if (crtc_state->vrr.enable)
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
+
+ /*
+ * For platforms that always use the VRR timing generator, we overwrite
+ * crtc_vblank_start with vtotal - guardband to reflect the delayed
+ * vblank start. This works for both default and optimized guardband values.
+ * On other platforms, we keep the original value from
+ * intel_get_transcoder_timings() and apply adjustments only in VRR-specific
+ * paths as needed.
+ */
+ if (intel_vrr_always_use_vrr_tg(display))
+ crtc_state->hw.adjusted_mode.crtc_vblank_start =
+ crtc_state->hw.adjusted_mode.crtc_vtotal -
+ crtc_state->vrr.guardband;
+
}
int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 7/8] drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
` (5 preceding siblings ...)
2025-10-09 9:01 ` [PATCH 6/8] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG Ankit Nautiyal
@ 2025-10-09 9:01 ` Ankit Nautiyal
2025-10-10 15:05 ` Ville Syrjälä
2025-10-09 9:01 ` [PATCH 8/8] drm/i915/display: Prepare for vblank_delay for LRR Ankit Nautiyal
` (4 subsequent siblings)
11 siblings, 1 reply; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 9:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
As we move towards using a shorter, optimized guardband, we need to adjust
how the delayed vblank start is computed.
Adjust the crtc_vblank_start using Vmin Vtotal - guardband only when
intel_vrr_always_use_vrr_tg() is true.
This also paves way for guardband optimization, by handling the movement of
the crtc_vblank_start for platforms that have VRR TG always active.
v2: Drop the helper and add the adjustment directly to
intel_vrr_compute_guardband(). Ville
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 221b25832e56..5f9b8e5c48be 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -436,7 +436,7 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
- const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+ struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
if (!intel_vrr_possible(crtc_state))
return;
@@ -444,6 +444,10 @@ void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
intel_vrr_max_guardband(crtc_state));
+ if (intel_vrr_always_use_vrr_tg(display))
+ adjusted_mode->crtc_vblank_start =
+ crtc_state->vrr.vmin - crtc_state->vrr.guardband;
+
if (DISPLAY_VER(display) < 13)
crtc_state->vrr.pipeline_full =
intel_vrr_guardband_to_pipeline_full(crtc_state,
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 8/8] drm/i915/display: Prepare for vblank_delay for LRR
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
` (6 preceding siblings ...)
2025-10-09 9:01 ` [PATCH 7/8] drm/i915/display: Add vblank_start adjustment logic for " Ankit Nautiyal
@ 2025-10-09 9:01 ` Ankit Nautiyal
2025-10-09 9:22 ` ✓ CI.KUnit: success for Preparatory patches for guardband optimization (rev2) Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Ankit Nautiyal @ 2025-10-09 9:01 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: ville.syrjala, Ankit Nautiyal
Update allow_vblank_delay_fastset() to permit vblank delay adjustments
during with LRR when VRR TG is always active.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cd499e58bed3..1426218c01d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4958,9 +4958,15 @@ static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_s
* Allow fastboot to fix up vblank delay (handled via LRR
* codepaths), a bit dodgy as the registers aren't
* double buffered but seems to be working more or less...
+ *
+ * Also allow this when the VRR timing generator is always on,
+ * and optimized guardband is used. In such cases,
+ * vblank delay may vary even without inherited state, but it's
+ * still safe as VRR guardband is still same.
*/
- return HAS_LRR(display) && old_crtc_state->inherited &&
- !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
+ return HAS_LRR(display) &&
+ (old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
+ !intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI);
}
bool
--
2.45.2
^ permalink raw reply related [flat|nested] 25+ messages in thread
* ✓ CI.KUnit: success for Preparatory patches for guardband optimization (rev2)
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
` (7 preceding siblings ...)
2025-10-09 9:01 ` [PATCH 8/8] drm/i915/display: Prepare for vblank_delay for LRR Ankit Nautiyal
@ 2025-10-09 9:22 ` Patchwork
2025-10-09 9:37 ` ✗ CI.checksparse: warning " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-10-09 9:22 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: Preparatory patches for guardband optimization (rev2)
URL : https://patchwork.freedesktop.org/series/155662/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[09:21:24] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:21:28] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:21:58] Starting KUnit Kernel (1/1)...
[09:21:58] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:21:58] ================== guc_buf (11 subtests) ===================
[09:21:58] [PASSED] test_smallest
[09:21:58] [PASSED] test_largest
[09:21:58] [PASSED] test_granular
[09:21:58] [PASSED] test_unique
[09:21:58] [PASSED] test_overlap
[09:21:58] [PASSED] test_reusable
[09:21:58] [PASSED] test_too_big
[09:21:58] [PASSED] test_flush
[09:21:58] [PASSED] test_lookup
[09:21:58] [PASSED] test_data
[09:21:58] [PASSED] test_class
[09:21:58] ===================== [PASSED] guc_buf =====================
[09:21:58] =================== guc_dbm (7 subtests) ===================
[09:21:58] [PASSED] test_empty
[09:21:58] [PASSED] test_default
[09:21:58] ======================== test_size ========================
[09:21:58] [PASSED] 4
[09:21:58] [PASSED] 8
[09:21:58] [PASSED] 32
[09:21:58] [PASSED] 256
[09:21:58] ==================== [PASSED] test_size ====================
[09:21:58] ======================= test_reuse ========================
[09:21:58] [PASSED] 4
[09:21:58] [PASSED] 8
[09:21:58] [PASSED] 32
[09:21:58] [PASSED] 256
[09:21:58] =================== [PASSED] test_reuse ====================
[09:21:58] =================== test_range_overlap ====================
[09:21:58] [PASSED] 4
[09:21:58] [PASSED] 8
[09:21:58] [PASSED] 32
[09:21:58] [PASSED] 256
[09:21:58] =============== [PASSED] test_range_overlap ================
[09:21:58] =================== test_range_compact ====================
[09:21:58] [PASSED] 4
[09:21:58] [PASSED] 8
[09:21:58] [PASSED] 32
[09:21:58] [PASSED] 256
[09:21:58] =============== [PASSED] test_range_compact ================
[09:21:58] ==================== test_range_spare =====================
[09:21:58] [PASSED] 4
[09:21:58] [PASSED] 8
[09:21:58] [PASSED] 32
[09:21:58] [PASSED] 256
[09:21:58] ================ [PASSED] test_range_spare =================
[09:21:58] ===================== [PASSED] guc_dbm =====================
[09:21:58] =================== guc_idm (6 subtests) ===================
[09:21:58] [PASSED] bad_init
[09:21:58] [PASSED] no_init
[09:21:58] [PASSED] init_fini
[09:21:58] [PASSED] check_used
[09:21:58] [PASSED] check_quota
[09:21:58] [PASSED] check_all
[09:21:58] ===================== [PASSED] guc_idm =====================
[09:21:58] ================== no_relay (3 subtests) ===================
[09:21:58] [PASSED] xe_drops_guc2pf_if_not_ready
[09:21:58] [PASSED] xe_drops_guc2vf_if_not_ready
[09:21:58] [PASSED] xe_rejects_send_if_not_ready
[09:21:58] ==================== [PASSED] no_relay =====================
[09:21:58] ================== pf_relay (14 subtests) ==================
[09:21:58] [PASSED] pf_rejects_guc2pf_too_short
[09:21:58] [PASSED] pf_rejects_guc2pf_too_long
[09:21:58] [PASSED] pf_rejects_guc2pf_no_payload
[09:21:58] [PASSED] pf_fails_no_payload
[09:21:58] [PASSED] pf_fails_bad_origin
[09:21:58] [PASSED] pf_fails_bad_type
[09:21:58] [PASSED] pf_txn_reports_error
[09:21:58] [PASSED] pf_txn_sends_pf2guc
[09:21:58] [PASSED] pf_sends_pf2guc
[09:21:58] [SKIPPED] pf_loopback_nop
[09:21:58] [SKIPPED] pf_loopback_echo
[09:21:58] [SKIPPED] pf_loopback_fail
[09:21:58] [SKIPPED] pf_loopback_busy
[09:21:58] [SKIPPED] pf_loopback_retry
[09:21:58] ==================== [PASSED] pf_relay =====================
[09:21:58] ================== vf_relay (3 subtests) ===================
[09:21:58] [PASSED] vf_rejects_guc2vf_too_short
[09:21:58] [PASSED] vf_rejects_guc2vf_too_long
[09:21:58] [PASSED] vf_rejects_guc2vf_no_payload
[09:21:58] ==================== [PASSED] vf_relay =====================
[09:21:58] ===================== lmtt (1 subtest) =====================
[09:21:58] ======================== test_ops =========================
[09:21:58] [PASSED] 2-level
[09:21:58] [PASSED] multi-level
[09:21:58] ==================== [PASSED] test_ops =====================
[09:21:58] ====================== [PASSED] lmtt =======================
[09:21:58] ================= pf_service (11 subtests) =================
[09:21:58] [PASSED] pf_negotiate_any
[09:21:58] [PASSED] pf_negotiate_base_match
[09:21:58] [PASSED] pf_negotiate_base_newer
[09:21:58] [PASSED] pf_negotiate_base_next
[09:21:58] [SKIPPED] pf_negotiate_base_older
[09:21:58] [PASSED] pf_negotiate_base_prev
[09:21:58] [PASSED] pf_negotiate_latest_match
[09:21:58] [PASSED] pf_negotiate_latest_newer
[09:21:58] [PASSED] pf_negotiate_latest_next
[09:21:58] [SKIPPED] pf_negotiate_latest_older
[09:21:58] [SKIPPED] pf_negotiate_latest_prev
[09:21:58] =================== [PASSED] pf_service ====================
[09:21:58] ================= xe_guc_g2g (2 subtests) ==================
[09:21:58] ============== xe_live_guc_g2g_kunit_default ==============
[09:21:58] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[09:21:58] ============== xe_live_guc_g2g_kunit_allmem ===============
[09:21:58] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[09:21:58] =================== [SKIPPED] xe_guc_g2g ===================
[09:21:58] =================== xe_mocs (2 subtests) ===================
[09:21:58] ================ xe_live_mocs_kernel_kunit ================
[09:21:58] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[09:21:58] ================ xe_live_mocs_reset_kunit =================
[09:21:58] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[09:21:58] ==================== [SKIPPED] xe_mocs =====================
[09:21:58] ================= xe_migrate (2 subtests) ==================
[09:21:58] ================= xe_migrate_sanity_kunit =================
[09:21:58] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[09:21:58] ================== xe_validate_ccs_kunit ==================
[09:21:58] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[09:21:58] =================== [SKIPPED] xe_migrate ===================
[09:21:58] ================== xe_dma_buf (1 subtest) ==================
[09:21:58] ==================== xe_dma_buf_kunit =====================
[09:21:58] ================ [SKIPPED] xe_dma_buf_kunit ================
[09:21:58] =================== [SKIPPED] xe_dma_buf ===================
[09:21:58] ================= xe_bo_shrink (1 subtest) =================
[09:21:58] =================== xe_bo_shrink_kunit ====================
[09:21:58] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[09:21:58] ================== [SKIPPED] xe_bo_shrink ==================
[09:21:58] ==================== xe_bo (2 subtests) ====================
[09:21:58] ================== xe_ccs_migrate_kunit ===================
[09:21:58] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[09:21:58] ==================== xe_bo_evict_kunit ====================
[09:21:58] =============== [SKIPPED] xe_bo_evict_kunit ================
[09:21:58] ===================== [SKIPPED] xe_bo ======================
[09:21:58] ==================== args (11 subtests) ====================
[09:21:58] [PASSED] count_args_test
[09:21:58] [PASSED] call_args_example
[09:21:58] [PASSED] call_args_test
[09:21:58] [PASSED] drop_first_arg_example
[09:21:58] [PASSED] drop_first_arg_test
[09:21:58] [PASSED] first_arg_example
[09:21:58] [PASSED] first_arg_test
[09:21:58] [PASSED] last_arg_example
[09:21:58] [PASSED] last_arg_test
[09:21:58] [PASSED] pick_arg_example
[09:21:58] [PASSED] sep_comma_example
[09:21:58] ====================== [PASSED] args =======================
[09:21:58] =================== xe_pci (3 subtests) ====================
[09:21:58] ==================== check_graphics_ip ====================
[09:21:58] [PASSED] 12.00 Xe_LP
[09:21:58] [PASSED] 12.10 Xe_LP+
[09:21:58] [PASSED] 12.55 Xe_HPG
[09:21:58] [PASSED] 12.60 Xe_HPC
[09:21:58] [PASSED] 12.70 Xe_LPG
[09:21:58] [PASSED] 12.71 Xe_LPG
[09:21:58] [PASSED] 12.74 Xe_LPG+
[09:21:58] [PASSED] 20.01 Xe2_HPG
[09:21:58] [PASSED] 20.02 Xe2_HPG
[09:21:58] [PASSED] 20.04 Xe2_LPG
[09:21:58] [PASSED] 30.00 Xe3_LPG
[09:21:58] [PASSED] 30.01 Xe3_LPG
[09:21:58] [PASSED] 30.03 Xe3_LPG
[09:21:58] ================ [PASSED] check_graphics_ip ================
[09:21:58] ===================== check_media_ip ======================
[09:21:58] [PASSED] 12.00 Xe_M
[09:21:58] [PASSED] 12.55 Xe_HPM
[09:21:58] [PASSED] 13.00 Xe_LPM+
[09:21:58] [PASSED] 13.01 Xe2_HPM
[09:21:58] [PASSED] 20.00 Xe2_LPM
[09:21:58] [PASSED] 30.00 Xe3_LPM
[09:21:58] [PASSED] 30.02 Xe3_LPM
[09:21:58] ================= [PASSED] check_media_ip ==================
[09:21:58] ================= check_platform_gt_count =================
[09:21:58] [PASSED] 0x9A60 (TIGERLAKE)
[09:21:58] [PASSED] 0x9A68 (TIGERLAKE)
[09:21:58] [PASSED] 0x9A70 (TIGERLAKE)
[09:21:58] [PASSED] 0x9A40 (TIGERLAKE)
[09:21:58] [PASSED] 0x9A49 (TIGERLAKE)
[09:21:58] [PASSED] 0x9A59 (TIGERLAKE)
[09:21:58] [PASSED] 0x9A78 (TIGERLAKE)
[09:21:58] [PASSED] 0x9AC0 (TIGERLAKE)
[09:21:58] [PASSED] 0x9AC9 (TIGERLAKE)
[09:21:58] [PASSED] 0x9AD9 (TIGERLAKE)
[09:21:58] [PASSED] 0x9AF8 (TIGERLAKE)
[09:21:58] [PASSED] 0x4C80 (ROCKETLAKE)
[09:21:58] [PASSED] 0x4C8A (ROCKETLAKE)
[09:21:58] [PASSED] 0x4C8B (ROCKETLAKE)
[09:21:58] [PASSED] 0x4C8C (ROCKETLAKE)
[09:21:58] [PASSED] 0x4C90 (ROCKETLAKE)
[09:21:58] [PASSED] 0x4C9A (ROCKETLAKE)
[09:21:58] [PASSED] 0x4680 (ALDERLAKE_S)
[09:21:58] [PASSED] 0x4682 (ALDERLAKE_S)
[09:21:58] [PASSED] 0x4688 (ALDERLAKE_S)
[09:21:58] [PASSED] 0x468A (ALDERLAKE_S)
[09:21:58] [PASSED] 0x468B (ALDERLAKE_S)
[09:21:58] [PASSED] 0x4690 (ALDERLAKE_S)
[09:21:58] [PASSED] 0x4692 (ALDERLAKE_S)
[09:21:58] [PASSED] 0x4693 (ALDERLAKE_S)
[09:21:58] [PASSED] 0x46A0 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46A1 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46A2 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46A3 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46A6 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46A8 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46AA (ALDERLAKE_P)
[09:21:58] [PASSED] 0x462A (ALDERLAKE_P)
[09:21:58] [PASSED] 0x4626 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x4628 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46B0 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46B1 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46B2 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46B3 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46C0 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46C1 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46C2 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46C3 (ALDERLAKE_P)
[09:21:58] [PASSED] 0x46D0 (ALDERLAKE_N)
[09:21:58] [PASSED] 0x46D1 (ALDERLAKE_N)
[09:21:58] [PASSED] 0x46D2 (ALDERLAKE_N)
[09:21:58] [PASSED] 0x46D3 (ALDERLAKE_N)
[09:21:58] [PASSED] 0x46D4 (ALDERLAKE_N)
[09:21:58] [PASSED] 0xA721 (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA7A1 (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA7A9 (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA7AC (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA7AD (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA720 (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA7A0 (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA7A8 (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA7AA (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA7AB (ALDERLAKE_P)
[09:21:58] [PASSED] 0xA780 (ALDERLAKE_S)
[09:21:58] [PASSED] 0xA781 (ALDERLAKE_S)
[09:21:58] [PASSED] 0xA782 (ALDERLAKE_S)
[09:21:58] [PASSED] 0xA783 (ALDERLAKE_S)
[09:21:58] [PASSED] 0xA788 (ALDERLAKE_S)
[09:21:58] [PASSED] 0xA789 (ALDERLAKE_S)
[09:21:58] [PASSED] 0xA78A (ALDERLAKE_S)
[09:21:58] [PASSED] 0xA78B (ALDERLAKE_S)
[09:21:58] [PASSED] 0x4905 (DG1)
[09:21:58] [PASSED] 0x4906 (DG1)
[09:21:58] [PASSED] 0x4907 (DG1)
[09:21:58] [PASSED] 0x4908 (DG1)
[09:21:58] [PASSED] 0x4909 (DG1)
[09:21:58] [PASSED] 0x56C0 (DG2)
[09:21:58] [PASSED] 0x56C2 (DG2)
[09:21:58] [PASSED] 0x56C1 (DG2)
[09:21:58] [PASSED] 0x7D51 (METEORLAKE)
[09:21:58] [PASSED] 0x7DD1 (METEORLAKE)
[09:21:58] [PASSED] 0x7D41 (METEORLAKE)
[09:21:58] [PASSED] 0x7D67 (METEORLAKE)
[09:21:58] [PASSED] 0xB640 (METEORLAKE)
[09:21:58] [PASSED] 0x56A0 (DG2)
[09:21:58] [PASSED] 0x56A1 (DG2)
[09:21:58] [PASSED] 0x56A2 (DG2)
[09:21:58] [PASSED] 0x56BE (DG2)
[09:21:58] [PASSED] 0x56BF (DG2)
[09:21:58] [PASSED] 0x5690 (DG2)
[09:21:58] [PASSED] 0x5691 (DG2)
[09:21:58] [PASSED] 0x5692 (DG2)
[09:21:58] [PASSED] 0x56A5 (DG2)
[09:21:58] [PASSED] 0x56A6 (DG2)
[09:21:58] [PASSED] 0x56B0 (DG2)
[09:21:58] [PASSED] 0x56B1 (DG2)
[09:21:58] [PASSED] 0x56BA (DG2)
[09:21:58] [PASSED] 0x56BB (DG2)
[09:21:58] [PASSED] 0x56BC (DG2)
[09:21:58] [PASSED] 0x56BD (DG2)
[09:21:58] [PASSED] 0x5693 (DG2)
[09:21:58] [PASSED] 0x5694 (DG2)
[09:21:58] [PASSED] 0x5695 (DG2)
[09:21:58] [PASSED] 0x56A3 (DG2)
[09:21:58] [PASSED] 0x56A4 (DG2)
[09:21:58] [PASSED] 0x56B2 (DG2)
[09:21:58] [PASSED] 0x56B3 (DG2)
[09:21:58] [PASSED] 0x5696 (DG2)
[09:21:58] [PASSED] 0x5697 (DG2)
[09:21:58] [PASSED] 0xB69 (PVC)
[09:21:58] [PASSED] 0xB6E (PVC)
[09:21:58] [PASSED] 0xBD4 (PVC)
[09:21:58] [PASSED] 0xBD5 (PVC)
[09:21:58] [PASSED] 0xBD6 (PVC)
[09:21:58] [PASSED] 0xBD7 (PVC)
[09:21:58] [PASSED] 0xBD8 (PVC)
[09:21:58] [PASSED] 0xBD9 (PVC)
[09:21:58] [PASSED] 0xBDA (PVC)
[09:21:58] [PASSED] 0xBDB (PVC)
[09:21:58] [PASSED] 0xBE0 (PVC)
[09:21:58] [PASSED] 0xBE1 (PVC)
[09:21:58] [PASSED] 0xBE5 (PVC)
[09:21:58] [PASSED] 0x7D40 (METEORLAKE)
[09:21:58] [PASSED] 0x7D45 (METEORLAKE)
[09:21:58] [PASSED] 0x7D55 (METEORLAKE)
[09:21:58] [PASSED] 0x7D60 (METEORLAKE)
[09:21:58] [PASSED] 0x7DD5 (METEORLAKE)
[09:21:58] [PASSED] 0x6420 (LUNARLAKE)
[09:21:58] [PASSED] 0x64A0 (LUNARLAKE)
[09:21:58] [PASSED] 0x64B0 (LUNARLAKE)
[09:21:58] [PASSED] 0xE202 (BATTLEMAGE)
[09:21:58] [PASSED] 0xE209 (BATTLEMAGE)
[09:21:58] [PASSED] 0xE20B (BATTLEMAGE)
[09:21:58] [PASSED] 0xE20C (BATTLEMAGE)
[09:21:58] [PASSED] 0xE20D (BATTLEMAGE)
[09:21:58] [PASSED] 0xE210 (BATTLEMAGE)
[09:21:58] [PASSED] 0xE211 (BATTLEMAGE)
[09:21:58] [PASSED] 0xE212 (BATTLEMAGE)
[09:21:58] [PASSED] 0xE216 (BATTLEMAGE)
[09:21:58] [PASSED] 0xE220 (BATTLEMAGE)
[09:21:58] [PASSED] 0xE221 (BATTLEMAGE)
[09:21:58] [PASSED] 0xE222 (BATTLEMAGE)
[09:21:58] [PASSED] 0xE223 (BATTLEMAGE)
[09:21:58] [PASSED] 0xB080 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB081 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB082 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB083 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB084 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB085 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB086 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB087 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB08F (PANTHERLAKE)
[09:21:58] [PASSED] 0xB090 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB0A0 (PANTHERLAKE)
[09:21:58] [PASSED] 0xB0B0 (PANTHERLAKE)
[09:21:58] [PASSED] 0xFD80 (PANTHERLAKE)
[09:21:58] [PASSED] 0xFD81 (PANTHERLAKE)
[09:21:58] ============= [PASSED] check_platform_gt_count =============
[09:21:58] ===================== [PASSED] xe_pci ======================
[09:21:58] =================== xe_rtp (2 subtests) ====================
[09:21:58] =============== xe_rtp_process_to_sr_tests ================
[09:21:58] [PASSED] coalesce-same-reg
[09:21:58] [PASSED] no-match-no-add
[09:21:58] [PASSED] match-or
[09:21:58] [PASSED] match-or-xfail
[09:21:58] [PASSED] no-match-no-add-multiple-rules
[09:21:58] [PASSED] two-regs-two-entries
[09:21:58] [PASSED] clr-one-set-other
[09:21:58] [PASSED] set-field
[09:21:58] [PASSED] conflict-duplicate
[09:21:58] [PASSED] conflict-not-disjoint
[09:21:58] [PASSED] conflict-reg-type
[09:21:58] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[09:21:58] ================== xe_rtp_process_tests ===================
[09:21:58] [PASSED] active1
[09:21:58] [PASSED] active2
[09:21:58] [PASSED] active-inactive
[09:21:58] [PASSED] inactive-active
[09:21:58] [PASSED] inactive-1st_or_active-inactive
[09:21:58] [PASSED] inactive-2nd_or_active-inactive
[09:21:58] [PASSED] inactive-last_or_active-inactive
[09:21:58] [PASSED] inactive-no_or_active-inactive
[09:21:58] ============== [PASSED] xe_rtp_process_tests ===============
[09:21:58] ===================== [PASSED] xe_rtp ======================
[09:21:58] ==================== xe_wa (1 subtest) =====================
[09:21:58] ======================== xe_wa_gt =========================
[09:21:58] [PASSED] TIGERLAKE B0
[09:21:58] [PASSED] DG1 A0
[09:21:58] [PASSED] DG1 B0
[09:21:58] [PASSED] ALDERLAKE_S A0
[09:21:58] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[09:21:58] [PASSED] ALDERLAKE_S C0
[09:21:58] [PASSED] ALDERLAKE_S D0
[09:21:58] [PASSED] ALDERLAKE_P A0
[09:21:58] [PASSED] ALDERLAKE_P B0
[09:21:58] [PASSED] ALDERLAKE_P C0
[09:21:58] [PASSED] ALDERLAKE_S RPLS D0
[09:21:58] [PASSED] ALDERLAKE_P RPLU E0
[09:21:58] [PASSED] DG2 G10 C0
[09:21:58] [PASSED] DG2 G11 B1
[09:21:58] [PASSED] DG2 G12 A1
[09:21:58] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[09:21:58] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[09:21:58] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[09:21:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[09:21:58] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[09:21:58] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[09:21:58] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[09:21:58] ==================== [PASSED] xe_wa_gt =====================
[09:21:58] ====================== [PASSED] xe_wa ======================
[09:21:58] ============================================================
[09:21:58] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[09:21:58] Elapsed time: 33.879s total, 4.301s configuring, 29.211s building, 0.322s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[09:21:58] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:22:00] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:22:23] Starting KUnit Kernel (1/1)...
[09:22:23] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:22:23] ============ drm_test_pick_cmdline (2 subtests) ============
[09:22:23] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[09:22:23] =============== drm_test_pick_cmdline_named ===============
[09:22:23] [PASSED] NTSC
[09:22:23] [PASSED] NTSC-J
[09:22:23] [PASSED] PAL
[09:22:23] [PASSED] PAL-M
[09:22:23] =========== [PASSED] drm_test_pick_cmdline_named ===========
[09:22:23] ============== [PASSED] drm_test_pick_cmdline ==============
[09:22:23] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[09:22:23] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[09:22:23] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[09:22:23] =========== drm_validate_clone_mode (2 subtests) ===========
[09:22:23] ============== drm_test_check_in_clone_mode ===============
[09:22:23] [PASSED] in_clone_mode
[09:22:23] [PASSED] not_in_clone_mode
[09:22:23] ========== [PASSED] drm_test_check_in_clone_mode ===========
[09:22:23] =============== drm_test_check_valid_clones ===============
[09:22:23] [PASSED] not_in_clone_mode
[09:22:23] [PASSED] valid_clone
[09:22:23] [PASSED] invalid_clone
[09:22:23] =========== [PASSED] drm_test_check_valid_clones ===========
[09:22:23] ============= [PASSED] drm_validate_clone_mode =============
[09:22:23] ============= drm_validate_modeset (1 subtest) =============
[09:22:23] [PASSED] drm_test_check_connector_changed_modeset
[09:22:23] ============== [PASSED] drm_validate_modeset ===============
[09:22:23] ====== drm_test_bridge_get_current_state (2 subtests) ======
[09:22:23] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[09:22:23] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[09:22:23] ======== [PASSED] drm_test_bridge_get_current_state ========
[09:22:23] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[09:22:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[09:22:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[09:22:23] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[09:22:23] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[09:22:23] ============== drm_bridge_alloc (2 subtests) ===============
[09:22:23] [PASSED] drm_test_drm_bridge_alloc_basic
[09:22:23] [PASSED] drm_test_drm_bridge_alloc_get_put
[09:22:23] ================ [PASSED] drm_bridge_alloc =================
[09:22:23] ================== drm_buddy (8 subtests) ==================
[09:22:23] [PASSED] drm_test_buddy_alloc_limit
[09:22:23] [PASSED] drm_test_buddy_alloc_optimistic
[09:22:23] [PASSED] drm_test_buddy_alloc_pessimistic
[09:22:23] [PASSED] drm_test_buddy_alloc_pathological
[09:22:23] [PASSED] drm_test_buddy_alloc_contiguous
[09:22:23] [PASSED] drm_test_buddy_alloc_clear
[09:22:24] [PASSED] drm_test_buddy_alloc_range_bias
[09:22:24] [PASSED] drm_test_buddy_fragmentation_performance
[09:22:24] ==================== [PASSED] drm_buddy ====================
[09:22:24] ============= drm_cmdline_parser (40 subtests) =============
[09:22:24] [PASSED] drm_test_cmdline_force_d_only
[09:22:24] [PASSED] drm_test_cmdline_force_D_only_dvi
[09:22:24] [PASSED] drm_test_cmdline_force_D_only_hdmi
[09:22:24] [PASSED] drm_test_cmdline_force_D_only_not_digital
[09:22:24] [PASSED] drm_test_cmdline_force_e_only
[09:22:24] [PASSED] drm_test_cmdline_res
[09:22:24] [PASSED] drm_test_cmdline_res_vesa
[09:22:24] [PASSED] drm_test_cmdline_res_vesa_rblank
[09:22:24] [PASSED] drm_test_cmdline_res_rblank
[09:22:24] [PASSED] drm_test_cmdline_res_bpp
[09:22:24] [PASSED] drm_test_cmdline_res_refresh
[09:22:24] [PASSED] drm_test_cmdline_res_bpp_refresh
[09:22:24] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[09:22:24] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[09:22:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[09:22:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[09:22:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[09:22:24] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[09:22:24] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[09:22:24] [PASSED] drm_test_cmdline_res_margins_force_on
[09:22:24] [PASSED] drm_test_cmdline_res_vesa_margins
[09:22:24] [PASSED] drm_test_cmdline_name
[09:22:24] [PASSED] drm_test_cmdline_name_bpp
[09:22:24] [PASSED] drm_test_cmdline_name_option
[09:22:24] [PASSED] drm_test_cmdline_name_bpp_option
[09:22:24] [PASSED] drm_test_cmdline_rotate_0
[09:22:24] [PASSED] drm_test_cmdline_rotate_90
[09:22:24] [PASSED] drm_test_cmdline_rotate_180
[09:22:24] [PASSED] drm_test_cmdline_rotate_270
[09:22:24] [PASSED] drm_test_cmdline_hmirror
[09:22:24] [PASSED] drm_test_cmdline_vmirror
[09:22:24] [PASSED] drm_test_cmdline_margin_options
[09:22:24] [PASSED] drm_test_cmdline_multiple_options
[09:22:24] [PASSED] drm_test_cmdline_bpp_extra_and_option
[09:22:24] [PASSED] drm_test_cmdline_extra_and_option
[09:22:24] [PASSED] drm_test_cmdline_freestanding_options
[09:22:24] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[09:22:24] [PASSED] drm_test_cmdline_panel_orientation
[09:22:24] ================ drm_test_cmdline_invalid =================
[09:22:24] [PASSED] margin_only
[09:22:24] [PASSED] interlace_only
[09:22:24] [PASSED] res_missing_x
[09:22:24] [PASSED] res_missing_y
[09:22:24] [PASSED] res_bad_y
[09:22:24] [PASSED] res_missing_y_bpp
[09:22:24] [PASSED] res_bad_bpp
[09:22:24] [PASSED] res_bad_refresh
[09:22:24] [PASSED] res_bpp_refresh_force_on_off
[09:22:24] [PASSED] res_invalid_mode
[09:22:24] [PASSED] res_bpp_wrong_place_mode
[09:22:24] [PASSED] name_bpp_refresh
[09:22:24] [PASSED] name_refresh
[09:22:24] [PASSED] name_refresh_wrong_mode
[09:22:24] [PASSED] name_refresh_invalid_mode
[09:22:24] [PASSED] rotate_multiple
[09:22:24] [PASSED] rotate_invalid_val
[09:22:24] [PASSED] rotate_truncated
[09:22:24] [PASSED] invalid_option
[09:22:24] [PASSED] invalid_tv_option
[09:22:24] [PASSED] truncated_tv_option
[09:22:24] ============ [PASSED] drm_test_cmdline_invalid =============
[09:22:24] =============== drm_test_cmdline_tv_options ===============
[09:22:24] [PASSED] NTSC
[09:22:24] [PASSED] NTSC_443
[09:22:24] [PASSED] NTSC_J
[09:22:24] [PASSED] PAL
[09:22:24] [PASSED] PAL_M
[09:22:24] [PASSED] PAL_N
[09:22:24] [PASSED] SECAM
[09:22:24] [PASSED] MONO_525
[09:22:24] [PASSED] MONO_625
[09:22:24] =========== [PASSED] drm_test_cmdline_tv_options ===========
[09:22:24] =============== [PASSED] drm_cmdline_parser ================
[09:22:24] ========== drmm_connector_hdmi_init (20 subtests) ==========
[09:22:24] [PASSED] drm_test_connector_hdmi_init_valid
[09:22:24] [PASSED] drm_test_connector_hdmi_init_bpc_8
[09:22:24] [PASSED] drm_test_connector_hdmi_init_bpc_10
[09:22:24] [PASSED] drm_test_connector_hdmi_init_bpc_12
[09:22:24] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[09:22:24] [PASSED] drm_test_connector_hdmi_init_bpc_null
[09:22:24] [PASSED] drm_test_connector_hdmi_init_formats_empty
[09:22:24] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[09:22:24] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:22:24] [PASSED] supported_formats=0x9 yuv420_allowed=1
[09:22:24] [PASSED] supported_formats=0x9 yuv420_allowed=0
[09:22:24] [PASSED] supported_formats=0x3 yuv420_allowed=1
[09:22:24] [PASSED] supported_formats=0x3 yuv420_allowed=0
[09:22:24] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[09:22:24] [PASSED] drm_test_connector_hdmi_init_null_ddc
[09:22:24] [PASSED] drm_test_connector_hdmi_init_null_product
[09:22:24] [PASSED] drm_test_connector_hdmi_init_null_vendor
[09:22:24] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[09:22:24] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[09:22:24] [PASSED] drm_test_connector_hdmi_init_product_valid
[09:22:24] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[09:22:24] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[09:22:24] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[09:22:24] ========= drm_test_connector_hdmi_init_type_valid =========
[09:22:24] [PASSED] HDMI-A
[09:22:24] [PASSED] HDMI-B
[09:22:24] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[09:22:24] ======== drm_test_connector_hdmi_init_type_invalid ========
[09:22:24] [PASSED] Unknown
[09:22:24] [PASSED] VGA
[09:22:24] [PASSED] DVI-I
[09:22:24] [PASSED] DVI-D
[09:22:24] [PASSED] DVI-A
[09:22:24] [PASSED] Composite
[09:22:24] [PASSED] SVIDEO
[09:22:24] [PASSED] LVDS
[09:22:24] [PASSED] Component
[09:22:24] [PASSED] DIN
[09:22:24] [PASSED] DP
[09:22:24] [PASSED] TV
[09:22:24] [PASSED] eDP
[09:22:24] [PASSED] Virtual
[09:22:24] [PASSED] DSI
[09:22:24] [PASSED] DPI
[09:22:24] [PASSED] Writeback
[09:22:24] [PASSED] SPI
[09:22:24] [PASSED] USB
[09:22:24] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[09:22:24] ============ [PASSED] drmm_connector_hdmi_init =============
[09:22:24] ============= drmm_connector_init (3 subtests) =============
[09:22:24] [PASSED] drm_test_drmm_connector_init
[09:22:24] [PASSED] drm_test_drmm_connector_init_null_ddc
[09:22:24] ========= drm_test_drmm_connector_init_type_valid =========
[09:22:24] [PASSED] Unknown
[09:22:24] [PASSED] VGA
[09:22:24] [PASSED] DVI-I
[09:22:24] [PASSED] DVI-D
[09:22:24] [PASSED] DVI-A
[09:22:24] [PASSED] Composite
[09:22:24] [PASSED] SVIDEO
[09:22:24] [PASSED] LVDS
[09:22:24] [PASSED] Component
[09:22:24] [PASSED] DIN
[09:22:24] [PASSED] DP
[09:22:24] [PASSED] HDMI-A
[09:22:24] [PASSED] HDMI-B
[09:22:24] [PASSED] TV
[09:22:24] [PASSED] eDP
[09:22:24] [PASSED] Virtual
[09:22:24] [PASSED] DSI
[09:22:24] [PASSED] DPI
[09:22:24] [PASSED] Writeback
[09:22:24] [PASSED] SPI
[09:22:24] [PASSED] USB
[09:22:24] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[09:22:24] =============== [PASSED] drmm_connector_init ===============
[09:22:24] ========= drm_connector_dynamic_init (6 subtests) ==========
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_init
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_init_properties
[09:22:24] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[09:22:24] [PASSED] Unknown
[09:22:24] [PASSED] VGA
[09:22:24] [PASSED] DVI-I
[09:22:24] [PASSED] DVI-D
[09:22:24] [PASSED] DVI-A
[09:22:24] [PASSED] Composite
[09:22:24] [PASSED] SVIDEO
[09:22:24] [PASSED] LVDS
[09:22:24] [PASSED] Component
[09:22:24] [PASSED] DIN
[09:22:24] [PASSED] DP
[09:22:24] [PASSED] HDMI-A
[09:22:24] [PASSED] HDMI-B
[09:22:24] [PASSED] TV
[09:22:24] [PASSED] eDP
[09:22:24] [PASSED] Virtual
[09:22:24] [PASSED] DSI
[09:22:24] [PASSED] DPI
[09:22:24] [PASSED] Writeback
[09:22:24] [PASSED] SPI
[09:22:24] [PASSED] USB
[09:22:24] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[09:22:24] ======== drm_test_drm_connector_dynamic_init_name =========
[09:22:24] [PASSED] Unknown
[09:22:24] [PASSED] VGA
[09:22:24] [PASSED] DVI-I
[09:22:24] [PASSED] DVI-D
[09:22:24] [PASSED] DVI-A
[09:22:24] [PASSED] Composite
[09:22:24] [PASSED] SVIDEO
[09:22:24] [PASSED] LVDS
[09:22:24] [PASSED] Component
[09:22:24] [PASSED] DIN
[09:22:24] [PASSED] DP
[09:22:24] [PASSED] HDMI-A
[09:22:24] [PASSED] HDMI-B
[09:22:24] [PASSED] TV
[09:22:24] [PASSED] eDP
[09:22:24] [PASSED] Virtual
[09:22:24] [PASSED] DSI
[09:22:24] [PASSED] DPI
[09:22:24] [PASSED] Writeback
[09:22:24] [PASSED] SPI
[09:22:24] [PASSED] USB
[09:22:24] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[09:22:24] =========== [PASSED] drm_connector_dynamic_init ============
[09:22:24] ==== drm_connector_dynamic_register_early (4 subtests) =====
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[09:22:24] ====== [PASSED] drm_connector_dynamic_register_early =======
[09:22:24] ======= drm_connector_dynamic_register (7 subtests) ========
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[09:22:24] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[09:22:24] ========= [PASSED] drm_connector_dynamic_register ==========
[09:22:24] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[09:22:24] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[09:22:24] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[09:22:24] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[09:22:24] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[09:22:24] ========== drm_test_get_tv_mode_from_name_valid ===========
[09:22:24] [PASSED] NTSC
[09:22:24] [PASSED] NTSC-443
[09:22:24] [PASSED] NTSC-J
[09:22:24] [PASSED] PAL
[09:22:24] [PASSED] PAL-M
[09:22:24] [PASSED] PAL-N
[09:22:24] [PASSED] SECAM
[09:22:24] [PASSED] Mono
[09:22:24] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[09:22:24] [PASSED] drm_test_get_tv_mode_from_name_truncated
[09:22:24] ============ [PASSED] drm_get_tv_mode_from_name ============
[09:22:24] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[09:22:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[09:22:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[09:22:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[09:22:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[09:22:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[09:22:24] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[09:22:24] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[09:22:24] [PASSED] VIC 96
[09:22:24] [PASSED] VIC 97
[09:22:24] [PASSED] VIC 101
[09:22:24] [PASSED] VIC 102
[09:22:24] [PASSED] VIC 106
[09:22:24] [PASSED] VIC 107
[09:22:24] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[09:22:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[09:22:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[09:22:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[09:22:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[09:22:24] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[09:22:24] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[09:22:24] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[09:22:24] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[09:22:24] [PASSED] Automatic
[09:22:24] [PASSED] Full
[09:22:24] [PASSED] Limited 16:235
[09:22:24] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[09:22:24] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[09:22:24] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[09:22:24] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[09:22:24] === drm_test_drm_hdmi_connector_get_output_format_name ====
[09:22:24] [PASSED] RGB
[09:22:24] [PASSED] YUV 4:2:0
[09:22:24] [PASSED] YUV 4:2:2
[09:22:24] [PASSED] YUV 4:4:4
[09:22:24] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[09:22:24] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[09:22:24] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[09:22:24] ============= drm_damage_helper (21 subtests) ==============
[09:22:24] [PASSED] drm_test_damage_iter_no_damage
[09:22:24] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[09:22:24] [PASSED] drm_test_damage_iter_no_damage_src_moved
[09:22:24] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[09:22:24] [PASSED] drm_test_damage_iter_no_damage_not_visible
[09:22:24] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[09:22:24] [PASSED] drm_test_damage_iter_no_damage_no_fb
[09:22:24] [PASSED] drm_test_damage_iter_simple_damage
[09:22:24] [PASSED] drm_test_damage_iter_single_damage
[09:22:24] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[09:22:24] [PASSED] drm_test_damage_iter_single_damage_outside_src
[09:22:24] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[09:22:24] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[09:22:24] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[09:22:24] [PASSED] drm_test_damage_iter_single_damage_src_moved
[09:22:24] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[09:22:24] [PASSED] drm_test_damage_iter_damage
[09:22:24] [PASSED] drm_test_damage_iter_damage_one_intersect
[09:22:24] [PASSED] drm_test_damage_iter_damage_one_outside
[09:22:24] [PASSED] drm_test_damage_iter_damage_src_moved
[09:22:24] [PASSED] drm_test_damage_iter_damage_not_visible
[09:22:24] ================ [PASSED] drm_damage_helper ================
[09:22:24] ============== drm_dp_mst_helper (3 subtests) ==============
[09:22:24] ============== drm_test_dp_mst_calc_pbn_mode ==============
[09:22:24] [PASSED] Clock 154000 BPP 30 DSC disabled
[09:22:24] [PASSED] Clock 234000 BPP 30 DSC disabled
[09:22:24] [PASSED] Clock 297000 BPP 24 DSC disabled
[09:22:24] [PASSED] Clock 332880 BPP 24 DSC enabled
[09:22:24] [PASSED] Clock 324540 BPP 24 DSC enabled
[09:22:24] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[09:22:24] ============== drm_test_dp_mst_calc_pbn_div ===============
[09:22:24] [PASSED] Link rate 2000000 lane count 4
[09:22:24] [PASSED] Link rate 2000000 lane count 2
[09:22:24] [PASSED] Link rate 2000000 lane count 1
[09:22:24] [PASSED] Link rate 1350000 lane count 4
[09:22:24] [PASSED] Link rate 1350000 lane count 2
[09:22:24] [PASSED] Link rate 1350000 lane count 1
[09:22:24] [PASSED] Link rate 1000000 lane count 4
[09:22:24] [PASSED] Link rate 1000000 lane count 2
[09:22:24] [PASSED] Link rate 1000000 lane count 1
[09:22:24] [PASSED] Link rate 810000 lane count 4
[09:22:24] [PASSED] Link rate 810000 lane count 2
[09:22:24] [PASSED] Link rate 810000 lane count 1
[09:22:24] [PASSED] Link rate 540000 lane count 4
[09:22:24] [PASSED] Link rate 540000 lane count 2
[09:22:24] [PASSED] Link rate 540000 lane count 1
[09:22:24] [PASSED] Link rate 270000 lane count 4
[09:22:24] [PASSED] Link rate 270000 lane count 2
[09:22:24] [PASSED] Link rate 270000 lane count 1
[09:22:24] [PASSED] Link rate 162000 lane count 4
[09:22:24] [PASSED] Link rate 162000 lane count 2
[09:22:24] [PASSED] Link rate 162000 lane count 1
[09:22:24] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[09:22:24] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[09:22:24] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[09:22:24] [PASSED] DP_POWER_UP_PHY with port number
[09:22:24] [PASSED] DP_POWER_DOWN_PHY with port number
[09:22:24] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[09:22:24] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[09:22:24] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[09:22:24] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[09:22:24] [PASSED] DP_QUERY_PAYLOAD with port number
[09:22:24] [PASSED] DP_QUERY_PAYLOAD with VCPI
[09:22:24] [PASSED] DP_REMOTE_DPCD_READ with port number
[09:22:24] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[09:22:24] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[09:22:24] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[09:22:24] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[09:22:24] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[09:22:24] [PASSED] DP_REMOTE_I2C_READ with port number
[09:22:24] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[09:22:24] [PASSED] DP_REMOTE_I2C_READ with transactions array
[09:22:24] [PASSED] DP_REMOTE_I2C_WRITE with port number
[09:22:24] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[09:22:24] [PASSED] DP_REMOTE_I2C_WRITE with data array
[09:22:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[09:22:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[09:22:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[09:22:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[09:22:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[09:22:24] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[09:22:24] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[09:22:24] ================ [PASSED] drm_dp_mst_helper ================
[09:22:24] ================== drm_exec (7 subtests) ===================
[09:22:24] [PASSED] sanitycheck
[09:22:24] [PASSED] test_lock
[09:22:24] [PASSED] test_lock_unlock
[09:22:24] [PASSED] test_duplicates
[09:22:24] [PASSED] test_prepare
[09:22:24] [PASSED] test_prepare_array
[09:22:24] [PASSED] test_multiple_loops
[09:22:24] ==================== [PASSED] drm_exec =====================
[09:22:24] =========== drm_format_helper_test (17 subtests) ===========
[09:22:24] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[09:22:24] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[09:22:24] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[09:22:24] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[09:22:24] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[09:22:24] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[09:22:24] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[09:22:24] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[09:22:24] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[09:22:24] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[09:22:24] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[09:22:24] ============== drm_test_fb_xrgb8888_to_mono ===============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[09:22:24] ==================== drm_test_fb_swab =====================
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ================ [PASSED] drm_test_fb_swab =================
[09:22:24] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[09:22:24] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[09:22:24] [PASSED] single_pixel_source_buffer
[09:22:24] [PASSED] single_pixel_clip_rectangle
[09:22:24] [PASSED] well_known_colors
[09:22:24] [PASSED] destination_pitch
[09:22:24] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[09:22:24] ================= drm_test_fb_clip_offset =================
[09:22:24] [PASSED] pass through
[09:22:24] [PASSED] horizontal offset
[09:22:24] [PASSED] vertical offset
[09:22:24] [PASSED] horizontal and vertical offset
[09:22:24] [PASSED] horizontal offset (custom pitch)
[09:22:24] [PASSED] vertical offset (custom pitch)
[09:22:24] [PASSED] horizontal and vertical offset (custom pitch)
[09:22:24] ============= [PASSED] drm_test_fb_clip_offset =============
[09:22:24] =================== drm_test_fb_memcpy ====================
[09:22:24] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[09:22:24] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[09:22:24] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[09:22:24] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[09:22:24] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[09:22:24] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[09:22:24] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[09:22:24] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[09:22:24] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[09:22:24] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[09:22:24] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[09:22:24] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[09:22:24] =============== [PASSED] drm_test_fb_memcpy ================
[09:22:24] ============= [PASSED] drm_format_helper_test ==============
[09:22:24] ================= drm_format (18 subtests) =================
[09:22:24] [PASSED] drm_test_format_block_width_invalid
[09:22:24] [PASSED] drm_test_format_block_width_one_plane
[09:22:24] [PASSED] drm_test_format_block_width_two_plane
[09:22:24] [PASSED] drm_test_format_block_width_three_plane
[09:22:24] [PASSED] drm_test_format_block_width_tiled
[09:22:24] [PASSED] drm_test_format_block_height_invalid
[09:22:24] [PASSED] drm_test_format_block_height_one_plane
[09:22:24] [PASSED] drm_test_format_block_height_two_plane
[09:22:24] [PASSED] drm_test_format_block_height_three_plane
[09:22:24] [PASSED] drm_test_format_block_height_tiled
[09:22:24] [PASSED] drm_test_format_min_pitch_invalid
[09:22:24] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[09:22:24] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[09:22:24] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[09:22:24] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[09:22:24] [PASSED] drm_test_format_min_pitch_two_plane
[09:22:24] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[09:22:24] [PASSED] drm_test_format_min_pitch_tiled
[09:22:24] =================== [PASSED] drm_format ====================
[09:22:24] ============== drm_framebuffer (10 subtests) ===============
[09:22:24] ========== drm_test_framebuffer_check_src_coords ==========
[09:22:24] [PASSED] Success: source fits into fb
[09:22:24] [PASSED] Fail: overflowing fb with x-axis coordinate
[09:22:24] [PASSED] Fail: overflowing fb with y-axis coordinate
[09:22:24] [PASSED] Fail: overflowing fb with source width
[09:22:24] [PASSED] Fail: overflowing fb with source height
[09:22:24] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[09:22:24] [PASSED] drm_test_framebuffer_cleanup
[09:22:24] =============== drm_test_framebuffer_create ===============
[09:22:24] [PASSED] ABGR8888 normal sizes
[09:22:24] [PASSED] ABGR8888 max sizes
[09:22:24] [PASSED] ABGR8888 pitch greater than min required
[09:22:24] [PASSED] ABGR8888 pitch less than min required
[09:22:24] [PASSED] ABGR8888 Invalid width
[09:22:24] [PASSED] ABGR8888 Invalid buffer handle
[09:22:24] [PASSED] No pixel format
[09:22:24] [PASSED] ABGR8888 Width 0
[09:22:24] [PASSED] ABGR8888 Height 0
[09:22:24] [PASSED] ABGR8888 Out of bound height * pitch combination
[09:22:24] [PASSED] ABGR8888 Large buffer offset
[09:22:24] [PASSED] ABGR8888 Buffer offset for inexistent plane
[09:22:24] [PASSED] ABGR8888 Invalid flag
[09:22:24] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[09:22:24] [PASSED] ABGR8888 Valid buffer modifier
[09:22:24] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[09:22:24] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[09:22:24] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[09:22:24] [PASSED] NV12 Normal sizes
[09:22:24] [PASSED] NV12 Max sizes
[09:22:24] [PASSED] NV12 Invalid pitch
[09:22:24] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[09:22:24] [PASSED] NV12 different modifier per-plane
[09:22:24] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[09:22:24] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[09:22:24] [PASSED] NV12 Modifier for inexistent plane
[09:22:24] [PASSED] NV12 Handle for inexistent plane
[09:22:24] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[09:22:24] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[09:22:24] [PASSED] YVU420 Normal sizes
[09:22:24] [PASSED] YVU420 Max sizes
[09:22:24] [PASSED] YVU420 Invalid pitch
[09:22:24] [PASSED] YVU420 Different pitches
[09:22:24] [PASSED] YVU420 Different buffer offsets/pitches
[09:22:24] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[09:22:24] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[09:22:24] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[09:22:24] [PASSED] YVU420 Valid modifier
[09:22:24] [PASSED] YVU420 Different modifiers per plane
[09:22:24] [PASSED] YVU420 Modifier for inexistent plane
[09:22:24] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[09:22:24] [PASSED] X0L2 Normal sizes
[09:22:24] [PASSED] X0L2 Max sizes
[09:22:24] [PASSED] X0L2 Invalid pitch
[09:22:24] [PASSED] X0L2 Pitch greater than minimum required
[09:22:24] [PASSED] X0L2 Handle for inexistent plane
[09:22:24] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[09:22:24] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[09:22:24] [PASSED] X0L2 Valid modifier
[09:22:24] [PASSED] X0L2 Modifier for inexistent plane
[09:22:24] =========== [PASSED] drm_test_framebuffer_create ===========
[09:22:24] [PASSED] drm_test_framebuffer_free
[09:22:24] [PASSED] drm_test_framebuffer_init
[09:22:24] [PASSED] drm_test_framebuffer_init_bad_format
[09:22:24] [PASSED] drm_test_framebuffer_init_dev_mismatch
[09:22:24] [PASSED] drm_test_framebuffer_lookup
[09:22:24] [PASSED] drm_test_framebuffer_lookup_inexistent
[09:22:24] [PASSED] drm_test_framebuffer_modifiers_not_supported
[09:22:24] ================= [PASSED] drm_framebuffer =================
[09:22:24] ================ drm_gem_shmem (8 subtests) ================
[09:22:24] [PASSED] drm_gem_shmem_test_obj_create
[09:22:24] [PASSED] drm_gem_shmem_test_obj_create_private
[09:22:24] [PASSED] drm_gem_shmem_test_pin_pages
[09:22:24] [PASSED] drm_gem_shmem_test_vmap
[09:22:24] [PASSED] drm_gem_shmem_test_get_pages_sgt
[09:22:24] [PASSED] drm_gem_shmem_test_get_sg_table
[09:22:24] [PASSED] drm_gem_shmem_test_madvise
[09:22:24] [PASSED] drm_gem_shmem_test_purge
[09:22:24] ================== [PASSED] drm_gem_shmem ==================
[09:22:24] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[09:22:24] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[09:22:24] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[09:22:24] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[09:22:24] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[09:22:24] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[09:22:24] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[09:22:24] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[09:22:24] [PASSED] Automatic
[09:22:24] [PASSED] Full
[09:22:24] [PASSED] Limited 16:235
[09:22:24] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[09:22:24] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[09:22:24] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[09:22:24] [PASSED] drm_test_check_disable_connector
[09:22:24] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[09:22:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[09:22:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[09:22:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[09:22:24] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[09:22:24] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[09:22:24] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[09:22:24] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[09:22:24] [PASSED] drm_test_check_output_bpc_dvi
[09:22:24] [PASSED] drm_test_check_output_bpc_format_vic_1
[09:22:24] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[09:22:24] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[09:22:24] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[09:22:24] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[09:22:24] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[09:22:24] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[09:22:24] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[09:22:24] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[09:22:24] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[09:22:24] [PASSED] drm_test_check_broadcast_rgb_value
[09:22:24] [PASSED] drm_test_check_bpc_8_value
[09:22:24] [PASSED] drm_test_check_bpc_10_value
[09:22:24] [PASSED] drm_test_check_bpc_12_value
[09:22:24] [PASSED] drm_test_check_format_value
[09:22:24] [PASSED] drm_test_check_tmds_char_value
[09:22:24] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[09:22:24] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[09:22:24] [PASSED] drm_test_check_mode_valid
[09:22:24] [PASSED] drm_test_check_mode_valid_reject
[09:22:24] [PASSED] drm_test_check_mode_valid_reject_rate
[09:22:24] [PASSED] drm_test_check_mode_valid_reject_max_clock
[09:22:24] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[09:22:24] ================= drm_managed (2 subtests) =================
[09:22:24] [PASSED] drm_test_managed_release_action
[09:22:24] [PASSED] drm_test_managed_run_action
[09:22:24] =================== [PASSED] drm_managed ===================
[09:22:24] =================== drm_mm (6 subtests) ====================
[09:22:24] [PASSED] drm_test_mm_init
[09:22:24] [PASSED] drm_test_mm_debug
[09:22:24] [PASSED] drm_test_mm_align32
[09:22:24] [PASSED] drm_test_mm_align64
[09:22:24] [PASSED] drm_test_mm_lowest
[09:22:24] [PASSED] drm_test_mm_highest
[09:22:24] ===================== [PASSED] drm_mm ======================
[09:22:24] ============= drm_modes_analog_tv (5 subtests) =============
[09:22:24] [PASSED] drm_test_modes_analog_tv_mono_576i
[09:22:24] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[09:22:24] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[09:22:24] [PASSED] drm_test_modes_analog_tv_pal_576i
[09:22:24] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[09:22:24] =============== [PASSED] drm_modes_analog_tv ===============
[09:22:24] ============== drm_plane_helper (2 subtests) ===============
[09:22:24] =============== drm_test_check_plane_state ================
[09:22:24] [PASSED] clipping_simple
[09:22:24] [PASSED] clipping_rotate_reflect
[09:22:24] [PASSED] positioning_simple
[09:22:24] [PASSED] upscaling
[09:22:24] [PASSED] downscaling
[09:22:24] [PASSED] rounding1
[09:22:24] [PASSED] rounding2
[09:22:24] [PASSED] rounding3
[09:22:24] [PASSED] rounding4
[09:22:24] =========== [PASSED] drm_test_check_plane_state ============
[09:22:24] =========== drm_test_check_invalid_plane_state ============
[09:22:24] [PASSED] positioning_invalid
[09:22:24] [PASSED] upscaling_invalid
[09:22:24] [PASSED] downscaling_invalid
[09:22:24] ======= [PASSED] drm_test_check_invalid_plane_state ========
[09:22:24] ================ [PASSED] drm_plane_helper =================
[09:22:24] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[09:22:24] ====== drm_test_connector_helper_tv_get_modes_check =======
[09:22:24] [PASSED] None
[09:22:24] [PASSED] PAL
[09:22:24] [PASSED] NTSC
[09:22:24] [PASSED] Both, NTSC Default
[09:22:24] [PASSED] Both, PAL Default
[09:22:24] [PASSED] Both, NTSC Default, with PAL on command-line
[09:22:24] [PASSED] Both, PAL Default, with NTSC on command-line
[09:22:24] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[09:22:24] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[09:22:24] ================== drm_rect (9 subtests) ===================
[09:22:24] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[09:22:24] [PASSED] drm_test_rect_clip_scaled_not_clipped
[09:22:24] [PASSED] drm_test_rect_clip_scaled_clipped
[09:22:24] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[09:22:24] ================= drm_test_rect_intersect =================
[09:22:24] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[09:22:24] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[09:22:24] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[09:22:24] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[09:22:24] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[09:22:24] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[09:22:24] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[09:22:24] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[09:22:24] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[09:22:24] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[09:22:24] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[09:22:24] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[09:22:24] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[09:22:24] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[09:22:24] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[09:22:24] ============= [PASSED] drm_test_rect_intersect =============
[09:22:24] ================ drm_test_rect_calc_hscale ================
[09:22:24] [PASSED] normal use
[09:22:24] [PASSED] out of max range
[09:22:24] [PASSED] out of min range
[09:22:24] [PASSED] zero dst
[09:22:24] [PASSED] negative src
[09:22:24] [PASSED] negative dst
[09:22:24] ============ [PASSED] drm_test_rect_calc_hscale ============
[09:22:24] ================ drm_test_rect_calc_vscale ================
[09:22:24] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[09:22:24] [PASSED] out of max range
[09:22:24] [PASSED] out of min range
[09:22:24] [PASSED] zero dst
[09:22:24] [PASSED] negative src
[09:22:24] [PASSED] negative dst
[09:22:24] ============ [PASSED] drm_test_rect_calc_vscale ============
[09:22:24] ================== drm_test_rect_rotate ===================
[09:22:24] [PASSED] reflect-x
[09:22:24] [PASSED] reflect-y
[09:22:24] [PASSED] rotate-0
[09:22:24] [PASSED] rotate-90
[09:22:24] [PASSED] rotate-180
[09:22:24] [PASSED] rotate-270
[09:22:24] ============== [PASSED] drm_test_rect_rotate ===============
[09:22:24] ================ drm_test_rect_rotate_inv =================
[09:22:24] [PASSED] reflect-x
[09:22:24] [PASSED] reflect-y
[09:22:24] [PASSED] rotate-0
[09:22:24] [PASSED] rotate-90
[09:22:24] [PASSED] rotate-180
[09:22:24] [PASSED] rotate-270
[09:22:24] ============ [PASSED] drm_test_rect_rotate_inv =============
[09:22:24] ==================== [PASSED] drm_rect =====================
[09:22:24] ============ drm_sysfb_modeset_test (1 subtest) ============
[09:22:24] ============ drm_test_sysfb_build_fourcc_list =============
[09:22:24] [PASSED] no native formats
[09:22:24] [PASSED] XRGB8888 as native format
[09:22:24] [PASSED] remove duplicates
[09:22:24] [PASSED] convert alpha formats
[09:22:24] [PASSED] random formats
[09:22:24] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[09:22:24] ============= [PASSED] drm_sysfb_modeset_test ==============
[09:22:24] ============================================================
[09:22:24] Testing complete. Ran 622 tests: passed: 622
[09:22:24] Elapsed time: 25.713s total, 1.661s configuring, 23.629s building, 0.385s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[09:22:24] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[09:22:26] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[09:22:35] Starting KUnit Kernel (1/1)...
[09:22:35] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[09:22:35] ================= ttm_device (5 subtests) ==================
[09:22:35] [PASSED] ttm_device_init_basic
[09:22:35] [PASSED] ttm_device_init_multiple
[09:22:35] [PASSED] ttm_device_fini_basic
[09:22:35] [PASSED] ttm_device_init_no_vma_man
[09:22:35] ================== ttm_device_init_pools ==================
[09:22:35] [PASSED] No DMA allocations, no DMA32 required
[09:22:35] [PASSED] DMA allocations, DMA32 required
[09:22:35] [PASSED] No DMA allocations, DMA32 required
[09:22:35] [PASSED] DMA allocations, no DMA32 required
[09:22:35] ============== [PASSED] ttm_device_init_pools ==============
[09:22:35] =================== [PASSED] ttm_device ====================
[09:22:35] ================== ttm_pool (8 subtests) ===================
[09:22:35] ================== ttm_pool_alloc_basic ===================
[09:22:35] [PASSED] One page
[09:22:35] [PASSED] More than one page
[09:22:35] [PASSED] Above the allocation limit
[09:22:35] [PASSED] One page, with coherent DMA mappings enabled
[09:22:35] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:22:35] ============== [PASSED] ttm_pool_alloc_basic ===============
[09:22:35] ============== ttm_pool_alloc_basic_dma_addr ==============
[09:22:35] [PASSED] One page
[09:22:35] [PASSED] More than one page
[09:22:35] [PASSED] Above the allocation limit
[09:22:35] [PASSED] One page, with coherent DMA mappings enabled
[09:22:35] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[09:22:35] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[09:22:35] [PASSED] ttm_pool_alloc_order_caching_match
[09:22:35] [PASSED] ttm_pool_alloc_caching_mismatch
[09:22:35] [PASSED] ttm_pool_alloc_order_mismatch
[09:22:35] [PASSED] ttm_pool_free_dma_alloc
[09:22:35] [PASSED] ttm_pool_free_no_dma_alloc
[09:22:35] [PASSED] ttm_pool_fini_basic
[09:22:35] ==================== [PASSED] ttm_pool =====================
[09:22:35] ================ ttm_resource (8 subtests) =================
[09:22:35] ================= ttm_resource_init_basic =================
[09:22:35] [PASSED] Init resource in TTM_PL_SYSTEM
[09:22:35] [PASSED] Init resource in TTM_PL_VRAM
[09:22:35] [PASSED] Init resource in a private placement
[09:22:35] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[09:22:35] ============= [PASSED] ttm_resource_init_basic =============
[09:22:35] [PASSED] ttm_resource_init_pinned
[09:22:35] [PASSED] ttm_resource_fini_basic
[09:22:35] [PASSED] ttm_resource_manager_init_basic
[09:22:35] [PASSED] ttm_resource_manager_usage_basic
[09:22:35] [PASSED] ttm_resource_manager_set_used_basic
[09:22:35] [PASSED] ttm_sys_man_alloc_basic
[09:22:35] [PASSED] ttm_sys_man_free_basic
[09:22:35] ================== [PASSED] ttm_resource ===================
[09:22:35] =================== ttm_tt (15 subtests) ===================
[09:22:35] ==================== ttm_tt_init_basic ====================
[09:22:35] [PASSED] Page-aligned size
[09:22:35] [PASSED] Extra pages requested
[09:22:35] ================ [PASSED] ttm_tt_init_basic ================
[09:22:35] [PASSED] ttm_tt_init_misaligned
[09:22:35] [PASSED] ttm_tt_fini_basic
[09:22:35] [PASSED] ttm_tt_fini_sg
[09:22:35] [PASSED] ttm_tt_fini_shmem
[09:22:35] [PASSED] ttm_tt_create_basic
[09:22:35] [PASSED] ttm_tt_create_invalid_bo_type
[09:22:35] [PASSED] ttm_tt_create_ttm_exists
[09:22:35] [PASSED] ttm_tt_create_failed
[09:22:35] [PASSED] ttm_tt_destroy_basic
[09:22:35] [PASSED] ttm_tt_populate_null_ttm
[09:22:35] [PASSED] ttm_tt_populate_populated_ttm
[09:22:35] [PASSED] ttm_tt_unpopulate_basic
[09:22:35] [PASSED] ttm_tt_unpopulate_empty_ttm
[09:22:35] [PASSED] ttm_tt_swapin_basic
[09:22:35] ===================== [PASSED] ttm_tt ======================
[09:22:35] =================== ttm_bo (14 subtests) ===================
[09:22:35] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[09:22:35] [PASSED] Cannot be interrupted and sleeps
[09:22:35] [PASSED] Cannot be interrupted, locks straight away
[09:22:35] [PASSED] Can be interrupted, sleeps
[09:22:35] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[09:22:35] [PASSED] ttm_bo_reserve_locked_no_sleep
[09:22:35] [PASSED] ttm_bo_reserve_no_wait_ticket
[09:22:35] [PASSED] ttm_bo_reserve_double_resv
[09:22:35] [PASSED] ttm_bo_reserve_interrupted
[09:22:35] [PASSED] ttm_bo_reserve_deadlock
[09:22:35] [PASSED] ttm_bo_unreserve_basic
[09:22:35] [PASSED] ttm_bo_unreserve_pinned
[09:22:35] [PASSED] ttm_bo_unreserve_bulk
[09:22:35] [PASSED] ttm_bo_fini_basic
[09:22:35] [PASSED] ttm_bo_fini_shared_resv
[09:22:35] [PASSED] ttm_bo_pin_basic
[09:22:35] [PASSED] ttm_bo_pin_unpin_resource
[09:22:35] [PASSED] ttm_bo_multiple_pin_one_unpin
[09:22:35] ===================== [PASSED] ttm_bo ======================
[09:22:35] ============== ttm_bo_validate (21 subtests) ===============
[09:22:35] ============== ttm_bo_init_reserved_sys_man ===============
[09:22:35] [PASSED] Buffer object for userspace
[09:22:35] [PASSED] Kernel buffer object
[09:22:35] [PASSED] Shared buffer object
[09:22:35] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[09:22:35] ============== ttm_bo_init_reserved_mock_man ==============
[09:22:35] [PASSED] Buffer object for userspace
[09:22:35] [PASSED] Kernel buffer object
[09:22:35] [PASSED] Shared buffer object
[09:22:35] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[09:22:35] [PASSED] ttm_bo_init_reserved_resv
[09:22:35] ================== ttm_bo_validate_basic ==================
[09:22:35] [PASSED] Buffer object for userspace
[09:22:35] [PASSED] Kernel buffer object
[09:22:35] [PASSED] Shared buffer object
[09:22:35] ============== [PASSED] ttm_bo_validate_basic ==============
[09:22:35] [PASSED] ttm_bo_validate_invalid_placement
[09:22:35] ============= ttm_bo_validate_same_placement ==============
[09:22:35] [PASSED] System manager
[09:22:35] [PASSED] VRAM manager
[09:22:35] ========= [PASSED] ttm_bo_validate_same_placement ==========
[09:22:35] [PASSED] ttm_bo_validate_failed_alloc
[09:22:35] [PASSED] ttm_bo_validate_pinned
[09:22:35] [PASSED] ttm_bo_validate_busy_placement
[09:22:35] ================ ttm_bo_validate_multihop =================
[09:22:35] [PASSED] Buffer object for userspace
[09:22:35] [PASSED] Kernel buffer object
[09:22:35] [PASSED] Shared buffer object
[09:22:35] ============ [PASSED] ttm_bo_validate_multihop =============
[09:22:35] ========== ttm_bo_validate_no_placement_signaled ==========
[09:22:35] [PASSED] Buffer object in system domain, no page vector
[09:22:35] [PASSED] Buffer object in system domain with an existing page vector
[09:22:35] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[09:22:35] ======== ttm_bo_validate_no_placement_not_signaled ========
[09:22:35] [PASSED] Buffer object for userspace
[09:22:35] [PASSED] Kernel buffer object
[09:22:35] [PASSED] Shared buffer object
[09:22:35] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[09:22:35] [PASSED] ttm_bo_validate_move_fence_signaled
[09:22:35] ========= ttm_bo_validate_move_fence_not_signaled =========
[09:22:35] [PASSED] Waits for GPU
[09:22:35] [PASSED] Tries to lock straight away
[09:22:35] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[09:22:35] [PASSED] ttm_bo_validate_happy_evict
[09:22:35] [PASSED] ttm_bo_validate_all_pinned_evict
[09:22:35] [PASSED] ttm_bo_validate_allowed_only_evict
[09:22:35] [PASSED] ttm_bo_validate_deleted_evict
[09:22:35] [PASSED] ttm_bo_validate_busy_domain_evict
[09:22:35] [PASSED] ttm_bo_validate_evict_gutting
[09:22:35] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[09:22:35] ================= [PASSED] ttm_bo_validate =================
[09:22:35] ============================================================
[09:22:35] Testing complete. Ran 101 tests: passed: 101
[09:22:35] Elapsed time: 11.337s total, 1.800s configuring, 9.321s building, 0.185s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✗ CI.checksparse: warning for Preparatory patches for guardband optimization (rev2)
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
` (8 preceding siblings ...)
2025-10-09 9:22 ` ✓ CI.KUnit: success for Preparatory patches for guardband optimization (rev2) Patchwork
@ 2025-10-09 9:37 ` Patchwork
2025-10-09 10:14 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-09 12:42 ` ✓ Xe.CI.Full: " Patchwork
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-10-09 9:37 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
== Series Details ==
Series: Preparatory patches for guardband optimization (rev2)
URL : https://patchwork.freedesktop.org/series/155662/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast e4621fd776939016f32f5585b188429d68e5ae5b
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2042:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2055:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Xe.CI.BAT: success for Preparatory patches for guardband optimization (rev2)
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
` (9 preceding siblings ...)
2025-10-09 9:37 ` ✗ CI.checksparse: warning " Patchwork
@ 2025-10-09 10:14 ` Patchwork
2025-10-09 12:42 ` ✓ Xe.CI.Full: " Patchwork
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-10-09 10:14 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 876 bytes --]
== Series Details ==
Series: Preparatory patches for guardband optimization (rev2)
URL : https://patchwork.freedesktop.org/series/155662/
State : success
== Summary ==
CI Bug Log - changes from xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b_BAT -> xe-pw-155662v2_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Changes
-------
No changes found
Build changes
-------------
* Linux: xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b -> xe-pw-155662v2
IGT_8580: 8580
xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b: e4621fd776939016f32f5585b188429d68e5ae5b
xe-pw-155662v2: 155662v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/index.html
[-- Attachment #2: Type: text/html, Size: 1424 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* ✓ Xe.CI.Full: success for Preparatory patches for guardband optimization (rev2)
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
` (10 preceding siblings ...)
2025-10-09 10:14 ` ✓ Xe.CI.BAT: success " Patchwork
@ 2025-10-09 12:42 ` Patchwork
11 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2025-10-09 12:42 UTC (permalink / raw)
To: Nautiyal, Ankit K; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 46619 bytes --]
== Series Details ==
Series: Preparatory patches for guardband optimization (rev2)
URL : https://patchwork.freedesktop.org/series/155662/
State : success
== Summary ==
CI Bug Log - changes from xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b_FULL -> xe-pw-155662v2_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
New tests
---------
New tests have been introduced between xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b_FULL and xe-pw-155662v2_FULL:
### New IGT tests (1) ###
* igt@kms_chamelium_edid:
- Statuses :
- Exec time: [None] s
Known issues
------------
Here are the changes found in xe-pw-155662v2_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1:
- shard-adlp: [PASS][1] -> [FAIL][2] ([Intel XE#3884])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-8/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-4/igt@kms_async_flips@crc-atomic@pipe-d-hdmi-a-1.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][3] ([Intel XE#2327]) +1 other test skip
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-addfb-size-overflow:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#610])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_big_fb@y-tiled-addfb-size-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-dg2-set2: NOTRUN -> [SKIP][5] ([Intel XE#1124]) +4 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-435/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-bmg: NOTRUN -> [SKIP][6] ([Intel XE#607])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
- shard-dg2-set2: NOTRUN -> [SKIP][7] ([Intel XE#607])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-bmg: NOTRUN -> [SKIP][8] ([Intel XE#1124]) +4 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
- shard-bmg: [PASS][9] -> [SKIP][10] ([Intel XE#2314] / [Intel XE#2894])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html
* igt@kms_bw@linear-tiling-4-displays-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][11] ([Intel XE#367]) +2 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
- shard-dg2-set2: NOTRUN -> [SKIP][12] ([Intel XE#367])
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@kms_bw@linear-tiling-4-displays-2160x1440p.html
* igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][13] ([Intel XE#2907])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-435/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs:
- shard-bmg: NOTRUN -> [SKIP][14] ([Intel XE#2887]) +7 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][15] ([Intel XE#455] / [Intel XE#787]) +15 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-466/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-a-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][16] ([Intel XE#787]) +55 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-466/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-a-dp-4.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#3442])
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#3432])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2:
- shard-bmg: NOTRUN -> [SKIP][19] ([Intel XE#2652] / [Intel XE#787]) +8 other tests skip
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs@pipe-c-dp-2.html
* igt@kms_cdclk@mode-transition:
- shard-bmg: NOTRUN -> [SKIP][20] ([Intel XE#2724])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium_color@ctm-red-to-blue:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#2325])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_chamelium_color@ctm-red-to-blue.html
* igt@kms_chamelium_edid@dp-edid-resolution-list:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2252]) +4 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_chamelium_edid@dp-edid-resolution-list.html
* igt@kms_chamelium_hpd@hdmi-hpd:
- shard-dg2-set2: NOTRUN -> [SKIP][23] ([Intel XE#373]) +5 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-466/igt@kms_chamelium_hpd@hdmi-hpd.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#2390])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-8/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_content_protection@lic-type-1:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2341])
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_content_protection@lic-type-1.html
* igt@kms_cursor_crc@cursor-onscreen-32x32:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#2320]) +3 other tests skip
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@kms_cursor_crc@cursor-onscreen-32x32.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2-set2: NOTRUN -> [SKIP][27] ([Intel XE#308])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-466/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#2321])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-max-size:
- shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#455]) +7 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@kms_cursor_crc@cursor-sliding-max-size.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-bmg: [PASS][30] -> [SKIP][31] ([Intel XE#2291]) +2 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-bmg: [PASS][32] -> [DMESG-WARN][33] ([Intel XE#5354])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#5428])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_dirtyfb@fbc-dirtyfb-ioctl.html
* igt@kms_dsc@dsc-with-bpc:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2244])
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@kms_dsc@dsc-with-bpc.html
* igt@kms_fbcon_fbt@psr:
- shard-bmg: NOTRUN -> [SKIP][36] ([Intel XE#776])
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_fbcon_fbt@psr.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ac-hdmi-a6-dp4:
- shard-dg2-set2: [PASS][37] -> [INCOMPLETE][38] ([Intel XE#2049] / [Intel XE#4842])
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-dg2-435/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ac-hdmi-a6-dp4.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ac-hdmi-a6-dp4.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop:
- shard-bmg: [PASS][39] -> [SKIP][40] ([Intel XE#2316]) +5 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-7/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop.html
* igt@kms_flip@flip-vs-rmfb:
- shard-adlp: [PASS][41] -> [DMESG-WARN][42] ([Intel XE#4543] / [Intel XE#5208])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-6/igt@kms_flip@flip-vs-rmfb.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-8/igt@kms_flip@flip-vs-rmfb.html
* igt@kms_flip@plain-flip-interruptible@d-hdmi-a1:
- shard-adlp: [PASS][43] -> [DMESG-WARN][44] ([Intel XE#4543]) +11 other tests dmesg-warn
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-1/igt@kms_flip@plain-flip-interruptible@d-hdmi-a1.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-1/igt@kms_flip@plain-flip-interruptible@d-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
- shard-bmg: NOTRUN -> [SKIP][45] ([Intel XE#2293] / [Intel XE#2380]) +2 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2293]) +2 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x:
- shard-adlp: [PASS][47] -> [DMESG-FAIL][48] ([Intel XE#4543])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x.html
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-x.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y:
- shard-adlp: [PASS][49] -> [FAIL][50] ([Intel XE#1874])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y.html
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-y.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-bmg: NOTRUN -> [SKIP][51] ([Intel XE#2311]) +19 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@drrs-suspend:
- shard-dg2-set2: NOTRUN -> [SKIP][52] ([Intel XE#651]) +10 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@kms_frontbuffer_tracking@drrs-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-bmg: NOTRUN -> [SKIP][53] ([Intel XE#5427])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt:
- shard-bmg: NOTRUN -> [SKIP][54] ([Intel XE#5390]) +5 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-bmg: NOTRUN -> [SKIP][55] ([Intel XE#2313]) +14 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
- shard-dg2-set2: NOTRUN -> [SKIP][56] ([Intel XE#653]) +15 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-bmg: NOTRUN -> [SKIP][57] ([Intel XE#2352])
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_hdr@static-toggle-suspend:
- shard-bmg: [PASS][58] -> [SKIP][59] ([Intel XE#1503]) +1 other test skip
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-5/igt@kms_hdr@static-toggle-suspend.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html
* igt@kms_joiner@invalid-modeset-force-big-joiner:
- shard-bmg: [PASS][60] -> [SKIP][61] ([Intel XE#3012])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-7/igt@kms_joiner@invalid-modeset-force-big-joiner.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][62] ([Intel XE#2925])
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-466/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_pipe_stress@stress-xrgb8888-ytiled:
- shard-bmg: NOTRUN -> [SKIP][63] ([Intel XE#4329])
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html
* igt@kms_plane_multiple@2x-tiling-x:
- shard-bmg: [PASS][64] -> [SKIP][65] ([Intel XE#4596])
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-5/igt@kms_plane_multiple@2x-tiling-x.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-x.html
* igt@kms_plane_multiple@tiling-yf:
- shard-bmg: NOTRUN -> [SKIP][66] ([Intel XE#5020])
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@kms_plane_multiple@tiling-yf.html
- shard-dg2-set2: NOTRUN -> [SKIP][67] ([Intel XE#5020])
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-bmg: NOTRUN -> [SKIP][68] ([Intel XE#870])
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_rpm@dpms-mode-unset-lpsp:
- shard-bmg: NOTRUN -> [SKIP][69] ([Intel XE#1439] / [Intel XE#836])
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][70] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
- shard-dg2-set2: NOTRUN -> [SKIP][71] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-435/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-bmg: NOTRUN -> [SKIP][72] ([Intel XE#1406] / [Intel XE#2387])
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@fbc-pr-cursor-plane-move:
- shard-dg2-set2: NOTRUN -> [SKIP][73] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +5 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@kms_psr@fbc-pr-cursor-plane-move.html
* igt@kms_psr@psr-primary-page-flip:
- shard-bmg: NOTRUN -> [SKIP][74] ([Intel XE#1406] / [Intel XE#2234] / [Intel XE#2850]) +8 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_psr@psr-primary-page-flip.html
* igt@kms_rotation_crc@bad-tiling:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_setmode@basic-clone-single-crtc:
- shard-bmg: NOTRUN -> [SKIP][76] ([Intel XE#1435])
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@kms_setmode@basic-clone-single-crtc.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-bmg: [PASS][77] -> [SKIP][78] ([Intel XE#1435])
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-dg2-set2: NOTRUN -> [SKIP][79] ([Intel XE#1091] / [Intel XE#2849])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-435/igt@sriov_basic@enable-vfs-autoprobe-off.html
* igt@xe_compute_preempt@compute-preempt:
- shard-dg2-set2: NOTRUN -> [SKIP][80] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-435/igt@xe_compute_preempt@compute-preempt.html
* igt@xe_compute_preempt@compute-preempt-many:
- shard-dg2-set2: NOTRUN -> [FAIL][81] ([Intel XE#5890]) +1 other test fail
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@xe_compute_preempt@compute-preempt-many.html
* igt@xe_eudebug@basic-vm-access-userptr-faultable:
- shard-dg2-set2: NOTRUN -> [SKIP][82] ([Intel XE#4837]) +7 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@xe_eudebug@basic-vm-access-userptr-faultable.html
* igt@xe_eudebug_online@stopped-thread:
- shard-bmg: NOTRUN -> [SKIP][83] ([Intel XE#4837]) +6 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@xe_eudebug_online@stopped-thread.html
* igt@xe_exec_basic@multigpu-once-basic-defer-bind:
- shard-bmg: NOTRUN -> [SKIP][84] ([Intel XE#2322]) +6 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
* igt@xe_exec_fault_mode@once-rebind-prefetch:
- shard-dg2-set2: NOTRUN -> [SKIP][85] ([Intel XE#288]) +8 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-436/igt@xe_exec_fault_mode@once-rebind-prefetch.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-adlp: [PASS][86] -> [DMESG-WARN][87] ([Intel XE#3876])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-4/igt@xe_exec_reset@parallel-gt-reset.html
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-9/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-huge:
- shard-bmg: NOTRUN -> [SKIP][88] ([Intel XE#4943]) +14 other tests skip
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-new-huge.html
* igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-new-race-nomemset:
- shard-dg2-set2: NOTRUN -> [SKIP][89] ([Intel XE#4915]) +100 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-new-race-nomemset.html
* igt@xe_live_ktest@xe_eudebug:
- shard-bmg: NOTRUN -> [SKIP][90] ([Intel XE#2833])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@xe_live_ktest@xe_eudebug.html
* igt@xe_oa@invalid-remove-userspace-config:
- shard-dg2-set2: NOTRUN -> [SKIP][91] ([Intel XE#3573]) +5 other tests skip
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-436/igt@xe_oa@invalid-remove-userspace-config.html
* igt@xe_pm@d3cold-mmap-system:
- shard-bmg: NOTRUN -> [SKIP][92] ([Intel XE#2284]) +2 other tests skip
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@xe_pm@d3cold-mmap-system.html
* igt@xe_pm@d3hot-i2c:
- shard-dg2-set2: NOTRUN -> [SKIP][93] ([Intel XE#5742])
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-436/igt@xe_pm@d3hot-i2c.html
- shard-bmg: NOTRUN -> [SKIP][94] ([Intel XE#5742])
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-3/igt@xe_pm@d3hot-i2c.html
* igt@xe_pm@s2idle-basic:
- shard-adlp: [PASS][95] -> [DMESG-WARN][96] ([Intel XE#2953] / [Intel XE#4173] / [Intel XE#4504])
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-3/igt@xe_pm@s2idle-basic.html
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-3/igt@xe_pm@s2idle-basic.html
* igt@xe_pmu@all-fn-engine-activity-load:
- shard-bmg: [PASS][97] -> [FAIL][98] ([Intel XE#5937])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-1/igt@xe_pmu@all-fn-engine-activity-load.html
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-5/igt@xe_pmu@all-fn-engine-activity-load.html
* igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq:
- shard-bmg: NOTRUN -> [SKIP][99] ([Intel XE#4733]) +2 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-1/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html
- shard-dg2-set2: NOTRUN -> [SKIP][100] ([Intel XE#4733])
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@xe_pxp@pxp-stale-bo-exec-post-termination-irq.html
* igt@xe_query@multigpu-query-mem-usage:
- shard-bmg: NOTRUN -> [SKIP][101] ([Intel XE#944]) +1 other test skip
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-8/igt@xe_query@multigpu-query-mem-usage.html
* igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling:
- shard-dg2-set2: NOTRUN -> [SKIP][102] ([Intel XE#4130])
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-464/igt@xe_sriov_auto_provisioning@resources-released-on-vfs-disabling.html
* igt@xe_sriov_flr@flr-twice:
- shard-bmg: NOTRUN -> [FAIL][103] ([Intel XE#5937])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-8/igt@xe_sriov_flr@flr-twice.html
#### Possible fixes ####
* igt@core_hotunplug@hotunplug-rescan:
- shard-dg2-set2: [INCOMPLETE][104] ([Intel XE#4842]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-dg2-433/igt@core_hotunplug@hotunplug-rescan.html
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-435/igt@core_hotunplug@hotunplug-rescan.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition:
- shard-adlp: [FAIL][106] ([Intel XE#3908]) -> [PASS][107] +1 other test pass
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-3/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-3/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
- shard-dg2-set2: [INCOMPLETE][108] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-dp-4:
- shard-dg2-set2: [INCOMPLETE][110] ([Intel XE#6168]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-dp-4.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-dp-4.html
* igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6:
- shard-dg2-set2: [DMESG-WARN][112] ([Intel XE#1727] / [Intel XE#3113]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6.html
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-466/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-6.html
* igt@kms_cursor_crc@cursor-rapid-movement-64x64:
- shard-adlp: [DMESG-WARN][114] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][115] +2 other tests pass
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-1/igt@kms_cursor_crc@cursor-rapid-movement-64x64.html
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-3/igt@kms_cursor_crc@cursor-rapid-movement-64x64.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-bmg: [SKIP][116] ([Intel XE#2291]) -> [PASS][117] +1 other test pass
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-hdmi-a6-dp4:
- shard-dg2-set2: [INCOMPLETE][118] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][119] +1 other test pass
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-dg2-464/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-hdmi-a6-dp4.html
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-436/igt@kms_flip@2x-flip-vs-suspend-interruptible@bc-hdmi-a6-dp4.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-bmg: [SKIP][120] ([Intel XE#2316]) -> [PASS][121] +2 other tests pass
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-7/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-lnl: [FAIL][122] ([Intel XE#301]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-lnl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-interruptible@b-hdmi-a1:
- shard-adlp: [DMESG-WARN][124] ([Intel XE#4543]) -> [PASS][125] +11 other tests pass
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-1/igt@kms_flip@plain-flip-interruptible@b-hdmi-a1.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-1/igt@kms_flip@plain-flip-interruptible@b-hdmi-a1.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x:
- shard-adlp: [DMESG-FAIL][126] ([Intel XE#4543]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-x.html
* igt@kms_setmode@basic:
- shard-lnl: [FAIL][128] -> [PASS][129] +1 other test pass
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-lnl-2/igt@kms_setmode@basic.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-lnl-2/igt@kms_setmode@basic.html
* igt@xe_ccs@suspend-resume:
- shard-bmg: [INCOMPLETE][130] -> [PASS][131] +1 other test pass
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-3/igt@xe_ccs@suspend-resume.html
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-8/igt@xe_ccs@suspend-resume.html
* igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init:
- shard-dg2-set2: [DMESG-WARN][132] -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-dg2-433/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-435/igt@xe_fault_injection@inject-fault-probe-function-xe_wopcm_init.html
#### Warnings ####
* igt@kms_content_protection@atomic:
- shard-bmg: [FAIL][134] ([Intel XE#1178]) -> [SKIP][135] ([Intel XE#2341])
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-4/igt@kms_content_protection@atomic.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@uevent:
- shard-bmg: [FAIL][136] ([Intel XE#1188]) -> [SKIP][137] ([Intel XE#2341])
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-7/igt@kms_content_protection@uevent.html
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_content_protection@uevent.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move:
- shard-bmg: [SKIP][138] ([Intel XE#2312]) -> [SKIP][139] ([Intel XE#2311]) +3 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-7/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-spr-indfb-move.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt:
- shard-bmg: [SKIP][140] ([Intel XE#5390]) -> [SKIP][141] ([Intel XE#2312]) +6 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][142] ([Intel XE#2312]) -> [SKIP][143] ([Intel XE#5390]) +1 other test skip
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][144] ([Intel XE#2311]) -> [SKIP][145] ([Intel XE#2312]) +10 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-7/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][146] ([Intel XE#2313]) -> [SKIP][147] ([Intel XE#2312]) +11 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-bmg: [SKIP][148] ([Intel XE#2312]) -> [SKIP][149] ([Intel XE#2313]) +6 other tests skip
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_plane_multiple@2x-tiling-y:
- shard-bmg: [SKIP][150] ([Intel XE#5021]) -> [SKIP][151] ([Intel XE#4596])
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-7/igt@kms_plane_multiple@2x-tiling-y.html
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-y.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [FAIL][152] ([Intel XE#1729]) -> [SKIP][153] ([Intel XE#2426])
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern.html
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-2/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][154] ([Intel XE#2509]) -> [SKIP][155] ([Intel XE#2426])
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
- shard-dg2-set2: [ABORT][156] ([Intel XE#5466]) -> [ABORT][157] ([Intel XE#4917] / [Intel XE#5466])
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b/shard-dg2-464/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/shard-dg2-466/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#1091]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1091
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
[Intel XE#1188]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1188
[Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
[Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
[Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
[Intel XE#2293]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2293
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
[Intel XE#2320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2320
[Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2325]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2325
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2352]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2352
[Intel XE#2380]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2380
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
[Intel XE#2724]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2724
[Intel XE#2833]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2833
[Intel XE#2849]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2849
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2925]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2925
[Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
[Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
[Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
[Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
[Intel XE#3432]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3432
[Intel XE#3442]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3442
[Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
[Intel XE#3884]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3884
[Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
[Intel XE#3908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3908
[Intel XE#4130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4130
[Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
[Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
[Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
[Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
[Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
[Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
[Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
[Intel XE#4842]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4842
[Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
[Intel XE#4917]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4917
[Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
[Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
[Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
[Intel XE#5208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5208
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
[Intel XE#5427]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5427
[Intel XE#5428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5428
[Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
[Intel XE#5624]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5624
[Intel XE#5742]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5742
[Intel XE#5890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5890
[Intel XE#5937]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5937
[Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
[Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
[Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
[Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
[Intel XE#6313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6313
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#776]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/776
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
[Intel XE#870]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/870
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
Build changes
-------------
* Linux: xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b -> xe-pw-155662v2
IGT_8580: 8580
xe-3888-e4621fd776939016f32f5585b188429d68e5ae5b: e4621fd776939016f32f5585b188429d68e5ae5b
xe-pw-155662v2: 155662v2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155662v2/index.html
[-- Attachment #2: Type: text/html, Size: 52705 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency
2025-10-09 9:00 ` [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency Ankit Nautiyal
@ 2025-10-10 6:40 ` Hogander, Jouni
2025-10-10 13:01 ` Nautiyal, Ankit K
0 siblings, 1 reply; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-10 6:40 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, Manna, Animesh
On Thu, 2025-10-09 at 14:30 +0530, Ankit Nautiyal wrote:
> Panel Replay and PSR2 selective update require sufficient vblank
> duration
> to accommodate wake latencies. However, the current
> wake_lines_fit_into_vblank() logic does not account for the minimum
> Set Context Latency (SCL) lines.
>
> Separate out _intel_psr_min_set_context_latency() to compute the
> minimum
> SCL requirement based on platform and feature usage.
>
> The alpm_config_valid() helper is updated to pass the necessary
> context for
> determining whether Panel Replay or PSR2 selective update is enabled.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 102 ++++++++++++++-------
> --
> 1 file changed, 61 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2131473cead6..212bd244beed 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1361,14 +1361,64 @@ static int
> intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
> return entry_setup_frames;
> }
>
> +static
> +int _intel_psr_min_set_context_latency(const struct intel_crtc_state
> *crtc_state,
> + bool needs_panel_replay,
> + bool needs_sel_update)
> +{
> + struct intel_display *display =
> to_intel_display(crtc_state);
> +
> + if (!crtc_state->has_psr)
> + return 0;
> +
> + /* Wa_14015401596 */
> + if (intel_vrr_possible(crtc_state) &&
> IS_DISPLAY_VER(display, 13, 14))
> + return 1;
> +
> + /* Rest is for SRD_STATUS needed on LunarLake and onwards */
> + if (DISPLAY_VER(display) < 20)
> + return 0;
> +
> + /*
> + * Comment on SRD_STATUS register in Bspec for LunarLake and
> onwards:
> + *
> + * To deterministically capture the transition of the state
> machine
> + * going from SRDOFFACK to IDLE, the delayed V. Blank should
> be at least
> + * one line after the non-delayed V. Blank.
> + *
> + * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
> + * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[
> VRR Vmax ]
> + * - TRANS_VTOTAL[ Vertical Active ])
> + *
> + * SRD_STATUS is used only by PSR1 on PantherLake.
> + * SRD_STATUS is used by PSR1 and Panel Replay DP on
> LunarLake.
> + */
> +
> + if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||
> + needs_sel_update))
> + return 0;
> + else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||
> +
> intel_crtc_has_type(crtc_state,
> +
> INTEL_OUTPUT_EDP)))
> + return 0;
> + else
> + return 1;
> +}
> +
> static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
> const struct intel_crtc_state
> *crtc_state,
> - bool aux_less)
> + bool aux_less,
> + bool needs_sel_update,
> + bool needs_panel_replay)
> {
> struct intel_display *display = to_intel_display(intel_dp);
> int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
> crtc_state->hw.adjusted_mode.crtc_vblank_start;
> int wake_lines;
> + int scl = _intel_psr_min_set_context_latency(crtc_state,
> +
> needs_sel_update,
> +
> needs_panel_replay);
Why can't you use crtc_state->set_context_latency?
> + vblank -= scl;
>
> if (aux_less)
> wake_lines = crtc_state-
> >alpm_state.aux_less_wake_lines;
> @@ -1390,7 +1440,9 @@ static bool wake_lines_fit_into_vblank(struct
> intel_dp *intel_dp,
>
> static bool alpm_config_valid(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> - bool aux_less)
> + bool aux_less,
> + bool needs_sel_update,
> + bool needs_panel_replay)
> {
> struct intel_display *display = to_intel_display(intel_dp);
>
> @@ -1400,7 +1452,8 @@ static bool alpm_config_valid(struct intel_dp
> *intel_dp,
> return false;
> }
>
> - if (!wake_lines_fit_into_vblank(intel_dp, crtc_state,
> aux_less)) {
> + if (!wake_lines_fit_into_vblank(intel_dp, crtc_state,
> aux_less,
> + needs_sel_update,
> needs_panel_replay)) {
> drm_dbg_kms(display->drm,
> "PSR2/Panel Replay not enabled, too
> short vblank time\n");
> return false;
> @@ -1492,7 +1545,7 @@ static bool intel_psr2_config_valid(struct
> intel_dp *intel_dp,
> return false;
> }
>
> - if (!alpm_config_valid(intel_dp, crtc_state, false))
> + if (!alpm_config_valid(intel_dp, crtc_state, false, true,
> crtc_state->has_panel_replay))
This is a bit misleading. Someone might think intel_psr2_config_valid
could be called with crtc_state->has_panel_replay == 1. Rather use
false here.
BR,
Jouni Högander
> return false;
>
> if (!crtc_state->enable_psr2_sel_fetch &&
> @@ -1643,7 +1696,7 @@ _panel_replay_compute_config(struct intel_dp
> *intel_dp,
> return false;
> }
>
> - if (!alpm_config_valid(intel_dp, crtc_state, true))
> + if (!alpm_config_valid(intel_dp, crtc_state, true, false,
> true))
> return false;
>
> return true;
> @@ -2371,43 +2424,10 @@ void
> intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
> */
> int intel_psr_min_set_context_latency(const struct intel_crtc_state
> *crtc_state)
> {
> - struct intel_display *display =
> to_intel_display(crtc_state);
> -
> - if (!crtc_state->has_psr)
> - return 0;
> -
> - /* Wa_14015401596 */
> - if (intel_vrr_possible(crtc_state) &&
> IS_DISPLAY_VER(display, 13, 14))
> - return 1;
> -
> - /* Rest is for SRD_STATUS needed on LunarLake and onwards */
> - if (DISPLAY_VER(display) < 20)
> - return 0;
>
> - /*
> - * Comment on SRD_STATUS register in Bspec for LunarLake and
> onwards:
> - *
> - * To deterministically capture the transition of the state
> machine
> - * going from SRDOFFACK to IDLE, the delayed V. Blank should
> be at least
> - * one line after the non-delayed V. Blank.
> - *
> - * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
> - * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[
> VRR Vmax ]
> - * - TRANS_VTOTAL[ Vertical Active ])
> - *
> - * SRD_STATUS is used only by PSR1 on PantherLake.
> - * SRD_STATUS is used by PSR1 and Panel Replay DP on
> LunarLake.
> - */
> -
> - if (DISPLAY_VER(display) >= 30 && (crtc_state-
> >has_panel_replay ||
> - crtc_state-
> >has_sel_update))
> - return 0;
> - else if (DISPLAY_VER(display) < 30 && (crtc_state-
> >has_sel_update ||
> -
> intel_crtc_has_type(crtc_state,
> -
> INTEL_OUTPUT_EDP)))
> - return 0;
> - else
> - return 1;
> + return _intel_psr_min_set_context_latency(crtc_state,
> + crtc_state-
> >has_panel_replay,
> + crtc_state-
> >has_sel_update);
> }
>
> static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features
2025-10-09 9:00 ` [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features Ankit Nautiyal
@ 2025-10-10 6:53 ` Hogander, Jouni
2025-10-10 13:42 ` Nautiyal, Ankit K
0 siblings, 1 reply; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-10 6:53 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, Manna, Animesh
On Thu, 2025-10-09 at 14:30 +0530, Ankit Nautiyal wrote:
> Currently, wake line latency checks rely on the vblank length,
> which does not account for either the extra vblank delay for icl/tgl
> or for
> the optimized guardband which will come into picture later at some
> point.
>
> Introduce intel_dp_compute_config_late() to handle late-stage
> configuration checks for DP/eDP features. For now, it validates
> whether the
> final vblank (with extra vblank delay) or guardband is sufficient to
> support wake line latencies required by Panel Replay and PSR2
> selective
> update.
>
> Check if vblank is sufficient for PSR features, and disable them if
> their
> wake requirements cannot be accomodated.
Now as we are adding this: Can't we just drop checks made earlier and
rely on psr_compute_config_late checking the vblank?
BR,
Jouni Högander
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> drivers/gpu/drm/i915/display/intel_psr.c | 51 ++++++++++++++++++++--
> --
> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> 5 files changed, 60 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c09aa759f4d4..94c593bbedf4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4560,6 +4560,9 @@ static int intel_ddi_compute_config_late(struct
> intel_encoder *encoder,
> struct drm_connector *connector = conn_state->connector;
> u8 port_sync_transcoders = 0;
>
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_compute_config_late(encoder, crtc_state,
> conn_state);
> +
> drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
> encoder->base.base.id, encoder->base.name,
> crtc_state->uapi.crtc->base.id, crtc_state-
> >uapi.crtc->name);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index a723e846321f..e481ff4c4959 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6979,3 +6979,12 @@ void intel_dp_mst_resume(struct intel_display
> *display)
> }
> }
> }
> +
> +void intel_dp_compute_config_late(struct intel_encoder *encoder,
> + struct intel_crtc_state
> *crtc_state,
> + struct drm_connector_state
> *conn_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_psr_compute_config_late(intel_dp, crtc_state);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index b379443e0211..0d9573ca44cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -218,5 +218,8 @@ int intel_dp_compute_min_hblank(struct
> intel_crtc_state *crtc_state,
> int intel_dp_dsc_bpp_step_x16(const struct intel_connector
> *connector);
> void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool
> force_on_external);
> bool intel_dp_in_hdr_mode(const struct drm_connector_state
> *conn_state);
> +void intel_dp_compute_config_late(struct intel_encoder *encoder,
> + struct intel_crtc_state
> *crtc_state,
> + struct drm_connector_state
> *conn_state);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 212bd244beed..dcab4127b399 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1405,6 +1405,20 @@ int _intel_psr_min_set_context_latency(const
> struct intel_crtc_state *crtc_state
> return 1;
> }
>
> +static bool _wake_lines_fit_into_vblank(const struct
> intel_crtc_state *crtc_state,
> + int vblank,
> + int wake_lines)
> +{
> + if (crtc_state->req_psr2_sdp_prior_scanline)
> + vblank -= 1;
> +
> + /* Vblank >= PSR2_CTL Block Count Number maximum line count
> */
> + if (vblank < wake_lines)
> + return false;
> +
> + return true;
> +}
> +
> static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
> const struct intel_crtc_state
> *crtc_state,
> bool aux_less,
> @@ -1428,14 +1442,7 @@ static bool wake_lines_fit_into_vblank(struct
> intel_dp *intel_dp,
> crtc_state-
> >alpm_state.fast_wake_lines) :
> crtc_state->alpm_state.io_wake_lines;
>
> - if (crtc_state->req_psr2_sdp_prior_scanline)
> - vblank -= 1;
> -
> - /* Vblank >= PSR2_CTL Block Count Number maximum line count
> */
> - if (vblank < wake_lines)
> - return false;
> -
> - return true;
> + return _wake_lines_fit_into_vblank(crtc_state, vblank,
> wake_lines);
> }
>
> static bool alpm_config_valid(struct intel_dp *intel_dp,
> @@ -4346,3 +4353,31 @@ bool intel_psr_needs_alpm_aux_less(struct
> intel_dp *intel_dp,
> {
> return intel_dp_is_edp(intel_dp) && crtc_state-
> >has_panel_replay;
> }
> +
> +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> + struct intel_crtc_state
> *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(intel_dp);
> + int vblank = intel_crtc_vblank_length(crtc_state);
> + int aux_less_wake_lines = crtc_state-
> >alpm_state.aux_less_wake_lines;
> + int wake_lines = DISPLAY_VER(display) < 20 ?
> + psr2_block_count_lines(crtc_state-
> >alpm_state.io_wake_lines,
> + crtc_state-
> >alpm_state.fast_wake_lines) :
> + crtc_state->alpm_state.io_wake_lines;
> +
> + if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
> + !_wake_lines_fit_into_vblank(crtc_state, vblank,
> aux_less_wake_lines)) {
> + drm_dbg_kms(display->drm,
> + "Disabling Panel replay: vblank
> insufficient for wakelines = %d\n",
> + aux_less_wake_lines);
> + crtc_state->has_panel_replay = false;
> + }
> +
> + if (crtc_state->has_sel_update &&
> + !_wake_lines_fit_into_vblank(crtc_state, vblank,
> wake_lines)) {
> + drm_dbg_kms(display->drm,
> + "Disabling Selective Update: vblank
> insufficient for wakelines = %d\n",
> + wake_lines);
> + crtc_state->has_sel_update = false;
> + }
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 9147996d6c9e..b17ce312dc37 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -83,5 +83,7 @@ void intel_psr_debugfs_register(struct
> intel_display *display);
> bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct
> intel_crtc_state *crtc_state);
> bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
> const struct intel_crtc_state
> *crtc_state);
> +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> + struct intel_crtc_state
> *crtc_state);
>
> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency
2025-10-10 6:40 ` Hogander, Jouni
@ 2025-10-10 13:01 ` Nautiyal, Ankit K
0 siblings, 0 replies; 25+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-10 13:01 UTC (permalink / raw)
To: Hogander, Jouni, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, Manna, Animesh
On 10/10/2025 12:10 PM, Hogander, Jouni wrote:
> On Thu, 2025-10-09 at 14:30 +0530, Ankit Nautiyal wrote:
>> Panel Replay and PSR2 selective update require sufficient vblank
>> duration
>> to accommodate wake latencies. However, the current
>> wake_lines_fit_into_vblank() logic does not account for the minimum
>> Set Context Latency (SCL) lines.
>>
>> Separate out _intel_psr_min_set_context_latency() to compute the
>> minimum
>> SCL requirement based on platform and feature usage.
>>
>> The alpm_config_valid() helper is updated to pass the necessary
>> context for
>> determining whether Panel Replay or PSR2 selective update is enabled.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Cc: Animesh Manna <animesh.manna@intel.com>
>> Cc: Jouni Högander <jouni.hogander@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_psr.c | 102 ++++++++++++++-------
>> --
>> 1 file changed, 61 insertions(+), 41 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 2131473cead6..212bd244beed 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -1361,14 +1361,64 @@ static int
>> intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
>> return entry_setup_frames;
>> }
>>
>> +static
>> +int _intel_psr_min_set_context_latency(const struct intel_crtc_state
>> *crtc_state,
>> + bool needs_panel_replay,
>> + bool needs_sel_update)
>> +{
>> + struct intel_display *display =
>> to_intel_display(crtc_state);
>> +
>> + if (!crtc_state->has_psr)
>> + return 0;
>> +
>> + /* Wa_14015401596 */
>> + if (intel_vrr_possible(crtc_state) &&
>> IS_DISPLAY_VER(display, 13, 14))
>> + return 1;
>> +
>> + /* Rest is for SRD_STATUS needed on LunarLake and onwards */
>> + if (DISPLAY_VER(display) < 20)
>> + return 0;
>> +
>> + /*
>> + * Comment on SRD_STATUS register in Bspec for LunarLake and
>> onwards:
>> + *
>> + * To deterministically capture the transition of the state
>> machine
>> + * going from SRDOFFACK to IDLE, the delayed V. Blank should
>> be at least
>> + * one line after the non-delayed V. Blank.
>> + *
>> + * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
>> + * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[
>> VRR Vmax ]
>> + * - TRANS_VTOTAL[ Vertical Active ])
>> + *
>> + * SRD_STATUS is used only by PSR1 on PantherLake.
>> + * SRD_STATUS is used by PSR1 and Panel Replay DP on
>> LunarLake.
>> + */
>> +
>> + if (DISPLAY_VER(display) >= 30 && (needs_panel_replay ||
>> + needs_sel_update))
>> + return 0;
>> + else if (DISPLAY_VER(display) < 30 && (needs_sel_update ||
>> +
>> intel_crtc_has_type(crtc_state,
>> +
>> INTEL_OUTPUT_EDP)))
>> + return 0;
>> + else
>> + return 1;
>> +}
>> +
>> static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
>> const struct intel_crtc_state
>> *crtc_state,
>> - bool aux_less)
>> + bool aux_less,
>> + bool needs_sel_update,
>> + bool needs_panel_replay)
>> {
>> struct intel_display *display = to_intel_display(intel_dp);
>> int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
>> crtc_state->hw.adjusted_mode.crtc_vblank_start;
>> int wake_lines;
>> + int scl = _intel_psr_min_set_context_latency(crtc_state,
>> +
>> needs_sel_update,
>> +
>> needs_panel_replay);
> Why can't you use crtc_state->set_context_latency?
This check wake_lines_fit_into_vblank() is called during
encoder->compute_config() path (specifically in psr_compute_config()).
At this point of time set_context_latency is not computed. It is
computed later in intel_crtc_compute_config().
There is some more discussion about it in :
https://lore.kernel.org/all/aOVOJp2zeN1eCp7O@intel.com/
Perhaps I should have mentioned this in cover-letter.
>
>> + vblank -= scl;
>>
>> if (aux_less)
>> wake_lines = crtc_state-
>>> alpm_state.aux_less_wake_lines;
>> @@ -1390,7 +1440,9 @@ static bool wake_lines_fit_into_vblank(struct
>> intel_dp *intel_dp,
>>
>> static bool alpm_config_valid(struct intel_dp *intel_dp,
>> struct intel_crtc_state *crtc_state,
>> - bool aux_less)
>> + bool aux_less,
>> + bool needs_sel_update,
>> + bool needs_panel_replay)
>> {
>> struct intel_display *display = to_intel_display(intel_dp);
>>
>> @@ -1400,7 +1452,8 @@ static bool alpm_config_valid(struct intel_dp
>> *intel_dp,
>> return false;
>> }
>>
>> - if (!wake_lines_fit_into_vblank(intel_dp, crtc_state,
>> aux_less)) {
>> + if (!wake_lines_fit_into_vblank(intel_dp, crtc_state,
>> aux_less,
>> + needs_sel_update,
>> needs_panel_replay)) {
>> drm_dbg_kms(display->drm,
>> "PSR2/Panel Replay not enabled, too
>> short vblank time\n");
>> return false;
>> @@ -1492,7 +1545,7 @@ static bool intel_psr2_config_valid(struct
>> intel_dp *intel_dp,
>> return false;
>> }
>>
>> - if (!alpm_config_valid(intel_dp, crtc_state, false))
>> + if (!alpm_config_valid(intel_dp, crtc_state, false, true,
>> crtc_state->has_panel_replay))
> This is a bit misleading. Someone might think intel_psr2_config_valid
> could be called with crtc_state->has_panel_replay == 1. Rather use
> false here.
Hmm makes sense we are checking for psr2_config_valid() only when
crtc_state->has_panel_replay is false.
Thanks for pointing this out, will fix this.
Regards,
Ankit
>
> BR,
>
> Jouni Högander
>
>> return false;
>>
>> if (!crtc_state->enable_psr2_sel_fetch &&
>> @@ -1643,7 +1696,7 @@ _panel_replay_compute_config(struct intel_dp
>> *intel_dp,
>> return false;
>> }
>>
>> - if (!alpm_config_valid(intel_dp, crtc_state, true))
>> + if (!alpm_config_valid(intel_dp, crtc_state, true, false,
>> true))
>> return false;
>>
>> return true;
>> @@ -2371,43 +2424,10 @@ void
>> intel_psr_trigger_frame_change_event(struct intel_dsb *dsb,
>> */
>> int intel_psr_min_set_context_latency(const struct intel_crtc_state
>> *crtc_state)
>> {
>> - struct intel_display *display =
>> to_intel_display(crtc_state);
>> -
>> - if (!crtc_state->has_psr)
>> - return 0;
>> -
>> - /* Wa_14015401596 */
>> - if (intel_vrr_possible(crtc_state) &&
>> IS_DISPLAY_VER(display, 13, 14))
>> - return 1;
>> -
>> - /* Rest is for SRD_STATUS needed on LunarLake and onwards */
>> - if (DISPLAY_VER(display) < 20)
>> - return 0;
>>
>> - /*
>> - * Comment on SRD_STATUS register in Bspec for LunarLake and
>> onwards:
>> - *
>> - * To deterministically capture the transition of the state
>> machine
>> - * going from SRDOFFACK to IDLE, the delayed V. Blank should
>> be at least
>> - * one line after the non-delayed V. Blank.
>> - *
>> - * Legacy TG: TRANS_SET_CONTEXT_LATENCY > 0
>> - * VRR TG: TRANS_VRR_CTL[ VRR Guardband ] < (TRANS_VRR_VMAX[
>> VRR Vmax ]
>> - * - TRANS_VTOTAL[ Vertical Active ])
>> - *
>> - * SRD_STATUS is used only by PSR1 on PantherLake.
>> - * SRD_STATUS is used by PSR1 and Panel Replay DP on
>> LunarLake.
>> - */
>> -
>> - if (DISPLAY_VER(display) >= 30 && (crtc_state-
>>> has_panel_replay ||
>> - crtc_state-
>>> has_sel_update))
>> - return 0;
>> - else if (DISPLAY_VER(display) < 30 && (crtc_state-
>>> has_sel_update ||
>> -
>> intel_crtc_has_type(crtc_state,
>> -
>> INTEL_OUTPUT_EDP)))
>> - return 0;
>> - else
>> - return 1;
>> + return _intel_psr_min_set_context_latency(crtc_state,
>> + crtc_state-
>>> has_panel_replay,
>> + crtc_state-
>>> has_sel_update);
>> }
>>
>> static u32 man_trk_ctl_enable_bit_get(struct intel_display *display)
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features
2025-10-10 6:53 ` Hogander, Jouni
@ 2025-10-10 13:42 ` Nautiyal, Ankit K
2025-10-13 10:57 ` Hogander, Jouni
0 siblings, 1 reply; 25+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-10 13:42 UTC (permalink / raw)
To: Hogander, Jouni, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, Manna, Animesh
On 10/10/2025 12:23 PM, Hogander, Jouni wrote:
> On Thu, 2025-10-09 at 14:30 +0530, Ankit Nautiyal wrote:
>> Currently, wake line latency checks rely on the vblank length,
>> which does not account for either the extra vblank delay for icl/tgl
>> or for
>> the optimized guardband which will come into picture later at some
>> point.
>>
>> Introduce intel_dp_compute_config_late() to handle late-stage
>> configuration checks for DP/eDP features. For now, it validates
>> whether the
>> final vblank (with extra vblank delay) or guardband is sufficient to
>> support wake line latencies required by Panel Replay and PSR2
>> selective
>> update.
>>
>> Check if vblank is sufficient for PSR features, and disable them if
>> their
>> wake requirements cannot be accomodated.
> Now as we are adding this: Can't we just drop checks made earlier and
> rely on psr_compute_config_late checking the vblank?
You're right to raise this question. The key point is that there are
dependencies between the PSR configuration, the VRR guardband, and SCL
that influence the sequence of checks.
Here’s how the flow works:
1. psr_compute_config()
This is called first to determine if PSR is possible.
At this stage:
-> We check if the vblank is long enough to accommodate wake lines.
-> However, we don’t yet know the actual guardband or whether SCL lines
need to be accounted for.
-> So, we can only establish whether the vblank length is sufficient in
a general sense.
-> On platforms like ICL/TGL (with extra vblank delay) or with optimized
guardband, the actual lines may be fewer than the full vblank length.
2. compute_scl()
-> This computes the SCL.
-> If PSR was not enabled earlier, SCL will be 0 at this point.
-> The vblank_start is adjusted to accommodate the SCL lines.
3. vrr_compute_guardband()
-> This sets the guardband.
-> With optimized guardband, we consider max PSR requirements and other
prefill latencies.
-> On platforms where VRR TG is always active, the guardband cannot be
changed dynamically and any change in guardband triggers a full modeset.
-> So, the goal is to set a guardband during modeset that works across
most scenarios.
4. psr_compute_config_late()
-> This is where we re-check if the guardband is sufficient for PSR wake
time latencies.
-> If not, we disable PSR features that can’t be supported with the
current timing.
As mentioned in the earlier comment, more details are available in the
following references:
[1] https://lore.kernel.org/all/aOVOJp2zeN1eCp7O@intel.com/
[2] https://patchwork.freedesktop.org/patch/678520/?series=151245&rev=13
So to answer your question: We can't entirely drop the early checks in
psr_compute_config(), as it helps to filter PSR early based on vblank
length, and also helps to get the SCL adjustments. By the time we reach
psr_compute_config_late() we have more accurate picture to take a call
to disable specific PSR features.
That said, do you see any issues if we disable these later?
Also, are there other parts or logic that depend on
crtc_state->has_panel_replay and crtc_state->has_sel_update that you
think could be moved to psr_compute_config_late()?
Regards,
Ankit
>
> BR,
>
> Jouni Högander
>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> Cc: Animesh Manna <animesh.manna@intel.com>
>> Cc: Jouni Högander <jouni.hogander@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++
>> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++
>> drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
>> drivers/gpu/drm/i915/display/intel_psr.c | 51 ++++++++++++++++++++--
>> --
>> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
>> 5 files changed, 60 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index c09aa759f4d4..94c593bbedf4 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -4560,6 +4560,9 @@ static int intel_ddi_compute_config_late(struct
>> intel_encoder *encoder,
>> struct drm_connector *connector = conn_state->connector;
>> u8 port_sync_transcoders = 0;
>>
>> + if (intel_crtc_has_dp_encoder(crtc_state))
>> + intel_dp_compute_config_late(encoder, crtc_state,
>> conn_state);
>> +
>> drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
>> encoder->base.base.id, encoder->base.name,
>> crtc_state->uapi.crtc->base.id, crtc_state-
>>> uapi.crtc->name);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>> b/drivers/gpu/drm/i915/display/intel_dp.c
>> index a723e846321f..e481ff4c4959 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -6979,3 +6979,12 @@ void intel_dp_mst_resume(struct intel_display
>> *display)
>> }
>> }
>> }
>> +
>> +void intel_dp_compute_config_late(struct intel_encoder *encoder,
>> + struct intel_crtc_state
>> *crtc_state,
>> + struct drm_connector_state
>> *conn_state)
>> +{
>> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> +
>> + intel_psr_compute_config_late(intel_dp, crtc_state);
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
>> b/drivers/gpu/drm/i915/display/intel_dp.h
>> index b379443e0211..0d9573ca44cb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>> @@ -218,5 +218,8 @@ int intel_dp_compute_min_hblank(struct
>> intel_crtc_state *crtc_state,
>> int intel_dp_dsc_bpp_step_x16(const struct intel_connector
>> *connector);
>> void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool
>> force_on_external);
>> bool intel_dp_in_hdr_mode(const struct drm_connector_state
>> *conn_state);
>> +void intel_dp_compute_config_late(struct intel_encoder *encoder,
>> + struct intel_crtc_state
>> *crtc_state,
>> + struct drm_connector_state
>> *conn_state);
>>
>> #endif /* __INTEL_DP_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>> b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 212bd244beed..dcab4127b399 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -1405,6 +1405,20 @@ int _intel_psr_min_set_context_latency(const
>> struct intel_crtc_state *crtc_state
>> return 1;
>> }
>>
>> +static bool _wake_lines_fit_into_vblank(const struct
>> intel_crtc_state *crtc_state,
>> + int vblank,
>> + int wake_lines)
>> +{
>> + if (crtc_state->req_psr2_sdp_prior_scanline)
>> + vblank -= 1;
>> +
>> + /* Vblank >= PSR2_CTL Block Count Number maximum line count
>> */
>> + if (vblank < wake_lines)
>> + return false;
>> +
>> + return true;
>> +}
>> +
>> static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
>> const struct intel_crtc_state
>> *crtc_state,
>> bool aux_less,
>> @@ -1428,14 +1442,7 @@ static bool wake_lines_fit_into_vblank(struct
>> intel_dp *intel_dp,
>> crtc_state-
>>> alpm_state.fast_wake_lines) :
>> crtc_state->alpm_state.io_wake_lines;
>>
>> - if (crtc_state->req_psr2_sdp_prior_scanline)
>> - vblank -= 1;
>> -
>> - /* Vblank >= PSR2_CTL Block Count Number maximum line count
>> */
>> - if (vblank < wake_lines)
>> - return false;
>> -
>> - return true;
>> + return _wake_lines_fit_into_vblank(crtc_state, vblank,
>> wake_lines);
>> }
>>
>> static bool alpm_config_valid(struct intel_dp *intel_dp,
>> @@ -4346,3 +4353,31 @@ bool intel_psr_needs_alpm_aux_less(struct
>> intel_dp *intel_dp,
>> {
>> return intel_dp_is_edp(intel_dp) && crtc_state-
>>> has_panel_replay;
>> }
>> +
>> +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>> + struct intel_crtc_state
>> *crtc_state)
>> +{
>> + struct intel_display *display = to_intel_display(intel_dp);
>> + int vblank = intel_crtc_vblank_length(crtc_state);
>> + int aux_less_wake_lines = crtc_state-
>>> alpm_state.aux_less_wake_lines;
>> + int wake_lines = DISPLAY_VER(display) < 20 ?
>> + psr2_block_count_lines(crtc_state-
>>> alpm_state.io_wake_lines,
>> + crtc_state-
>>> alpm_state.fast_wake_lines) :
>> + crtc_state->alpm_state.io_wake_lines;
>> +
>> + if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
>> + !_wake_lines_fit_into_vblank(crtc_state, vblank,
>> aux_less_wake_lines)) {
>> + drm_dbg_kms(display->drm,
>> + "Disabling Panel replay: vblank
>> insufficient for wakelines = %d\n",
>> + aux_less_wake_lines);
>> + crtc_state->has_panel_replay = false;
>> + }
>> +
>> + if (crtc_state->has_sel_update &&
>> + !_wake_lines_fit_into_vblank(crtc_state, vblank,
>> wake_lines)) {
>> + drm_dbg_kms(display->drm,
>> + "Disabling Selective Update: vblank
>> insufficient for wakelines = %d\n",
>> + wake_lines);
>> + crtc_state->has_sel_update = false;
>> + }
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
>> b/drivers/gpu/drm/i915/display/intel_psr.h
>> index 9147996d6c9e..b17ce312dc37 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>> @@ -83,5 +83,7 @@ void intel_psr_debugfs_register(struct
>> intel_display *display);
>> bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct
>> intel_crtc_state *crtc_state);
>> bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>> const struct intel_crtc_state
>> *crtc_state);
>> +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>> + struct intel_crtc_state
>> *crtc_state);
>>
>> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband
2025-10-09 9:00 ` [PATCH 2/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband Ankit Nautiyal
@ 2025-10-10 14:53 ` Ville Syrjälä
2025-10-13 2:31 ` Nautiyal, Ankit K
0 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjälä @ 2025-10-10 14:53 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe
On Thu, Oct 09, 2025 at 02:30:56PM +0530, Ankit Nautiyal wrote:
> The helper intel_vrr_compute_config_late() practically just computes the
> guardband. Rename intel_vrr_compute_config_late() to
> intel_vrr_compute_guardband().
>
> Since we are going to compute the guardband and then move the
> vblank_start for optmizing guardband move it to
> intel_crtc_compute_config() which handles such changes.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_vrr.h | 2 +-
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b57efd870774..cd499e58bed3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2414,6 +2414,8 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> + intel_vrr_compute_guardband(crtc_state);
> +
> ret = intel_dpll_crtc_compute_clock(state, crtc);
Hmm. The intel_dpll_crtc_compute_clock() probably needs to move to the
very start of the function, so that we'll have an accurate clock for the
eventual guardband calculations. In fact my plan has been to move it
into .compute_config() entirely, but I haven't had time to revisit
this topic in a while :/
For easier bisectability I'd do that move first as a separate patch.
> if (ret)
> return ret;
The other thing we have here is intel_crtc_compute_pipe_mode(). I have
a feeling I didn't consider the joiner aspect at all with the prefill
helpers. We might need the pipe_mode for the guardband calculations.
I'll have to have a look at what I did there and think a bit more about
how the joiner affects that stuff.
And the other thing I haven't considered at all is MSO. Right now
adjusted_mode will contain the per-segment timings with MSO which,
now that I think about it again, migth be a bad idea (my idea IIRC).
Eg. adjusted_mode based linetime calculations will be skewed by the
overlap included in the segement timings.
We may have to rethink the MSO apporoach to keep the full timings in
adjusted_mode and either introduce yet another mode for the per-segment
timings, or perhaps just do the full<->segment conversions as needed
(set_transcoder_timings()+its readout, compute_m_n(), maybe some other
places as well?).
> @@ -4722,8 +4724,6 @@ intel_modeset_pipe_config_late(struct intel_atomic_state *state,
> struct drm_connector *connector;
> int i;
>
> - intel_vrr_compute_config_late(crtc_state);
> -
> for_each_new_connector_in_state(&state->base, connector,
> conn_state, i) {
> struct intel_encoder *encoder =
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 4bc14b5e685f..8d71d7dc9d12 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -433,7 +433,7 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
> intel_vrr_max_vblank_guardband(crtc_state));
> }
>
> -void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
> +void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
> index 7317f8730089..bc9044621635 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
> @@ -21,7 +21,7 @@ bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
> void intel_vrr_check_modeset(struct intel_atomic_state *state);
> void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state);
> -void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state);
> +void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state);
> void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
> void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
> void intel_vrr_send_push(struct intel_dsb *dsb,
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/8] drm/i915/vblank: Add helper to get correct vblank length
2025-10-09 9:00 ` [PATCH 3/8] drm/i915/vblank: Add helper to get correct vblank length Ankit Nautiyal
@ 2025-10-10 14:54 ` Ville Syrjälä
0 siblings, 0 replies; 25+ messages in thread
From: Ville Syrjälä @ 2025-10-10 14:54 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe
On Thu, Oct 09, 2025 at 02:30:57PM +0530, Ankit Nautiyal wrote:
> Currently crtc_vblank_start is assumed to be the vblank_start for the fixed
> refresh rate case. That value can be different from the variable refresh
> rate case whenever always_use_vrr_tg()==false. On icl/tgl it's always
> different due to the extra vblank delay, and also on adl+ it could be
> different if we were to use an optimized guardband.
>
> So places where crtc_vblank_start is used to compute vblank length needs
> change so as to account for cases where vrr is enabled. Specifically
> with vrr.enable the effective vblank length is actually guardband.
>
> Add a helper to get the correct vblank length for both vrr and fixed
> refresh rate cases. Use this helper where vblank_start is used to
> compute the vblank length.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 10 ++++++++++
> drivers/gpu/drm/i915/display/intel_vblank.h | 2 ++
> drivers/gpu/drm/i915/display/skl_watermark.c | 3 ++-
> 3 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 0b7fcc05e64c..2fc0c1c0bb87 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -767,3 +767,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
>
> return scanline;
> }
> +
> +int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
> +{
> + const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +
> + if (crtc_state->vrr.enable)
> + return crtc_state->vrr.guardband;
> + else
> + return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
> index 21fbb08d61d5..98d04cacd65f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> @@ -48,4 +48,6 @@ const struct intel_crtc_state *
> intel_pre_commit_crtc_state(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
>
> +int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);
> +
> #endif /* __INTEL_VBLANK_H__ */
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 9df9ee137bf9..06e5e6c77d2e 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -28,6 +28,7 @@
> #include "intel_flipq.h"
> #include "intel_pcode.h"
> #include "intel_plane.h"
> +#include "intel_vblank.h"
> #include "intel_wm.h"
> #include "skl_universal_plane_regs.h"
> #include "skl_watermark.h"
> @@ -2241,7 +2242,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
> scaler_prefill_latency(crtc_state) +
> dsc_prefill_latency(crtc_state) +
> wm0_lines >
> - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
> + intel_crtc_vblank_length(crtc_state);
> }
>
> static int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 7/8] drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG
2025-10-09 9:01 ` [PATCH 7/8] drm/i915/display: Add vblank_start adjustment logic for " Ankit Nautiyal
@ 2025-10-10 15:05 ` Ville Syrjälä
2025-10-13 2:23 ` Nautiyal, Ankit K
0 siblings, 1 reply; 25+ messages in thread
From: Ville Syrjälä @ 2025-10-10 15:05 UTC (permalink / raw)
To: Ankit Nautiyal; +Cc: intel-gfx, intel-xe
On Thu, Oct 09, 2025 at 02:31:01PM +0530, Ankit Nautiyal wrote:
> As we move towards using a shorter, optimized guardband, we need to adjust
> how the delayed vblank start is computed.
>
> Adjust the crtc_vblank_start using Vmin Vtotal - guardband only when
> intel_vrr_always_use_vrr_tg() is true.
>
> This also paves way for guardband optimization, by handling the movement of
> the crtc_vblank_start for platforms that have VRR TG always active.
>
> v2: Drop the helper and add the adjustment directly to
> intel_vrr_compute_guardband(). Ville
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vrr.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 221b25832e56..5f9b8e5c48be 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -436,7 +436,7 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
> void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
> {
> struct intel_display *display = to_intel_display(crtc_state);
> - const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>
> if (!intel_vrr_possible(crtc_state))
> return;
> @@ -444,6 +444,10 @@ void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
> crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
> intel_vrr_max_guardband(crtc_state));
>
> + if (intel_vrr_always_use_vrr_tg(display))
> + adjusted_mode->crtc_vblank_start =
> + crtc_state->vrr.vmin - crtc_state->vrr.guardband;
Since this is for the fixed refresh rate timings I think we should use
adjusted_mode.crtc_vtotal here instead of vmin (yes the two should be
equivalent at least for now, but I think it's better to be consistent).
And this should be squashed with the readout equivalent to make sure
both sides stay in sync so there's no possibility of angering the state
checker by only having the changes on one side.
> +
> if (DISPLAY_VER(display) < 13)
> crtc_state->vrr.pipeline_full =
> intel_vrr_guardband_to_pipeline_full(crtc_state,
> --
> 2.45.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 7/8] drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG
2025-10-10 15:05 ` Ville Syrjälä
@ 2025-10-13 2:23 ` Nautiyal, Ankit K
0 siblings, 0 replies; 25+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-13 2:23 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On 10/10/2025 8:35 PM, Ville Syrjälä wrote:
> On Thu, Oct 09, 2025 at 02:31:01PM +0530, Ankit Nautiyal wrote:
>> As we move towards using a shorter, optimized guardband, we need to adjust
>> how the delayed vblank start is computed.
>>
>> Adjust the crtc_vblank_start using Vmin Vtotal - guardband only when
>> intel_vrr_always_use_vrr_tg() is true.
>>
>> This also paves way for guardband optimization, by handling the movement of
>> the crtc_vblank_start for platforms that have VRR TG always active.
>>
>> v2: Drop the helper and add the adjustment directly to
>> intel_vrr_compute_guardband(). Ville
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_vrr.c | 6 +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 221b25832e56..5f9b8e5c48be 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -436,7 +436,7 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
>> void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
>> {
>> struct intel_display *display = to_intel_display(crtc_state);
>> - const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>>
>> if (!intel_vrr_possible(crtc_state))
>> return;
>> @@ -444,6 +444,10 @@ void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
>> crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay,
>> intel_vrr_max_guardband(crtc_state));
>>
>> + if (intel_vrr_always_use_vrr_tg(display))
>> + adjusted_mode->crtc_vblank_start =
>> + crtc_state->vrr.vmin - crtc_state->vrr.guardband;
> Since this is for the fixed refresh rate timings I think we should use
> adjusted_mode.crtc_vtotal here instead of vmin (yes the two should be
> equivalent at least for now, but I think it's better to be consistent).
Got it.
>
> And this should be squashed with the readout equivalent to make sure
> both sides stay in sync so there's no possibility of angering the state
> checker by only having the changes on one side.
Right sure, I will merge the two patches.
Regards,
Ankit
>
>> +
>> if (DISPLAY_VER(display) < 13)
>> crtc_state->vrr.pipeline_full =
>> intel_vrr_guardband_to_pipeline_full(crtc_state,
>> --
>> 2.45.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband
2025-10-10 14:53 ` Ville Syrjälä
@ 2025-10-13 2:31 ` Nautiyal, Ankit K
0 siblings, 0 replies; 25+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-13 2:31 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, intel-xe
On 10/10/2025 8:23 PM, Ville Syrjälä wrote:
> On Thu, Oct 09, 2025 at 02:30:56PM +0530, Ankit Nautiyal wrote:
>> The helper intel_vrr_compute_config_late() practically just computes the
>> guardband. Rename intel_vrr_compute_config_late() to
>> intel_vrr_compute_guardband().
>>
>> Since we are going to compute the guardband and then move the
>> vblank_start for optmizing guardband move it to
>> intel_crtc_compute_config() which handles such changes.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
>> drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_vrr.h | 2 +-
>> 3 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index b57efd870774..cd499e58bed3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -2414,6 +2414,8 @@ static int intel_crtc_compute_config(struct intel_atomic_state *state,
>> if (ret)
>> return ret;
>>
>> + intel_vrr_compute_guardband(crtc_state);
>> +
>> ret = intel_dpll_crtc_compute_clock(state, crtc);
> Hmm. The intel_dpll_crtc_compute_clock() probably needs to move to the
> very start of the function, so that we'll have an accurate clock for the
> eventual guardband calculations. In fact my plan has been to move it
> into .compute_config() entirely, but I haven't had time to revisit
> this topic in a while :/
>
> For easier bisectability I'd do that move first as a separate patch.
Ohh I missed that, will move intel_dpll_crtc_compute_clock() in the
beginning of the function.
>
>> if (ret)
>> return ret;
> The other thing we have here is intel_crtc_compute_pipe_mode(). I have
> a feeling I didn't consider the joiner aspect at all with the prefill
> helpers. We might need the pipe_mode for the guardband calculations.
> I'll have to have a look at what I did there and think a bit more about
> how the joiner affects that stuff.
Hmm in that case I guess will move intel_vrr_compute_guardband() at the
last or perhaps atleast after intel_crtc_compute_pipe_mode().
>
>
> And the other thing I haven't considered at all is MSO. Right now
> adjusted_mode will contain the per-segment timings with MSO which,
> now that I think about it again, migth be a bad idea (my idea IIRC).
> Eg. adjusted_mode based linetime calculations will be skewed by the
> overlap included in the segement timings.
>
> We may have to rethink the MSO apporoach to keep the full timings in
> adjusted_mode and either introduce yet another mode for the per-segment
> timings, or perhaps just do the full<->segment conversions as needed
> (set_transcoder_timings()+its readout, compute_m_n(), maybe some other
> places as well?).
I still look into the series for pre-fill, but yes now I can see how
joiner and MSO need to be accounted for the prefill computation.
Regards,
Ankit
>
>> @@ -4722,8 +4724,6 @@ intel_modeset_pipe_config_late(struct intel_atomic_state *state,
>> struct drm_connector *connector;
>> int i;
>>
>> - intel_vrr_compute_config_late(crtc_state);
>> -
>> for_each_new_connector_in_state(&state->base, connector,
>> conn_state, i) {
>> struct intel_encoder *encoder =
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 4bc14b5e685f..8d71d7dc9d12 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -433,7 +433,7 @@ intel_vrr_max_guardband(struct intel_crtc_state *crtc_state)
>> intel_vrr_max_vblank_guardband(crtc_state));
>> }
>>
>> -void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state)
>> +void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
>> {
>> struct intel_display *display = to_intel_display(crtc_state);
>> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h
>> index 7317f8730089..bc9044621635 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.h
>> @@ -21,7 +21,7 @@ bool intel_vrr_possible(const struct intel_crtc_state *crtc_state);
>> void intel_vrr_check_modeset(struct intel_atomic_state *state);
>> void intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>> struct drm_connector_state *conn_state);
>> -void intel_vrr_compute_config_late(struct intel_crtc_state *crtc_state);
>> +void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state);
>> void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
>> void intel_vrr_enable(const struct intel_crtc_state *crtc_state);
>> void intel_vrr_send_push(struct intel_dsb *dsb,
>> --
>> 2.45.2
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features
2025-10-10 13:42 ` Nautiyal, Ankit K
@ 2025-10-13 10:57 ` Hogander, Jouni
2025-10-13 12:29 ` Nautiyal, Ankit K
0 siblings, 1 reply; 25+ messages in thread
From: Hogander, Jouni @ 2025-10-13 10:57 UTC (permalink / raw)
To: intel-xe@lists.freedesktop.org, Nautiyal, Ankit K,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, Manna, Animesh
On Fri, 2025-10-10 at 19:12 +0530, Nautiyal, Ankit K wrote:
>
> On 10/10/2025 12:23 PM, Hogander, Jouni wrote:
> > On Thu, 2025-10-09 at 14:30 +0530, Ankit Nautiyal wrote:
> > > Currently, wake line latency checks rely on the vblank length,
> > > which does not account for either the extra vblank delay for
> > > icl/tgl
> > > or for
> > > the optimized guardband which will come into picture later at
> > > some
> > > point.
> > >
> > > Introduce intel_dp_compute_config_late() to handle late-stage
> > > configuration checks for DP/eDP features. For now, it validates
> > > whether the
> > > final vblank (with extra vblank delay) or guardband is sufficient
> > > to
> > > support wake line latencies required by Panel Replay and PSR2
> > > selective
> > > update.
> > >
> > > Check if vblank is sufficient for PSR features, and disable them
> > > if
> > > their
> > > wake requirements cannot be accomodated.
> > Now as we are adding this: Can't we just drop checks made earlier
> > and
> > rely on psr_compute_config_late checking the vblank?
>
>
> You're right to raise this question. The key point is that there are
> dependencies between the PSR configuration, the VRR guardband, and
> SCL
> that influence the sequence of checks.
>
> Here’s how the flow works:
>
>
> 1. psr_compute_config()
> This is called first to determine if PSR is possible.
> At this stage:
>
> -> We check if the vblank is long enough to accommodate wake lines.
> -> However, we don’t yet know the actual guardband or whether SCL
> lines
> need to be accounted for.
> -> So, we can only establish whether the vblank length is sufficient
> in
> a general sense.
> -> On platforms like ICL/TGL (with extra vblank delay) or with
> optimized
> guardband, the actual lines may be fewer than the full vblank length.
Please add a comment into psr_compute_config that it is roughly
checking if PSR is possible with current understanding of vblank
length. It will be checked later in psr_compute_config_late against
optimized vblank length.
>
>
> 2. compute_scl()
>
> -> This computes the SCL.
> -> If PSR was not enabled earlier, SCL will be 0 at this point.
> -> The vblank_start is adjusted to accommodate the SCL lines.
>
>
> 3. vrr_compute_guardband()
>
> -> This sets the guardband.
> -> With optimized guardband, we consider max PSR requirements and
> other
> prefill latencies.
> -> On platforms where VRR TG is always active, the guardband cannot
> be
> changed dynamically and any change in guardband triggers a full
> modeset.
> -> So, the goal is to set a guardband during modeset that works
> across
> most scenarios.
>
>
> 4. psr_compute_config_late()
>
> -> This is where we re-check if the guardband is sufficient for PSR
> wake
> time latencies.
> -> If not, we disable PSR features that can’t be supported with the
> current timing.
Add comment into psr_compute_config_late about SCL being left untouched
and containing intel_psr_set_context_latency if PSR was possible after
intel_psr_compute_config.
>
>
> As mentioned in the earlier comment, more details are available in
> the
> following references:
> [1] https://lore.kernel.org/all/aOVOJp2zeN1eCp7O@intel.com/
> [2]
> https://patchwork.freedesktop.org/patch/678520/?series=151245&rev=13
>
> So to answer your question: We can't entirely drop the early checks
> in
> psr_compute_config(), as it helps to filter PSR early based on vblank
> length, and also helps to get the SCL adjustments. By the time we
> reach
> psr_compute_config_late() we have more accurate picture to take a
> call
> to disable specific PSR features.
>
>
> That said, do you see any issues if we disable these later?
> Also, are there other parts or logic that depend on
> crtc_state->has_panel_replay and crtc_state->has_sel_update that you
> think could be moved to psr_compute_config_late()?
I don't see other need for psr_compute_config_late ATM.
BR,
Jouni Högander
>
> Regards,
>
> Ankit
>
> >
> > BR,
> >
> > Jouni Högander
> >
> > > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> > > Cc: Animesh Manna <animesh.manna@intel.com>
> > > Cc: Jouni Högander <jouni.hogander@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++
> > > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++
> > > drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
> > > drivers/gpu/drm/i915/display/intel_psr.c | 51
> > > ++++++++++++++++++++--
> > > --
> > > drivers/gpu/drm/i915/display/intel_psr.h | 2 +
> > > 5 files changed, 60 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index c09aa759f4d4..94c593bbedf4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -4560,6 +4560,9 @@ static int
> > > intel_ddi_compute_config_late(struct
> > > intel_encoder *encoder,
> > > struct drm_connector *connector = conn_state->connector;
> > > u8 port_sync_transcoders = 0;
> > >
> > > + if (intel_crtc_has_dp_encoder(crtc_state))
> > > + intel_dp_compute_config_late(encoder,
> > > crtc_state,
> > > conn_state);
> > > +
> > > drm_dbg_kms(display->drm, "[ENCODER:%d:%s]
> > > [CRTC:%d:%s]\n",
> > > encoder->base.base.id, encoder->base.name,
> > > crtc_state->uapi.crtc->base.id, crtc_state-
> > > > uapi.crtc->name);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index a723e846321f..e481ff4c4959 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -6979,3 +6979,12 @@ void intel_dp_mst_resume(struct
> > > intel_display
> > > *display)
> > > }
> > > }
> > > }
> > > +
> > > +void intel_dp_compute_config_late(struct intel_encoder *encoder,
> > > + struct intel_crtc_state
> > > *crtc_state,
> > > + struct drm_connector_state
> > > *conn_state)
> > > +{
> > > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > +
> > > + intel_psr_compute_config_late(intel_dp, crtc_state);
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> > > b/drivers/gpu/drm/i915/display/intel_dp.h
> > > index b379443e0211..0d9573ca44cb 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > @@ -218,5 +218,8 @@ int intel_dp_compute_min_hblank(struct
> > > intel_crtc_state *crtc_state,
> > > int intel_dp_dsc_bpp_step_x16(const struct intel_connector
> > > *connector);
> > > void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool
> > > force_on_external);
> > > bool intel_dp_in_hdr_mode(const struct drm_connector_state
> > > *conn_state);
> > > +void intel_dp_compute_config_late(struct intel_encoder *encoder,
> > > + struct intel_crtc_state
> > > *crtc_state,
> > > + struct drm_connector_state
> > > *conn_state);
> > >
> > > #endif /* __INTEL_DP_H__ */
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 212bd244beed..dcab4127b399 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1405,6 +1405,20 @@ int
> > > _intel_psr_min_set_context_latency(const
> > > struct intel_crtc_state *crtc_state
> > > return 1;
> > > }
> > >
> > > +static bool _wake_lines_fit_into_vblank(const struct
> > > intel_crtc_state *crtc_state,
> > > + int vblank,
> > > + int wake_lines)
> > > +{
> > > + if (crtc_state->req_psr2_sdp_prior_scanline)
> > > + vblank -= 1;
> > > +
> > > + /* Vblank >= PSR2_CTL Block Count Number maximum line
> > > count
> > > */
> > > + if (vblank < wake_lines)
> > > + return false;
> > > +
> > > + return true;
> > > +}
> > > +
> > > static bool wake_lines_fit_into_vblank(struct intel_dp
> > > *intel_dp,
> > > const struct
> > > intel_crtc_state
> > > *crtc_state,
> > > bool aux_less,
> > > @@ -1428,14 +1442,7 @@ static bool
> > > wake_lines_fit_into_vblank(struct
> > > intel_dp *intel_dp,
> > > crtc_state-
> > > > alpm_state.fast_wake_lines) :
> > > crtc_state->alpm_state.io_wake_lines;
> > >
> > > - if (crtc_state->req_psr2_sdp_prior_scanline)
> > > - vblank -= 1;
> > > -
> > > - /* Vblank >= PSR2_CTL Block Count Number maximum line
> > > count
> > > */
> > > - if (vblank < wake_lines)
> > > - return false;
> > > -
> > > - return true;
> > > + return _wake_lines_fit_into_vblank(crtc_state, vblank,
> > > wake_lines);
> > > }
> > >
> > > static bool alpm_config_valid(struct intel_dp *intel_dp,
> > > @@ -4346,3 +4353,31 @@ bool intel_psr_needs_alpm_aux_less(struct
> > > intel_dp *intel_dp,
> > > {
> > > return intel_dp_is_edp(intel_dp) && crtc_state-
> > > > has_panel_replay;
> > > }
> > > +
> > > +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state
> > > *crtc_state)
> > > +{
> > > + struct intel_display *display =
> > > to_intel_display(intel_dp);
> > > + int vblank = intel_crtc_vblank_length(crtc_state);
> > > + int aux_less_wake_lines = crtc_state-
> > > > alpm_state.aux_less_wake_lines;
> > > + int wake_lines = DISPLAY_VER(display) < 20 ?
> > > + psr2_block_count_lines(crtc_state-
> > > > alpm_state.io_wake_lines,
> > > + crtc_state-
> > > > alpm_state.fast_wake_lines) :
> > > + crtc_state->alpm_state.io_wake_lines;
> > > +
> > > + if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)
> > > &&
> > > + !_wake_lines_fit_into_vblank(crtc_state, vblank,
> > > aux_less_wake_lines)) {
> > > + drm_dbg_kms(display->drm,
> > > + "Disabling Panel replay: vblank
> > > insufficient for wakelines = %d\n",
> > > + aux_less_wake_lines);
> > > + crtc_state->has_panel_replay = false;
> > > + }
> > > +
> > > + if (crtc_state->has_sel_update &&
> > > + !_wake_lines_fit_into_vblank(crtc_state, vblank,
> > > wake_lines)) {
> > > + drm_dbg_kms(display->drm,
> > > + "Disabling Selective Update: vblank
> > > insufficient for wakelines = %d\n",
> > > + wake_lines);
> > > + crtc_state->has_sel_update = false;
> > > + }
> > > +}
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index 9147996d6c9e..b17ce312dc37 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -83,5 +83,7 @@ void intel_psr_debugfs_register(struct
> > > intel_display *display);
> > > bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const
> > > struct
> > > intel_crtc_state *crtc_state);
> > > bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
> > > const struct intel_crtc_state
> > > *crtc_state);
> > > +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state
> > > *crtc_state);
> > >
> > > #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features
2025-10-13 10:57 ` Hogander, Jouni
@ 2025-10-13 12:29 ` Nautiyal, Ankit K
0 siblings, 0 replies; 25+ messages in thread
From: Nautiyal, Ankit K @ 2025-10-13 12:29 UTC (permalink / raw)
To: Hogander, Jouni, intel-xe@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, Manna, Animesh
On 10/13/2025 4:27 PM, Hogander, Jouni wrote:
> On Fri, 2025-10-10 at 19:12 +0530, Nautiyal, Ankit K wrote:
>> On 10/10/2025 12:23 PM, Hogander, Jouni wrote:
>>> On Thu, 2025-10-09 at 14:30 +0530, Ankit Nautiyal wrote:
>>>> Currently, wake line latency checks rely on the vblank length,
>>>> which does not account for either the extra vblank delay for
>>>> icl/tgl
>>>> or for
>>>> the optimized guardband which will come into picture later at
>>>> some
>>>> point.
>>>>
>>>> Introduce intel_dp_compute_config_late() to handle late-stage
>>>> configuration checks for DP/eDP features. For now, it validates
>>>> whether the
>>>> final vblank (with extra vblank delay) or guardband is sufficient
>>>> to
>>>> support wake line latencies required by Panel Replay and PSR2
>>>> selective
>>>> update.
>>>>
>>>> Check if vblank is sufficient for PSR features, and disable them
>>>> if
>>>> their
>>>> wake requirements cannot be accomodated.
>>> Now as we are adding this: Can't we just drop checks made earlier
>>> and
>>> rely on psr_compute_config_late checking the vblank?
>>
>> You're right to raise this question. The key point is that there are
>> dependencies between the PSR configuration, the VRR guardband, and
>> SCL
>> that influence the sequence of checks.
>>
>> Here’s how the flow works:
>>
>>
>> 1. psr_compute_config()
>> This is called first to determine if PSR is possible.
>> At this stage:
>>
>> -> We check if the vblank is long enough to accommodate wake lines.
>> -> However, we don’t yet know the actual guardband or whether SCL
>> lines
>> need to be accounted for.
>> -> So, we can only establish whether the vblank length is sufficient
>> in
>> a general sense.
>> -> On platforms like ICL/TGL (with extra vblank delay) or with
>> optimized
>> guardband, the actual lines may be fewer than the full vblank length.
> Please add a comment into psr_compute_config that it is roughly
> checking if PSR is possible with current understanding of vblank
> length. It will be checked later in psr_compute_config_late against
> optimized vblank length.
Makes sense. Will add the appropriate comment.
>>
>> 2. compute_scl()
>>
>> -> This computes the SCL.
>> -> If PSR was not enabled earlier, SCL will be 0 at this point.
>> -> The vblank_start is adjusted to accommodate the SCL lines.
>>
>>
>> 3. vrr_compute_guardband()
>>
>> -> This sets the guardband.
>> -> With optimized guardband, we consider max PSR requirements and
>> other
>> prefill latencies.
>> -> On platforms where VRR TG is always active, the guardband cannot
>> be
>> changed dynamically and any change in guardband triggers a full
>> modeset.
>> -> So, the goal is to set a guardband during modeset that works
>> across
>> most scenarios.
>>
>>
>> 4. psr_compute_config_late()
>>
>> -> This is where we re-check if the guardband is sufficient for PSR
>> wake
>> time latencies.
>> -> If not, we disable PSR features that can’t be supported with the
>> current timing.
> Add comment into psr_compute_config_late about SCL being left untouched
> and containing intel_psr_set_context_latency if PSR was possible after
> intel_psr_compute_config.
Hmm sure can add rationale for not re-setting SCL.
Thanks & Regards,
Ankit
>
>>
>> As mentioned in the earlier comment, more details are available in
>> the
>> following references:
>> [1] https://lore.kernel.org/all/aOVOJp2zeN1eCp7O@intel.com/
>> [2]
>> https://patchwork.freedesktop.org/patch/678520/?series=151245&rev=13
>>
>> So to answer your question: We can't entirely drop the early checks
>> in
>> psr_compute_config(), as it helps to filter PSR early based on vblank
>> length, and also helps to get the SCL adjustments. By the time we
>> reach
>> psr_compute_config_late() we have more accurate picture to take a
>> call
>> to disable specific PSR features.
>>
>>
>> That said, do you see any issues if we disable these later?
>> Also, are there other parts or logic that depend on
>> crtc_state->has_panel_replay and crtc_state->has_sel_update that you
>> think could be moved to psr_compute_config_late()?
> I don't see other need for psr_compute_config_late ATM.
>
> BR,
>
> Jouni Högander
>> Regards,
>>
>> Ankit
>>
>>> BR,
>>>
>>> Jouni Högander
>>>
>>>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>>>> Cc: Animesh Manna <animesh.manna@intel.com>
>>>> Cc: Jouni Högander <jouni.hogander@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++
>>>> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++
>>>> drivers/gpu/drm/i915/display/intel_dp.h | 3 ++
>>>> drivers/gpu/drm/i915/display/intel_psr.c | 51
>>>> ++++++++++++++++++++--
>>>> --
>>>> drivers/gpu/drm/i915/display/intel_psr.h | 2 +
>>>> 5 files changed, 60 insertions(+), 8 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
>>>> b/drivers/gpu/drm/i915/display/intel_ddi.c
>>>> index c09aa759f4d4..94c593bbedf4 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>>>> @@ -4560,6 +4560,9 @@ static int
>>>> intel_ddi_compute_config_late(struct
>>>> intel_encoder *encoder,
>>>> struct drm_connector *connector = conn_state->connector;
>>>> u8 port_sync_transcoders = 0;
>>>>
>>>> + if (intel_crtc_has_dp_encoder(crtc_state))
>>>> + intel_dp_compute_config_late(encoder,
>>>> crtc_state,
>>>> conn_state);
>>>> +
>>>> drm_dbg_kms(display->drm, "[ENCODER:%d:%s]
>>>> [CRTC:%d:%s]\n",
>>>> encoder->base.base.id, encoder->base.name,
>>>> crtc_state->uapi.crtc->base.id, crtc_state-
>>>>> uapi.crtc->name);
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> index a723e846321f..e481ff4c4959 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>>>> @@ -6979,3 +6979,12 @@ void intel_dp_mst_resume(struct
>>>> intel_display
>>>> *display)
>>>> }
>>>> }
>>>> }
>>>> +
>>>> +void intel_dp_compute_config_late(struct intel_encoder *encoder,
>>>> + struct intel_crtc_state
>>>> *crtc_state,
>>>> + struct drm_connector_state
>>>> *conn_state)
>>>> +{
>>>> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>>> +
>>>> + intel_psr_compute_config_late(intel_dp, crtc_state);
>>>> +}
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
>>>> b/drivers/gpu/drm/i915/display/intel_dp.h
>>>> index b379443e0211..0d9573ca44cb 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_dp.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
>>>> @@ -218,5 +218,8 @@ int intel_dp_compute_min_hblank(struct
>>>> intel_crtc_state *crtc_state,
>>>> int intel_dp_dsc_bpp_step_x16(const struct intel_connector
>>>> *connector);
>>>> void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool
>>>> force_on_external);
>>>> bool intel_dp_in_hdr_mode(const struct drm_connector_state
>>>> *conn_state);
>>>> +void intel_dp_compute_config_late(struct intel_encoder *encoder,
>>>> + struct intel_crtc_state
>>>> *crtc_state,
>>>> + struct drm_connector_state
>>>> *conn_state);
>>>>
>>>> #endif /* __INTEL_DP_H__ */
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>>> index 212bd244beed..dcab4127b399 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>>> @@ -1405,6 +1405,20 @@ int
>>>> _intel_psr_min_set_context_latency(const
>>>> struct intel_crtc_state *crtc_state
>>>> return 1;
>>>> }
>>>>
>>>> +static bool _wake_lines_fit_into_vblank(const struct
>>>> intel_crtc_state *crtc_state,
>>>> + int vblank,
>>>> + int wake_lines)
>>>> +{
>>>> + if (crtc_state->req_psr2_sdp_prior_scanline)
>>>> + vblank -= 1;
>>>> +
>>>> + /* Vblank >= PSR2_CTL Block Count Number maximum line
>>>> count
>>>> */
>>>> + if (vblank < wake_lines)
>>>> + return false;
>>>> +
>>>> + return true;
>>>> +}
>>>> +
>>>> static bool wake_lines_fit_into_vblank(struct intel_dp
>>>> *intel_dp,
>>>> const struct
>>>> intel_crtc_state
>>>> *crtc_state,
>>>> bool aux_less,
>>>> @@ -1428,14 +1442,7 @@ static bool
>>>> wake_lines_fit_into_vblank(struct
>>>> intel_dp *intel_dp,
>>>> crtc_state-
>>>>> alpm_state.fast_wake_lines) :
>>>> crtc_state->alpm_state.io_wake_lines;
>>>>
>>>> - if (crtc_state->req_psr2_sdp_prior_scanline)
>>>> - vblank -= 1;
>>>> -
>>>> - /* Vblank >= PSR2_CTL Block Count Number maximum line
>>>> count
>>>> */
>>>> - if (vblank < wake_lines)
>>>> - return false;
>>>> -
>>>> - return true;
>>>> + return _wake_lines_fit_into_vblank(crtc_state, vblank,
>>>> wake_lines);
>>>> }
>>>>
>>>> static bool alpm_config_valid(struct intel_dp *intel_dp,
>>>> @@ -4346,3 +4353,31 @@ bool intel_psr_needs_alpm_aux_less(struct
>>>> intel_dp *intel_dp,
>>>> {
>>>> return intel_dp_is_edp(intel_dp) && crtc_state-
>>>>> has_panel_replay;
>>>> }
>>>> +
>>>> +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>>>> + struct intel_crtc_state
>>>> *crtc_state)
>>>> +{
>>>> + struct intel_display *display =
>>>> to_intel_display(intel_dp);
>>>> + int vblank = intel_crtc_vblank_length(crtc_state);
>>>> + int aux_less_wake_lines = crtc_state-
>>>>> alpm_state.aux_less_wake_lines;
>>>> + int wake_lines = DISPLAY_VER(display) < 20 ?
>>>> + psr2_block_count_lines(crtc_state-
>>>>> alpm_state.io_wake_lines,
>>>> + crtc_state-
>>>>> alpm_state.fast_wake_lines) :
>>>> + crtc_state->alpm_state.io_wake_lines;
>>>> +
>>>> + if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state)
>>>> &&
>>>> + !_wake_lines_fit_into_vblank(crtc_state, vblank,
>>>> aux_less_wake_lines)) {
>>>> + drm_dbg_kms(display->drm,
>>>> + "Disabling Panel replay: vblank
>>>> insufficient for wakelines = %d\n",
>>>> + aux_less_wake_lines);
>>>> + crtc_state->has_panel_replay = false;
>>>> + }
>>>> +
>>>> + if (crtc_state->has_sel_update &&
>>>> + !_wake_lines_fit_into_vblank(crtc_state, vblank,
>>>> wake_lines)) {
>>>> + drm_dbg_kms(display->drm,
>>>> + "Disabling Selective Update: vblank
>>>> insufficient for wakelines = %d\n",
>>>> + wake_lines);
>>>> + crtc_state->has_sel_update = false;
>>>> + }
>>>> +}
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
>>>> b/drivers/gpu/drm/i915/display/intel_psr.h
>>>> index 9147996d6c9e..b17ce312dc37 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_psr.h
>>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
>>>> @@ -83,5 +83,7 @@ void intel_psr_debugfs_register(struct
>>>> intel_display *display);
>>>> bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const
>>>> struct
>>>> intel_crtc_state *crtc_state);
>>>> bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
>>>> const struct intel_crtc_state
>>>> *crtc_state);
>>>> +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
>>>> + struct intel_crtc_state
>>>> *crtc_state);
>>>>
>>>> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2025-10-13 12:29 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-09 9:00 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-09 9:00 ` [PATCH 1/8] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
2025-10-09 9:00 ` [PATCH 2/8] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband Ankit Nautiyal
2025-10-10 14:53 ` Ville Syrjälä
2025-10-13 2:31 ` Nautiyal, Ankit K
2025-10-09 9:00 ` [PATCH 3/8] drm/i915/vblank: Add helper to get correct vblank length Ankit Nautiyal
2025-10-10 14:54 ` Ville Syrjälä
2025-10-09 9:00 ` [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency Ankit Nautiyal
2025-10-10 6:40 ` Hogander, Jouni
2025-10-10 13:01 ` Nautiyal, Ankit K
2025-10-09 9:00 ` [PATCH 5/8] drm/i915/display: Check if final vblank is sufficient for PSR features Ankit Nautiyal
2025-10-10 6:53 ` Hogander, Jouni
2025-10-10 13:42 ` Nautiyal, Ankit K
2025-10-13 10:57 ` Hogander, Jouni
2025-10-13 12:29 ` Nautiyal, Ankit K
2025-10-09 9:01 ` [PATCH 6/8] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG Ankit Nautiyal
2025-10-09 9:01 ` [PATCH 7/8] drm/i915/display: Add vblank_start adjustment logic for " Ankit Nautiyal
2025-10-10 15:05 ` Ville Syrjälä
2025-10-13 2:23 ` Nautiyal, Ankit K
2025-10-09 9:01 ` [PATCH 8/8] drm/i915/display: Prepare for vblank_delay for LRR Ankit Nautiyal
2025-10-09 9:22 ` ✓ CI.KUnit: success for Preparatory patches for guardband optimization (rev2) Patchwork
2025-10-09 9:37 ` ✗ CI.checksparse: warning " Patchwork
2025-10-09 10:14 ` ✓ Xe.CI.BAT: success " Patchwork
2025-10-09 12:42 ` ✓ Xe.CI.Full: " Patchwork
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2025-10-09 7:17 [PATCH 0/8] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-09 7:17 ` [PATCH 4/8] drm/i915/psr: Consider SCL lines when validating vblank for wake latency Ankit Nautiyal
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