From: Tejas Upadhyay <tejas.upadhyay@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Matt Roper <matthew.d.roper@intel.com>,
Shekhar Chauhan <shekhar.chauhan@intel.com>,
Matthew Auld <matthew.auld@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Tejas Upadhyay <tejas.upadhyay@intel.com>
Subject: [PATCH V2 1/3] drm/xe: Move enable host l2 VRAM post MCR init
Date: Wed, 14 Aug 2024 15:26:12 +0530 [thread overview]
Message-ID: <20240814095614.909774-2-tejas.upadhyay@intel.com> (raw)
In-Reply-To: <20240814095614.909774-1-tejas.upadhyay@intel.com>
enable host l2 VRAM is reading MCR register thus
should be moved after MCR init is done.
V2(Matt):
- Reword commit message
V1(Lucas):
- Reorder patch and reorder flow of L2 VRAM enable
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
drivers/gpu/drm/xe/xe_gt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 58895ed22f6e..238c7d1053f0 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -557,7 +557,6 @@ int xe_gt_init_hwconfig(struct xe_gt *gt)
xe_gt_mcr_init_early(gt);
xe_pat_init(gt);
- xe_gt_enable_host_l2_vram(gt);
err = xe_uc_init(>->uc);
if (err)
@@ -569,6 +568,7 @@ int xe_gt_init_hwconfig(struct xe_gt *gt)
xe_gt_topology_init(gt);
xe_gt_mcr_init(gt);
+ xe_gt_enable_host_l2_vram(gt);
out_fw:
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
--
2.25.1
next prev parent reply other threads:[~2024-08-14 9:54 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-14 9:56 [PATCH V2 0/3] Shuffle enable_host_l2_vram order and use MCR reg Tejas Upadhyay
2024-08-14 9:56 ` Tejas Upadhyay [this message]
2024-08-14 16:34 ` [PATCH V2 1/3] drm/xe: Move enable host l2 VRAM post MCR init Lucas De Marchi
2024-08-14 19:23 ` Matt Roper
2024-08-15 13:56 ` Lucas De Marchi
2024-08-14 9:56 ` [PATCH V2 2/3] drm/xe: Write all slices if its mcr register Tejas Upadhyay
2024-08-14 9:56 ` [PATCH V2 3/3] drm/xe: Define STATELESS_COMPRESSION_CTRL as " Tejas Upadhyay
2024-08-14 15:24 ` Chauhan, Shekhar
2024-08-14 10:01 ` ✓ CI.Patch_applied: success for Shuffle enable_host_l2_vram order and use MCR reg (rev2) Patchwork
2024-08-14 10:02 ` ✓ CI.checkpatch: " Patchwork
2024-08-14 10:04 ` ✓ CI.KUnit: " Patchwork
2024-08-14 10:18 ` ✓ CI.Build: " Patchwork
2024-08-14 10:20 ` ✓ CI.Hooks: " Patchwork
2024-08-14 10:22 ` ✓ CI.checksparse: " Patchwork
2024-08-14 10:49 ` ✓ CI.BAT: " Patchwork
2024-08-14 12:39 ` ✗ CI.FULL: failure " Patchwork
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