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From: Tejas Upadhyay <tejas.upadhyay@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Matt Roper <matthew.d.roper@intel.com>,
	Shekhar Chauhan <shekhar.chauhan@intel.com>,
	Matthew Auld <matthew.auld@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Tejas Upadhyay <tejas.upadhyay@intel.com>
Subject: [PATCH V2 2/3] drm/xe: Write all slices if its mcr register
Date: Wed, 14 Aug 2024 15:26:13 +0530	[thread overview]
Message-ID: <20240814095614.909774-3-tejas.upadhyay@intel.com> (raw)
In-Reply-To: <20240814095614.909774-1-tejas.upadhyay@intel.com>

Register GAMREQSTRM_CTRL should be considered mcr register
which should write to all slices as per documentation.

Bspec: 71185
Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
---
 drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
 drivers/gpu/drm/xe/xe_gt.c           | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 5f33dee35f8a..aeb17fcb27ac 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -83,7 +83,7 @@
 #define STATELESS_COMPRESSION_CTRL		XE_REG(0x4148)
 #define   UNIFIED_COMPRESSION_FORMAT		REG_GENMASK(3, 0)
 
-#define XE2_GAMREQSTRM_CTRL			XE_REG(0x4194)
+#define XE2_GAMREQSTRM_CTRL			XE_REG_MCR(0x4194)
 #define   CG_DIS_CNTLBUS			REG_BIT(6)
 
 #define CCS_AUX_INV				XE_REG(0x4208)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 238c7d1053f0..224c137967c3 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -110,9 +110,9 @@ static void xe_gt_enable_host_l2_vram(struct xe_gt *gt)
 
 	if (!xe_gt_is_media_type(gt)) {
 		xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
-		reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
+		reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
 		reg |= CG_DIS_CNTLBUS;
-		xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
+		xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
 	}
 
 	xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3);
@@ -134,9 +134,9 @@ static void xe_gt_disable_host_l2_vram(struct xe_gt *gt)
 	if (WARN_ON(err))
 		return;
 
-	reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
+	reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
 	reg &= ~CG_DIS_CNTLBUS;
-	xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
+	xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
 
 	xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
 }
-- 
2.25.1


  parent reply	other threads:[~2024-08-14  9:54 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-14  9:56 [PATCH V2 0/3] Shuffle enable_host_l2_vram order and use MCR reg Tejas Upadhyay
2024-08-14  9:56 ` [PATCH V2 1/3] drm/xe: Move enable host l2 VRAM post MCR init Tejas Upadhyay
2024-08-14 16:34   ` Lucas De Marchi
2024-08-14 19:23     ` Matt Roper
2024-08-15 13:56       ` Lucas De Marchi
2024-08-14  9:56 ` Tejas Upadhyay [this message]
2024-08-14  9:56 ` [PATCH V2 3/3] drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register Tejas Upadhyay
2024-08-14 15:24   ` Chauhan, Shekhar
2024-08-14 10:01 ` ✓ CI.Patch_applied: success for Shuffle enable_host_l2_vram order and use MCR reg (rev2) Patchwork
2024-08-14 10:02 ` ✓ CI.checkpatch: " Patchwork
2024-08-14 10:04 ` ✓ CI.KUnit: " Patchwork
2024-08-14 10:18 ` ✓ CI.Build: " Patchwork
2024-08-14 10:20 ` ✓ CI.Hooks: " Patchwork
2024-08-14 10:22 ` ✓ CI.checksparse: " Patchwork
2024-08-14 10:49 ` ✓ CI.BAT: " Patchwork
2024-08-14 12:39 ` ✗ CI.FULL: failure " Patchwork

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