From: "Chauhan, Shekhar" <shekhar.chauhan@intel.com>
To: Tejas Upadhyay <tejas.upadhyay@intel.com>,
<intel-xe@lists.freedesktop.org>
Cc: Matt Roper <matthew.d.roper@intel.com>,
Matthew Auld <matthew.auld@intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [PATCH V2 3/3] drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register
Date: Wed, 14 Aug 2024 20:54:44 +0530 [thread overview]
Message-ID: <d72b05ba-1525-40d2-8e35-cafd396f5012@intel.com> (raw)
In-Reply-To: <20240814095614.909774-4-tejas.upadhyay@intel.com>
Will get to your other patches soon.
On 8/14/2024 3:26 PM, Tejas Upadhyay wrote:
> Register STATELESS_COMPRESSION_CTRL should be considered
> mcr register which should write to all slices as per
> documentation.
>
> Bspec: 71185
> Fixes: ecabb5e6ce54 ("drm/xe/xe2: Add performance turning changes")
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
LGTM,
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index aeb17fcb27ac..0d1a4a9f4e11 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -80,7 +80,7 @@
> #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0)
> #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
>
> -#define STATELESS_COMPRESSION_CTRL XE_REG(0x4148)
> +#define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148)
> #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0)
>
> #define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194)
--
-shekhar
next prev parent reply other threads:[~2024-08-14 15:24 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-14 9:56 [PATCH V2 0/3] Shuffle enable_host_l2_vram order and use MCR reg Tejas Upadhyay
2024-08-14 9:56 ` [PATCH V2 1/3] drm/xe: Move enable host l2 VRAM post MCR init Tejas Upadhyay
2024-08-14 16:34 ` Lucas De Marchi
2024-08-14 19:23 ` Matt Roper
2024-08-15 13:56 ` Lucas De Marchi
2024-08-14 9:56 ` [PATCH V2 2/3] drm/xe: Write all slices if its mcr register Tejas Upadhyay
2024-08-14 9:56 ` [PATCH V2 3/3] drm/xe: Define STATELESS_COMPRESSION_CTRL as " Tejas Upadhyay
2024-08-14 15:24 ` Chauhan, Shekhar [this message]
2024-08-14 10:01 ` ✓ CI.Patch_applied: success for Shuffle enable_host_l2_vram order and use MCR reg (rev2) Patchwork
2024-08-14 10:02 ` ✓ CI.checkpatch: " Patchwork
2024-08-14 10:04 ` ✓ CI.KUnit: " Patchwork
2024-08-14 10:18 ` ✓ CI.Build: " Patchwork
2024-08-14 10:20 ` ✓ CI.Hooks: " Patchwork
2024-08-14 10:22 ` ✓ CI.checksparse: " Patchwork
2024-08-14 10:49 ` ✓ CI.BAT: " Patchwork
2024-08-14 12:39 ` ✗ CI.FULL: failure " Patchwork
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