Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 14/14] drm/i915: Eliminate intel_compute_sagv_mask()
Date: Fri,  7 Mar 2025 20:01:39 +0200	[thread overview]
Message-ID: <20250307180139.15744-15-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20250307180139.15744-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_compute_sagv_mask() has become pointless. Just inline
its contents into the existing loop in skl_compute_wm().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 64 ++++++++------------
 1 file changed, 24 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index ccb312401896..e0fd8e2c6873 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -455,42 +455,6 @@ bool intel_can_enable_sagv(struct drm_i915_private *i915,
 	return bw_state->pipe_sagv_reject == 0;
 }
 
-static int intel_compute_sagv_mask(struct intel_atomic_state *state)
-{
-	struct intel_display *display = to_intel_display(state);
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	struct intel_crtc *crtc;
-	struct intel_crtc_state *new_crtc_state;
-	int i;
-
-	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
-		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
-
-		/*
-		 * We store use_sagv_wm in the crtc state rather than relying on
-		 * that bw state since we have no convenient way to get at the
-		 * latter from the plane commit hooks (especially in the legacy
-		 * cursor case).
-		 *
-		 * drm_atomic_check_only() gets upset if we pull more crtcs
-		 * into the state, so we have to calculate this based on the
-		 * individual intel_crtc_can_enable_sagv() rather than
-		 * the overall intel_can_enable_sagv(). Otherwise the
-		 * crtcs not included in the commit would not switch to the
-		 * SAGV watermarks when we are about to enable SAGV, and that
-		 * would lead to underruns. This does mean extra power draw
-		 * when only a subset of the crtcs are blocking SAGV as the
-		 * other crtcs can't be allowed to use the more optimal
-		 * normal (ie. non-SAGV) watermarks.
-		 */
-		pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) &&
-			DISPLAY_VER(i915) >= 12 &&
-			intel_crtc_can_enable_sagv(new_crtc_state);
-	}
-
-	return 0;
-}
-
 static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
 			      u16 start, u16 end)
 {
@@ -3022,6 +2986,7 @@ intel_program_dpkgc_latency(struct intel_atomic_state *state)
 static int
 skl_compute_wm(struct intel_atomic_state *state)
 {
+	struct intel_display *display = to_intel_display(state);
 	struct intel_crtc *crtc;
 	struct intel_crtc_state __maybe_unused *new_crtc_state;
 	int ret, i;
@@ -3036,16 +3001,35 @@ skl_compute_wm(struct intel_atomic_state *state)
 	if (ret)
 		return ret;
 
-	ret = intel_compute_sagv_mask(state);
-	if (ret)
-		return ret;
-
 	/*
 	 * skl_compute_ddb() will have adjusted the final watermarks
 	 * based on how much ddb is available. Now we can actually
 	 * check if the final watermarks changed.
 	 */
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+		/*
+		 * We store use_sagv_wm in the crtc state rather than relying on
+		 * that bw state since we have no convenient way to get at the
+		 * latter from the plane commit hooks (especially in the legacy
+		 * cursor case).
+		 *
+		 * drm_atomic_check_only() gets upset if we pull more crtcs
+		 * into the state, so we have to calculate this based on the
+		 * individual intel_crtc_can_enable_sagv() rather than
+		 * the overall intel_can_enable_sagv(). Otherwise the
+		 * crtcs not included in the commit would not switch to the
+		 * SAGV watermarks when we are about to enable SAGV, and that
+		 * would lead to underruns. This does mean extra power draw
+		 * when only a subset of the crtcs are blocking SAGV as the
+		 * other crtcs can't be allowed to use the more optimal
+		 * normal (ie. non-SAGV) watermarks.
+		 */
+		pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(display) &&
+			DISPLAY_VER(display) >= 12 &&
+			intel_crtc_can_enable_sagv(new_crtc_state);
+
 		ret = skl_wm_add_affected_planes(state, crtc);
 		if (ret)
 			return ret;
-- 
2.45.3


  parent reply	other threads:[~2025-03-07 18:02 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-07 18:01 [PATCH 00/14] drm/i915: sagv/bw cleanup Ville Syrjala
2025-03-07 18:01 ` [PATCH 01/14] drm/i915: Drop the cached per-pipe min_cdclk[] from bw state Ville Syrjala
2025-03-07 18:01 ` [PATCH 02/14] drm/i915: s/intel_crtc_bw/intel_dbuf_bw/ Ville Syrjala
2025-03-07 18:01 ` [PATCH 03/14] drm/i915: Extract intel_dbuf_bw_changed() Ville Syrjala
2025-03-07 18:01 ` [PATCH 04/14] drm/i915: Pass intel_dbuf_bw to skl_*_calc_dbuf_bw() explicitly Ville Syrjala
2025-03-07 18:01 ` [PATCH 05/14] drm/i915: Avoid triggering unwanted cdclk changes due to dbuf bandwidth changes Ville Syrjala
2025-03-07 18:01 ` [PATCH 06/14] drm/i915: Do more bw readout Ville Syrjala
2025-03-07 18:01 ` [PATCH 07/14] drm/i915: Flag even inactive crtcs as "inherited" Ville Syrjala
2025-03-07 18:01 ` [PATCH 08/14] drm/i915: Drop force_check_qgv Ville Syrjala
2025-03-07 18:01 ` [PATCH 09/14] drm/i915: Extract intel_bw_modeset_checks() Ville Syrjala
2025-03-07 18:01 ` [PATCH 10/14] drm/i915: Extract intel_bw_check_sagv_mask() Ville Syrjala
2025-03-07 18:01 ` [PATCH 11/14] drm/i915: Make intel_bw_check_sagv_mask() internal to intel_bw.c Ville Syrjala
2025-03-07 18:01 ` [PATCH 12/14] drm/i915: Make intel_bw_modeset_checks() internal to intel_bw_atomic_check() Ville Syrjala
2025-03-07 18:01 ` [PATCH 13/14] drm/i915: Skip bw stuff if per-crtc sagv state doesn't change Ville Syrjala
2025-03-07 18:01 ` Ville Syrjala [this message]
2025-03-07 19:11 ` ✓ CI.Patch_applied: success for drm/i915: sagv/bw cleanup Patchwork
2025-03-07 19:12 ` ✗ CI.checkpatch: warning " Patchwork
2025-03-07 19:13 ` ✓ CI.KUnit: success " Patchwork
2025-03-07 19:29 ` ✓ CI.Build: " Patchwork
2025-03-07 19:32 ` ✓ CI.Hooks: " Patchwork
2025-03-07 19:33 ` ✗ CI.checksparse: warning " Patchwork
2025-03-07 19:56 ` ✓ Xe.CI.BAT: success " Patchwork
2025-03-08 23:24 ` ✗ Xe.CI.Full: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20250307180139.15744-15-ville.syrjala@linux.intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-xe@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox