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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 02/14] drm/i915: s/intel_crtc_bw/intel_dbuf_bw/
Date: Fri,  7 Mar 2025 20:01:27 +0200	[thread overview]
Message-ID: <20250307180139.15744-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20250307180139.15744-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename the intel_crtc_bw struct to intel_dbuf_bw to better
reflect what it does.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 7b9ae926c5c4..2bc020690515 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1124,15 +1124,15 @@ static bool intel_bw_state_changed(struct drm_i915_private *i915,
 	enum pipe pipe;
 
 	for_each_pipe(i915, pipe) {
-		const struct intel_dbuf_bw *old_crtc_bw =
+		const struct intel_dbuf_bw *old_dbuf_bw =
 			&old_bw_state->dbuf_bw[pipe];
-		const struct intel_dbuf_bw *new_crtc_bw =
+		const struct intel_dbuf_bw *new_dbuf_bw =
 			&new_bw_state->dbuf_bw[pipe];
 		enum dbuf_slice slice;
 
 		for_each_dbuf_slice(i915, slice) {
-			if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
-			    old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
+			if (old_dbuf_bw->max_bw[slice] != new_dbuf_bw->max_bw[slice] ||
+			    old_dbuf_bw->active_planes[slice] != new_dbuf_bw->active_planes[slice])
 				return true;
 		}
 
@@ -1151,7 +1151,7 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
 				   unsigned int data_rate)
 {
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
+	struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[crtc->pipe];
 	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
 	enum dbuf_slice slice;
 
@@ -1160,8 +1160,8 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
 	 * equal share of the total bw to each plane.
 	 */
 	for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
-		crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
-		crtc_bw->active_planes[slice] |= BIT(plane_id);
+		dbuf_bw->max_bw[slice] = max(dbuf_bw->max_bw[slice], data_rate);
+		dbuf_bw->active_planes[slice] |= BIT(plane_id);
 	}
 }
 
@@ -1170,10 +1170,10 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
+	struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[crtc->pipe];
 	enum plane_id plane_id;
 
-	memset(crtc_bw, 0, sizeof(*crtc_bw));
+	memset(dbuf_bw, 0, sizeof(*dbuf_bw));
 
 	if (!crtc_state->hw.active)
 		return;
@@ -1215,10 +1215,10 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
 		 * equal share of the total bw to each plane.
 		 */
 		for_each_pipe(i915, pipe) {
-			const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
+			const struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[pipe];
 
-			max_bw = max(crtc_bw->max_bw[slice], max_bw);
-			num_active_planes += hweight8(crtc_bw->active_planes[slice]);
+			max_bw = max(dbuf_bw->max_bw[slice], max_bw);
+			num_active_planes += hweight8(dbuf_bw->active_planes[slice]);
 		}
 		max_bw *= num_active_planes;
 
-- 
2.45.3


  parent reply	other threads:[~2025-03-07 18:01 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-07 18:01 [PATCH 00/14] drm/i915: sagv/bw cleanup Ville Syrjala
2025-03-07 18:01 ` [PATCH 01/14] drm/i915: Drop the cached per-pipe min_cdclk[] from bw state Ville Syrjala
2025-03-07 18:01 ` Ville Syrjala [this message]
2025-03-07 18:01 ` [PATCH 03/14] drm/i915: Extract intel_dbuf_bw_changed() Ville Syrjala
2025-03-07 18:01 ` [PATCH 04/14] drm/i915: Pass intel_dbuf_bw to skl_*_calc_dbuf_bw() explicitly Ville Syrjala
2025-03-07 18:01 ` [PATCH 05/14] drm/i915: Avoid triggering unwanted cdclk changes due to dbuf bandwidth changes Ville Syrjala
2025-03-07 18:01 ` [PATCH 06/14] drm/i915: Do more bw readout Ville Syrjala
2025-03-07 18:01 ` [PATCH 07/14] drm/i915: Flag even inactive crtcs as "inherited" Ville Syrjala
2025-03-07 18:01 ` [PATCH 08/14] drm/i915: Drop force_check_qgv Ville Syrjala
2025-03-07 18:01 ` [PATCH 09/14] drm/i915: Extract intel_bw_modeset_checks() Ville Syrjala
2025-03-07 18:01 ` [PATCH 10/14] drm/i915: Extract intel_bw_check_sagv_mask() Ville Syrjala
2025-03-07 18:01 ` [PATCH 11/14] drm/i915: Make intel_bw_check_sagv_mask() internal to intel_bw.c Ville Syrjala
2025-03-07 18:01 ` [PATCH 12/14] drm/i915: Make intel_bw_modeset_checks() internal to intel_bw_atomic_check() Ville Syrjala
2025-03-07 18:01 ` [PATCH 13/14] drm/i915: Skip bw stuff if per-crtc sagv state doesn't change Ville Syrjala
2025-03-07 18:01 ` [PATCH 14/14] drm/i915: Eliminate intel_compute_sagv_mask() Ville Syrjala
2025-03-07 19:11 ` ✓ CI.Patch_applied: success for drm/i915: sagv/bw cleanup Patchwork
2025-03-07 19:12 ` ✗ CI.checkpatch: warning " Patchwork
2025-03-07 19:13 ` ✓ CI.KUnit: success " Patchwork
2025-03-07 19:29 ` ✓ CI.Build: " Patchwork
2025-03-07 19:32 ` ✓ CI.Hooks: " Patchwork
2025-03-07 19:33 ` ✗ CI.checksparse: warning " Patchwork
2025-03-07 19:56 ` ✓ Xe.CI.BAT: success " Patchwork
2025-03-08 23:24 ` ✗ Xe.CI.Full: failure " Patchwork

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