From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org
Subject: [PATCH 08/14] drm/i915: Drop force_check_qgv
Date: Fri, 7 Mar 2025 20:01:33 +0200 [thread overview]
Message-ID: <20250307180139.15744-9-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20250307180139.15744-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Remove the force_check_qgv flag and just fill the pipe_sagv_reject
bitmask properly during readout. This will cause the initial commit
to re-enable SAGV if possible.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_bw.h | 6 ------
2 files changed, 6 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index bbb040be0502..e11fd94e9e29 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1399,9 +1399,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
new_bw_state = intel_atomic_get_new_bw_state(state);
if (new_bw_state &&
- (intel_can_enable_sagv(i915, old_bw_state) !=
- intel_can_enable_sagv(i915, new_bw_state) ||
- new_bw_state->force_check_qgv))
+ intel_can_enable_sagv(i915, old_bw_state) !=
+ intel_can_enable_sagv(i915, new_bw_state))
changed = true;
/*
@@ -1415,8 +1414,6 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
if (ret)
return ret;
- new_bw_state->force_check_qgv = false;
-
return 0;
}
@@ -1430,7 +1427,6 @@ static void intel_bw_crtc_update(struct intel_bw_state *bw_state,
intel_bw_crtc_data_rate(crtc_state);
bw_state->num_active_planes[crtc->pipe] =
intel_bw_crtc_num_active_planes(crtc_state);
- bw_state->force_check_qgv = true;
drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
@@ -1448,6 +1444,7 @@ void intel_bw_update_hw_state(struct intel_display *display)
return;
bw_state->active_pipes = 0;
+ bw_state->pipe_sagv_reject = 0;
for_each_intel_crtc(display->drm, crtc) {
const struct intel_crtc_state *crtc_state =
@@ -1461,6 +1458,9 @@ void intel_bw_update_hw_state(struct intel_display *display)
intel_bw_crtc_update(bw_state, crtc_state);
skl_crtc_calc_dbuf_bw(&bw_state->dbuf_bw[pipe], crtc_state);
+
+ /* initially SAGV has been forced off */
+ bw_state->pipe_sagv_reject |= BIT(pipe);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index e977c3586dc3..d3f92951b057 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -49,12 +49,6 @@ struct intel_bw_state {
*/
u16 qgv_points_mask;
- /*
- * Flag to force the QGV comparison in atomic check right after the
- * hw state readout
- */
- bool force_check_qgv;
-
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
--
2.45.3
next prev parent reply other threads:[~2025-03-07 18:02 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-07 18:01 [PATCH 00/14] drm/i915: sagv/bw cleanup Ville Syrjala
2025-03-07 18:01 ` [PATCH 01/14] drm/i915: Drop the cached per-pipe min_cdclk[] from bw state Ville Syrjala
2025-03-07 18:01 ` [PATCH 02/14] drm/i915: s/intel_crtc_bw/intel_dbuf_bw/ Ville Syrjala
2025-03-07 18:01 ` [PATCH 03/14] drm/i915: Extract intel_dbuf_bw_changed() Ville Syrjala
2025-03-07 18:01 ` [PATCH 04/14] drm/i915: Pass intel_dbuf_bw to skl_*_calc_dbuf_bw() explicitly Ville Syrjala
2025-03-07 18:01 ` [PATCH 05/14] drm/i915: Avoid triggering unwanted cdclk changes due to dbuf bandwidth changes Ville Syrjala
2025-03-07 18:01 ` [PATCH 06/14] drm/i915: Do more bw readout Ville Syrjala
2025-03-07 18:01 ` [PATCH 07/14] drm/i915: Flag even inactive crtcs as "inherited" Ville Syrjala
2025-03-07 18:01 ` Ville Syrjala [this message]
2025-03-07 18:01 ` [PATCH 09/14] drm/i915: Extract intel_bw_modeset_checks() Ville Syrjala
2025-03-07 18:01 ` [PATCH 10/14] drm/i915: Extract intel_bw_check_sagv_mask() Ville Syrjala
2025-03-07 18:01 ` [PATCH 11/14] drm/i915: Make intel_bw_check_sagv_mask() internal to intel_bw.c Ville Syrjala
2025-03-07 18:01 ` [PATCH 12/14] drm/i915: Make intel_bw_modeset_checks() internal to intel_bw_atomic_check() Ville Syrjala
2025-03-07 18:01 ` [PATCH 13/14] drm/i915: Skip bw stuff if per-crtc sagv state doesn't change Ville Syrjala
2025-03-07 18:01 ` [PATCH 14/14] drm/i915: Eliminate intel_compute_sagv_mask() Ville Syrjala
2025-03-07 19:11 ` ✓ CI.Patch_applied: success for drm/i915: sagv/bw cleanup Patchwork
2025-03-07 19:12 ` ✗ CI.checkpatch: warning " Patchwork
2025-03-07 19:13 ` ✓ CI.KUnit: success " Patchwork
2025-03-07 19:29 ` ✓ CI.Build: " Patchwork
2025-03-07 19:32 ` ✓ CI.Hooks: " Patchwork
2025-03-07 19:33 ` ✗ CI.checksparse: warning " Patchwork
2025-03-07 19:56 ` ✓ Xe.CI.BAT: success " Patchwork
2025-03-08 23:24 ` ✗ Xe.CI.Full: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250307180139.15744-9-ville.syrjala@linux.intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=intel-xe@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox