[PATCH 0/9] drm/i915: Reorder cdclk stuff for vblank/guardband length checks

[PATCH 0/9] drm/i915: Reorder cdclk stuff for vblank/guardband length checks

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently skl_is_vblank_too_short() is trying to do the
prefill vs. vblank/guardband length checks using a completely
stale cdclk frequency. Attempt to shuffle thigns around
sufficiently so that we might be able to remedy it. Note however
that this series does not yet fix the actual cdclk factor used
in the checks. That part will come in a separate series.

I also took the opportunity to carve up intel_bw.c a bit since
it's basically made up of three completely independent things.
While not strictly necessary for the reordering, it's nice to
untangle intel_bw.c for clarity.

Ville Syrjälä (9):
  drm/i915/bw: Untangle dbuf bw from the sagv/mem bw stuff
  drm/i915: s/"not not"/"not"/
  drm/i915/bw: Relocate intel_bw_crtc_min_cdclk()
  drm/i915/ips: Eliminate the cdclk_state stuff from
    hsw_ips_compute_config()
  drm/i915/fbc: Decouple FBC from intel_cdclk_atomic_check()
  drm/i915: s/min_cdck[]/plane_min_cdclk[]/
  drm/i915: Compute per-crtc min_cdclk earlier
  drm/i915: Include the per-crtc minimum cdclk in the crtc state dump
  drm/i915: Neuter cdclk_prefill_adjustment()

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/hsw_ips.c        |  61 ++--
 drivers/gpu/drm/i915/display/intel_bw.c       | 247 +--------------
 drivers/gpu/drm/i915/display/intel_bw.h       |   5 -
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  46 ++-
 drivers/gpu/drm/i915/display/intel_cdclk.h    |   9 +-
 drivers/gpu/drm/i915/display/intel_crtc.c     |  44 +++
 drivers/gpu/drm/i915/display/intel_crtc.h     |   4 +
 .../drm/i915/display/intel_crtc_state_dump.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_dbuf_bw.c  | 295 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dbuf_bw.h  |  37 +++
 drivers/gpu/drm/i915/display/intel_display.c  |   3 +
 .../gpu/drm/i915/display/intel_display_core.h |   4 +
 .../drm/i915/display/intel_display_driver.c   |   5 +
 .../drm/i915/display/intel_display_types.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_fbc.c      |  49 ++-
 drivers/gpu/drm/i915/display/intel_fbc.h      |   1 +
 .../drm/i915/display/intel_modeset_setup.c    |  14 +-
 drivers/gpu/drm/i915/display/intel_plane.c    |   4 +-
 drivers/gpu/drm/i915/display/skl_watermark.c  |  14 +-
 drivers/gpu/drm/xe/Makefile                   |   1 +
 21 files changed, 510 insertions(+), 342 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dbuf_bw.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dbuf_bw.h

-- 
2.49.1

[PATCH 1/9] drm/i915/bw: Untangle dbuf bw from the sagv/mem bw stuff

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently intel_bw.c contains basically three completely independent
parts:
- SAGV/memory bandwidth handling
- DBuf bandwidth handling
- "Maximum pipe read bandwidth" calculation, which is some kind
  of internal per-pipe bandwidth limit.

Carve out the DBuf bandwdith handling into a separate file since
there is no actual dependency between it and the rest of intel_bw.c.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_bw.c       | 191 ------------
 drivers/gpu/drm/i915/display/intel_bw.h       |   4 -
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  32 +-
 drivers/gpu/drm/i915/display/intel_cdclk.h    |   7 +-
 drivers/gpu/drm/i915/display/intel_dbuf_bw.c  | 295 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dbuf_bw.h  |  37 +++
 .../gpu/drm/i915/display/intel_display_core.h |   4 +
 .../drm/i915/display/intel_display_driver.c   |   5 +
 .../drm/i915/display/intel_modeset_setup.c    |   3 +
 drivers/gpu/drm/xe/Makefile                   |   1 +
 11 files changed, 363 insertions(+), 217 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dbuf_bw.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_dbuf_bw.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 6d7800e25e55..dbdf88b42919 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -241,6 +241,7 @@ i915-y += \
 	display/intel_crtc.o \
 	display/intel_crtc_state_dump.o \
 	display/intel_cursor.o \
+	display/intel_dbuf_bw.o \
 	display/intel_display.o \
 	display/intel_display_conversion.o \
 	display/intel_display_driver.o \
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index b53bcb693e79..a4d16711d336 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -3,16 +3,12 @@
  * Copyright © 2019 Intel Corporation
  */
 
-#include <drm/drm_atomic_state_helper.h>
-
 #include "soc/intel_dram.h"
 
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "i915_utils.h"
-#include "intel_atomic.h"
 #include "intel_bw.h"
-#include "intel_cdclk.h"
 #include "intel_crtc.h"
 #include "intel_display_core.h"
 #include "intel_display_regs.h"
@@ -22,14 +18,8 @@
 #include "intel_uncore.h"
 #include "skl_watermark.h"
 
-struct intel_dbuf_bw {
-	unsigned int max_bw[I915_MAX_DBUF_SLICES];
-	u8 active_planes[I915_MAX_DBUF_SLICES];
-};
-
 struct intel_bw_state {
 	struct intel_global_state base;
-	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
 
 	/*
 	 * Contains a bit mask, used to determine, whether correspondent
@@ -1264,184 +1254,6 @@ static int intel_bw_check_qgv_points(struct intel_display *display,
 					   old_bw_state, new_bw_state);
 }
 
-static bool intel_dbuf_bw_changed(struct intel_display *display,
-				  const struct intel_dbuf_bw *old_dbuf_bw,
-				  const struct intel_dbuf_bw *new_dbuf_bw)
-{
-	enum dbuf_slice slice;
-
-	for_each_dbuf_slice(display, slice) {
-		if (old_dbuf_bw->max_bw[slice] != new_dbuf_bw->max_bw[slice] ||
-		    old_dbuf_bw->active_planes[slice] != new_dbuf_bw->active_planes[slice])
-			return true;
-	}
-
-	return false;
-}
-
-static bool intel_bw_state_changed(struct intel_display *display,
-				   const struct intel_bw_state *old_bw_state,
-				   const struct intel_bw_state *new_bw_state)
-{
-	enum pipe pipe;
-
-	for_each_pipe(display, pipe) {
-		const struct intel_dbuf_bw *old_dbuf_bw =
-			&old_bw_state->dbuf_bw[pipe];
-		const struct intel_dbuf_bw *new_dbuf_bw =
-			&new_bw_state->dbuf_bw[pipe];
-
-		if (intel_dbuf_bw_changed(display, old_dbuf_bw, new_dbuf_bw))
-			return true;
-	}
-
-	return false;
-}
-
-static void skl_plane_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw,
-				   struct intel_crtc *crtc,
-				   enum plane_id plane_id,
-				   const struct skl_ddb_entry *ddb,
-				   unsigned int data_rate)
-{
-	struct intel_display *display = to_intel_display(crtc);
-	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);
-	enum dbuf_slice slice;
-
-	/*
-	 * The arbiter can only really guarantee an
-	 * equal share of the total bw to each plane.
-	 */
-	for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) {
-		dbuf_bw->max_bw[slice] = max(dbuf_bw->max_bw[slice], data_rate);
-		dbuf_bw->active_planes[slice] |= BIT(plane_id);
-	}
-}
-
-static void skl_crtc_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw,
-				  const struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(crtc_state);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	enum plane_id plane_id;
-
-	memset(dbuf_bw, 0, sizeof(*dbuf_bw));
-
-	if (!crtc_state->hw.active)
-		return;
-
-	for_each_plane_id_on_crtc(crtc, plane_id) {
-		/*
-		 * We assume cursors are small enough
-		 * to not cause bandwidth problems.
-		 */
-		if (plane_id == PLANE_CURSOR)
-			continue;
-
-		skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,
-				       &crtc_state->wm.skl.plane_ddb[plane_id],
-				       crtc_state->data_rate[plane_id]);
-
-		if (DISPLAY_VER(display) < 11)
-			skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,
-					       &crtc_state->wm.skl.plane_ddb_y[plane_id],
-					       crtc_state->data_rate[plane_id]);
-	}
-}
-
-/* "Maximum Data Buffer Bandwidth" */
-static int
-intel_bw_dbuf_min_cdclk(struct intel_display *display,
-			const struct intel_bw_state *bw_state)
-{
-	unsigned int total_max_bw = 0;
-	enum dbuf_slice slice;
-
-	for_each_dbuf_slice(display, slice) {
-		int num_active_planes = 0;
-		unsigned int max_bw = 0;
-		enum pipe pipe;
-
-		/*
-		 * The arbiter can only really guarantee an
-		 * equal share of the total bw to each plane.
-		 */
-		for_each_pipe(display, pipe) {
-			const struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[pipe];
-
-			max_bw = max(dbuf_bw->max_bw[slice], max_bw);
-			num_active_planes += hweight8(dbuf_bw->active_planes[slice]);
-		}
-		max_bw *= num_active_planes;
-
-		total_max_bw = max(total_max_bw, max_bw);
-	}
-
-	return DIV_ROUND_UP(total_max_bw, 64);
-}
-
-int intel_bw_min_cdclk(struct intel_display *display,
-		       const struct intel_bw_state *bw_state)
-{
-	int min_cdclk;
-
-	min_cdclk = intel_bw_dbuf_min_cdclk(display, bw_state);
-
-	return min_cdclk;
-}
-
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
-			    bool *need_cdclk_calc)
-{
-	struct intel_display *display = to_intel_display(state);
-	struct intel_bw_state *new_bw_state = NULL;
-	const struct intel_bw_state *old_bw_state = NULL;
-	const struct intel_crtc_state *old_crtc_state;
-	const struct intel_crtc_state *new_crtc_state;
-	struct intel_crtc *crtc;
-	int ret, i;
-
-	if (DISPLAY_VER(display) < 9)
-		return 0;
-
-	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
-					    new_crtc_state, i) {
-		struct intel_dbuf_bw old_dbuf_bw, new_dbuf_bw;
-
-		skl_crtc_calc_dbuf_bw(&old_dbuf_bw, old_crtc_state);
-		skl_crtc_calc_dbuf_bw(&new_dbuf_bw, new_crtc_state);
-
-		if (!intel_dbuf_bw_changed(display, &old_dbuf_bw, &new_dbuf_bw))
-			continue;
-
-		new_bw_state = intel_atomic_get_bw_state(state);
-		if (IS_ERR(new_bw_state))
-			return PTR_ERR(new_bw_state);
-
-		old_bw_state = intel_atomic_get_old_bw_state(state);
-
-		new_bw_state->dbuf_bw[crtc->pipe] = new_dbuf_bw;
-	}
-
-	if (!old_bw_state)
-		return 0;
-
-	if (intel_bw_state_changed(display, old_bw_state, new_bw_state)) {
-		int ret = intel_atomic_lock_global_state(&new_bw_state->base);
-		if (ret)
-			return ret;
-	}
-
-	ret = intel_cdclk_update_bw_min_cdclk(state,
-					      intel_bw_min_cdclk(display, old_bw_state),
-					      intel_bw_min_cdclk(display, new_bw_state),
-					      need_cdclk_calc);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
 static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
 {
 	struct intel_display *display = to_intel_display(state);
@@ -1647,8 +1459,6 @@ void intel_bw_update_hw_state(struct intel_display *display)
 		if (DISPLAY_VER(display) >= 11)
 			intel_bw_crtc_update(bw_state, crtc_state);
 
-		skl_crtc_calc_dbuf_bw(&bw_state->dbuf_bw[pipe], crtc_state);
-
 		/* initially SAGV has been forced off */
 		bw_state->pipe_sagv_reject |= BIT(pipe);
 	}
@@ -1666,7 +1476,6 @@ void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc)
 
 	bw_state->data_rate[pipe] = 0;
 	bw_state->num_active_planes[pipe] = 0;
-	memset(&bw_state->dbuf_bw[pipe], 0, sizeof(bw_state->dbuf_bw[pipe]));
 }
 
 static struct intel_global_state *
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 4bb3a637b295..051e163f2f15 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -30,10 +30,6 @@ void intel_bw_init_hw(struct intel_display *display);
 int intel_bw_init(struct intel_display *display);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
 int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);
-int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
-			    bool *need_cdclk_calc);
-int intel_bw_min_cdclk(struct intel_display *display,
-		       const struct intel_bw_state *bw_state);
 void intel_bw_update_hw_state(struct intel_display *display);
 void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f2e092f89ddd..23b9e100d824 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -38,6 +38,7 @@
 #include "intel_bw.h"
 #include "intel_cdclk.h"
 #include "intel_crtc.h"
+#include "intel_dbuf_bw.h"
 #include "intel_de.h"
 #include "intel_display_regs.h"
 #include "intel_display_types.h"
@@ -133,8 +134,8 @@ struct intel_cdclk_state {
 	 */
 	struct intel_cdclk_config actual;
 
-	/* minimum acceptable cdclk to satisfy bandwidth requirements */
-	int bw_min_cdclk;
+	/* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */
+	int dbuf_bw_min_cdclk;
 	/* minimum acceptable cdclk for each pipe */
 	int min_cdclk[I915_MAX_PIPES];
 	/* minimum acceptable voltage level for each pipe */
@@ -2891,9 +2892,9 @@ static int intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state,
 	return 0;
 }
 
-int intel_cdclk_update_bw_min_cdclk(struct intel_atomic_state *state,
-				    int old_min_cdclk, int new_min_cdclk,
-				    bool *need_cdclk_calc)
+int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state,
+					 int old_min_cdclk, int new_min_cdclk,
+					 bool *need_cdclk_calc)
 {
 	struct intel_display *display = to_intel_display(state);
 	struct intel_cdclk_state *cdclk_state;
@@ -2910,7 +2911,7 @@ int intel_cdclk_update_bw_min_cdclk(struct intel_atomic_state *state,
 	if (IS_ERR(cdclk_state))
 		return PTR_ERR(cdclk_state);
 
-	old_min_cdclk = cdclk_state->bw_min_cdclk;
+	old_min_cdclk = cdclk_state->dbuf_bw_min_cdclk;
 
 	if (new_min_cdclk == old_min_cdclk)
 		return 0;
@@ -2918,7 +2919,7 @@ int intel_cdclk_update_bw_min_cdclk(struct intel_atomic_state *state,
 	if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
 		return 0;
 
-	cdclk_state->bw_min_cdclk = new_min_cdclk;
+	cdclk_state->dbuf_bw_min_cdclk = new_min_cdclk;
 
 	ret = intel_atomic_lock_global_state(&cdclk_state->base);
 	if (ret)
@@ -2927,7 +2928,7 @@ int intel_cdclk_update_bw_min_cdclk(struct intel_atomic_state *state,
 	*need_cdclk_calc = true;
 
 	drm_dbg_kms(display->drm,
-		    "bandwidth min cdclk: %d kHz -> %d kHz\n",
+		    "dbuf bandwidth min cdclk: %d kHz -> %d kHz\n",
 		    old_min_cdclk, new_min_cdclk);
 
 	return 0;
@@ -2950,7 +2951,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
 	int min_cdclk;
 
 	min_cdclk = cdclk_state->force_min_cdclk;
-	min_cdclk = max(min_cdclk, cdclk_state->bw_min_cdclk);
+	min_cdclk = max(min_cdclk, cdclk_state->dbuf_bw_min_cdclk);
 	for_each_pipe(display, pipe)
 		min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);
 
@@ -3476,7 +3477,7 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state)
 	if (ret)
 		return ret;
 
-	ret = intel_bw_calc_min_cdclk(state, &need_cdclk_calc);
+	ret = intel_dbuf_bw_calc_min_cdclk(state, &need_cdclk_calc);
 	if (ret)
 		return ret;
 
@@ -3503,8 +3504,8 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state)
 
 void intel_cdclk_update_hw_state(struct intel_display *display)
 {
-	const struct intel_bw_state *bw_state =
-		to_intel_bw_state(display->bw.obj.state);
+	const struct intel_dbuf_bw_state *dbuf_bw_state =
+		to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
 	struct intel_cdclk_state *cdclk_state =
 		to_intel_cdclk_state(display->cdclk.obj.state);
 	struct intel_crtc *crtc;
@@ -3526,7 +3527,7 @@ void intel_cdclk_update_hw_state(struct intel_display *display)
 		cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
 	}
 
-	cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(display, bw_state);
+	cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state);
 }
 
 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc)
@@ -4020,11 +4021,6 @@ int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe
 	return cdclk_state->min_cdclk[pipe];
 }
 
-int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state)
-{
-	return cdclk_state->bw_min_cdclk;
-}
-
 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)
 {
 	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 72963f6f399a..d9d7a8b3a48a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -46,9 +46,9 @@ struct intel_cdclk_state *
 intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
 void intel_cdclk_update_hw_state(struct intel_display *display);
 void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc);
-int intel_cdclk_update_bw_min_cdclk(struct intel_atomic_state *state,
-				    int old_min_cdclk, int new_min_cdclk,
-				    bool *need_cdclk_calc);
+int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state,
+					 int old_min_cdclk, int new_min_cdclk,
+					 bool *need_cdclk_calc);
 
 #define to_intel_cdclk_state(global_state) \
 	container_of_const((global_state), struct intel_cdclk_state, base)
@@ -65,7 +65,6 @@ int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
-int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
 void intel_cdclk_read_hw(struct intel_display *display);
diff --git a/drivers/gpu/drm/i915/display/intel_dbuf_bw.c b/drivers/gpu/drm/i915/display/intel_dbuf_bw.c
new file mode 100644
index 000000000000..8b8894c37f63
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dbuf_bw.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#include <drm/drm_print.h>
+
+#include "intel_dbuf_bw.h"
+#include "intel_display_core.h"
+#include "intel_display_types.h"
+#include "skl_watermark.h"
+
+struct intel_dbuf_bw {
+	unsigned int max_bw[I915_MAX_DBUF_SLICES];
+	u8 active_planes[I915_MAX_DBUF_SLICES];
+};
+
+struct intel_dbuf_bw_state {
+	struct intel_global_state base;
+	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
+};
+
+struct intel_dbuf_bw_state *to_intel_dbuf_bw_state(struct intel_global_state *obj_state)
+{
+	return container_of(obj_state, struct intel_dbuf_bw_state, base);
+}
+
+struct intel_dbuf_bw_state *
+intel_atomic_get_old_dbuf_bw_state(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_global_state *dbuf_bw_state;
+
+	dbuf_bw_state = intel_atomic_get_old_global_obj_state(state, &display->dbuf_bw.obj);
+
+	return to_intel_dbuf_bw_state(dbuf_bw_state);
+}
+
+struct intel_dbuf_bw_state *
+intel_atomic_get_new_dbuf_bw_state(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_global_state *dbuf_bw_state;
+
+	dbuf_bw_state = intel_atomic_get_new_global_obj_state(state, &display->dbuf_bw.obj);
+
+	return to_intel_dbuf_bw_state(dbuf_bw_state);
+}
+
+struct intel_dbuf_bw_state *
+intel_atomic_get_dbuf_bw_state(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_global_state *dbuf_bw_state;
+
+	dbuf_bw_state = intel_atomic_get_global_obj_state(state, &display->dbuf_bw.obj);
+	if (IS_ERR(dbuf_bw_state))
+		return ERR_CAST(dbuf_bw_state);
+
+	return to_intel_dbuf_bw_state(dbuf_bw_state);
+}
+
+static bool intel_dbuf_bw_changed(struct intel_display *display,
+				  const struct intel_dbuf_bw *old_dbuf_bw,
+				  const struct intel_dbuf_bw *new_dbuf_bw)
+{
+	enum dbuf_slice slice;
+
+	for_each_dbuf_slice(display, slice) {
+		if (old_dbuf_bw->max_bw[slice] != new_dbuf_bw->max_bw[slice] ||
+		    old_dbuf_bw->active_planes[slice] != new_dbuf_bw->active_planes[slice])
+			return true;
+	}
+
+	return false;
+}
+
+static bool intel_dbuf_bw_state_changed(struct intel_display *display,
+					const struct intel_dbuf_bw_state *old_dbuf_bw_state,
+					const struct intel_dbuf_bw_state *new_dbuf_bw_state)
+{
+	enum pipe pipe;
+
+	for_each_pipe(display, pipe) {
+		const struct intel_dbuf_bw *old_dbuf_bw =
+			&old_dbuf_bw_state->dbuf_bw[pipe];
+		const struct intel_dbuf_bw *new_dbuf_bw =
+			&new_dbuf_bw_state->dbuf_bw[pipe];
+
+		if (intel_dbuf_bw_changed(display, old_dbuf_bw, new_dbuf_bw))
+			return true;
+	}
+
+	return false;
+}
+
+static void skl_plane_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw,
+				   struct intel_crtc *crtc,
+				   enum plane_id plane_id,
+				   const struct skl_ddb_entry *ddb,
+				   unsigned int data_rate)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);
+	enum dbuf_slice slice;
+
+	/*
+	 * The arbiter can only really guarantee an
+	 * equal share of the total bw to each plane.
+	 */
+	for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) {
+		dbuf_bw->max_bw[slice] = max(dbuf_bw->max_bw[slice], data_rate);
+		dbuf_bw->active_planes[slice] |= BIT(plane_id);
+	}
+}
+
+static void skl_crtc_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw,
+				  const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum plane_id plane_id;
+
+	memset(dbuf_bw, 0, sizeof(*dbuf_bw));
+
+	if (!crtc_state->hw.active)
+		return;
+
+	for_each_plane_id_on_crtc(crtc, plane_id) {
+		/*
+		 * We assume cursors are small enough
+		 * to not cause bandwidth problems.
+		 */
+		if (plane_id == PLANE_CURSOR)
+			continue;
+
+		skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,
+				       &crtc_state->wm.skl.plane_ddb[plane_id],
+				       crtc_state->data_rate[plane_id]);
+
+		if (DISPLAY_VER(display) < 11)
+			skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,
+					       &crtc_state->wm.skl.plane_ddb_y[plane_id],
+					       crtc_state->data_rate[plane_id]);
+	}
+}
+
+/* "Maximum Data Buffer Bandwidth" */
+int intel_dbuf_bw_min_cdclk(struct intel_display *display,
+			    const struct intel_dbuf_bw_state *dbuf_bw_state)
+{
+	unsigned int total_max_bw = 0;
+	enum dbuf_slice slice;
+
+	for_each_dbuf_slice(display, slice) {
+		int num_active_planes = 0;
+		unsigned int max_bw = 0;
+		enum pipe pipe;
+
+		/*
+		 * The arbiter can only really guarantee an
+		 * equal share of the total bw to each plane.
+		 */
+		for_each_pipe(display, pipe) {
+			const struct intel_dbuf_bw *dbuf_bw = &dbuf_bw_state->dbuf_bw[pipe];
+
+			max_bw = max(dbuf_bw->max_bw[slice], max_bw);
+			num_active_planes += hweight8(dbuf_bw->active_planes[slice]);
+		}
+		max_bw *= num_active_planes;
+
+		total_max_bw = max(total_max_bw, max_bw);
+	}
+
+	return DIV_ROUND_UP(total_max_bw, 64);
+}
+
+int intel_dbuf_bw_calc_min_cdclk(struct intel_atomic_state *state,
+				 bool *need_cdclk_calc)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_dbuf_bw_state *new_dbuf_bw_state = NULL;
+	const struct intel_dbuf_bw_state *old_dbuf_bw_state = NULL;
+	const struct intel_crtc_state *old_crtc_state;
+	const struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc *crtc;
+	int ret, i;
+
+	if (DISPLAY_VER(display) < 9)
+		return 0;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		struct intel_dbuf_bw old_dbuf_bw, new_dbuf_bw;
+
+		skl_crtc_calc_dbuf_bw(&old_dbuf_bw, old_crtc_state);
+		skl_crtc_calc_dbuf_bw(&new_dbuf_bw, new_crtc_state);
+
+		if (!intel_dbuf_bw_changed(display, &old_dbuf_bw, &new_dbuf_bw))
+			continue;
+
+		new_dbuf_bw_state = intel_atomic_get_dbuf_bw_state(state);
+		if (IS_ERR(new_dbuf_bw_state))
+			return PTR_ERR(new_dbuf_bw_state);
+
+		old_dbuf_bw_state = intel_atomic_get_old_dbuf_bw_state(state);
+
+		new_dbuf_bw_state->dbuf_bw[crtc->pipe] = new_dbuf_bw;
+	}
+
+	if (!old_dbuf_bw_state)
+		return 0;
+
+	if (intel_dbuf_bw_state_changed(display, old_dbuf_bw_state, new_dbuf_bw_state)) {
+		ret = intel_atomic_lock_global_state(&new_dbuf_bw_state->base);
+		if (ret)
+			return ret;
+	}
+
+	ret = intel_cdclk_update_dbuf_bw_min_cdclk(state,
+						   intel_dbuf_bw_min_cdclk(display, old_dbuf_bw_state),
+						   intel_dbuf_bw_min_cdclk(display, new_dbuf_bw_state),
+						   need_cdclk_calc);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+void intel_dbuf_bw_update_hw_state(struct intel_display *display)
+{
+	struct intel_dbuf_bw_state *dbuf_bw_state =
+		to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
+	struct intel_crtc *crtc;
+
+	if (DISPLAY_VER(display) < 9)
+		return;
+
+	for_each_intel_crtc(display->drm, crtc) {
+		const struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
+
+		skl_crtc_calc_dbuf_bw(&dbuf_bw_state->dbuf_bw[crtc->pipe], crtc_state);
+	}
+}
+
+void intel_dbuf_bw_crtc_disable_noatomic(struct intel_crtc *crtc)
+{
+	struct intel_display *display = to_intel_display(crtc);
+	struct intel_dbuf_bw_state *dbuf_bw_state =
+		to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
+	enum pipe pipe = crtc->pipe;
+
+	if (DISPLAY_VER(display) < 9)
+		return;
+
+	memset(&dbuf_bw_state->dbuf_bw[pipe], 0, sizeof(dbuf_bw_state->dbuf_bw[pipe]));
+}
+
+static struct intel_global_state *
+intel_dbuf_bw_duplicate_state(struct intel_global_obj *obj)
+{
+	struct intel_dbuf_bw_state *state;
+
+	state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return NULL;
+
+	return &state->base;
+}
+
+static void intel_dbuf_bw_destroy_state(struct intel_global_obj *obj,
+					struct intel_global_state *state)
+{
+	kfree(state);
+}
+
+static const struct intel_global_state_funcs intel_dbuf_bw_funcs = {
+	.atomic_duplicate_state = intel_dbuf_bw_duplicate_state,
+	.atomic_destroy_state = intel_dbuf_bw_destroy_state,
+};
+
+int intel_dbuf_bw_init(struct intel_display *display)
+{
+	struct intel_dbuf_bw_state *state;
+
+	state = kzalloc(sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return -ENOMEM;
+
+	intel_atomic_global_obj_init(display, &display->dbuf_bw.obj,
+				     &state->base, &intel_dbuf_bw_funcs);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dbuf_bw.h b/drivers/gpu/drm/i915/display/intel_dbuf_bw.h
new file mode 100644
index 000000000000..61875b9d5969
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dbuf_bw.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2025 Intel Corporation
+ */
+
+#ifndef __INTEL_DBUF_BW_H__
+#define __INTEL_DBUF_BW_H__
+
+#include <drm/drm_atomic.h>
+
+struct intel_atomic_state;
+struct intel_dbuf_bw_state;
+struct intel_crtc;
+struct intel_display;
+struct intel_global_state;
+
+struct intel_dbuf_bw_state *
+to_intel_dbuf_bw_state(struct intel_global_state *obj_state);
+
+struct intel_dbuf_bw_state *
+intel_atomic_get_old_dbuf_bw_state(struct intel_atomic_state *state);
+
+struct intel_dbuf_bw_state *
+intel_atomic_get_new_dbuf_bw_state(struct intel_atomic_state *state);
+
+struct intel_dbuf_bw_state *
+intel_atomic_get_dbuf_bw_state(struct intel_atomic_state *state);
+
+int intel_dbuf_bw_init(struct intel_display *display);
+int intel_dbuf_bw_calc_min_cdclk(struct intel_atomic_state *state,
+				 bool *need_cdclk_calc);
+int intel_dbuf_bw_min_cdclk(struct intel_display *display,
+			    const struct intel_dbuf_bw_state *dbuf_bw_state);
+void intel_dbuf_bw_update_hw_state(struct intel_display *display);
+void intel_dbuf_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
+
+#endif /* __INTEL_DBUF_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index df4da52cbdb3..32664098b407 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -369,6 +369,10 @@ struct intel_display {
 		struct intel_global_obj obj;
 	} dbuf;
 
+	struct {
+		struct intel_global_obj obj;
+	} dbuf_bw;
+
 	struct {
 		/*
 		 * dkl.phy_lock protects against concurrent access of the
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index f84a0b26b7a6..38672d2896e3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -28,6 +28,7 @@
 #include "intel_cdclk.h"
 #include "intel_color.h"
 #include "intel_crtc.h"
+#include "intel_dbuf_bw.h"
 #include "intel_display_core.h"
 #include "intel_display_debugfs.h"
 #include "intel_display_driver.h"
@@ -285,6 +286,10 @@ int intel_display_driver_probe_noirq(struct intel_display *display)
 	if (ret)
 		goto cleanup_wq_unordered;
 
+	ret = intel_dbuf_bw_init(display);
+	if (ret)
+		goto cleanup_wq_unordered;
+
 	ret = intel_bw_init(display);
 	if (ret)
 		goto cleanup_wq_unordered;
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 8415f3d703ed..deb877b2aebd 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -19,6 +19,7 @@
 #include "intel_color.h"
 #include "intel_crtc.h"
 #include "intel_crtc_state_dump.h"
+#include "intel_dbuf_bw.h"
 #include "intel_ddi.h"
 #include "intel_de.h"
 #include "intel_display.h"
@@ -176,6 +177,7 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
 	intel_cdclk_crtc_disable_noatomic(crtc);
 	skl_wm_crtc_disable_noatomic(crtc);
 	intel_bw_crtc_disable_noatomic(crtc);
+	intel_dbuf_bw_crtc_disable_noatomic(crtc);
 
 	intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0);
 }
@@ -872,6 +874,7 @@ static void intel_modeset_readout_hw_state(struct intel_display *display)
 		intel_wm_get_hw_state(display);
 
 	intel_bw_update_hw_state(display);
+	intel_dbuf_bw_update_hw_state(display);
 	intel_cdclk_update_hw_state(display);
 
 	intel_pmdemand_init_pmdemand_params(display, pmdemand_state);
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 84321fad3265..88ba3d32802d 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -243,6 +243,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
 	i915-display/intel_crtc_state_dump.o \
 	i915-display/intel_cursor.o \
 	i915-display/intel_cx0_phy.o \
+	i915-display/intel_dbuf_bw.o \
 	i915-display/intel_ddi.o \
 	i915-display/intel_ddi_buf_trans.o \
 	i915-display/intel_display.o \
-- 
2.49.1

[PATCH 2/9] drm/i915: s/"not not"/"not"/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Elimiante the repeated "not not" in the bw code comments.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index a4d16711d336..d03da1ed4541 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -831,7 +831,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat
 {
 	/*
 	 * We assume cursors are small enough
-	 * to not not cause bandwidth problems.
+	 * to not cause bandwidth problems.
 	 */
 	return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
 }
@@ -846,7 +846,7 @@ static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
 	for_each_plane_id_on_crtc(crtc, plane_id) {
 		/*
 		 * We assume cursors are small enough
-		 * to not not cause bandwidth problems.
+		 * to not cause bandwidth problems.
 		 */
 		if (plane_id == PLANE_CURSOR)
 			continue;
-- 
2.49.1

[PATCH 3/9] drm/i915/bw: Relocate intel_bw_crtc_min_cdclk()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_bw_crtc_min_cdclk() (aka. the thing that deals with what bspec
calls "Maximum Pipe Read Bandwidth") doesn't really have anything to
do with the rest of intel_bw.c (which is all about SAGV/QGV and
memory bandwidth). Move it into intel_crtc.c (for the lack of a better
place).

And I don't really want to call intel_bw.c functions from intel_crtc.c,
so move out intel_bw_crtc_data_rate() as well. And when we move that we
pretty much have to move intel_bw_crtc_num_active_planes() as well since
the two are meant to be used as a pair (they both implement the same
"ignore the cursor" logic).

And in an effort to keep the namespaces at least semi-sensible we
flip the intel_bw_crtc_ prefix into intel_crtc_bw_.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c    | 56 +++-------------------
 drivers/gpu/drm/i915/display/intel_bw.h    |  1 -
 drivers/gpu/drm/i915/display/intel_cdclk.c |  3 +-
 drivers/gpu/drm/i915/display/intel_crtc.c  | 44 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_crtc.h  |  4 ++
 5 files changed, 55 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index d03da1ed4541..92a060e02cf3 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -827,50 +827,6 @@ void intel_bw_init_hw(struct intel_display *display)
 		icl_get_bw_info(display, dram_info, &icl_sa_info);
 }
 
-static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
-{
-	/*
-	 * We assume cursors are small enough
-	 * to not cause bandwidth problems.
-	 */
-	return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
-}
-
-static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(crtc_state);
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	unsigned int data_rate = 0;
-	enum plane_id plane_id;
-
-	for_each_plane_id_on_crtc(crtc, plane_id) {
-		/*
-		 * We assume cursors are small enough
-		 * to not cause bandwidth problems.
-		 */
-		if (plane_id == PLANE_CURSOR)
-			continue;
-
-		data_rate += crtc_state->data_rate[plane_id];
-
-		if (DISPLAY_VER(display) < 11)
-			data_rate += crtc_state->data_rate_y[plane_id];
-	}
-
-	return data_rate;
-}
-
-/* "Maximum Pipe Read Bandwidth" */
-int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(crtc_state);
-
-	if (DISPLAY_VER(display) < 12)
-		return 0;
-
-	return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
-}
-
 static unsigned int intel_bw_num_active_planes(struct intel_display *display,
 					       const struct intel_bw_state *bw_state)
 {
@@ -1264,13 +1220,13 @@ static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *chan
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
 		unsigned int old_data_rate =
-			intel_bw_crtc_data_rate(old_crtc_state);
+			intel_crtc_bw_data_rate(old_crtc_state);
 		unsigned int new_data_rate =
-			intel_bw_crtc_data_rate(new_crtc_state);
+			intel_crtc_bw_data_rate(new_crtc_state);
 		unsigned int old_active_planes =
-			intel_bw_crtc_num_active_planes(old_crtc_state);
+			intel_crtc_bw_num_active_planes(old_crtc_state);
 		unsigned int new_active_planes =
-			intel_bw_crtc_num_active_planes(new_crtc_state);
+			intel_crtc_bw_num_active_planes(new_crtc_state);
 		struct intel_bw_state *new_bw_state;
 
 		/*
@@ -1426,9 +1382,9 @@ static void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
 	bw_state->data_rate[crtc->pipe] =
-		intel_bw_crtc_data_rate(crtc_state);
+		intel_crtc_bw_data_rate(crtc_state);
 	bw_state->num_active_planes[crtc->pipe] =
-		intel_bw_crtc_num_active_planes(crtc_state);
+		intel_crtc_bw_num_active_planes(crtc_state);
 
 	drm_dbg_kms(display->drm, "pipe %c data rate %u num active planes %u\n",
 		    pipe_name(crtc->pipe),
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 051e163f2f15..99b447388245 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -29,7 +29,6 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state);
 void intel_bw_init_hw(struct intel_display *display);
 int intel_bw_init(struct intel_display *display);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
-int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);
 void intel_bw_update_hw_state(struct intel_display *display);
 void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
 
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 23b9e100d824..80a6c98eea5d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -35,7 +35,6 @@
 #include "i915_utils.h"
 #include "intel_atomic.h"
 #include "intel_audio.h"
-#include "intel_bw.h"
 #include "intel_cdclk.h"
 #include "intel_crtc.h"
 #include "intel_dbuf_bw.h"
@@ -2838,7 +2837,7 @@ static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_stat
 		return 0;
 
 	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
-	min_cdclk = max(min_cdclk, intel_bw_crtc_min_cdclk(crtc_state));
+	min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state));
 	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
 	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
 	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 7b39c3a5887c..d300ba1dcd2c 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -795,3 +795,47 @@ bool intel_any_crtc_active_changed(struct intel_atomic_state *state)
 
 	return false;
 }
+
+unsigned int intel_crtc_bw_num_active_planes(const struct intel_crtc_state *crtc_state)
+{
+	/*
+	 * We assume cursors are small enough
+	 * to not cause bandwidth problems.
+	 */
+	return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
+}
+
+unsigned int intel_crtc_bw_data_rate(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	unsigned int data_rate = 0;
+	enum plane_id plane_id;
+
+	for_each_plane_id_on_crtc(crtc, plane_id) {
+		/*
+		 * We assume cursors are small enough
+		 * to not cause bandwidth problems.
+		 */
+		if (plane_id == PLANE_CURSOR)
+			continue;
+
+		data_rate += crtc_state->data_rate[plane_id];
+
+		if (DISPLAY_VER(display) < 11)
+			data_rate += crtc_state->data_rate_y[plane_id];
+	}
+
+	return data_rate;
+}
+
+/* "Maximum Pipe Read Bandwidth" */
+int intel_crtc_bw_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (DISPLAY_VER(display) < 12)
+		return 0;
+
+	return DIV_ROUND_UP_ULL(mul_u32_u32(intel_crtc_bw_data_rate(crtc_state), 10), 512);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
index cee09e7cd3dc..07917e8a9ae3 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.h
+++ b/drivers/gpu/drm/i915/display/intel_crtc.h
@@ -65,4 +65,8 @@ bool intel_any_crtc_active_changed(struct intel_atomic_state *state);
 bool intel_crtc_active_changed(const struct intel_crtc_state *old_crtc_state,
 			       const struct intel_crtc_state *new_crtc_state);
 
+unsigned int intel_crtc_bw_num_active_planes(const struct intel_crtc_state *crtc_state);
+unsigned int intel_crtc_bw_data_rate(const struct intel_crtc_state *crtc_state);
+int intel_crtc_bw_min_cdclk(const struct intel_crtc_state *crtc_state);
+
 #endif
-- 
2.49.1

[PATCH 4/9] drm/i915/ips: Eliminate the cdclk_state stuff from hsw_ips_compute_config()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reorganize the IPS CDCLK handling such that the computed CDCLK
frequency will always satisfy the IPS requirements. The only
exceptional case is if IPS would push the CDCLK above the platform
max, but in that case we can simply disable IPS.

To make this 100% race free we must move the enable_ips modparam
check out from the min CDCLK computation path so that there is no
chance of hsw_min_cdclk() and hsw_ips_compute_config() observing
a different enable_ips value during the same commit.

This allows us to completely remove the cdclk_state stuff
from the IPS code. We only ever have to compare the IPS min
CDCLK against the platform max CDCLK. Thus we eliminate any ordering
requirements between intel_cdclk_atomic_check() and
hsw_ips_compute_config().

Additionally we reduce the three copies of the code doing the
95% calculation into just one.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c | 61 ++++++++++++--------------
 1 file changed, 28 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 927fe56aec77..f444c5b7a27b 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -191,45 +191,46 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
 
 static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
-	/* IPS only exists on ULT machines and is tied to pipe A. */
 	if (!hsw_crtc_supports_ips(crtc))
 		return false;
 
-	if (!display->params.enable_ips)
-		return false;
-
 	if (crtc_state->pipe_bpp > 24)
 		return false;
 
-	/*
-	 * We compare against max which means we must take
-	 * the increased cdclk requirement into account when
-	 * calculating the new cdclk.
-	 *
-	 * Should measure whether using a lower cdclk w/o IPS
-	 */
-	if (display->platform.broadwell &&
-	    crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)
-		return false;
-
 	return true;
 }
 
+static int _hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	if (display->platform.broadwell)
+		return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
+
+	/* no IPS specific limits to worry about */
+	return 0;
+}
+
 int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
-
-	if (!display->platform.broadwell)
-		return 0;
+	int min_cdclk;
 
 	if (!hsw_crtc_state_ips_capable(crtc_state))
 		return 0;
 
-	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-	return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
+	min_cdclk = _hsw_ips_min_cdclk(crtc_state);
+
+	/*
+	 * Do not ask for more than the max CDCLK frequency,
+	 * if that is not enough IPS will simply not be used.
+	 */
+	if (min_cdclk > display->cdclk.max_cdclk_freq)
+		return 0;
+
+	return min_cdclk;
 }
 
 int hsw_ips_compute_config(struct intel_atomic_state *state,
@@ -244,6 +245,12 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
 	if (!hsw_crtc_state_ips_capable(crtc_state))
 		return 0;
 
+	if (_hsw_ips_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq)
+		return 0;
+
+	if (!display->params.enable_ips)
+		return 0;
+
 	/*
 	 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
 	 * enabled and disabled dynamically based on package C states,
@@ -257,18 +264,6 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
 	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
 		return 0;
 
-	if (display->platform.broadwell) {
-		const struct intel_cdclk_state *cdclk_state;
-
-		cdclk_state = intel_atomic_get_cdclk_state(state);
-		if (IS_ERR(cdclk_state))
-			return PTR_ERR(cdclk_state);
-
-		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-		if (crtc_state->pixel_rate > intel_cdclk_logical(cdclk_state) * 95 / 100)
-			return 0;
-	}
-
 	crtc_state->ips_enabled = true;
 
 	return 0;
-- 
2.49.1

[PATCH 5/9] drm/i915/fbc: Decouple FBC from intel_cdclk_atomic_check()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Always account for FBC requirements in intel_crtc_compute_min_cdclk()
so that we don't to worry about the actual CDCLK frequency in
intel_fbc_check_plane() any longer.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c |  1 +
 drivers/gpu/drm/i915/display/intel_fbc.c   | 49 ++++++++++++++++------
 drivers/gpu/drm/i915/display/intel_fbc.h   |  1 +
 3 files changed, 38 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 80a6c98eea5d..d55b3dc23356 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2838,6 +2838,7 @@ static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_stat
 
 	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
 	min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state));
+	min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state));
 	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
 	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
 	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 4edb4342833e..90060c60c5f4 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -53,7 +53,6 @@
 #include "i915_vgpu.h"
 #include "i915_vma.h"
 #include "i9xx_plane_regs.h"
-#include "intel_cdclk.h"
 #include "intel_de.h"
 #include "intel_display_device.h"
 #include "intel_display_regs.h"
@@ -1417,6 +1416,18 @@ intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
 	}
 }
 
+static int _intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+
+	/* WaFbcExceedCdClockThreshold:hsw,bdw */
+	if (display->platform.haswell || display->platform.broadwell)
+		return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
+
+	/* no FBC specific limits to worry about */
+	return 0;
+}
+
 static int intel_fbc_check_plane(struct intel_atomic_state *state,
 				 struct intel_plane *plane)
 {
@@ -1556,18 +1567,9 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 		return 0;
 	}
 
-	/* WaFbcExceedCdClockThreshold:hsw,bdw */
-	if (display->platform.haswell || display->platform.broadwell) {
-		const struct intel_cdclk_state *cdclk_state;
-
-		cdclk_state = intel_atomic_get_cdclk_state(state);
-		if (IS_ERR(cdclk_state))
-			return PTR_ERR(cdclk_state);
-
-		if (crtc_state->pixel_rate >= intel_cdclk_logical(cdclk_state) * 95 / 100) {
-			plane_state->no_fbc_reason = "pixel rate too high";
-			return 0;
-		}
+	if (_intel_fbc_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) {
+		plane_state->no_fbc_reason = "pixel rate too high";
+		return 0;
 	}
 
 	plane_state->no_fbc_reason = NULL;
@@ -1575,6 +1577,27 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 	return 0;
 }
 
+int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	int min_cdclk;
+
+	if (!plane->fbc)
+		return 0;
+
+	min_cdclk = _intel_fbc_min_cdclk(crtc_state);
+
+	/*
+	 * Do not ask for more than the max CDCLK frequency,
+	 * if that is not enough FBC will simply not be used.
+	 */
+	if (min_cdclk > display->cdclk.max_cdclk_freq)
+		return 0;
+
+	return min_cdclk;
+}
 
 static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
 				    struct intel_crtc *crtc,
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 0e715cb6b4e6..c86562404a00 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -28,6 +28,7 @@ enum intel_fbc_id {
 };
 
 int intel_fbc_atomic_check(struct intel_atomic_state *state);
+int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state);
 bool intel_fbc_pre_update(struct intel_atomic_state *state,
 			  struct intel_crtc *crtc);
 void intel_fbc_post_update(struct intel_atomic_state *state,
-- 
2.49.1

[PATCH 6/9] drm/i915: s/min_cdck[]/plane_min_cdclk[]/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Rename crtc_state->min_cdclk[] into crtc_state->plane_min_cdclk[]
to better reflect what it represents.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c         | 2 +-
 drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
 drivers/gpu/drm/i915/display/intel_modeset_setup.c | 6 +++---
 drivers/gpu/drm/i915/display/intel_plane.c         | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d55b3dc23356..ed64fac7897d 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2824,7 +2824,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
 	int min_cdclk = 0;
 
 	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
-		min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
+		min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]);
 
 	return min_cdclk;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 87b7cec35320..f77d120733fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1192,7 +1192,7 @@ struct intel_crtc_state {
 
 	struct intel_crtc_wm_state wm;
 
-	int min_cdclk[I915_MAX_PLANES];
+	int plane_min_cdclk[I915_MAX_PLANES];
 
 	/* for packed/planar CbCr */
 	u32 data_rate[I915_MAX_PLANES];
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index deb877b2aebd..d5c432b613ce 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -853,16 +853,16 @@ static void intel_modeset_readout_hw_state(struct intel_display *display)
 			 */
 			if (plane_state->uapi.visible && plane->min_cdclk) {
 				if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)
-					crtc_state->min_cdclk[plane->id] =
+					crtc_state->plane_min_cdclk[plane->id] =
 						DIV_ROUND_UP(crtc_state->pixel_rate, 2);
 				else
-					crtc_state->min_cdclk[plane->id] =
+					crtc_state->plane_min_cdclk[plane->id] =
 						crtc_state->pixel_rate;
 			}
 			drm_dbg_kms(display->drm,
 				    "[PLANE:%d:%s] min_cdclk %d kHz\n",
 				    plane->base.base.id, plane->base.name,
-				    crtc_state->min_cdclk[plane->id]);
+				    crtc_state->plane_min_cdclk[plane->id]);
 		}
 
 		intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 074de9275951..78329deb395a 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -304,7 +304,7 @@ static void intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 
 	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 
-	new_crtc_state->min_cdclk[plane->id] =
+	new_crtc_state->plane_min_cdclk[plane->id] =
 		plane->min_cdclk(new_crtc_state, plane_state);
 }
 
@@ -391,7 +391,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 	crtc_state->data_rate_y[plane->id] = 0;
 	crtc_state->rel_data_rate[plane->id] = 0;
 	crtc_state->rel_data_rate_y[plane->id] = 0;
-	crtc_state->min_cdclk[plane->id] = 0;
+	crtc_state->plane_min_cdclk[plane->id] = 0;
 
 	plane_state->uapi.visible = false;
 }
-- 
2.49.1

[PATCH 7/9] drm/i915: Compute per-crtc min_cdclk earlier

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we compute the min_cdclk for each pipe during
intel_cdclk_atomic_check(). But that is too late for the
pipe prefill vs. vblank length checks (done during
intel_compute_global_watermarks).

We can't just reorder these things due to other dependencies,
so instead pull only the per-crtc minimum cdclk calculation
ahead. We should have enough information for that as soon
as we've computed the min cdclk for the planes.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c         | 8 ++++----
 drivers/gpu/drm/i915/display/intel_cdclk.h         | 2 ++
 drivers/gpu/drm/i915/display/intel_display.c       | 3 +++
 drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
 drivers/gpu/drm/i915/display/intel_modeset_setup.c | 5 +++++
 5 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ed64fac7897d..af918e0e72ef 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2829,7 +2829,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
 	return min_cdclk;
 }
 
-static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
+int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
 {
 	int min_cdclk;
 
@@ -3302,8 +3302,8 @@ static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state,
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i) {
 		ret = intel_cdclk_update_crtc_min_cdclk(state, crtc,
-							intel_crtc_compute_min_cdclk(old_crtc_state),
-							intel_crtc_compute_min_cdclk(new_crtc_state),
+							old_crtc_state->min_cdclk,
+							new_crtc_state->min_cdclk,
 							need_cdclk_calc);
 		if (ret)
 			return ret;
@@ -3523,7 +3523,7 @@ void intel_cdclk_update_hw_state(struct intel_display *display)
 		if (crtc_state->hw.active)
 			cdclk_state->active_pipes |= BIT(pipe);
 
-		cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state);
+		cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk;
 		cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index d9d7a8b3a48a..bad2da8d45d2 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -69,4 +69,6 @@ bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
 void intel_cdclk_read_hw(struct intel_display *display);
 
+int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);
+
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5b2612d4ec2..539017018884 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6443,6 +6443,9 @@ int intel_atomic_check(struct drm_device *dev,
 	if (ret)
 		goto fail;
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
+		new_crtc_state->min_cdclk = intel_crtc_min_cdclk(new_crtc_state);
+
 	ret = intel_compute_global_watermarks(state);
 	if (ret)
 		goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f77d120733fd..203dd38a9ec4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1192,6 +1192,8 @@ struct intel_crtc_state {
 
 	struct intel_crtc_wm_state wm;
 
+	int min_cdclk;
+
 	int plane_min_cdclk[I915_MAX_PLANES];
 
 	/* for packed/planar CbCr */
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index d5c432b613ce..0dcb0597879a 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -865,6 +865,11 @@ static void intel_modeset_readout_hw_state(struct intel_display *display)
 				    crtc_state->plane_min_cdclk[plane->id]);
 		}
 
+		crtc_state->min_cdclk = intel_crtc_min_cdclk(crtc_state);
+
+		drm_dbg_kms(display->drm, "[CRTC:%d:%s] min_cdclk %d kHz\n",
+			    crtc->base.base.id, crtc->base.name, crtc_state->min_cdclk);
+
 		intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
 						 crtc_state->port_clock);
 	}
-- 
2.49.1

[PATCH 8/9] drm/i915: Include the per-crtc minimum cdclk in the crtc state dump

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Include the crtc minimum cdclk in the crtc state dump. Might help
figuring out who needed how much cdclk.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index a14bcda4446c..23e25e97d060 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -314,9 +314,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
 	drm_printf(&p, "pipe mode: " DRM_MODE_FMT "\n",
 		   DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
 	intel_dump_crtc_timings(&p, &pipe_config->hw.pipe_mode);
-	drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
+	drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d, min cdclk %d\n",
 		   pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
-		   pipe_config->pixel_rate);
+		   pipe_config->pixel_rate, pipe_config->min_cdclk);
 
 	drm_printf(&p, "linetime: %d, ips linetime: %d\n",
 		   pipe_config->linetime, pipe_config->ips_linetime);
-- 
2.49.1

[PATCH 9/9] drm/i915: Neuter cdclk_prefill_adjustment()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

cdclk_prefill_adjustment() currently uses a stale cdclk
value. And even if it was using the correct value it'd
still just 'return 1' because the ratio that it's
calculating is always <= 1.0, and it just rounds the ratio
into an integer (and clamps the result to a maximum of 1).
So for the moment, let's just 'return 1' since that's what
the code ends up doing anyway.

This is actually safe because 1.0 is the worst case (ie. slowest
prefill) and thus the actual prefill is always guaranteed to be
at least as fast as what we assumed during the check.

We'll replace this soon with something that gives more accurate
estimates.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 14 +-------------
 1 file changed, 1 insertion(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9df9ee137bf9..1b062c6c0e03 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2148,19 +2148,7 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,
 static int
 cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
 {
-	struct intel_display *display = to_intel_display(crtc_state);
-	struct intel_atomic_state *state =
-		to_intel_atomic_state(crtc_state->uapi.state);
-	const struct intel_cdclk_state *cdclk_state;
-
-	cdclk_state = intel_atomic_get_cdclk_state(state);
-	if (IS_ERR(cdclk_state)) {
-		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
-		return 1;
-	}
-
-	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
-				   2 * intel_cdclk_logical(cdclk_state)));
+	return 1;
 }
 
 static int
-- 
2.49.1

✗ CI.checkpatch: warning for drm/i915: Reorder cdclk stuff for vblank/guardband length checks

[Patchwork]

== Series Details ==

Series: drm/i915: Reorder cdclk stuff for vblank/guardband length checks
URL   : https://patchwork.freedesktop.org/series/155859/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
fbd08a78c3a3bb17964db2a326514c69c1dca660
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 043be339de95445152bd7a9866a50e24afef9f1f
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
Date:   Mon Oct 13 23:12:36 2025 +0300

    drm/i915: Neuter cdclk_prefill_adjustment()
    
    cdclk_prefill_adjustment() currently uses a stale cdclk
    value. And even if it was using the correct value it'd
    still just 'return 1' because the ratio that it's
    calculating is always <= 1.0, and it just rounds the ratio
    into an integer (and clamps the result to a maximum of 1).
    So for the moment, let's just 'return 1' since that's what
    the code ends up doing anyway.
    
    This is actually safe because 1.0 is the worst case (ie. slowest
    prefill) and thus the actual prefill is always guaranteed to be
    at least as fast as what we assumed during the check.
    
    We'll replace this soon with something that gives more accurate
    estimates.
    
    Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
+ /mt/dim checkpatch c917f7d11493984be9f381ca0a7667bd3e587ada drm-intel
479a25ba65c6 drm/i915/bw: Untangle dbuf bw from the sagv/mem bw stuff
-:425: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#425: 
new file mode 100644

-:650: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#650: FILE: drivers/gpu/drm/i915/display/intel_dbuf_bw.c:221:
+						   intel_dbuf_bw_min_cdclk(display, old_dbuf_bw_state),

-:651: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#651: FILE: drivers/gpu/drm/i915/display/intel_dbuf_bw.c:222:
+						   intel_dbuf_bw_min_cdclk(display, new_dbuf_bw_state),

total: 0 errors, 3 warnings, 0 checks, 750 lines checked
fa3840adda05 drm/i915: s/"not not"/"not"/
e07c466509cf drm/i915/bw: Relocate intel_bw_crtc_min_cdclk()
b01f01509a58 drm/i915/ips: Eliminate the cdclk_state stuff from hsw_ips_compute_config()
afb0a0a8ad92 drm/i915/fbc: Decouple FBC from intel_cdclk_atomic_check()
7ff5c8315035 drm/i915: s/min_cdck[]/plane_min_cdclk[]/
8b2c959d2bae drm/i915: Compute per-crtc min_cdclk earlier
9fc210b64b31 drm/i915: Include the per-crtc minimum cdclk in the crtc state dump
043be339de95 drm/i915: Neuter cdclk_prefill_adjustment()

✓ CI.KUnit: success for drm/i915: Reorder cdclk stuff for vblank/guardband length checks

[Patchwork]

== Series Details ==

Series: drm/i915: Reorder cdclk stuff for vblank/guardband length checks
URL   : https://patchwork.freedesktop.org/series/155859/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[00:16:32] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:16:37] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:17:07] Starting KUnit Kernel (1/1)...
[00:17:07] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:17:07] ================== guc_buf (11 subtests) ===================
[00:17:07] [PASSED] test_smallest
[00:17:07] [PASSED] test_largest
[00:17:07] [PASSED] test_granular
[00:17:07] [PASSED] test_unique
[00:17:07] [PASSED] test_overlap
[00:17:07] [PASSED] test_reusable
[00:17:07] [PASSED] test_too_big
[00:17:07] [PASSED] test_flush
[00:17:07] [PASSED] test_lookup
[00:17:07] [PASSED] test_data
[00:17:07] [PASSED] test_class
[00:17:07] ===================== [PASSED] guc_buf =====================
[00:17:07] =================== guc_dbm (7 subtests) ===================
[00:17:07] [PASSED] test_empty
[00:17:07] [PASSED] test_default
[00:17:07] ======================== test_size  ========================
[00:17:07] [PASSED] 4
[00:17:07] [PASSED] 8
[00:17:07] [PASSED] 32
[00:17:07] [PASSED] 256
[00:17:07] ==================== [PASSED] test_size ====================
[00:17:07] ======================= test_reuse  ========================
[00:17:07] [PASSED] 4
[00:17:07] [PASSED] 8
[00:17:07] [PASSED] 32
[00:17:07] [PASSED] 256
[00:17:07] =================== [PASSED] test_reuse ====================
[00:17:07] =================== test_range_overlap  ====================
[00:17:07] [PASSED] 4
[00:17:07] [PASSED] 8
[00:17:07] [PASSED] 32
[00:17:07] [PASSED] 256
[00:17:07] =============== [PASSED] test_range_overlap ================
[00:17:07] =================== test_range_compact  ====================
[00:17:07] [PASSED] 4
[00:17:07] [PASSED] 8
[00:17:07] [PASSED] 32
[00:17:07] [PASSED] 256
[00:17:07] =============== [PASSED] test_range_compact ================
[00:17:07] ==================== test_range_spare  =====================
[00:17:07] [PASSED] 4
[00:17:07] [PASSED] 8
[00:17:07] [PASSED] 32
[00:17:07] [PASSED] 256
[00:17:07] ================ [PASSED] test_range_spare =================
[00:17:07] ===================== [PASSED] guc_dbm =====================
[00:17:07] =================== guc_idm (6 subtests) ===================
[00:17:07] [PASSED] bad_init
[00:17:07] [PASSED] no_init
[00:17:07] [PASSED] init_fini
[00:17:07] [PASSED] check_used
[00:17:07] [PASSED] check_quota
[00:17:07] [PASSED] check_all
[00:17:07] ===================== [PASSED] guc_idm =====================
[00:17:07] ================== no_relay (3 subtests) ===================
[00:17:07] [PASSED] xe_drops_guc2pf_if_not_ready
[00:17:07] [PASSED] xe_drops_guc2vf_if_not_ready
[00:17:07] [PASSED] xe_rejects_send_if_not_ready
[00:17:07] ==================== [PASSED] no_relay =====================
[00:17:07] ================== pf_relay (14 subtests) ==================
[00:17:07] [PASSED] pf_rejects_guc2pf_too_short
[00:17:07] [PASSED] pf_rejects_guc2pf_too_long
[00:17:07] [PASSED] pf_rejects_guc2pf_no_payload
[00:17:07] [PASSED] pf_fails_no_payload
[00:17:07] [PASSED] pf_fails_bad_origin
[00:17:07] [PASSED] pf_fails_bad_type
[00:17:07] [PASSED] pf_txn_reports_error
[00:17:07] [PASSED] pf_txn_sends_pf2guc
[00:17:07] [PASSED] pf_sends_pf2guc
[00:17:07] [SKIPPED] pf_loopback_nop
[00:17:07] [SKIPPED] pf_loopback_echo
[00:17:07] [SKIPPED] pf_loopback_fail
[00:17:07] [SKIPPED] pf_loopback_busy
[00:17:07] [SKIPPED] pf_loopback_retry
[00:17:07] ==================== [PASSED] pf_relay =====================
[00:17:07] ================== vf_relay (3 subtests) ===================
[00:17:07] [PASSED] vf_rejects_guc2vf_too_short
[00:17:07] [PASSED] vf_rejects_guc2vf_too_long
[00:17:07] [PASSED] vf_rejects_guc2vf_no_payload
[00:17:07] ==================== [PASSED] vf_relay =====================
[00:17:07] ===================== lmtt (1 subtest) =====================
[00:17:07] ======================== test_ops  =========================
[00:17:07] [PASSED] 2-level
[00:17:07] [PASSED] multi-level
[00:17:07] ==================== [PASSED] test_ops =====================
[00:17:07] ====================== [PASSED] lmtt =======================
[00:17:07] ================= pf_service (11 subtests) =================
[00:17:07] [PASSED] pf_negotiate_any
[00:17:07] [PASSED] pf_negotiate_base_match
[00:17:07] [PASSED] pf_negotiate_base_newer
[00:17:07] [PASSED] pf_negotiate_base_next
[00:17:07] [SKIPPED] pf_negotiate_base_older
[00:17:07] [PASSED] pf_negotiate_base_prev
[00:17:07] [PASSED] pf_negotiate_latest_match
[00:17:07] [PASSED] pf_negotiate_latest_newer
[00:17:07] [PASSED] pf_negotiate_latest_next
[00:17:07] [SKIPPED] pf_negotiate_latest_older
[00:17:07] [SKIPPED] pf_negotiate_latest_prev
[00:17:07] =================== [PASSED] pf_service ====================
[00:17:07] ================= xe_guc_g2g (2 subtests) ==================
[00:17:07] ============== xe_live_guc_g2g_kunit_default  ==============
[00:17:07] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[00:17:07] ============== xe_live_guc_g2g_kunit_allmem  ===============
[00:17:07] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[00:17:07] =================== [SKIPPED] xe_guc_g2g ===================
[00:17:07] =================== xe_mocs (2 subtests) ===================
[00:17:07] ================ xe_live_mocs_kernel_kunit  ================
[00:17:07] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[00:17:07] ================ xe_live_mocs_reset_kunit  =================
[00:17:07] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[00:17:07] ==================== [SKIPPED] xe_mocs =====================
[00:17:07] ================= xe_migrate (2 subtests) ==================
[00:17:07] ================= xe_migrate_sanity_kunit  =================
[00:17:07] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[00:17:07] ================== xe_validate_ccs_kunit  ==================
[00:17:07] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[00:17:07] =================== [SKIPPED] xe_migrate ===================
[00:17:07] ================== xe_dma_buf (1 subtest) ==================
[00:17:07] ==================== xe_dma_buf_kunit  =====================
[00:17:07] ================ [SKIPPED] xe_dma_buf_kunit ================
[00:17:07] =================== [SKIPPED] xe_dma_buf ===================
[00:17:07] ================= xe_bo_shrink (1 subtest) =================
[00:17:07] =================== xe_bo_shrink_kunit  ====================
[00:17:07] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[00:17:07] ================== [SKIPPED] xe_bo_shrink ==================
[00:17:07] ==================== xe_bo (2 subtests) ====================
[00:17:07] ================== xe_ccs_migrate_kunit  ===================
[00:17:07] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[00:17:07] ==================== xe_bo_evict_kunit  ====================
[00:17:07] =============== [SKIPPED] xe_bo_evict_kunit ================
[00:17:07] ===================== [SKIPPED] xe_bo ======================
[00:17:07] ==================== args (11 subtests) ====================
[00:17:07] [PASSED] count_args_test
[00:17:07] [PASSED] call_args_example
[00:17:07] [PASSED] call_args_test
[00:17:07] [PASSED] drop_first_arg_example
[00:17:07] [PASSED] drop_first_arg_test
[00:17:07] [PASSED] first_arg_example
[00:17:07] [PASSED] first_arg_test
[00:17:07] [PASSED] last_arg_example
[00:17:07] [PASSED] last_arg_test
[00:17:07] [PASSED] pick_arg_example
[00:17:07] [PASSED] sep_comma_example
[00:17:07] ====================== [PASSED] args =======================
[00:17:07] =================== xe_pci (3 subtests) ====================
[00:17:07] ==================== check_graphics_ip  ====================
[00:17:07] [PASSED] 12.00 Xe_LP
[00:17:07] [PASSED] 12.10 Xe_LP+
[00:17:07] [PASSED] 12.55 Xe_HPG
[00:17:07] [PASSED] 12.60 Xe_HPC
[00:17:07] [PASSED] 12.70 Xe_LPG
[00:17:07] [PASSED] 12.71 Xe_LPG
[00:17:07] [PASSED] 12.74 Xe_LPG+
[00:17:07] [PASSED] 20.01 Xe2_HPG
[00:17:07] [PASSED] 20.02 Xe2_HPG
[00:17:07] [PASSED] 20.04 Xe2_LPG
[00:17:07] [PASSED] 30.00 Xe3_LPG
[00:17:07] [PASSED] 30.01 Xe3_LPG
[00:17:07] [PASSED] 30.03 Xe3_LPG
[00:17:07] ================ [PASSED] check_graphics_ip ================
[00:17:07] ===================== check_media_ip  ======================
[00:17:07] [PASSED] 12.00 Xe_M
[00:17:07] [PASSED] 12.55 Xe_HPM
[00:17:07] [PASSED] 13.00 Xe_LPM+
[00:17:07] [PASSED] 13.01 Xe2_HPM
[00:17:07] [PASSED] 20.00 Xe2_LPM
[00:17:07] [PASSED] 30.00 Xe3_LPM
[00:17:07] [PASSED] 30.02 Xe3_LPM
[00:17:07] ================= [PASSED] check_media_ip ==================
[00:17:07] ================= check_platform_gt_count  =================
[00:17:07] [PASSED] 0x9A60 (TIGERLAKE)
[00:17:07] [PASSED] 0x9A68 (TIGERLAKE)
[00:17:07] [PASSED] 0x9A70 (TIGERLAKE)
[00:17:07] [PASSED] 0x9A40 (TIGERLAKE)
[00:17:07] [PASSED] 0x9A49 (TIGERLAKE)
[00:17:07] [PASSED] 0x9A59 (TIGERLAKE)
[00:17:07] [PASSED] 0x9A78 (TIGERLAKE)
[00:17:07] [PASSED] 0x9AC0 (TIGERLAKE)
[00:17:07] [PASSED] 0x9AC9 (TIGERLAKE)
[00:17:07] [PASSED] 0x9AD9 (TIGERLAKE)
[00:17:07] [PASSED] 0x9AF8 (TIGERLAKE)
[00:17:07] [PASSED] 0x4C80 (ROCKETLAKE)
[00:17:07] [PASSED] 0x4C8A (ROCKETLAKE)
[00:17:07] [PASSED] 0x4C8B (ROCKETLAKE)
[00:17:07] [PASSED] 0x4C8C (ROCKETLAKE)
[00:17:07] [PASSED] 0x4C90 (ROCKETLAKE)
[00:17:07] [PASSED] 0x4C9A (ROCKETLAKE)
[00:17:07] [PASSED] 0x4680 (ALDERLAKE_S)
[00:17:07] [PASSED] 0x4682 (ALDERLAKE_S)
[00:17:07] [PASSED] 0x4688 (ALDERLAKE_S)
[00:17:07] [PASSED] 0x468A (ALDERLAKE_S)
[00:17:07] [PASSED] 0x468B (ALDERLAKE_S)
[00:17:07] [PASSED] 0x4690 (ALDERLAKE_S)
[00:17:07] [PASSED] 0x4692 (ALDERLAKE_S)
[00:17:07] [PASSED] 0x4693 (ALDERLAKE_S)
[00:17:07] [PASSED] 0x46A0 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46A1 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46A2 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46A3 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46A6 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46A8 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46AA (ALDERLAKE_P)
[00:17:07] [PASSED] 0x462A (ALDERLAKE_P)
[00:17:07] [PASSED] 0x4626 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x4628 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46B0 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46B1 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46B2 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46B3 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46C0 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46C1 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46C2 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46C3 (ALDERLAKE_P)
[00:17:07] [PASSED] 0x46D0 (ALDERLAKE_N)
[00:17:07] [PASSED] 0x46D1 (ALDERLAKE_N)
[00:17:07] [PASSED] 0x46D2 (ALDERLAKE_N)
[00:17:07] [PASSED] 0x46D3 (ALDERLAKE_N)
[00:17:07] [PASSED] 0x46D4 (ALDERLAKE_N)
[00:17:07] [PASSED] 0xA721 (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA7A1 (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA7A9 (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA7AC (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA7AD (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA720 (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA7A0 (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA7A8 (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA7AA (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA7AB (ALDERLAKE_P)
[00:17:07] [PASSED] 0xA780 (ALDERLAKE_S)
[00:17:07] [PASSED] 0xA781 (ALDERLAKE_S)
[00:17:07] [PASSED] 0xA782 (ALDERLAKE_S)
[00:17:07] [PASSED] 0xA783 (ALDERLAKE_S)
[00:17:07] [PASSED] 0xA788 (ALDERLAKE_S)
[00:17:07] [PASSED] 0xA789 (ALDERLAKE_S)
[00:17:07] [PASSED] 0xA78A (ALDERLAKE_S)
[00:17:07] [PASSED] 0xA78B (ALDERLAKE_S)
[00:17:07] [PASSED] 0x4905 (DG1)
[00:17:07] [PASSED] 0x4906 (DG1)
[00:17:07] [PASSED] 0x4907 (DG1)
[00:17:07] [PASSED] 0x4908 (DG1)
[00:17:07] [PASSED] 0x4909 (DG1)
[00:17:07] [PASSED] 0x56C0 (DG2)
[00:17:07] [PASSED] 0x56C2 (DG2)
[00:17:07] [PASSED] 0x56C1 (DG2)
[00:17:07] [PASSED] 0x7D51 (METEORLAKE)
[00:17:07] [PASSED] 0x7DD1 (METEORLAKE)
[00:17:07] [PASSED] 0x7D41 (METEORLAKE)
[00:17:07] [PASSED] 0x7D67 (METEORLAKE)
[00:17:07] [PASSED] 0xB640 (METEORLAKE)
[00:17:07] [PASSED] 0x56A0 (DG2)
[00:17:07] [PASSED] 0x56A1 (DG2)
[00:17:07] [PASSED] 0x56A2 (DG2)
[00:17:07] [PASSED] 0x56BE (DG2)
[00:17:07] [PASSED] 0x56BF (DG2)
[00:17:07] [PASSED] 0x5690 (DG2)
[00:17:07] [PASSED] 0x5691 (DG2)
[00:17:07] [PASSED] 0x5692 (DG2)
[00:17:07] [PASSED] 0x56A5 (DG2)
[00:17:07] [PASSED] 0x56A6 (DG2)
[00:17:07] [PASSED] 0x56B0 (DG2)
[00:17:07] [PASSED] 0x56B1 (DG2)
[00:17:07] [PASSED] 0x56BA (DG2)
[00:17:07] [PASSED] 0x56BB (DG2)
[00:17:07] [PASSED] 0x56BC (DG2)
[00:17:07] [PASSED] 0x56BD (DG2)
[00:17:07] [PASSED] 0x5693 (DG2)
[00:17:07] [PASSED] 0x5694 (DG2)
[00:17:07] [PASSED] 0x5695 (DG2)
[00:17:07] [PASSED] 0x56A3 (DG2)
[00:17:07] [PASSED] 0x56A4 (DG2)
[00:17:07] [PASSED] 0x56B2 (DG2)
[00:17:07] [PASSED] 0x56B3 (DG2)
[00:17:07] [PASSED] 0x5696 (DG2)
[00:17:07] [PASSED] 0x5697 (DG2)
[00:17:07] [PASSED] 0xB69 (PVC)
[00:17:07] [PASSED] 0xB6E (PVC)
[00:17:07] [PASSED] 0xBD4 (PVC)
[00:17:07] [PASSED] 0xBD5 (PVC)
[00:17:07] [PASSED] 0xBD6 (PVC)
[00:17:07] [PASSED] 0xBD7 (PVC)
[00:17:07] [PASSED] 0xBD8 (PVC)
[00:17:07] [PASSED] 0xBD9 (PVC)
[00:17:07] [PASSED] 0xBDA (PVC)
[00:17:07] [PASSED] 0xBDB (PVC)
[00:17:07] [PASSED] 0xBE0 (PVC)
[00:17:07] [PASSED] 0xBE1 (PVC)
[00:17:07] [PASSED] 0xBE5 (PVC)
[00:17:07] [PASSED] 0x7D40 (METEORLAKE)
[00:17:07] [PASSED] 0x7D45 (METEORLAKE)
[00:17:07] [PASSED] 0x7D55 (METEORLAKE)
[00:17:07] [PASSED] 0x7D60 (METEORLAKE)
[00:17:07] [PASSED] 0x7DD5 (METEORLAKE)
[00:17:07] [PASSED] 0x6420 (LUNARLAKE)
[00:17:07] [PASSED] 0x64A0 (LUNARLAKE)
[00:17:07] [PASSED] 0x64B0 (LUNARLAKE)
[00:17:07] [PASSED] 0xE202 (BATTLEMAGE)
[00:17:07] [PASSED] 0xE209 (BATTLEMAGE)
[00:17:07] [PASSED] 0xE20B (BATTLEMAGE)
[00:17:07] [PASSED] 0xE20C (BATTLEMAGE)
[00:17:07] [PASSED] 0xE20D (BATTLEMAGE)
[00:17:07] [PASSED] 0xE210 (BATTLEMAGE)
[00:17:07] [PASSED] 0xE211 (BATTLEMAGE)
[00:17:07] [PASSED] 0xE212 (BATTLEMAGE)
[00:17:07] [PASSED] 0xE216 (BATTLEMAGE)
[00:17:07] [PASSED] 0xE220 (BATTLEMAGE)
[00:17:07] [PASSED] 0xE221 (BATTLEMAGE)
[00:17:07] [PASSED] 0xE222 (BATTLEMAGE)
[00:17:07] [PASSED] 0xE223 (BATTLEMAGE)
[00:17:07] [PASSED] 0xB080 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB081 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB082 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB083 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB084 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB085 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB086 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB087 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB08F (PANTHERLAKE)
[00:17:07] [PASSED] 0xB090 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB0A0 (PANTHERLAKE)
[00:17:07] [PASSED] 0xB0B0 (PANTHERLAKE)
[00:17:07] [PASSED] 0xFD80 (PANTHERLAKE)
[00:17:07] [PASSED] 0xFD81 (PANTHERLAKE)
[00:17:07] ============= [PASSED] check_platform_gt_count =============
[00:17:07] ===================== [PASSED] xe_pci ======================
[00:17:07] =================== xe_rtp (2 subtests) ====================
[00:17:07] =============== xe_rtp_process_to_sr_tests  ================
[00:17:07] [PASSED] coalesce-same-reg
[00:17:07] [PASSED] no-match-no-add
[00:17:07] [PASSED] match-or
[00:17:07] [PASSED] match-or-xfail
[00:17:07] [PASSED] no-match-no-add-multiple-rules
[00:17:07] [PASSED] two-regs-two-entries
[00:17:07] [PASSED] clr-one-set-other
[00:17:07] [PASSED] set-field
[00:17:07] [PASSED] conflict-duplicate
[00:17:07] [PASSED] conflict-not-disjoint
[00:17:07] [PASSED] conflict-reg-type
[00:17:07] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[00:17:07] ================== xe_rtp_process_tests  ===================
[00:17:07] [PASSED] active1
[00:17:07] [PASSED] active2
[00:17:07] [PASSED] active-inactive
[00:17:07] [PASSED] inactive-active
[00:17:07] [PASSED] inactive-1st_or_active-inactive
[00:17:07] [PASSED] inactive-2nd_or_active-inactive
[00:17:07] [PASSED] inactive-last_or_active-inactive
[00:17:07] [PASSED] inactive-no_or_active-inactive
[00:17:07] ============== [PASSED] xe_rtp_process_tests ===============
[00:17:07] ===================== [PASSED] xe_rtp ======================
[00:17:07] ==================== xe_wa (1 subtest) =====================
[00:17:07] ======================== xe_wa_gt  =========================
[00:17:07] [PASSED] TIGERLAKE B0
[00:17:07] [PASSED] DG1 A0
[00:17:07] [PASSED] DG1 B0
[00:17:07] [PASSED] ALDERLAKE_S A0
[00:17:07] [PASSED] ALDERLAKE_S B0
stty: 'standard input': Inappropriate ioctl for device
[00:17:07] [PASSED] ALDERLAKE_S C0
[00:17:07] [PASSED] ALDERLAKE_S D0
[00:17:07] [PASSED] ALDERLAKE_P A0
[00:17:07] [PASSED] ALDERLAKE_P B0
[00:17:07] [PASSED] ALDERLAKE_P C0
[00:17:07] [PASSED] ALDERLAKE_S RPLS D0
[00:17:07] [PASSED] ALDERLAKE_P RPLU E0
[00:17:07] [PASSED] DG2 G10 C0
[00:17:07] [PASSED] DG2 G11 B1
[00:17:07] [PASSED] DG2 G12 A1
[00:17:07] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[00:17:07] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[00:17:07] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[00:17:07] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[00:17:07] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[00:17:07] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[00:17:07] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[00:17:07] ==================== [PASSED] xe_wa_gt =====================
[00:17:07] ====================== [PASSED] xe_wa ======================
[00:17:07] ============================================================
[00:17:07] Testing complete. Ran 306 tests: passed: 288, skipped: 18
[00:17:07] Elapsed time: 34.972s total, 4.218s configuring, 30.387s building, 0.331s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[00:17:08] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:17:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:17:34] Starting KUnit Kernel (1/1)...
[00:17:34] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:17:34] ============ drm_test_pick_cmdline (2 subtests) ============
[00:17:34] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[00:17:34] =============== drm_test_pick_cmdline_named  ===============
[00:17:34] [PASSED] NTSC
[00:17:34] [PASSED] NTSC-J
[00:17:34] [PASSED] PAL
[00:17:34] [PASSED] PAL-M
[00:17:34] =========== [PASSED] drm_test_pick_cmdline_named ===========
[00:17:34] ============== [PASSED] drm_test_pick_cmdline ==============
[00:17:34] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[00:17:34] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[00:17:34] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[00:17:34] =========== drm_validate_clone_mode (2 subtests) ===========
[00:17:34] ============== drm_test_check_in_clone_mode  ===============
[00:17:34] [PASSED] in_clone_mode
[00:17:34] [PASSED] not_in_clone_mode
[00:17:34] ========== [PASSED] drm_test_check_in_clone_mode ===========
[00:17:34] =============== drm_test_check_valid_clones  ===============
[00:17:34] [PASSED] not_in_clone_mode
[00:17:34] [PASSED] valid_clone
[00:17:34] [PASSED] invalid_clone
[00:17:34] =========== [PASSED] drm_test_check_valid_clones ===========
[00:17:34] ============= [PASSED] drm_validate_clone_mode =============
[00:17:34] ============= drm_validate_modeset (1 subtest) =============
[00:17:34] [PASSED] drm_test_check_connector_changed_modeset
[00:17:34] ============== [PASSED] drm_validate_modeset ===============
[00:17:34] ====== drm_test_bridge_get_current_state (2 subtests) ======
[00:17:34] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[00:17:34] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[00:17:34] ======== [PASSED] drm_test_bridge_get_current_state ========
[00:17:34] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[00:17:34] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[00:17:34] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[00:17:34] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[00:17:34] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[00:17:34] ============== drm_bridge_alloc (2 subtests) ===============
[00:17:34] [PASSED] drm_test_drm_bridge_alloc_basic
[00:17:34] [PASSED] drm_test_drm_bridge_alloc_get_put
[00:17:34] ================ [PASSED] drm_bridge_alloc =================
[00:17:34] ================== drm_buddy (8 subtests) ==================
[00:17:34] [PASSED] drm_test_buddy_alloc_limit
[00:17:34] [PASSED] drm_test_buddy_alloc_optimistic
[00:17:34] [PASSED] drm_test_buddy_alloc_pessimistic
[00:17:34] [PASSED] drm_test_buddy_alloc_pathological
[00:17:34] [PASSED] drm_test_buddy_alloc_contiguous
[00:17:34] [PASSED] drm_test_buddy_alloc_clear
[00:17:34] [PASSED] drm_test_buddy_alloc_range_bias
[00:17:35] [PASSED] drm_test_buddy_fragmentation_performance
[00:17:35] ==================== [PASSED] drm_buddy ====================
[00:17:35] ============= drm_cmdline_parser (40 subtests) =============
[00:17:35] [PASSED] drm_test_cmdline_force_d_only
[00:17:35] [PASSED] drm_test_cmdline_force_D_only_dvi
[00:17:35] [PASSED] drm_test_cmdline_force_D_only_hdmi
[00:17:35] [PASSED] drm_test_cmdline_force_D_only_not_digital
[00:17:35] [PASSED] drm_test_cmdline_force_e_only
[00:17:35] [PASSED] drm_test_cmdline_res
[00:17:35] [PASSED] drm_test_cmdline_res_vesa
[00:17:35] [PASSED] drm_test_cmdline_res_vesa_rblank
[00:17:35] [PASSED] drm_test_cmdline_res_rblank
[00:17:35] [PASSED] drm_test_cmdline_res_bpp
[00:17:35] [PASSED] drm_test_cmdline_res_refresh
[00:17:35] [PASSED] drm_test_cmdline_res_bpp_refresh
[00:17:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[00:17:35] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[00:17:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[00:17:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[00:17:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[00:17:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[00:17:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[00:17:35] [PASSED] drm_test_cmdline_res_margins_force_on
[00:17:35] [PASSED] drm_test_cmdline_res_vesa_margins
[00:17:35] [PASSED] drm_test_cmdline_name
[00:17:35] [PASSED] drm_test_cmdline_name_bpp
[00:17:35] [PASSED] drm_test_cmdline_name_option
[00:17:35] [PASSED] drm_test_cmdline_name_bpp_option
[00:17:35] [PASSED] drm_test_cmdline_rotate_0
[00:17:35] [PASSED] drm_test_cmdline_rotate_90
[00:17:35] [PASSED] drm_test_cmdline_rotate_180
[00:17:35] [PASSED] drm_test_cmdline_rotate_270
[00:17:35] [PASSED] drm_test_cmdline_hmirror
[00:17:35] [PASSED] drm_test_cmdline_vmirror
[00:17:35] [PASSED] drm_test_cmdline_margin_options
[00:17:35] [PASSED] drm_test_cmdline_multiple_options
[00:17:35] [PASSED] drm_test_cmdline_bpp_extra_and_option
[00:17:35] [PASSED] drm_test_cmdline_extra_and_option
[00:17:35] [PASSED] drm_test_cmdline_freestanding_options
[00:17:35] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[00:17:35] [PASSED] drm_test_cmdline_panel_orientation
[00:17:35] ================ drm_test_cmdline_invalid  =================
[00:17:35] [PASSED] margin_only
[00:17:35] [PASSED] interlace_only
[00:17:35] [PASSED] res_missing_x
[00:17:35] [PASSED] res_missing_y
[00:17:35] [PASSED] res_bad_y
[00:17:35] [PASSED] res_missing_y_bpp
[00:17:35] [PASSED] res_bad_bpp
[00:17:35] [PASSED] res_bad_refresh
[00:17:35] [PASSED] res_bpp_refresh_force_on_off
[00:17:35] [PASSED] res_invalid_mode
[00:17:35] [PASSED] res_bpp_wrong_place_mode
[00:17:35] [PASSED] name_bpp_refresh
[00:17:35] [PASSED] name_refresh
[00:17:35] [PASSED] name_refresh_wrong_mode
[00:17:35] [PASSED] name_refresh_invalid_mode
[00:17:35] [PASSED] rotate_multiple
[00:17:35] [PASSED] rotate_invalid_val
[00:17:35] [PASSED] rotate_truncated
[00:17:35] [PASSED] invalid_option
[00:17:35] [PASSED] invalid_tv_option
[00:17:35] [PASSED] truncated_tv_option
[00:17:35] ============ [PASSED] drm_test_cmdline_invalid =============
[00:17:35] =============== drm_test_cmdline_tv_options  ===============
[00:17:35] [PASSED] NTSC
[00:17:35] [PASSED] NTSC_443
[00:17:35] [PASSED] NTSC_J
[00:17:35] [PASSED] PAL
[00:17:35] [PASSED] PAL_M
[00:17:35] [PASSED] PAL_N
[00:17:35] [PASSED] SECAM
[00:17:35] [PASSED] MONO_525
[00:17:35] [PASSED] MONO_625
[00:17:35] =========== [PASSED] drm_test_cmdline_tv_options ===========
[00:17:35] =============== [PASSED] drm_cmdline_parser ================
[00:17:35] ========== drmm_connector_hdmi_init (20 subtests) ==========
[00:17:35] [PASSED] drm_test_connector_hdmi_init_valid
[00:17:35] [PASSED] drm_test_connector_hdmi_init_bpc_8
[00:17:35] [PASSED] drm_test_connector_hdmi_init_bpc_10
[00:17:35] [PASSED] drm_test_connector_hdmi_init_bpc_12
[00:17:35] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[00:17:35] [PASSED] drm_test_connector_hdmi_init_bpc_null
[00:17:35] [PASSED] drm_test_connector_hdmi_init_formats_empty
[00:17:35] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[00:17:35] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[00:17:35] [PASSED] supported_formats=0x9 yuv420_allowed=1
[00:17:35] [PASSED] supported_formats=0x9 yuv420_allowed=0
[00:17:35] [PASSED] supported_formats=0x3 yuv420_allowed=1
[00:17:35] [PASSED] supported_formats=0x3 yuv420_allowed=0
[00:17:35] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[00:17:35] [PASSED] drm_test_connector_hdmi_init_null_ddc
[00:17:35] [PASSED] drm_test_connector_hdmi_init_null_product
[00:17:35] [PASSED] drm_test_connector_hdmi_init_null_vendor
[00:17:35] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[00:17:35] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[00:17:35] [PASSED] drm_test_connector_hdmi_init_product_valid
[00:17:35] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[00:17:35] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[00:17:35] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[00:17:35] ========= drm_test_connector_hdmi_init_type_valid  =========
[00:17:35] [PASSED] HDMI-A
[00:17:35] [PASSED] HDMI-B
[00:17:35] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[00:17:35] ======== drm_test_connector_hdmi_init_type_invalid  ========
[00:17:35] [PASSED] Unknown
[00:17:35] [PASSED] VGA
[00:17:35] [PASSED] DVI-I
[00:17:35] [PASSED] DVI-D
[00:17:35] [PASSED] DVI-A
[00:17:35] [PASSED] Composite
[00:17:35] [PASSED] SVIDEO
[00:17:35] [PASSED] LVDS
[00:17:35] [PASSED] Component
[00:17:35] [PASSED] DIN
[00:17:35] [PASSED] DP
[00:17:35] [PASSED] TV
[00:17:35] [PASSED] eDP
[00:17:35] [PASSED] Virtual
[00:17:35] [PASSED] DSI
[00:17:35] [PASSED] DPI
[00:17:35] [PASSED] Writeback
[00:17:35] [PASSED] SPI
[00:17:35] [PASSED] USB
[00:17:35] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[00:17:35] ============ [PASSED] drmm_connector_hdmi_init =============
[00:17:35] ============= drmm_connector_init (3 subtests) =============
[00:17:35] [PASSED] drm_test_drmm_connector_init
[00:17:35] [PASSED] drm_test_drmm_connector_init_null_ddc
[00:17:35] ========= drm_test_drmm_connector_init_type_valid  =========
[00:17:35] [PASSED] Unknown
[00:17:35] [PASSED] VGA
[00:17:35] [PASSED] DVI-I
[00:17:35] [PASSED] DVI-D
[00:17:35] [PASSED] DVI-A
[00:17:35] [PASSED] Composite
[00:17:35] [PASSED] SVIDEO
[00:17:35] [PASSED] LVDS
[00:17:35] [PASSED] Component
[00:17:35] [PASSED] DIN
[00:17:35] [PASSED] DP
[00:17:35] [PASSED] HDMI-A
[00:17:35] [PASSED] HDMI-B
[00:17:35] [PASSED] TV
[00:17:35] [PASSED] eDP
[00:17:35] [PASSED] Virtual
[00:17:35] [PASSED] DSI
[00:17:35] [PASSED] DPI
[00:17:35] [PASSED] Writeback
[00:17:35] [PASSED] SPI
[00:17:35] [PASSED] USB
[00:17:35] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[00:17:35] =============== [PASSED] drmm_connector_init ===============
[00:17:35] ========= drm_connector_dynamic_init (6 subtests) ==========
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_init
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_init_properties
[00:17:35] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[00:17:35] [PASSED] Unknown
[00:17:35] [PASSED] VGA
[00:17:35] [PASSED] DVI-I
[00:17:35] [PASSED] DVI-D
[00:17:35] [PASSED] DVI-A
[00:17:35] [PASSED] Composite
[00:17:35] [PASSED] SVIDEO
[00:17:35] [PASSED] LVDS
[00:17:35] [PASSED] Component
[00:17:35] [PASSED] DIN
[00:17:35] [PASSED] DP
[00:17:35] [PASSED] HDMI-A
[00:17:35] [PASSED] HDMI-B
[00:17:35] [PASSED] TV
[00:17:35] [PASSED] eDP
[00:17:35] [PASSED] Virtual
[00:17:35] [PASSED] DSI
[00:17:35] [PASSED] DPI
[00:17:35] [PASSED] Writeback
[00:17:35] [PASSED] SPI
[00:17:35] [PASSED] USB
[00:17:35] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[00:17:35] ======== drm_test_drm_connector_dynamic_init_name  =========
[00:17:35] [PASSED] Unknown
[00:17:35] [PASSED] VGA
[00:17:35] [PASSED] DVI-I
[00:17:35] [PASSED] DVI-D
[00:17:35] [PASSED] DVI-A
[00:17:35] [PASSED] Composite
[00:17:35] [PASSED] SVIDEO
[00:17:35] [PASSED] LVDS
[00:17:35] [PASSED] Component
[00:17:35] [PASSED] DIN
[00:17:35] [PASSED] DP
[00:17:35] [PASSED] HDMI-A
[00:17:35] [PASSED] HDMI-B
[00:17:35] [PASSED] TV
[00:17:35] [PASSED] eDP
[00:17:35] [PASSED] Virtual
[00:17:35] [PASSED] DSI
[00:17:35] [PASSED] DPI
[00:17:35] [PASSED] Writeback
[00:17:35] [PASSED] SPI
[00:17:35] [PASSED] USB
[00:17:35] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[00:17:35] =========== [PASSED] drm_connector_dynamic_init ============
[00:17:35] ==== drm_connector_dynamic_register_early (4 subtests) =====
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[00:17:35] ====== [PASSED] drm_connector_dynamic_register_early =======
[00:17:35] ======= drm_connector_dynamic_register (7 subtests) ========
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[00:17:35] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[00:17:35] ========= [PASSED] drm_connector_dynamic_register ==========
[00:17:35] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[00:17:35] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[00:17:35] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[00:17:35] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[00:17:35] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[00:17:35] ========== drm_test_get_tv_mode_from_name_valid  ===========
[00:17:35] [PASSED] NTSC
[00:17:35] [PASSED] NTSC-443
[00:17:35] [PASSED] NTSC-J
[00:17:35] [PASSED] PAL
[00:17:35] [PASSED] PAL-M
[00:17:35] [PASSED] PAL-N
[00:17:35] [PASSED] SECAM
[00:17:35] [PASSED] Mono
[00:17:35] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[00:17:35] [PASSED] drm_test_get_tv_mode_from_name_truncated
[00:17:35] ============ [PASSED] drm_get_tv_mode_from_name ============
[00:17:35] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[00:17:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[00:17:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[00:17:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[00:17:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[00:17:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[00:17:35] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[00:17:35] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[00:17:35] [PASSED] VIC 96
[00:17:35] [PASSED] VIC 97
[00:17:35] [PASSED] VIC 101
[00:17:35] [PASSED] VIC 102
[00:17:35] [PASSED] VIC 106
[00:17:35] [PASSED] VIC 107
[00:17:35] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[00:17:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[00:17:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[00:17:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[00:17:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[00:17:35] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[00:17:35] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[00:17:35] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[00:17:35] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[00:17:35] [PASSED] Automatic
[00:17:35] [PASSED] Full
[00:17:35] [PASSED] Limited 16:235
[00:17:35] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[00:17:35] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[00:17:35] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[00:17:35] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[00:17:35] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[00:17:35] [PASSED] RGB
[00:17:35] [PASSED] YUV 4:2:0
[00:17:35] [PASSED] YUV 4:2:2
[00:17:35] [PASSED] YUV 4:4:4
[00:17:35] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[00:17:35] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[00:17:35] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[00:17:35] ============= drm_damage_helper (21 subtests) ==============
[00:17:35] [PASSED] drm_test_damage_iter_no_damage
[00:17:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[00:17:35] [PASSED] drm_test_damage_iter_no_damage_src_moved
[00:17:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[00:17:35] [PASSED] drm_test_damage_iter_no_damage_not_visible
[00:17:35] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[00:17:35] [PASSED] drm_test_damage_iter_no_damage_no_fb
[00:17:35] [PASSED] drm_test_damage_iter_simple_damage
[00:17:35] [PASSED] drm_test_damage_iter_single_damage
[00:17:35] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[00:17:35] [PASSED] drm_test_damage_iter_single_damage_outside_src
[00:17:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[00:17:35] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[00:17:35] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[00:17:35] [PASSED] drm_test_damage_iter_single_damage_src_moved
[00:17:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[00:17:35] [PASSED] drm_test_damage_iter_damage
[00:17:35] [PASSED] drm_test_damage_iter_damage_one_intersect
[00:17:35] [PASSED] drm_test_damage_iter_damage_one_outside
[00:17:35] [PASSED] drm_test_damage_iter_damage_src_moved
[00:17:35] [PASSED] drm_test_damage_iter_damage_not_visible
[00:17:35] ================ [PASSED] drm_damage_helper ================
[00:17:35] ============== drm_dp_mst_helper (3 subtests) ==============
[00:17:35] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[00:17:35] [PASSED] Clock 154000 BPP 30 DSC disabled
[00:17:35] [PASSED] Clock 234000 BPP 30 DSC disabled
[00:17:35] [PASSED] Clock 297000 BPP 24 DSC disabled
[00:17:35] [PASSED] Clock 332880 BPP 24 DSC enabled
[00:17:35] [PASSED] Clock 324540 BPP 24 DSC enabled
[00:17:35] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[00:17:35] ============== drm_test_dp_mst_calc_pbn_div  ===============
[00:17:35] [PASSED] Link rate 2000000 lane count 4
[00:17:35] [PASSED] Link rate 2000000 lane count 2
[00:17:35] [PASSED] Link rate 2000000 lane count 1
[00:17:35] [PASSED] Link rate 1350000 lane count 4
[00:17:35] [PASSED] Link rate 1350000 lane count 2
[00:17:35] [PASSED] Link rate 1350000 lane count 1
[00:17:35] [PASSED] Link rate 1000000 lane count 4
[00:17:35] [PASSED] Link rate 1000000 lane count 2
[00:17:35] [PASSED] Link rate 1000000 lane count 1
[00:17:35] [PASSED] Link rate 810000 lane count 4
[00:17:35] [PASSED] Link rate 810000 lane count 2
[00:17:35] [PASSED] Link rate 810000 lane count 1
[00:17:35] [PASSED] Link rate 540000 lane count 4
[00:17:35] [PASSED] Link rate 540000 lane count 2
[00:17:35] [PASSED] Link rate 540000 lane count 1
[00:17:35] [PASSED] Link rate 270000 lane count 4
[00:17:35] [PASSED] Link rate 270000 lane count 2
[00:17:35] [PASSED] Link rate 270000 lane count 1
[00:17:35] [PASSED] Link rate 162000 lane count 4
[00:17:35] [PASSED] Link rate 162000 lane count 2
[00:17:35] [PASSED] Link rate 162000 lane count 1
[00:17:35] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[00:17:35] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[00:17:35] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[00:17:35] [PASSED] DP_POWER_UP_PHY with port number
[00:17:35] [PASSED] DP_POWER_DOWN_PHY with port number
[00:17:35] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[00:17:35] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[00:17:35] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[00:17:35] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[00:17:35] [PASSED] DP_QUERY_PAYLOAD with port number
[00:17:35] [PASSED] DP_QUERY_PAYLOAD with VCPI
[00:17:35] [PASSED] DP_REMOTE_DPCD_READ with port number
[00:17:35] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[00:17:35] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[00:17:35] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[00:17:35] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[00:17:35] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[00:17:35] [PASSED] DP_REMOTE_I2C_READ with port number
[00:17:35] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[00:17:35] [PASSED] DP_REMOTE_I2C_READ with transactions array
[00:17:35] [PASSED] DP_REMOTE_I2C_WRITE with port number
[00:17:35] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[00:17:35] [PASSED] DP_REMOTE_I2C_WRITE with data array
[00:17:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[00:17:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[00:17:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[00:17:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[00:17:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[00:17:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[00:17:35] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[00:17:35] ================ [PASSED] drm_dp_mst_helper ================
[00:17:35] ================== drm_exec (7 subtests) ===================
[00:17:35] [PASSED] sanitycheck
[00:17:35] [PASSED] test_lock
[00:17:35] [PASSED] test_lock_unlock
[00:17:35] [PASSED] test_duplicates
[00:17:35] [PASSED] test_prepare
[00:17:35] [PASSED] test_prepare_array
[00:17:35] [PASSED] test_multiple_loops
[00:17:35] ==================== [PASSED] drm_exec =====================
[00:17:35] =========== drm_format_helper_test (17 subtests) ===========
[00:17:35] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[00:17:35] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[00:17:35] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[00:17:35] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[00:17:35] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[00:17:35] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[00:17:35] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[00:17:35] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[00:17:35] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[00:17:35] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[00:17:35] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[00:17:35] ============== drm_test_fb_xrgb8888_to_mono  ===============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[00:17:35] ==================== drm_test_fb_swab  =====================
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ================ [PASSED] drm_test_fb_swab =================
[00:17:35] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[00:17:35] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[00:17:35] [PASSED] single_pixel_source_buffer
[00:17:35] [PASSED] single_pixel_clip_rectangle
[00:17:35] [PASSED] well_known_colors
[00:17:35] [PASSED] destination_pitch
[00:17:35] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[00:17:35] ================= drm_test_fb_clip_offset  =================
[00:17:35] [PASSED] pass through
[00:17:35] [PASSED] horizontal offset
[00:17:35] [PASSED] vertical offset
[00:17:35] [PASSED] horizontal and vertical offset
[00:17:35] [PASSED] horizontal offset (custom pitch)
[00:17:35] [PASSED] vertical offset (custom pitch)
[00:17:35] [PASSED] horizontal and vertical offset (custom pitch)
[00:17:35] ============= [PASSED] drm_test_fb_clip_offset =============
[00:17:35] =================== drm_test_fb_memcpy  ====================
[00:17:35] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[00:17:35] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[00:17:35] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[00:17:35] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[00:17:35] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[00:17:35] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[00:17:35] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[00:17:35] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[00:17:35] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[00:17:35] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[00:17:35] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[00:17:35] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[00:17:35] =============== [PASSED] drm_test_fb_memcpy ================
[00:17:35] ============= [PASSED] drm_format_helper_test ==============
[00:17:35] ================= drm_format (18 subtests) =================
[00:17:35] [PASSED] drm_test_format_block_width_invalid
[00:17:35] [PASSED] drm_test_format_block_width_one_plane
[00:17:35] [PASSED] drm_test_format_block_width_two_plane
[00:17:35] [PASSED] drm_test_format_block_width_three_plane
[00:17:35] [PASSED] drm_test_format_block_width_tiled
[00:17:35] [PASSED] drm_test_format_block_height_invalid
[00:17:35] [PASSED] drm_test_format_block_height_one_plane
[00:17:35] [PASSED] drm_test_format_block_height_two_plane
[00:17:35] [PASSED] drm_test_format_block_height_three_plane
[00:17:35] [PASSED] drm_test_format_block_height_tiled
[00:17:35] [PASSED] drm_test_format_min_pitch_invalid
[00:17:35] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[00:17:35] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[00:17:35] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[00:17:35] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[00:17:35] [PASSED] drm_test_format_min_pitch_two_plane
[00:17:35] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[00:17:35] [PASSED] drm_test_format_min_pitch_tiled
[00:17:35] =================== [PASSED] drm_format ====================
[00:17:35] ============== drm_framebuffer (10 subtests) ===============
[00:17:35] ========== drm_test_framebuffer_check_src_coords  ==========
[00:17:35] [PASSED] Success: source fits into fb
[00:17:35] [PASSED] Fail: overflowing fb with x-axis coordinate
[00:17:35] [PASSED] Fail: overflowing fb with y-axis coordinate
[00:17:35] [PASSED] Fail: overflowing fb with source width
[00:17:35] [PASSED] Fail: overflowing fb with source height
[00:17:35] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[00:17:35] [PASSED] drm_test_framebuffer_cleanup
[00:17:35] =============== drm_test_framebuffer_create  ===============
[00:17:35] [PASSED] ABGR8888 normal sizes
[00:17:35] [PASSED] ABGR8888 max sizes
[00:17:35] [PASSED] ABGR8888 pitch greater than min required
[00:17:35] [PASSED] ABGR8888 pitch less than min required
[00:17:35] [PASSED] ABGR8888 Invalid width
[00:17:35] [PASSED] ABGR8888 Invalid buffer handle
[00:17:35] [PASSED] No pixel format
[00:17:35] [PASSED] ABGR8888 Width 0
[00:17:35] [PASSED] ABGR8888 Height 0
[00:17:35] [PASSED] ABGR8888 Out of bound height * pitch combination
[00:17:35] [PASSED] ABGR8888 Large buffer offset
[00:17:35] [PASSED] ABGR8888 Buffer offset for inexistent plane
[00:17:35] [PASSED] ABGR8888 Invalid flag
[00:17:35] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[00:17:35] [PASSED] ABGR8888 Valid buffer modifier
[00:17:35] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[00:17:35] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[00:17:35] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[00:17:35] [PASSED] NV12 Normal sizes
[00:17:35] [PASSED] NV12 Max sizes
[00:17:35] [PASSED] NV12 Invalid pitch
[00:17:35] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[00:17:35] [PASSED] NV12 different  modifier per-plane
[00:17:35] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[00:17:35] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[00:17:35] [PASSED] NV12 Modifier for inexistent plane
[00:17:35] [PASSED] NV12 Handle for inexistent plane
[00:17:35] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[00:17:35] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[00:17:35] [PASSED] YVU420 Normal sizes
[00:17:35] [PASSED] YVU420 Max sizes
[00:17:35] [PASSED] YVU420 Invalid pitch
[00:17:35] [PASSED] YVU420 Different pitches
[00:17:35] [PASSED] YVU420 Different buffer offsets/pitches
[00:17:35] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[00:17:35] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[00:17:35] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[00:17:35] [PASSED] YVU420 Valid modifier
[00:17:35] [PASSED] YVU420 Different modifiers per plane
[00:17:35] [PASSED] YVU420 Modifier for inexistent plane
[00:17:35] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[00:17:35] [PASSED] X0L2 Normal sizes
[00:17:35] [PASSED] X0L2 Max sizes
[00:17:35] [PASSED] X0L2 Invalid pitch
[00:17:35] [PASSED] X0L2 Pitch greater than minimum required
[00:17:35] [PASSED] X0L2 Handle for inexistent plane
[00:17:35] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[00:17:35] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[00:17:35] [PASSED] X0L2 Valid modifier
[00:17:35] [PASSED] X0L2 Modifier for inexistent plane
[00:17:35] =========== [PASSED] drm_test_framebuffer_create ===========
[00:17:35] [PASSED] drm_test_framebuffer_free
[00:17:35] [PASSED] drm_test_framebuffer_init
[00:17:35] [PASSED] drm_test_framebuffer_init_bad_format
[00:17:35] [PASSED] drm_test_framebuffer_init_dev_mismatch
[00:17:35] [PASSED] drm_test_framebuffer_lookup
[00:17:35] [PASSED] drm_test_framebuffer_lookup_inexistent
[00:17:35] [PASSED] drm_test_framebuffer_modifiers_not_supported
[00:17:35] ================= [PASSED] drm_framebuffer =================
[00:17:35] ================ drm_gem_shmem (8 subtests) ================
[00:17:35] [PASSED] drm_gem_shmem_test_obj_create
[00:17:35] [PASSED] drm_gem_shmem_test_obj_create_private
[00:17:35] [PASSED] drm_gem_shmem_test_pin_pages
[00:17:35] [PASSED] drm_gem_shmem_test_vmap
[00:17:35] [PASSED] drm_gem_shmem_test_get_pages_sgt
[00:17:35] [PASSED] drm_gem_shmem_test_get_sg_table
[00:17:35] [PASSED] drm_gem_shmem_test_madvise
[00:17:35] [PASSED] drm_gem_shmem_test_purge
[00:17:35] ================== [PASSED] drm_gem_shmem ==================
[00:17:35] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[00:17:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[00:17:35] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[00:17:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[00:17:35] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[00:17:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[00:17:35] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[00:17:35] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[00:17:35] [PASSED] Automatic
[00:17:35] [PASSED] Full
[00:17:35] [PASSED] Limited 16:235
[00:17:35] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[00:17:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[00:17:35] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[00:17:35] [PASSED] drm_test_check_disable_connector
[00:17:35] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[00:17:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[00:17:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[00:17:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[00:17:35] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[00:17:35] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[00:17:35] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[00:17:35] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[00:17:35] [PASSED] drm_test_check_output_bpc_dvi
[00:17:35] [PASSED] drm_test_check_output_bpc_format_vic_1
[00:17:35] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[00:17:35] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[00:17:35] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[00:17:35] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[00:17:35] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[00:17:35] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[00:17:35] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[00:17:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[00:17:35] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[00:17:35] [PASSED] drm_test_check_broadcast_rgb_value
[00:17:35] [PASSED] drm_test_check_bpc_8_value
[00:17:35] [PASSED] drm_test_check_bpc_10_value
[00:17:35] [PASSED] drm_test_check_bpc_12_value
[00:17:35] [PASSED] drm_test_check_format_value
[00:17:35] [PASSED] drm_test_check_tmds_char_value
[00:17:35] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[00:17:35] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[00:17:35] [PASSED] drm_test_check_mode_valid
[00:17:35] [PASSED] drm_test_check_mode_valid_reject
[00:17:35] [PASSED] drm_test_check_mode_valid_reject_rate
[00:17:35] [PASSED] drm_test_check_mode_valid_reject_max_clock
[00:17:35] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[00:17:35] ================= drm_managed (2 subtests) =================
[00:17:35] [PASSED] drm_test_managed_release_action
[00:17:35] [PASSED] drm_test_managed_run_action
[00:17:35] =================== [PASSED] drm_managed ===================
[00:17:35] =================== drm_mm (6 subtests) ====================
[00:17:35] [PASSED] drm_test_mm_init
[00:17:35] [PASSED] drm_test_mm_debug
[00:17:35] [PASSED] drm_test_mm_align32
[00:17:35] [PASSED] drm_test_mm_align64
[00:17:35] [PASSED] drm_test_mm_lowest
[00:17:35] [PASSED] drm_test_mm_highest
[00:17:35] ===================== [PASSED] drm_mm ======================
[00:17:35] ============= drm_modes_analog_tv (5 subtests) =============
[00:17:35] [PASSED] drm_test_modes_analog_tv_mono_576i
[00:17:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[00:17:35] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[00:17:35] [PASSED] drm_test_modes_analog_tv_pal_576i
[00:17:35] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[00:17:35] =============== [PASSED] drm_modes_analog_tv ===============
[00:17:35] ============== drm_plane_helper (2 subtests) ===============
[00:17:35] =============== drm_test_check_plane_state  ================
[00:17:35] [PASSED] clipping_simple
[00:17:35] [PASSED] clipping_rotate_reflect
[00:17:35] [PASSED] positioning_simple
[00:17:35] [PASSED] upscaling
[00:17:35] [PASSED] downscaling
[00:17:35] [PASSED] rounding1
[00:17:35] [PASSED] rounding2
[00:17:35] [PASSED] rounding3
[00:17:35] [PASSED] rounding4
[00:17:35] =========== [PASSED] drm_test_check_plane_state ============
[00:17:35] =========== drm_test_check_invalid_plane_state  ============
[00:17:35] [PASSED] positioning_invalid
[00:17:35] [PASSED] upscaling_invalid
[00:17:35] [PASSED] downscaling_invalid
[00:17:35] ======= [PASSED] drm_test_check_invalid_plane_state ========
[00:17:35] ================ [PASSED] drm_plane_helper =================
[00:17:35] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[00:17:35] ====== drm_test_connector_helper_tv_get_modes_check  =======
[00:17:35] [PASSED] None
[00:17:35] [PASSED] PAL
[00:17:35] [PASSED] NTSC
[00:17:35] [PASSED] Both, NTSC Default
[00:17:35] [PASSED] Both, PAL Default
[00:17:35] [PASSED] Both, NTSC Default, with PAL on command-line
[00:17:35] [PASSED] Both, PAL Default, with NTSC on command-line
[00:17:35] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[00:17:35] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[00:17:35] ================== drm_rect (9 subtests) ===================
[00:17:35] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[00:17:35] [PASSED] drm_test_rect_clip_scaled_not_clipped
[00:17:35] [PASSED] drm_test_rect_clip_scaled_clipped
[00:17:35] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[00:17:35] ================= drm_test_rect_intersect  =================
[00:17:35] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[00:17:35] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[00:17:35] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[00:17:35] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[00:17:35] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[00:17:35] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[00:17:35] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[00:17:35] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[00:17:35] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[00:17:35] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[00:17:35] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[00:17:35] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[00:17:35] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[00:17:35] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[00:17:35] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[00:17:35] ============= [PASSED] drm_test_rect_intersect =============
[00:17:35] ================ drm_test_rect_calc_hscale  ================
[00:17:35] [PASSED] normal use
[00:17:35] [PASSED] out of max range
[00:17:35] [PASSED] out of min range
[00:17:35] [PASSED] zero dst
[00:17:35] [PASSED] negative src
[00:17:35] [PASSED] negative dst
[00:17:35] ============ [PASSED] drm_test_rect_calc_hscale ============
[00:17:35] ================ drm_test_rect_calc_vscale  ================
[00:17:35] [PASSED] normal use
stty: 'standard input': Inappropriate ioctl for device
[00:17:35] [PASSED] out of max range
[00:17:35] [PASSED] out of min range
[00:17:35] [PASSED] zero dst
[00:17:35] [PASSED] negative src
[00:17:35] [PASSED] negative dst
[00:17:35] ============ [PASSED] drm_test_rect_calc_vscale ============
[00:17:35] ================== drm_test_rect_rotate  ===================
[00:17:35] [PASSED] reflect-x
[00:17:35] [PASSED] reflect-y
[00:17:35] [PASSED] rotate-0
[00:17:35] [PASSED] rotate-90
[00:17:35] [PASSED] rotate-180
[00:17:35] [PASSED] rotate-270
[00:17:35] ============== [PASSED] drm_test_rect_rotate ===============
[00:17:35] ================ drm_test_rect_rotate_inv  =================
[00:17:35] [PASSED] reflect-x
[00:17:35] [PASSED] reflect-y
[00:17:35] [PASSED] rotate-0
[00:17:35] [PASSED] rotate-90
[00:17:35] [PASSED] rotate-180
[00:17:35] [PASSED] rotate-270
[00:17:35] ============ [PASSED] drm_test_rect_rotate_inv =============
[00:17:35] ==================== [PASSED] drm_rect =====================
[00:17:35] ============ drm_sysfb_modeset_test (1 subtest) ============
[00:17:35] ============ drm_test_sysfb_build_fourcc_list  =============
[00:17:35] [PASSED] no native formats
[00:17:35] [PASSED] XRGB8888 as native format
[00:17:35] [PASSED] remove duplicates
[00:17:35] [PASSED] convert alpha formats
[00:17:35] [PASSED] random formats
[00:17:35] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[00:17:35] ============= [PASSED] drm_sysfb_modeset_test ==============
[00:17:35] ============================================================
[00:17:35] Testing complete. Ran 622 tests: passed: 622
[00:17:35] Elapsed time: 27.100s total, 1.726s configuring, 24.907s building, 0.432s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[00:17:35] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[00:17:36] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[00:17:46] Starting KUnit Kernel (1/1)...
[00:17:46] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[00:17:46] ================= ttm_device (5 subtests) ==================
[00:17:46] [PASSED] ttm_device_init_basic
[00:17:46] [PASSED] ttm_device_init_multiple
[00:17:46] [PASSED] ttm_device_fini_basic
[00:17:46] [PASSED] ttm_device_init_no_vma_man
[00:17:46] ================== ttm_device_init_pools  ==================
[00:17:46] [PASSED] No DMA allocations, no DMA32 required
[00:17:46] [PASSED] DMA allocations, DMA32 required
[00:17:46] [PASSED] No DMA allocations, DMA32 required
[00:17:46] [PASSED] DMA allocations, no DMA32 required
[00:17:46] ============== [PASSED] ttm_device_init_pools ==============
[00:17:46] =================== [PASSED] ttm_device ====================
[00:17:46] ================== ttm_pool (8 subtests) ===================
[00:17:46] ================== ttm_pool_alloc_basic  ===================
[00:17:46] [PASSED] One page
[00:17:46] [PASSED] More than one page
[00:17:46] [PASSED] Above the allocation limit
[00:17:46] [PASSED] One page, with coherent DMA mappings enabled
[00:17:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:17:46] ============== [PASSED] ttm_pool_alloc_basic ===============
[00:17:46] ============== ttm_pool_alloc_basic_dma_addr  ==============
[00:17:46] [PASSED] One page
[00:17:46] [PASSED] More than one page
[00:17:46] [PASSED] Above the allocation limit
[00:17:46] [PASSED] One page, with coherent DMA mappings enabled
[00:17:46] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[00:17:46] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[00:17:46] [PASSED] ttm_pool_alloc_order_caching_match
[00:17:46] [PASSED] ttm_pool_alloc_caching_mismatch
[00:17:46] [PASSED] ttm_pool_alloc_order_mismatch
[00:17:46] [PASSED] ttm_pool_free_dma_alloc
[00:17:46] [PASSED] ttm_pool_free_no_dma_alloc
[00:17:46] [PASSED] ttm_pool_fini_basic
[00:17:46] ==================== [PASSED] ttm_pool =====================
[00:17:46] ================ ttm_resource (8 subtests) =================
[00:17:46] ================= ttm_resource_init_basic  =================
[00:17:46] [PASSED] Init resource in TTM_PL_SYSTEM
[00:17:46] [PASSED] Init resource in TTM_PL_VRAM
[00:17:46] [PASSED] Init resource in a private placement
[00:17:46] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[00:17:46] ============= [PASSED] ttm_resource_init_basic =============
[00:17:46] [PASSED] ttm_resource_init_pinned
[00:17:46] [PASSED] ttm_resource_fini_basic
[00:17:46] [PASSED] ttm_resource_manager_init_basic
[00:17:46] [PASSED] ttm_resource_manager_usage_basic
[00:17:46] [PASSED] ttm_resource_manager_set_used_basic
[00:17:46] [PASSED] ttm_sys_man_alloc_basic
[00:17:46] [PASSED] ttm_sys_man_free_basic
[00:17:46] ================== [PASSED] ttm_resource ===================
[00:17:46] =================== ttm_tt (15 subtests) ===================
[00:17:46] ==================== ttm_tt_init_basic  ====================
[00:17:46] [PASSED] Page-aligned size
[00:17:46] [PASSED] Extra pages requested
[00:17:46] ================ [PASSED] ttm_tt_init_basic ================
[00:17:46] [PASSED] ttm_tt_init_misaligned
[00:17:46] [PASSED] ttm_tt_fini_basic
[00:17:46] [PASSED] ttm_tt_fini_sg
[00:17:46] [PASSED] ttm_tt_fini_shmem
[00:17:46] [PASSED] ttm_tt_create_basic
[00:17:46] [PASSED] ttm_tt_create_invalid_bo_type
[00:17:46] [PASSED] ttm_tt_create_ttm_exists
[00:17:46] [PASSED] ttm_tt_create_failed
[00:17:46] [PASSED] ttm_tt_destroy_basic
[00:17:46] [PASSED] ttm_tt_populate_null_ttm
[00:17:46] [PASSED] ttm_tt_populate_populated_ttm
[00:17:46] [PASSED] ttm_tt_unpopulate_basic
[00:17:46] [PASSED] ttm_tt_unpopulate_empty_ttm
[00:17:46] [PASSED] ttm_tt_swapin_basic
[00:17:46] ===================== [PASSED] ttm_tt ======================
[00:17:46] =================== ttm_bo (14 subtests) ===================
[00:17:46] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[00:17:46] [PASSED] Cannot be interrupted and sleeps
[00:17:46] [PASSED] Cannot be interrupted, locks straight away
[00:17:46] [PASSED] Can be interrupted, sleeps
[00:17:46] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[00:17:46] [PASSED] ttm_bo_reserve_locked_no_sleep
[00:17:46] [PASSED] ttm_bo_reserve_no_wait_ticket
[00:17:46] [PASSED] ttm_bo_reserve_double_resv
[00:17:46] [PASSED] ttm_bo_reserve_interrupted
[00:17:46] [PASSED] ttm_bo_reserve_deadlock
[00:17:46] [PASSED] ttm_bo_unreserve_basic
[00:17:46] [PASSED] ttm_bo_unreserve_pinned
[00:17:46] [PASSED] ttm_bo_unreserve_bulk
[00:17:46] [PASSED] ttm_bo_fini_basic
[00:17:46] [PASSED] ttm_bo_fini_shared_resv
[00:17:46] [PASSED] ttm_bo_pin_basic
[00:17:46] [PASSED] ttm_bo_pin_unpin_resource
[00:17:46] [PASSED] ttm_bo_multiple_pin_one_unpin
[00:17:46] ===================== [PASSED] ttm_bo ======================
[00:17:46] ============== ttm_bo_validate (21 subtests) ===============
[00:17:46] ============== ttm_bo_init_reserved_sys_man  ===============
[00:17:46] [PASSED] Buffer object for userspace
[00:17:46] [PASSED] Kernel buffer object
[00:17:46] [PASSED] Shared buffer object
[00:17:46] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[00:17:46] ============== ttm_bo_init_reserved_mock_man  ==============
[00:17:46] [PASSED] Buffer object for userspace
[00:17:46] [PASSED] Kernel buffer object
[00:17:46] [PASSED] Shared buffer object
[00:17:46] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[00:17:46] [PASSED] ttm_bo_init_reserved_resv
[00:17:46] ================== ttm_bo_validate_basic  ==================
[00:17:46] [PASSED] Buffer object for userspace
[00:17:46] [PASSED] Kernel buffer object
[00:17:46] [PASSED] Shared buffer object
[00:17:46] ============== [PASSED] ttm_bo_validate_basic ==============
[00:17:46] [PASSED] ttm_bo_validate_invalid_placement
[00:17:46] ============= ttm_bo_validate_same_placement  ==============
[00:17:46] [PASSED] System manager
[00:17:46] [PASSED] VRAM manager
[00:17:46] ========= [PASSED] ttm_bo_validate_same_placement ==========
[00:17:46] [PASSED] ttm_bo_validate_failed_alloc
[00:17:46] [PASSED] ttm_bo_validate_pinned
[00:17:46] [PASSED] ttm_bo_validate_busy_placement
[00:17:46] ================ ttm_bo_validate_multihop  =================
[00:17:46] [PASSED] Buffer object for userspace
[00:17:46] [PASSED] Kernel buffer object
[00:17:46] [PASSED] Shared buffer object
[00:17:46] ============ [PASSED] ttm_bo_validate_multihop =============
[00:17:46] ========== ttm_bo_validate_no_placement_signaled  ==========
[00:17:46] [PASSED] Buffer object in system domain, no page vector
[00:17:46] [PASSED] Buffer object in system domain with an existing page vector
[00:17:46] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[00:17:46] ======== ttm_bo_validate_no_placement_not_signaled  ========
[00:17:46] [PASSED] Buffer object for userspace
[00:17:46] [PASSED] Kernel buffer object
[00:17:46] [PASSED] Shared buffer object
[00:17:46] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[00:17:46] [PASSED] ttm_bo_validate_move_fence_signaled
[00:17:46] ========= ttm_bo_validate_move_fence_not_signaled  =========
[00:17:46] [PASSED] Waits for GPU
[00:17:46] [PASSED] Tries to lock straight away
[00:17:46] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[00:17:46] [PASSED] ttm_bo_validate_happy_evict
[00:17:46] [PASSED] ttm_bo_validate_all_pinned_evict
[00:17:46] [PASSED] ttm_bo_validate_allowed_only_evict
[00:17:46] [PASSED] ttm_bo_validate_deleted_evict
[00:17:46] [PASSED] ttm_bo_validate_busy_domain_evict
[00:17:46] [PASSED] ttm_bo_validate_evict_gutting
[00:17:46] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[00:17:46] ================= [PASSED] ttm_bo_validate =================
[00:17:46] ============================================================
[00:17:46] Testing complete. Ran 101 tests: passed: 101
[00:17:46] Elapsed time: 11.297s total, 1.732s configuring, 9.348s building, 0.182s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/i915: Reorder cdclk stuff for vblank/guardband length checks

[Patchwork]

== Series Details ==

Series: drm/i915: Reorder cdclk stuff for vblank/guardband length checks
URL   : https://patchwork.freedesktop.org/series/155859/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast c917f7d11493984be9f381ca0a7667bd3e587ada
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2044:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2057:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2057:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2057:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:
+drivers/gpu/drm/i915/intel_uncore.c:1928:1: warning: context imbalance in 'fwtable_read8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1929:1: warning: context imbalance in 'fwtable_read16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1930:1: warning: context imbalance in 'fwtable_read32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1931:1: warning: context imbalance in 'fwtable_read64' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1996:1: warning: context imbalance in 'gen6_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1997:1: warning: context imbalance in 'gen6_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:1998:1: warning: context imbalance in 'gen6_write32' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2018:1: warning: context imbalance in 'fwtable_write8' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2019:1: warning: context imbalance in 'fwtable_write16' - unexpected unlock
+drivers/gpu/drm/i915/intel_uncore.c:2020:1: warning: context imbalance in 'fwtable_write32' - unexpected unlock

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915: Reorder cdclk stuff for vblank/guardband length checks

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 887 bytes --]

== Series Details ==

Series: drm/i915: Reorder cdclk stuff for vblank/guardband length checks
URL   : https://patchwork.freedesktop.org/series/155859/
State : success

== Summary ==

CI Bug Log - changes from xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada_BAT -> xe-pw-155859v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada -> xe-pw-155859v1

  IGT_8582: 8582
  xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada: c917f7d11493984be9f381ca0a7667bd3e587ada
  xe-pw-155859v1: 155859v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/index.html

[-- Attachment #2: Type: text/html, Size: 1435 bytes --]

✗ Xe.CI.Full: failure for drm/i915: Reorder cdclk stuff for vblank/guardband length checks

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 59621 bytes --]

== Series Details ==

Series: drm/i915: Reorder cdclk stuff for vblank/guardband length checks
URL   : https://patchwork.freedesktop.org/series/155859/
State : failure

== Summary ==

CI Bug Log - changes from xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada_FULL -> xe-pw-155859v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-155859v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-155859v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-155859v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@xe_evict@evict-beng-mixed-many-threads-small:
    - shard-dg2-set2:     NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@xe_evict@evict-beng-mixed-many-threads-small.html

  
Known issues
------------

  Here are the changes found in xe-pw-155859v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][2] ([Intel XE#316])
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][3] ([Intel XE#610])
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][4] ([Intel XE#1407]) +2 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@linear-32bpp-rotate-270:
    - shard-adlp:         NOTRUN -> [SKIP][5] ([Intel XE#316]) +2 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_big_fb@linear-32bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][6] ([Intel XE#619])
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-435/igt@kms_big_fb@y-tiled-addfb.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1477])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
    - shard-adlp:         NOTRUN -> [SKIP][8] ([Intel XE#1124]) +6 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][9] ([Intel XE#1124]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-adlp:         NOTRUN -> [SKIP][10] ([Intel XE#607])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][11] ([Intel XE#1124]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p:
    - shard-bmg:          [PASS][12] -> [SKIP][13] ([Intel XE#2314] / [Intel XE#2894]) +1 other test skip
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-4/igt@kms_bw@connected-linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p:
    - shard-adlp:         NOTRUN -> [SKIP][14] ([Intel XE#2191]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@kms_bw@connected-linear-tiling-2-displays-3840x2160p.html

  * igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#2191])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-435/igt@kms_bw@connected-linear-tiling-3-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-2-displays-1920x1080p:
    - shard-adlp:         NOTRUN -> [SKIP][16] ([Intel XE#367])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html

  * igt@kms_bw@linear-tiling-3-displays-2160x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][17] ([Intel XE#367])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_bw@linear-tiling-3-displays-2160x1440p.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc:
    - shard-adlp:         NOTRUN -> [SKIP][18] ([Intel XE#455] / [Intel XE#787]) +29 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][19] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][20] ([Intel XE#787]) +44 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][21] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-8/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][22] ([Intel XE#2887]) +2 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][23] ([Intel XE#2669]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs@pipe-b-edp-1.html

  * igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#787]) +27 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@kms_ccs@crc-primary-rotation-180-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-6.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-dg2-set2:     NOTRUN -> [SKIP][25] ([Intel XE#2907])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc:
    - shard-dg2-set2:     [PASS][26] -> [INCOMPLETE][27] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4:
    - shard-dg2-set2:     [PASS][28] -> [INCOMPLETE][29] ([Intel XE#6168])
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-dp-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6:
    - shard-dg2-set2:     [PASS][30] -> [DMESG-WARN][31] ([Intel XE#1727] / [Intel XE#3113])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-432/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-a-hdmi-a-6.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#306]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-lnl:          NOTRUN -> [SKIP][33] ([Intel XE#373])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate:
    - shard-adlp:         NOTRUN -> [SKIP][34] ([Intel XE#373]) +6 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][35] ([Intel XE#373])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@kms_chamelium_hpd@hdmi-hpd-after-hibernate.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][36] ([Intel XE#1178])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-8/igt@kms_content_protection@atomic-dpms@pipe-a-dp-2.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-adlp:         NOTRUN -> [SKIP][37] ([Intel XE#307]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-lnl:          NOTRUN -> [SKIP][38] ([Intel XE#1468])
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-adlp:         NOTRUN -> [SKIP][39] ([Intel XE#308])
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1424]) +1 other test skip
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][41] -> [SKIP][42] ([Intel XE#2291]) +6 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-5/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
    - shard-adlp:         NOTRUN -> [SKIP][43] ([Intel XE#309]) +4 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#309])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-bmg:          [PASS][45] -> [FAIL][46] ([Intel XE#1475])
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-bmg:          [PASS][47] -> [FAIL][48] ([Intel XE#5299])
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2-set2:     NOTRUN -> [SKIP][49] ([Intel XE#323])
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
    - shard-adlp:         NOTRUN -> [SKIP][50] ([Intel XE#323])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-bmg:          [PASS][51] -> [SKIP][52] ([Intel XE#4302])
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-1/igt@kms_display_modes@extended-mode-basic.html
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-bmg:          [PASS][53] -> [SKIP][54] ([Intel XE#1340])
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dp_aux_dev:
    - shard-bmg:          [PASS][55] -> [SKIP][56] ([Intel XE#3009])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-5/igt@kms_dp_aux_dev.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-4/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-lnl:          NOTRUN -> [SKIP][57] ([Intel XE#4354])
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-adlp:         NOTRUN -> [SKIP][58] ([Intel XE#4356])
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-adlp:         NOTRUN -> [SKIP][59] ([Intel XE#4331])
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_feature_discovery@chamelium:
    - shard-dg2-set2:     NOTRUN -> [SKIP][60] ([Intel XE#701])
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-2x:
    - shard-bmg:          [PASS][61] -> [SKIP][62] ([Intel XE#2373])
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_feature_discovery@display-2x.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][63] ([Intel XE#1421]) +1 other test skip
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-adlp:         NOTRUN -> [SKIP][64] ([Intel XE#310]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-bmg:          [PASS][65] -> [SKIP][66] ([Intel XE#2316]) +12 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-1/igt@kms_flip@2x-nonexisting-fb.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
    - shard-adlp:         [PASS][67] -> [DMESG-WARN][68] ([Intel XE#4543]) +6 other tests dmesg-warn
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-2/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#1401] / [Intel XE#1745]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][70] ([Intel XE#1401]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][71] ([Intel XE#4543] / [Intel XE#4921]) +3 other tests dmesg-fail
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt:
    - shard-adlp:         NOTRUN -> [SKIP][72] ([Intel XE#651]) +8 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@drrs-suspend:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#651]) +3 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_frontbuffer_tracking@drrs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render:
    - shard-adlp:         NOTRUN -> [DMESG-FAIL][74] ([Intel XE#4543]) +5 other tests dmesg-fail
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][75] ([Intel XE#656]) +28 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-plflip-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][76] ([Intel XE#651]) +4 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
    - shard-adlp:         NOTRUN -> [SKIP][77] ([Intel XE#653]) +7 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][78] ([Intel XE#656]) +6 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#653]) +4 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-lnl:          NOTRUN -> [SKIP][80] ([Intel XE#3374] / [Intel XE#3544])
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@static-swap:
    - shard-bmg:          [PASS][81] -> [SKIP][82] ([Intel XE#1503]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_hdr@static-swap.html
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-4/igt@kms_hdr@static-swap.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-bmg:          [PASS][83] -> [SKIP][84] ([Intel XE#3012])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_joiner@basic-force-big-joiner.html
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-4/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-adlp:         NOTRUN -> [SKIP][85] ([Intel XE#3012])
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-lnl:          NOTRUN -> [SKIP][86] ([Intel XE#4329])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-adlp:         NOTRUN -> [SKIP][87] ([Intel XE#4596])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-bmg:          [PASS][88] -> [SKIP][89] ([Intel XE#4596])
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-1/igt@kms_plane_multiple@2x-tiling-x.html
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-adlp:         NOTRUN -> [SKIP][90] ([Intel XE#1129])
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-adlp:         NOTRUN -> [SKIP][91] ([Intel XE#836])
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-lnl:          NOTRUN -> [SKIP][92] ([Intel XE#1406] / [Intel XE#2893] / [Intel XE#4608])
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][93] ([Intel XE#1406] / [Intel XE#4608]) +1 other test skip
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-dg2-set2:     NOTRUN -> [SKIP][94] ([Intel XE#1406] / [Intel XE#1489]) +2 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][95] ([Intel XE#1406] / [Intel XE#2893])
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb:
    - shard-adlp:         NOTRUN -> [SKIP][96] ([Intel XE#1406] / [Intel XE#1489]) +4 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-adlp:         NOTRUN -> [SKIP][97] ([Intel XE#1122] / [Intel XE#1406] / [Intel XE#5580]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@fbc-pr-cursor-plane-move:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#1406]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_psr@fbc-pr-cursor-plane-move.html

  * igt@kms_psr@pr-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][99] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +1 other test skip
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@kms_psr@pr-dpms.html

  * igt@kms_psr@psr2-suspend:
    - shard-adlp:         NOTRUN -> [SKIP][100] ([Intel XE#1406] / [Intel XE#2850] / [Intel XE#929]) +7 other tests skip
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@kms_psr@psr2-suspend.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-dg2-set2:     NOTRUN -> [SKIP][101] ([Intel XE#1127])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
    - shard-adlp:         NOTRUN -> [SKIP][102] ([Intel XE#3414]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-adlp:         NOTRUN -> [SKIP][103] ([Intel XE#455]) +8 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_setmode@basic:
    - shard-lnl:          [PASS][104] -> [FAIL][105] ([i915#15106]) +1 other test fail
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-lnl-7/igt@kms_setmode@basic.html
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-1/igt@kms_setmode@basic.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-lnl:          NOTRUN -> [SKIP][106] ([Intel XE#330])
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@kms_tv_load_detect@load-detect.html

  * igt@xe_ccs@suspend-resume:
    - shard-adlp:         NOTRUN -> [SKIP][107] ([Intel XE#455] / [Intel XE#488] / [Intel XE#5607])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@xe_ccs@suspend-resume.html

  * igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute:
    - shard-dg2-set2:     NOTRUN -> [SKIP][108] ([Intel XE#1280] / [Intel XE#455]) +1 other test skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@xe_compute_preempt@compute-threadgroup-preempt@engine-drm_xe_engine_class_compute.html

  * igt@xe_create@create-big-vram:
    - shard-adlp:         NOTRUN -> [SKIP][109] ([Intel XE#1062])
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@xe_create@create-big-vram.html

  * igt@xe_eu_stall@blocking-re-enable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][110] ([Intel XE#5626]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@xe_eu_stall@blocking-re-enable.html

  * igt@xe_eudebug@sysfs-toggle:
    - shard-lnl:          NOTRUN -> [SKIP][111] ([Intel XE#4837]) +3 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@xe_eudebug@sysfs-toggle.html

  * igt@xe_eudebug_online@interrupt-other-debuggable:
    - shard-dg2-set2:     NOTRUN -> [SKIP][112] ([Intel XE#4837]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@xe_eudebug_online@interrupt-other-debuggable.html

  * igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram:
    - shard-adlp:         NOTRUN -> [SKIP][113] ([Intel XE#4837] / [Intel XE#5565]) +7 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@xe_eudebug_online@writes-caching-vram-bb-vram-target-vram.html

  * igt@xe_evict@evict-beng-small-multi-vm:
    - shard-adlp:         NOTRUN -> [SKIP][114] ([Intel XE#261] / [Intel XE#5564] / [Intel XE#688])
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@xe_evict@evict-beng-small-multi-vm.html

  * igt@xe_evict@evict-large:
    - shard-adlp:         NOTRUN -> [SKIP][115] ([Intel XE#261] / [Intel XE#5564]) +1 other test skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@xe_evict@evict-large.html

  * igt@xe_evict@evict-mixed-many-threads-small:
    - shard-lnl:          NOTRUN -> [SKIP][116] ([Intel XE#688]) +1 other test skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@xe_evict@evict-mixed-many-threads-small.html

  * igt@xe_evict@evict-threads-large:
    - shard-adlp:         NOTRUN -> [SKIP][117] ([Intel XE#261]) +2 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@xe_evict@evict-threads-large.html

  * igt@xe_evict_ccs@evict-overcommit-standalone-nofree-reopen:
    - shard-adlp:         NOTRUN -> [SKIP][118] ([Intel XE#688]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@xe_evict_ccs@evict-overcommit-standalone-nofree-reopen.html

  * igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind:
    - shard-lnl:          NOTRUN -> [SKIP][119] ([Intel XE#1392]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@xe_exec_basic@multigpu-no-exec-basic-defer-bind.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
    - shard-adlp:         NOTRUN -> [SKIP][120] ([Intel XE#1392] / [Intel XE#5575]) +6 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html

  * igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault:
    - shard-adlp:         NOTRUN -> [SKIP][121] ([Intel XE#288] / [Intel XE#5561]) +18 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@xe_exec_fault_mode@invalid-va-scratch-nopagefault.html

  * igt@xe_exec_fault_mode@many-execqueues-basic:
    - shard-dg2-set2:     NOTRUN -> [SKIP][122] ([Intel XE#288])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@xe_exec_fault_mode@many-execqueues-basic.html

  * igt@xe_exec_system_allocator@process-many-large-mmap-file-mlock:
    - shard-adlp:         NOTRUN -> [SKIP][123] ([Intel XE#4915]) +151 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@xe_exec_system_allocator@process-many-large-mmap-file-mlock.html

  * igt@xe_exec_system_allocator@threads-many-large-mmap-huge:
    - shard-lnl:          NOTRUN -> [SKIP][124] ([Intel XE#4943]) +5 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@xe_exec_system_allocator@threads-many-large-mmap-huge.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-huge-nomemset:
    - shard-bmg:          NOTRUN -> [SKIP][125] ([Intel XE#4943])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-4/igt@xe_exec_system_allocator@threads-shared-vm-many-execqueues-mmap-huge-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-race-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][126] ([Intel XE#4915]) +32 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@xe_exec_system_allocator@threads-shared-vm-many-stride-new-race-nomemset.html

  * igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv:
    - shard-dg2-set2:     NOTRUN -> [ABORT][127] ([Intel XE#5466])
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html
    - shard-adlp:         NOTRUN -> [ABORT][128] ([Intel XE#5530])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@xe_fault_injection@probe-fail-guc-xe_guc_ct_send_recv.html

  * igt@xe_mmap@pci-membarrier:
    - shard-lnl:          NOTRUN -> [SKIP][129] ([Intel XE#5100])
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@xe_mmap@pci-membarrier.html

  * igt@xe_oa@mmio-triggered-reports-read:
    - shard-adlp:         NOTRUN -> [SKIP][130] ([Intel XE#6032])
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@xe_oa@mmio-triggered-reports-read.html

  * igt@xe_oa@privileged-forked-access-vaddr:
    - shard-bmg:          [PASS][131] -> [DMESG-WARN][132] ([Intel XE#3428]) +8 other tests dmesg-warn
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@xe_oa@privileged-forked-access-vaddr.html
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@xe_oa@privileged-forked-access-vaddr.html

  * igt@xe_oa@privileged-forked-access-vaddr@ccs-0:
    - shard-bmg:          NOTRUN -> [DMESG-WARN][133] ([Intel XE#3428])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@xe_oa@privileged-forked-access-vaddr@ccs-0.html

  * igt@xe_oa@syncs-syncobj-cfg:
    - shard-adlp:         NOTRUN -> [SKIP][134] ([Intel XE#3573]) +4 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@xe_oa@syncs-syncobj-cfg.html

  * igt@xe_pat@display-vs-wb-transient:
    - shard-adlp:         NOTRUN -> [SKIP][135] ([Intel XE#1337] / [Intel XE#5572])
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@xe_pat@display-vs-wb-transient.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][136] ([Intel XE#1337])
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@xe_pat@display-vs-wb-transient.html

  * igt@xe_pm@d3cold-mmap-vram:
    - shard-lnl:          NOTRUN -> [SKIP][137] ([Intel XE#2284] / [Intel XE#366]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@xe_pm@d3cold-mmap-vram.html

  * igt@xe_pm@d3hot-mmap-vram:
    - shard-adlp:         NOTRUN -> [SKIP][138] ([Intel XE#1948])
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@xe_pm@d3hot-mmap-vram.html

  * igt@xe_pm@s2idle-d3hot-basic-exec:
    - shard-bmg:          [PASS][139] -> [DMESG-WARN][140] ([Intel XE#3428] / [Intel XE#4504])
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@xe_pm@s2idle-d3hot-basic-exec.html
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@xe_pm@s2idle-d3hot-basic-exec.html

  * igt@xe_pmu@fn-engine-activity-load:
    - shard-dg2-set2:     NOTRUN -> [SKIP][141] ([Intel XE#4650]) +1 other test skip
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-463/igt@xe_pmu@fn-engine-activity-load.html

  * igt@xe_pxp@display-black-pxp-fb:
    - shard-adlp:         NOTRUN -> [SKIP][142] ([Intel XE#4733])
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@xe_pxp@display-black-pxp-fb.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-bmg:          NOTRUN -> [SKIP][143] ([Intel XE#4733])
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-4/igt@xe_pxp@display-pxp-fb.html
    - shard-dg2-set2:     NOTRUN -> [SKIP][144] ([Intel XE#4733])
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_pxp@pxp-termination-key-update-post-suspend:
    - shard-adlp:         NOTRUN -> [SKIP][145] ([Intel XE#4733] / [Intel XE#5594])
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@xe_pxp@pxp-termination-key-update-post-suspend.html

  * igt@xe_query@multigpu-query-config:
    - shard-lnl:          NOTRUN -> [SKIP][146] ([Intel XE#944])
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@xe_query@multigpu-query-config.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-adlp:         NOTRUN -> [SKIP][147] ([Intel XE#944]) +1 other test skip
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-9/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  * igt@xe_render_copy@render-stress-2-copies:
    - shard-adlp:         NOTRUN -> [SKIP][148] ([Intel XE#4814] / [Intel XE#5614])
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-6/igt@xe_render_copy@render-stress-2-copies.html

  * igt@xe_sriov_scheduling@equal-throughput:
    - shard-lnl:          NOTRUN -> [SKIP][149] ([Intel XE#4351])
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-3/igt@xe_sriov_scheduling@equal-throughput.html

  
#### Possible fixes ####

  * igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1:
    - shard-lnl:          [FAIL][150] ([Intel XE#5993]) -> [PASS][151] +3 other tests pass
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-lnl-5/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-8/igt@kms_async_flips@async-flip-with-page-flip-events-linear@pipe-c-edp-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs:
    - shard-dg2-set2:     [INCOMPLETE][152] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#4345] / [Intel XE#6168]) -> [PASS][153] +1 other test pass
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6:
    - shard-dg2-set2:     [INCOMPLETE][154] ([Intel XE#1727] / [Intel XE#3113] / [Intel XE#6168]) -> [PASS][155] +1 other test pass
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-dg2-464/igt@kms_ccs@random-ccs-data-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-6.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
    - shard-bmg:          [SKIP][156] ([Intel XE#2291]) -> [PASS][157] +7 other tests pass
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-1/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-bmg:          [SKIP][158] ([Intel XE#4354]) -> [PASS][159]
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@kms_dp_link_training@non-uhbr-sst.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-2/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-bmg:          [SKIP][160] ([Intel XE#2316]) -> [PASS][161] +12 other tests pass
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-2/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
    - shard-lnl:          [FAIL][162] ([Intel XE#301]) -> [PASS][163] +1 other test pass
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-lnl-1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-lnl-8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-bmg:          [INCOMPLETE][164] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][165] +1 other test pass
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-2/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@d-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][166] ([Intel XE#4543]) -> [PASS][167] +1 other test pass
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-adlp-2/igt@kms_flip@plain-flip-ts-check-interruptible@d-hdmi-a1.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-adlp-1/igt@kms_flip@plain-flip-ts-check-interruptible@d-hdmi-a1.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-bmg:          [SKIP][168] ([Intel XE#3012]) -> [PASS][169]
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-3/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-bmg:          [SKIP][170] ([Intel XE#4596]) -> [PASS][171]
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_plane_multiple@2x-tiling-none.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-bmg:          [SKIP][172] ([Intel XE#1435]) -> [PASS][173]
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-2/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * {igt@xe_pmu@fn-engine-activity-sched-if-idle@engine-drm_xe_engine_class_video_enhance1}:
    - shard-bmg:          [DMESG-WARN][174] ([Intel XE#3876]) -> [PASS][175] +1 other test pass
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-6/igt@xe_pmu@fn-engine-activity-sched-if-idle@engine-drm_xe_engine_class_video_enhance1.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-4/igt@xe_pmu@fn-engine-activity-sched-if-idle@engine-drm_xe_engine_class_video_enhance1.html

  
#### Warnings ####

  * igt@kms_content_protection@atomic-dpms:
    - shard-bmg:          [SKIP][176] ([Intel XE#2341]) -> [FAIL][177] ([Intel XE#1178])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_content_protection@atomic-dpms.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-8/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@legacy:
    - shard-bmg:          [FAIL][178] ([Intel XE#1178]) -> [SKIP][179] ([Intel XE#2341]) +2 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_content_protection@legacy.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@kms_content_protection@legacy.html

  * igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][180] ([Intel XE#2311]) -> [SKIP][181] ([Intel XE#2312]) +25 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-5/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-bmg:          [SKIP][182] ([Intel XE#2312]) -> [SKIP][183] ([Intel XE#5390]) +10 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff:
    - shard-bmg:          [SKIP][184] ([Intel XE#5390]) -> [SKIP][185] ([Intel XE#2312]) +9 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-bmg:          [SKIP][186] ([Intel XE#2312]) -> [SKIP][187] ([Intel XE#2311]) +21 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt:
    - shard-bmg:          [SKIP][188] ([Intel XE#2312]) -> [SKIP][189] ([Intel XE#2313]) +20 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][190] ([Intel XE#2313]) -> [SKIP][191] ([Intel XE#2312]) +24 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-2/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-bmg:          [SKIP][192] ([Intel XE#3374] / [Intel XE#3544]) -> [SKIP][193] ([Intel XE#3544])
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-4/igt@kms_hdr@brightness-with-hdr.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-1/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-bmg:          [SKIP][194] ([Intel XE#5021]) -> [SKIP][195] ([Intel XE#4596])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-3/igt@kms_plane_multiple@2x-tiling-yf.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-bmg:          [SKIP][196] ([Intel XE#2426]) -> [SKIP][197] ([Intel XE#2509])
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#1062]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1062
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1127]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1127
  [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1280]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1280
  [Intel XE#1337]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1337
  [Intel XE#1340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1340
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1401]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1401
  [Intel XE#1406]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1406
  [Intel XE#1407]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1407
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1468]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1468
  [Intel XE#1475]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1475
  [Intel XE#1477]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1477
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1948
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2373
  [Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
  [Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2669]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2669
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
  [Intel XE#3009]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3009
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#3012]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3012
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#3113]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3113
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
  [Intel XE#330]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/330
  [Intel XE#3374]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3374
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3428]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3428
  [Intel XE#3544]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3544
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#3876]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3876
  [Intel XE#4302]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4302
  [Intel XE#4329]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4329
  [Intel XE#4331]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4331
  [Intel XE#4345]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4345
  [Intel XE#4351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4351
  [Intel XE#4354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4354
  [Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
  [Intel XE#4504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4504
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4650]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4650
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4814]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4814
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4921]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4921
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5021]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5021
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5299]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5299
  [Intel XE#5390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5390
  [Intel XE#5466]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5466
  [Intel XE#5503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5503
  [Intel XE#5530]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5530
  [Intel XE#5561]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5561
  [Intel XE#5564]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5564
  [Intel XE#5565]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5565
  [Intel XE#5572]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5572
  [Intel XE#5575]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5575
  [Intel XE#5580]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5580
  [Intel XE#5594]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5594
  [Intel XE#5607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5607
  [Intel XE#5614]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5614
  [Intel XE#5626]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5626
  [Intel XE#5993]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5993
  [Intel XE#6011]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6011
  [Intel XE#6032]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6032
  [Intel XE#607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/607
  [Intel XE#610]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/610
  [Intel XE#6168]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6168
  [Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
  [Intel XE#6312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6312
  [Intel XE#6320]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6320
  [Intel XE#6326]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6326
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/701
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [i915#15106]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15106


Build changes
-------------

  * Linux: xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada -> xe-pw-155859v1

  IGT_8582: 8582
  xe-3911-c917f7d11493984be9f381ca0a7667bd3e587ada: c917f7d11493984be9f381ca0a7667bd3e587ada
  xe-pw-155859v1: 155859v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-155859v1/index.html

[-- Attachment #2: Type: text/html, Size: 69160 bytes --]

RE: [PATCH 1/9] drm/i915/bw: Untangle dbuf bw from the sagv/mem bw stuff

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Monday, 13 October 2025 23.12
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 1/9] drm/i915/bw: Untangle dbuf bw from the sagv/mem bw stuff
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently intel_bw.c contains basically three completely independent
> parts:
> - SAGV/memory bandwidth handling
> - DBuf bandwidth handling
> - "Maximum pipe read bandwidth" calculation, which is some kind
>   of internal per-pipe bandwidth limit.
> 
> Carve out the DBuf bandwdith handling into a separate file since there is no actual dependency between it and the rest of
> intel_bw.c.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  drivers/gpu/drm/i915/display/intel_bw.c       | 191 ------------
>  drivers/gpu/drm/i915/display/intel_bw.h       |   4 -
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  32 +-
>  drivers/gpu/drm/i915/display/intel_cdclk.h    |   7 +-
>  drivers/gpu/drm/i915/display/intel_dbuf_bw.c  | 295 ++++++++++++++++++  drivers/gpu/drm/i915/display/intel_dbuf_bw.h  |
> 37 +++
>  .../gpu/drm/i915/display/intel_display_core.h |   4 +
>  .../drm/i915/display/intel_display_driver.c   |   5 +
>  .../drm/i915/display/intel_modeset_setup.c    |   3 +
>  drivers/gpu/drm/xe/Makefile                   |   1 +
>  11 files changed, 363 insertions(+), 217 deletions(-)  create mode 100644 drivers/gpu/drm/i915/display/intel_dbuf_bw.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_dbuf_bw.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 6d7800e25e55..dbdf88b42919 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -241,6 +241,7 @@ i915-y += \
>  	display/intel_crtc.o \
>  	display/intel_crtc_state_dump.o \
>  	display/intel_cursor.o \
> +	display/intel_dbuf_bw.o \
>  	display/intel_display.o \
>  	display/intel_display_conversion.o \
>  	display/intel_display_driver.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index b53bcb693e79..a4d16711d336 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -3,16 +3,12 @@
>   * Copyright © 2019 Intel Corporation
>   */
> 
> -#include <drm/drm_atomic_state_helper.h>
> -
>  #include "soc/intel_dram.h"
> 
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "i915_utils.h"
> -#include "intel_atomic.h"
>  #include "intel_bw.h"
> -#include "intel_cdclk.h"
>  #include "intel_crtc.h"
>  #include "intel_display_core.h"
>  #include "intel_display_regs.h"
> @@ -22,14 +18,8 @@
>  #include "intel_uncore.h"
>  #include "skl_watermark.h"
> 
> -struct intel_dbuf_bw {
> -	unsigned int max_bw[I915_MAX_DBUF_SLICES];
> -	u8 active_planes[I915_MAX_DBUF_SLICES];
> -};
> -
>  struct intel_bw_state {
>  	struct intel_global_state base;
> -	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
> 
>  	/*
>  	 * Contains a bit mask, used to determine, whether correspondent @@ -1264,184 +1254,6 @@ static int
> intel_bw_check_qgv_points(struct intel_display *display,
>  					   old_bw_state, new_bw_state);
>  }
> 
> -static bool intel_dbuf_bw_changed(struct intel_display *display,
> -				  const struct intel_dbuf_bw *old_dbuf_bw,
> -				  const struct intel_dbuf_bw *new_dbuf_bw)
> -{
> -	enum dbuf_slice slice;
> -
> -	for_each_dbuf_slice(display, slice) {
> -		if (old_dbuf_bw->max_bw[slice] != new_dbuf_bw->max_bw[slice] ||
> -		    old_dbuf_bw->active_planes[slice] != new_dbuf_bw->active_planes[slice])
> -			return true;
> -	}
> -
> -	return false;
> -}
> -
> -static bool intel_bw_state_changed(struct intel_display *display,
> -				   const struct intel_bw_state *old_bw_state,
> -				   const struct intel_bw_state *new_bw_state)
> -{
> -	enum pipe pipe;
> -
> -	for_each_pipe(display, pipe) {
> -		const struct intel_dbuf_bw *old_dbuf_bw =
> -			&old_bw_state->dbuf_bw[pipe];
> -		const struct intel_dbuf_bw *new_dbuf_bw =
> -			&new_bw_state->dbuf_bw[pipe];
> -
> -		if (intel_dbuf_bw_changed(display, old_dbuf_bw, new_dbuf_bw))
> -			return true;
> -	}
> -
> -	return false;
> -}
> -
> -static void skl_plane_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw,
> -				   struct intel_crtc *crtc,
> -				   enum plane_id plane_id,
> -				   const struct skl_ddb_entry *ddb,
> -				   unsigned int data_rate)
> -{
> -	struct intel_display *display = to_intel_display(crtc);
> -	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);
> -	enum dbuf_slice slice;
> -
> -	/*
> -	 * The arbiter can only really guarantee an
> -	 * equal share of the total bw to each plane.
> -	 */
> -	for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) {
> -		dbuf_bw->max_bw[slice] = max(dbuf_bw->max_bw[slice], data_rate);
> -		dbuf_bw->active_planes[slice] |= BIT(plane_id);
> -	}
> -}
> -
> -static void skl_crtc_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw,
> -				  const struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_display *display = to_intel_display(crtc_state);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	enum plane_id plane_id;
> -
> -	memset(dbuf_bw, 0, sizeof(*dbuf_bw));
> -
> -	if (!crtc_state->hw.active)
> -		return;
> -
> -	for_each_plane_id_on_crtc(crtc, plane_id) {
> -		/*
> -		 * We assume cursors are small enough
> -		 * to not cause bandwidth problems.
> -		 */
> -		if (plane_id == PLANE_CURSOR)
> -			continue;
> -
> -		skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,
> -				       &crtc_state->wm.skl.plane_ddb[plane_id],
> -				       crtc_state->data_rate[plane_id]);
> -
> -		if (DISPLAY_VER(display) < 11)
> -			skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,
> -					       &crtc_state->wm.skl.plane_ddb_y[plane_id],
> -					       crtc_state->data_rate[plane_id]);
> -	}
> -}
> -
> -/* "Maximum Data Buffer Bandwidth" */
> -static int
> -intel_bw_dbuf_min_cdclk(struct intel_display *display,
> -			const struct intel_bw_state *bw_state)
> -{
> -	unsigned int total_max_bw = 0;
> -	enum dbuf_slice slice;
> -
> -	for_each_dbuf_slice(display, slice) {
> -		int num_active_planes = 0;
> -		unsigned int max_bw = 0;
> -		enum pipe pipe;
> -
> -		/*
> -		 * The arbiter can only really guarantee an
> -		 * equal share of the total bw to each plane.
> -		 */
> -		for_each_pipe(display, pipe) {
> -			const struct intel_dbuf_bw *dbuf_bw = &bw_state->dbuf_bw[pipe];
> -
> -			max_bw = max(dbuf_bw->max_bw[slice], max_bw);
> -			num_active_planes += hweight8(dbuf_bw->active_planes[slice]);
> -		}
> -		max_bw *= num_active_planes;
> -
> -		total_max_bw = max(total_max_bw, max_bw);
> -	}
> -
> -	return DIV_ROUND_UP(total_max_bw, 64);
> -}
> -
> -int intel_bw_min_cdclk(struct intel_display *display,
> -		       const struct intel_bw_state *bw_state)
> -{
> -	int min_cdclk;
> -
> -	min_cdclk = intel_bw_dbuf_min_cdclk(display, bw_state);
> -
> -	return min_cdclk;
> -}
> -
> -int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> -			    bool *need_cdclk_calc)
> -{
> -	struct intel_display *display = to_intel_display(state);
> -	struct intel_bw_state *new_bw_state = NULL;
> -	const struct intel_bw_state *old_bw_state = NULL;
> -	const struct intel_crtc_state *old_crtc_state;
> -	const struct intel_crtc_state *new_crtc_state;
> -	struct intel_crtc *crtc;
> -	int ret, i;
> -
> -	if (DISPLAY_VER(display) < 9)
> -		return 0;
> -
> -	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> -					    new_crtc_state, i) {
> -		struct intel_dbuf_bw old_dbuf_bw, new_dbuf_bw;
> -
> -		skl_crtc_calc_dbuf_bw(&old_dbuf_bw, old_crtc_state);
> -		skl_crtc_calc_dbuf_bw(&new_dbuf_bw, new_crtc_state);
> -
> -		if (!intel_dbuf_bw_changed(display, &old_dbuf_bw, &new_dbuf_bw))
> -			continue;
> -
> -		new_bw_state = intel_atomic_get_bw_state(state);
> -		if (IS_ERR(new_bw_state))
> -			return PTR_ERR(new_bw_state);
> -
> -		old_bw_state = intel_atomic_get_old_bw_state(state);
> -
> -		new_bw_state->dbuf_bw[crtc->pipe] = new_dbuf_bw;
> -	}
> -
> -	if (!old_bw_state)
> -		return 0;
> -
> -	if (intel_bw_state_changed(display, old_bw_state, new_bw_state)) {
> -		int ret = intel_atomic_lock_global_state(&new_bw_state->base);
> -		if (ret)
> -			return ret;
> -	}
> -
> -	ret = intel_cdclk_update_bw_min_cdclk(state,
> -					      intel_bw_min_cdclk(display, old_bw_state),
> -					      intel_bw_min_cdclk(display, new_bw_state),
> -					      need_cdclk_calc);
> -	if (ret)
> -		return ret;
> -
> -	return 0;
> -}
> -
>  static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)  {
>  	struct intel_display *display = to_intel_display(state); @@ -1647,8 +1459,6 @@ void intel_bw_update_hw_state(struct
> intel_display *display)
>  		if (DISPLAY_VER(display) >= 11)
>  			intel_bw_crtc_update(bw_state, crtc_state);
> 
> -		skl_crtc_calc_dbuf_bw(&bw_state->dbuf_bw[pipe], crtc_state);
> -
>  		/* initially SAGV has been forced off */
>  		bw_state->pipe_sagv_reject |= BIT(pipe);
>  	}
> @@ -1666,7 +1476,6 @@ void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc)
> 
>  	bw_state->data_rate[pipe] = 0;
>  	bw_state->num_active_planes[pipe] = 0;
> -	memset(&bw_state->dbuf_bw[pipe], 0, sizeof(bw_state->dbuf_bw[pipe]));
>  }
> 
>  static struct intel_global_state *
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 4bb3a637b295..051e163f2f15 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -30,10 +30,6 @@ void intel_bw_init_hw(struct intel_display *display);  int intel_bw_init(struct intel_display *display);  int
> intel_bw_atomic_check(struct intel_atomic_state *state);  int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);
> -int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
> -			    bool *need_cdclk_calc);
> -int intel_bw_min_cdclk(struct intel_display *display,
> -		       const struct intel_bw_state *bw_state);
>  void intel_bw_update_hw_state(struct intel_display *display);  void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f2e092f89ddd..23b9e100d824 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -38,6 +38,7 @@
>  #include "intel_bw.h"
>  #include "intel_cdclk.h"
>  #include "intel_crtc.h"
> +#include "intel_dbuf_bw.h"
>  #include "intel_de.h"
>  #include "intel_display_regs.h"
>  #include "intel_display_types.h"
> @@ -133,8 +134,8 @@ struct intel_cdclk_state {
>  	 */
>  	struct intel_cdclk_config actual;
> 
> -	/* minimum acceptable cdclk to satisfy bandwidth requirements */
> -	int bw_min_cdclk;
> +	/* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */
> +	int dbuf_bw_min_cdclk;
>  	/* minimum acceptable cdclk for each pipe */
>  	int min_cdclk[I915_MAX_PIPES];
>  	/* minimum acceptable voltage level for each pipe */ @@ -2891,9 +2892,9 @@ static int
> intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state,
>  	return 0;
>  }
> 
> -int intel_cdclk_update_bw_min_cdclk(struct intel_atomic_state *state,
> -				    int old_min_cdclk, int new_min_cdclk,
> -				    bool *need_cdclk_calc)
> +int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state,
> +					 int old_min_cdclk, int new_min_cdclk,
> +					 bool *need_cdclk_calc)
>  {
>  	struct intel_display *display = to_intel_display(state);
>  	struct intel_cdclk_state *cdclk_state; @@ -2910,7 +2911,7 @@ int intel_cdclk_update_bw_min_cdclk(struct
> intel_atomic_state *state,
>  	if (IS_ERR(cdclk_state))
>  		return PTR_ERR(cdclk_state);
> 
> -	old_min_cdclk = cdclk_state->bw_min_cdclk;
> +	old_min_cdclk = cdclk_state->dbuf_bw_min_cdclk;
> 
>  	if (new_min_cdclk == old_min_cdclk)
>  		return 0;
> @@ -2918,7 +2919,7 @@ int intel_cdclk_update_bw_min_cdclk(struct intel_atomic_state *state,
>  	if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
>  		return 0;
> 
> -	cdclk_state->bw_min_cdclk = new_min_cdclk;
> +	cdclk_state->dbuf_bw_min_cdclk = new_min_cdclk;
> 
>  	ret = intel_atomic_lock_global_state(&cdclk_state->base);
>  	if (ret)
> @@ -2927,7 +2928,7 @@ int intel_cdclk_update_bw_min_cdclk(struct intel_atomic_state *state,
>  	*need_cdclk_calc = true;
> 
>  	drm_dbg_kms(display->drm,
> -		    "bandwidth min cdclk: %d kHz -> %d kHz\n",
> +		    "dbuf bandwidth min cdclk: %d kHz -> %d kHz\n",
>  		    old_min_cdclk, new_min_cdclk);
> 
>  	return 0;
> @@ -2950,7 +2951,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
>  	int min_cdclk;
> 
>  	min_cdclk = cdclk_state->force_min_cdclk;
> -	min_cdclk = max(min_cdclk, cdclk_state->bw_min_cdclk);
> +	min_cdclk = max(min_cdclk, cdclk_state->dbuf_bw_min_cdclk);
>  	for_each_pipe(display, pipe)
>  		min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);
> 
> @@ -3476,7 +3477,7 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state)
>  	if (ret)
>  		return ret;
> 
> -	ret = intel_bw_calc_min_cdclk(state, &need_cdclk_calc);
> +	ret = intel_dbuf_bw_calc_min_cdclk(state, &need_cdclk_calc);
>  	if (ret)
>  		return ret;
> 
> @@ -3503,8 +3504,8 @@ int intel_cdclk_atomic_check(struct intel_atomic_state *state)
> 
>  void intel_cdclk_update_hw_state(struct intel_display *display)  {
> -	const struct intel_bw_state *bw_state =
> -		to_intel_bw_state(display->bw.obj.state);
> +	const struct intel_dbuf_bw_state *dbuf_bw_state =
> +		to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
>  	struct intel_cdclk_state *cdclk_state =
>  		to_intel_cdclk_state(display->cdclk.obj.state);
>  	struct intel_crtc *crtc;
> @@ -3526,7 +3527,7 @@ void intel_cdclk_update_hw_state(struct intel_display *display)
>  		cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
>  	}
> 
> -	cdclk_state->bw_min_cdclk = intel_bw_min_cdclk(display, bw_state);
> +	cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display,
> +dbuf_bw_state);
>  }
> 
>  void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc) @@ -4020,11 +4021,6 @@ int intel_cdclk_min_cdclk(const struct
> intel_cdclk_state *cdclk_state, enum pipe
>  	return cdclk_state->min_cdclk[pipe];
>  }
> 
> -int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state) -{
> -	return cdclk_state->bw_min_cdclk;
> -}
> -
>  bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)  {
>  	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state; diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 72963f6f399a..d9d7a8b3a48a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -46,9 +46,9 @@ struct intel_cdclk_state *  intel_atomic_get_cdclk_state(struct intel_atomic_state *state);  void
> intel_cdclk_update_hw_state(struct intel_display *display);  void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc); -int
> intel_cdclk_update_bw_min_cdclk(struct intel_atomic_state *state,
> -				    int old_min_cdclk, int new_min_cdclk,
> -				    bool *need_cdclk_calc);
> +int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state,
> +					 int old_min_cdclk, int new_min_cdclk,
> +					 bool *need_cdclk_calc);
> 
>  #define to_intel_cdclk_state(global_state) \
>  	container_of_const((global_state), struct intel_cdclk_state, base) @@ -65,7 +65,6 @@ int intel_cdclk_logical(const struct
> intel_cdclk_state *cdclk_state);  int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state);  int
> intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state);  int intel_cdclk_min_cdclk(const struct
> intel_cdclk_state *cdclk_state, enum pipe pipe); -int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);  bool
> intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);  void intel_cdclk_force_min_cdclk(struct
> intel_cdclk_state *cdclk_state, int force_min_cdclk);  void intel_cdclk_read_hw(struct intel_display *display); diff --git
> a/drivers/gpu/drm/i915/display/intel_dbuf_bw.c b/drivers/gpu/drm/i915/display/intel_dbuf_bw.c
> new file mode 100644
> index 000000000000..8b8894c37f63
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dbuf_bw.c
> @@ -0,0 +1,295 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#include <drm/drm_print.h>
> +
> +#include "intel_dbuf_bw.h"
> +#include "intel_display_core.h"
> +#include "intel_display_types.h"
> +#include "skl_watermark.h"
> +
> +struct intel_dbuf_bw {
> +	unsigned int max_bw[I915_MAX_DBUF_SLICES];
> +	u8 active_planes[I915_MAX_DBUF_SLICES];
> +};
> +
> +struct intel_dbuf_bw_state {
> +	struct intel_global_state base;
> +	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES]; };
> +
> +struct intel_dbuf_bw_state *to_intel_dbuf_bw_state(struct
> +intel_global_state *obj_state) {
> +	return container_of(obj_state, struct intel_dbuf_bw_state, base); }
> +
> +struct intel_dbuf_bw_state *
> +intel_atomic_get_old_dbuf_bw_state(struct intel_atomic_state *state) {
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_global_state *dbuf_bw_state;
> +
> +	dbuf_bw_state = intel_atomic_get_old_global_obj_state(state,
> +&display->dbuf_bw.obj);
> +
> +	return to_intel_dbuf_bw_state(dbuf_bw_state);
> +}
> +
> +struct intel_dbuf_bw_state *
> +intel_atomic_get_new_dbuf_bw_state(struct intel_atomic_state *state) {
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_global_state *dbuf_bw_state;
> +
> +	dbuf_bw_state = intel_atomic_get_new_global_obj_state(state,
> +&display->dbuf_bw.obj);
> +
> +	return to_intel_dbuf_bw_state(dbuf_bw_state);
> +}
> +
> +struct intel_dbuf_bw_state *
> +intel_atomic_get_dbuf_bw_state(struct intel_atomic_state *state) {
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_global_state *dbuf_bw_state;
> +
> +	dbuf_bw_state = intel_atomic_get_global_obj_state(state, &display->dbuf_bw.obj);
> +	if (IS_ERR(dbuf_bw_state))
> +		return ERR_CAST(dbuf_bw_state);
> +
> +	return to_intel_dbuf_bw_state(dbuf_bw_state);
> +}
> +
> +static bool intel_dbuf_bw_changed(struct intel_display *display,
> +				  const struct intel_dbuf_bw *old_dbuf_bw,
> +				  const struct intel_dbuf_bw *new_dbuf_bw) {
> +	enum dbuf_slice slice;
> +
> +	for_each_dbuf_slice(display, slice) {
> +		if (old_dbuf_bw->max_bw[slice] != new_dbuf_bw->max_bw[slice] ||
> +		    old_dbuf_bw->active_planes[slice] != new_dbuf_bw->active_planes[slice])
> +			return true;
> +	}
> +
> +	return false;
> +}
> +
> +static bool intel_dbuf_bw_state_changed(struct intel_display *display,
> +					const struct intel_dbuf_bw_state *old_dbuf_bw_state,
> +					const struct intel_dbuf_bw_state *new_dbuf_bw_state) {
> +	enum pipe pipe;
> +
> +	for_each_pipe(display, pipe) {
> +		const struct intel_dbuf_bw *old_dbuf_bw =
> +			&old_dbuf_bw_state->dbuf_bw[pipe];
> +		const struct intel_dbuf_bw *new_dbuf_bw =
> +			&new_dbuf_bw_state->dbuf_bw[pipe];
> +
> +		if (intel_dbuf_bw_changed(display, old_dbuf_bw, new_dbuf_bw))
> +			return true;
> +	}
> +
> +	return false;
> +}
> +
> +static void skl_plane_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw,
> +				   struct intel_crtc *crtc,
> +				   enum plane_id plane_id,
> +				   const struct skl_ddb_entry *ddb,
> +				   unsigned int data_rate)
> +{
> +	struct intel_display *display = to_intel_display(crtc);
> +	unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(display, ddb);
> +	enum dbuf_slice slice;
> +
> +	/*
> +	 * The arbiter can only really guarantee an
> +	 * equal share of the total bw to each plane.
> +	 */
> +	for_each_dbuf_slice_in_mask(display, slice, dbuf_mask) {
> +		dbuf_bw->max_bw[slice] = max(dbuf_bw->max_bw[slice], data_rate);
> +		dbuf_bw->active_planes[slice] |= BIT(plane_id);
> +	}
> +}
> +
> +static void skl_crtc_calc_dbuf_bw(struct intel_dbuf_bw *dbuf_bw,
> +				  const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	enum plane_id plane_id;
> +
> +	memset(dbuf_bw, 0, sizeof(*dbuf_bw));
> +
> +	if (!crtc_state->hw.active)
> +		return;
> +
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		/*
> +		 * We assume cursors are small enough
> +		 * to not cause bandwidth problems.
> +		 */
> +		if (plane_id == PLANE_CURSOR)
> +			continue;
> +
> +		skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,
> +				       &crtc_state->wm.skl.plane_ddb[plane_id],
> +				       crtc_state->data_rate[plane_id]);
> +
> +		if (DISPLAY_VER(display) < 11)
> +			skl_plane_calc_dbuf_bw(dbuf_bw, crtc, plane_id,
> +					       &crtc_state->wm.skl.plane_ddb_y[plane_id],
> +					       crtc_state->data_rate[plane_id]);
> +	}
> +}
> +
> +/* "Maximum Data Buffer Bandwidth" */
> +int intel_dbuf_bw_min_cdclk(struct intel_display *display,
> +			    const struct intel_dbuf_bw_state *dbuf_bw_state) {
> +	unsigned int total_max_bw = 0;
> +	enum dbuf_slice slice;
> +
> +	for_each_dbuf_slice(display, slice) {
> +		int num_active_planes = 0;
> +		unsigned int max_bw = 0;
> +		enum pipe pipe;
> +
> +		/*
> +		 * The arbiter can only really guarantee an
> +		 * equal share of the total bw to each plane.
> +		 */
> +		for_each_pipe(display, pipe) {
> +			const struct intel_dbuf_bw *dbuf_bw = &dbuf_bw_state->dbuf_bw[pipe];
> +
> +			max_bw = max(dbuf_bw->max_bw[slice], max_bw);
> +			num_active_planes += hweight8(dbuf_bw->active_planes[slice]);
> +		}
> +		max_bw *= num_active_planes;
> +
> +		total_max_bw = max(total_max_bw, max_bw);
> +	}
> +
> +	return DIV_ROUND_UP(total_max_bw, 64); }
> +
> +int intel_dbuf_bw_calc_min_cdclk(struct intel_atomic_state *state,
> +				 bool *need_cdclk_calc)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_dbuf_bw_state *new_dbuf_bw_state = NULL;
> +	const struct intel_dbuf_bw_state *old_dbuf_bw_state = NULL;
> +	const struct intel_crtc_state *old_crtc_state;
> +	const struct intel_crtc_state *new_crtc_state;
> +	struct intel_crtc *crtc;
> +	int ret, i;
> +
> +	if (DISPLAY_VER(display) < 9)
> +		return 0;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		struct intel_dbuf_bw old_dbuf_bw, new_dbuf_bw;
> +
> +		skl_crtc_calc_dbuf_bw(&old_dbuf_bw, old_crtc_state);
> +		skl_crtc_calc_dbuf_bw(&new_dbuf_bw, new_crtc_state);
> +
> +		if (!intel_dbuf_bw_changed(display, &old_dbuf_bw, &new_dbuf_bw))
> +			continue;
> +
> +		new_dbuf_bw_state = intel_atomic_get_dbuf_bw_state(state);
> +		if (IS_ERR(new_dbuf_bw_state))
> +			return PTR_ERR(new_dbuf_bw_state);
> +
> +		old_dbuf_bw_state = intel_atomic_get_old_dbuf_bw_state(state);
> +
> +		new_dbuf_bw_state->dbuf_bw[crtc->pipe] = new_dbuf_bw;
> +	}
> +
> +	if (!old_dbuf_bw_state)
> +		return 0;
> +
> +	if (intel_dbuf_bw_state_changed(display, old_dbuf_bw_state, new_dbuf_bw_state)) {
> +		ret = intel_atomic_lock_global_state(&new_dbuf_bw_state->base);
> +		if (ret)
> +			return ret;
> +	}
> +
> +	ret = intel_cdclk_update_dbuf_bw_min_cdclk(state,
> +						   intel_dbuf_bw_min_cdclk(display, old_dbuf_bw_state),
> +						   intel_dbuf_bw_min_cdclk(display, new_dbuf_bw_state),
> +						   need_cdclk_calc);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +void intel_dbuf_bw_update_hw_state(struct intel_display *display) {
> +	struct intel_dbuf_bw_state *dbuf_bw_state =
> +		to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
> +	struct intel_crtc *crtc;
> +
> +	if (DISPLAY_VER(display) < 9)
> +		return;
> +
> +	for_each_intel_crtc(display->drm, crtc) {
> +		const struct intel_crtc_state *crtc_state =
> +			to_intel_crtc_state(crtc->base.state);
> +
> +		skl_crtc_calc_dbuf_bw(&dbuf_bw_state->dbuf_bw[crtc->pipe], crtc_state);
> +	}
> +}
> +
> +void intel_dbuf_bw_crtc_disable_noatomic(struct intel_crtc *crtc) {
> +	struct intel_display *display = to_intel_display(crtc);
> +	struct intel_dbuf_bw_state *dbuf_bw_state =
> +		to_intel_dbuf_bw_state(display->dbuf_bw.obj.state);
> +	enum pipe pipe = crtc->pipe;
> +
> +	if (DISPLAY_VER(display) < 9)
> +		return;
> +
> +	memset(&dbuf_bw_state->dbuf_bw[pipe], 0,
> +sizeof(dbuf_bw_state->dbuf_bw[pipe]));
> +}
> +
> +static struct intel_global_state *
> +intel_dbuf_bw_duplicate_state(struct intel_global_obj *obj) {
> +	struct intel_dbuf_bw_state *state;
> +
> +	state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
> +	if (!state)
> +		return NULL;
> +
> +	return &state->base;
> +}
> +
> +static void intel_dbuf_bw_destroy_state(struct intel_global_obj *obj,
> +					struct intel_global_state *state)
> +{
> +	kfree(state);
> +}
> +
> +static const struct intel_global_state_funcs intel_dbuf_bw_funcs = {
> +	.atomic_duplicate_state = intel_dbuf_bw_duplicate_state,
> +	.atomic_destroy_state = intel_dbuf_bw_destroy_state, };
> +
> +int intel_dbuf_bw_init(struct intel_display *display) {
> +	struct intel_dbuf_bw_state *state;
> +
> +	state = kzalloc(sizeof(*state), GFP_KERNEL);
> +	if (!state)
> +		return -ENOMEM;
> +
> +	intel_atomic_global_obj_init(display, &display->dbuf_bw.obj,
> +				     &state->base, &intel_dbuf_bw_funcs);
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dbuf_bw.h b/drivers/gpu/drm/i915/display/intel_dbuf_bw.h
> new file mode 100644
> index 000000000000..61875b9d5969
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dbuf_bw.h
> @@ -0,0 +1,37 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2025 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DBUF_BW_H__
> +#define __INTEL_DBUF_BW_H__
> +
> +#include <drm/drm_atomic.h>
> +
> +struct intel_atomic_state;
> +struct intel_dbuf_bw_state;
> +struct intel_crtc;
> +struct intel_display;
> +struct intel_global_state;
> +
> +struct intel_dbuf_bw_state *
> +to_intel_dbuf_bw_state(struct intel_global_state *obj_state);
> +
> +struct intel_dbuf_bw_state *
> +intel_atomic_get_old_dbuf_bw_state(struct intel_atomic_state *state);
> +
> +struct intel_dbuf_bw_state *
> +intel_atomic_get_new_dbuf_bw_state(struct intel_atomic_state *state);
> +
> +struct intel_dbuf_bw_state *
> +intel_atomic_get_dbuf_bw_state(struct intel_atomic_state *state);
> +
> +int intel_dbuf_bw_init(struct intel_display *display); int
> +intel_dbuf_bw_calc_min_cdclk(struct intel_atomic_state *state,
> +				 bool *need_cdclk_calc);
> +int intel_dbuf_bw_min_cdclk(struct intel_display *display,
> +			    const struct intel_dbuf_bw_state *dbuf_bw_state); void
> +intel_dbuf_bw_update_hw_state(struct intel_display *display); void
> +intel_dbuf_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
> +
> +#endif /* __INTEL_DBUF_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index df4da52cbdb3..32664098b407 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -369,6 +369,10 @@ struct intel_display {
>  		struct intel_global_obj obj;
>  	} dbuf;
> 
> +	struct {
> +		struct intel_global_obj obj;
> +	} dbuf_bw;
> +
>  	struct {
>  		/*
>  		 * dkl.phy_lock protects against concurrent access of the diff --git
> a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index f84a0b26b7a6..38672d2896e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -28,6 +28,7 @@
>  #include "intel_cdclk.h"
>  #include "intel_color.h"
>  #include "intel_crtc.h"
> +#include "intel_dbuf_bw.h"
>  #include "intel_display_core.h"
>  #include "intel_display_debugfs.h"
>  #include "intel_display_driver.h"
> @@ -285,6 +286,10 @@ int intel_display_driver_probe_noirq(struct intel_display *display)
>  	if (ret)
>  		goto cleanup_wq_unordered;
> 
> +	ret = intel_dbuf_bw_init(display);
> +	if (ret)
> +		goto cleanup_wq_unordered;
> +
>  	ret = intel_bw_init(display);
>  	if (ret)
>  		goto cleanup_wq_unordered;
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 8415f3d703ed..deb877b2aebd 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -19,6 +19,7 @@
>  #include "intel_color.h"
>  #include "intel_crtc.h"
>  #include "intel_crtc_state_dump.h"
> +#include "intel_dbuf_bw.h"
>  #include "intel_ddi.h"
>  #include "intel_de.h"
>  #include "intel_display.h"
> @@ -176,6 +177,7 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
>  	intel_cdclk_crtc_disable_noatomic(crtc);
>  	skl_wm_crtc_disable_noatomic(crtc);
>  	intel_bw_crtc_disable_noatomic(crtc);
> +	intel_dbuf_bw_crtc_disable_noatomic(crtc);
> 
>  	intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, 0);  } @@ -872,6 +874,7 @@ static void
> intel_modeset_readout_hw_state(struct intel_display *display)
>  		intel_wm_get_hw_state(display);
> 
>  	intel_bw_update_hw_state(display);
> +	intel_dbuf_bw_update_hw_state(display);
>  	intel_cdclk_update_hw_state(display);
> 
>  	intel_pmdemand_init_pmdemand_params(display, pmdemand_state); diff --git a/drivers/gpu/drm/xe/Makefile
> b/drivers/gpu/drm/xe/Makefile index 84321fad3265..88ba3d32802d 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -243,6 +243,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \
>  	i915-display/intel_crtc_state_dump.o \
>  	i915-display/intel_cursor.o \
>  	i915-display/intel_cx0_phy.o \
> +	i915-display/intel_dbuf_bw.o \
>  	i915-display/intel_ddi.o \
>  	i915-display/intel_ddi_buf_trans.o \
>  	i915-display/intel_display.o \
> --
> 2.49.1

RE: [PATCH 2/9] drm/i915: s/"not not"/"not"/

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Monday, 13 October 2025 23.12
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 2/9] drm/i915: s/"not not"/"not"/
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Elimiante the repeated "not not" in the bw code comments.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index a4d16711d336..d03da1ed4541 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -831,7 +831,7 @@ static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_stat  {
>  	/*
>  	 * We assume cursors are small enough
> -	 * to not not cause bandwidth problems.
> +	 * to not cause bandwidth problems.
>  	 */
>  	return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));  } @@ -846,7 +846,7 @@ static unsigned int
> intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_
>  	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		/*
>  		 * We assume cursors are small enough
> -		 * to not not cause bandwidth problems.
> +		 * to not cause bandwidth problems.
>  		 */
>  		if (plane_id == PLANE_CURSOR)
>  			continue;
> --
> 2.49.1

RE: [PATCH 3/9] drm/i915/bw: Relocate intel_bw_crtc_min_cdclk()

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Monday, 13 October 2025 23.13
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 3/9] drm/i915/bw: Relocate intel_bw_crtc_min_cdclk()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> intel_bw_crtc_min_cdclk() (aka. the thing that deals with what bspec calls "Maximum Pipe Read Bandwidth") doesn't really have
> anything to do with the rest of intel_bw.c (which is all about SAGV/QGV and memory bandwidth). Move it into intel_crtc.c (for the
> lack of a better place).
> 
> And I don't really want to call intel_bw.c functions from intel_crtc.c, so move out intel_bw_crtc_data_rate() as well. And when we
> move that we pretty much have to move intel_bw_crtc_num_active_planes() as well since the two are meant to be used as a pair
> (they both implement the same "ignore the cursor" logic).
> 
> And in an effort to keep the namespaces at least semi-sensible we flip the intel_bw_crtc_ prefix into intel_crtc_bw_.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c    | 56 +++-------------------
>  drivers/gpu/drm/i915/display/intel_bw.h    |  1 -
>  drivers/gpu/drm/i915/display/intel_cdclk.c |  3 +-  drivers/gpu/drm/i915/display/intel_crtc.c  | 44 +++++++++++++++++
> drivers/gpu/drm/i915/display/intel_crtc.h  |  4 ++
>  5 files changed, 55 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index d03da1ed4541..92a060e02cf3 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -827,50 +827,6 @@ void intel_bw_init_hw(struct intel_display *display)
>  		icl_get_bw_info(display, dram_info, &icl_sa_info);  }
> 
> -static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state) -{
> -	/*
> -	 * We assume cursors are small enough
> -	 * to not cause bandwidth problems.
> -	 */
> -	return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
> -}
> -
> -static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state) -{
> -	struct intel_display *display = to_intel_display(crtc_state);
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	unsigned int data_rate = 0;
> -	enum plane_id plane_id;
> -
> -	for_each_plane_id_on_crtc(crtc, plane_id) {
> -		/*
> -		 * We assume cursors are small enough
> -		 * to not cause bandwidth problems.
> -		 */
> -		if (plane_id == PLANE_CURSOR)
> -			continue;
> -
> -		data_rate += crtc_state->data_rate[plane_id];
> -
> -		if (DISPLAY_VER(display) < 11)
> -			data_rate += crtc_state->data_rate_y[plane_id];
> -	}
> -
> -	return data_rate;
> -}
> -
> -/* "Maximum Pipe Read Bandwidth" */
> -int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state) -{
> -	struct intel_display *display = to_intel_display(crtc_state);
> -
> -	if (DISPLAY_VER(display) < 12)
> -		return 0;
> -
> -	return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
> -}
> -
>  static unsigned int intel_bw_num_active_planes(struct intel_display *display,
>  					       const struct intel_bw_state *bw_state)  { @@ -1264,13 +1220,13 @@ static int
> intel_bw_check_data_rate(struct intel_atomic_state *state, bool *chan
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
>  		unsigned int old_data_rate =
> -			intel_bw_crtc_data_rate(old_crtc_state);
> +			intel_crtc_bw_data_rate(old_crtc_state);
>  		unsigned int new_data_rate =
> -			intel_bw_crtc_data_rate(new_crtc_state);
> +			intel_crtc_bw_data_rate(new_crtc_state);
>  		unsigned int old_active_planes =
> -			intel_bw_crtc_num_active_planes(old_crtc_state);
> +			intel_crtc_bw_num_active_planes(old_crtc_state);
>  		unsigned int new_active_planes =
> -			intel_bw_crtc_num_active_planes(new_crtc_state);
> +			intel_crtc_bw_num_active_planes(new_crtc_state);
>  		struct intel_bw_state *new_bw_state;
> 
>  		/*
> @@ -1426,9 +1382,9 @@ static void intel_bw_crtc_update(struct intel_bw_state *bw_state,
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> 
>  	bw_state->data_rate[crtc->pipe] =
> -		intel_bw_crtc_data_rate(crtc_state);
> +		intel_crtc_bw_data_rate(crtc_state);
>  	bw_state->num_active_planes[crtc->pipe] =
> -		intel_bw_crtc_num_active_planes(crtc_state);
> +		intel_crtc_bw_num_active_planes(crtc_state);
> 
>  	drm_dbg_kms(display->drm, "pipe %c data rate %u num active planes %u\n",
>  		    pipe_name(crtc->pipe),
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 051e163f2f15..99b447388245 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -29,7 +29,6 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state);  void intel_bw_init_hw(struct intel_display
> *display);  int intel_bw_init(struct intel_display *display);  int intel_bw_atomic_check(struct intel_atomic_state *state); -int
> intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);  void intel_bw_update_hw_state(struct intel_display
> *display);  void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 23b9e100d824..80a6c98eea5d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -35,7 +35,6 @@
>  #include "i915_utils.h"
>  #include "intel_atomic.h"
>  #include "intel_audio.h"
> -#include "intel_bw.h"
>  #include "intel_cdclk.h"
>  #include "intel_crtc.h"
>  #include "intel_dbuf_bw.h"
> @@ -2838,7 +2837,7 @@ static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_stat
>  		return 0;
> 
>  	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
> -	min_cdclk = max(min_cdclk, intel_bw_crtc_min_cdclk(crtc_state));
> +	min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state));
>  	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
>  	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
>  	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 7b39c3a5887c..d300ba1dcd2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -795,3 +795,47 @@ bool intel_any_crtc_active_changed(struct intel_atomic_state *state)
> 
>  	return false;
>  }
> +
> +unsigned int intel_crtc_bw_num_active_planes(const struct
> +intel_crtc_state *crtc_state) {
> +	/*
> +	 * We assume cursors are small enough
> +	 * to not cause bandwidth problems.
> +	 */
> +	return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); }
> +
> +unsigned int intel_crtc_bw_data_rate(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	unsigned int data_rate = 0;
> +	enum plane_id plane_id;
> +
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
> +		/*
> +		 * We assume cursors are small enough
> +		 * to not cause bandwidth problems.
> +		 */
> +		if (plane_id == PLANE_CURSOR)
> +			continue;
> +
> +		data_rate += crtc_state->data_rate[plane_id];
> +
> +		if (DISPLAY_VER(display) < 11)
> +			data_rate += crtc_state->data_rate_y[plane_id];
> +	}
> +
> +	return data_rate;
> +}
> +
> +/* "Maximum Pipe Read Bandwidth" */
> +int intel_crtc_bw_min_cdclk(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (DISPLAY_VER(display) < 12)
> +		return 0;
> +
> +	return
> +DIV_ROUND_UP_ULL(mul_u32_u32(intel_crtc_bw_data_rate(crtc_state), 10),
> +512); }
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.h b/drivers/gpu/drm/i915/display/intel_crtc.h
> index cee09e7cd3dc..07917e8a9ae3 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.h
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.h
> @@ -65,4 +65,8 @@ bool intel_any_crtc_active_changed(struct intel_atomic_state *state);  bool
> intel_crtc_active_changed(const struct intel_crtc_state *old_crtc_state,
>  			       const struct intel_crtc_state *new_crtc_state);
> 
> +unsigned int intel_crtc_bw_num_active_planes(const struct
> +intel_crtc_state *crtc_state); unsigned int
> +intel_crtc_bw_data_rate(const struct intel_crtc_state *crtc_state); int
> +intel_crtc_bw_min_cdclk(const struct intel_crtc_state *crtc_state);
> +
>  #endif
> --
> 2.49.1

RE: [PATCH 4/9] drm/i915/ips: Eliminate the cdclk_state stuff from hsw_ips_compute_config()

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Monday, 13 October 2025 23.13
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 4/9] drm/i915/ips: Eliminate the cdclk_state stuff from hsw_ips_compute_config()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reorganize the IPS CDCLK handling such that the computed CDCLK frequency will always satisfy the IPS requirements. The only
> exceptional case is if IPS would push the CDCLK above the platform max, but in that case we can simply disable IPS.
> 
> To make this 100% race free we must move the enable_ips modparam check out from the min CDCLK computation path so that
> there is no chance of hsw_min_cdclk() and hsw_ips_compute_config() observing a different enable_ips value during the same
> commit.
> 
> This allows us to completely remove the cdclk_state stuff from the IPS code. We only ever have to compare the IPS min CDCLK
> against the platform max CDCLK. Thus we eliminate any ordering requirements between intel_cdclk_atomic_check() and
> hsw_ips_compute_config().
> 
> Additionally we reduce the three copies of the code doing the 95% calculation into just one.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/hsw_ips.c | 61 ++++++++++++--------------
>  1 file changed, 28 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index 927fe56aec77..f444c5b7a27b 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -191,45 +191,46 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
> 
>  static bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)  {
> -	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> 
> -	/* IPS only exists on ULT machines and is tied to pipe A. */
>  	if (!hsw_crtc_supports_ips(crtc))
>  		return false;
> 
> -	if (!display->params.enable_ips)
> -		return false;
> -
>  	if (crtc_state->pipe_bpp > 24)
>  		return false;
> 
> -	/*
> -	 * We compare against max which means we must take
> -	 * the increased cdclk requirement into account when
> -	 * calculating the new cdclk.
> -	 *
> -	 * Should measure whether using a lower cdclk w/o IPS
> -	 */
> -	if (display->platform.broadwell &&
> -	    crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)
> -		return false;
> -
>  	return true;
>  }
> 
> +static int _hsw_ips_min_cdclk(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	if (display->platform.broadwell)
> +		return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
> +
> +	/* no IPS specific limits to worry about */
> +	return 0;
> +}
> +
>  int hsw_ips_min_cdclk(const struct intel_crtc_state *crtc_state)  {
>  	struct intel_display *display = to_intel_display(crtc_state);
> -
> -	if (!display->platform.broadwell)
> -		return 0;
> +	int min_cdclk;
> 
>  	if (!hsw_crtc_state_ips_capable(crtc_state))
>  		return 0;
> 
> -	/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> -	return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
> +	min_cdclk = _hsw_ips_min_cdclk(crtc_state);
> +
> +	/*
> +	 * Do not ask for more than the max CDCLK frequency,
> +	 * if that is not enough IPS will simply not be used.
> +	 */
> +	if (min_cdclk > display->cdclk.max_cdclk_freq)
> +		return 0;
> +
> +	return min_cdclk;
>  }
> 
>  int hsw_ips_compute_config(struct intel_atomic_state *state, @@ -244,6 +245,12 @@ int hsw_ips_compute_config(struct
> intel_atomic_state *state,
>  	if (!hsw_crtc_state_ips_capable(crtc_state))
>  		return 0;
> 
> +	if (_hsw_ips_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq)
> +		return 0;
> +
> +	if (!display->params.enable_ips)
> +		return 0;
> +
>  	/*
>  	 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
>  	 * enabled and disabled dynamically based on package C states, @@ -257,18 +264,6 @@ int
> hsw_ips_compute_config(struct intel_atomic_state *state,
>  	if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
>  		return 0;
> 
> -	if (display->platform.broadwell) {
> -		const struct intel_cdclk_state *cdclk_state;
> -
> -		cdclk_state = intel_atomic_get_cdclk_state(state);
> -		if (IS_ERR(cdclk_state))
> -			return PTR_ERR(cdclk_state);
> -
> -		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> -		if (crtc_state->pixel_rate > intel_cdclk_logical(cdclk_state) * 95 / 100)
> -			return 0;
> -	}
> -
>  	crtc_state->ips_enabled = true;
> 
>  	return 0;
> --
> 2.49.1

RE: [PATCH 5/9] drm/i915/fbc: Decouple FBC from intel_cdclk_atomic_check()

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Monday, 13 October 2025 23.13
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 5/9] drm/i915/fbc: Decouple FBC from intel_cdclk_atomic_check()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Always account for FBC requirements in intel_crtc_compute_min_cdclk() so that we don't to worry about the actual CDCLK
> frequency in
> intel_fbc_check_plane() any longer.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c |  1 +
>  drivers/gpu/drm/i915/display/intel_fbc.c   | 49 ++++++++++++++++------
>  drivers/gpu/drm/i915/display/intel_fbc.h   |  1 +
>  3 files changed, 38 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 80a6c98eea5d..d55b3dc23356 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2838,6 +2838,7 @@ static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_stat
> 
>  	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
>  	min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state));
> +	min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state));
>  	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
>  	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
>  	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state)); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 4edb4342833e..90060c60c5f4 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -53,7 +53,6 @@
>  #include "i915_vgpu.h"
>  #include "i915_vma.h"
>  #include "i9xx_plane_regs.h"
> -#include "intel_cdclk.h"
>  #include "intel_de.h"
>  #include "intel_display_device.h"
>  #include "intel_display_regs.h"
> @@ -1417,6 +1416,18 @@ intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
>  	}
>  }
> 
> +static int _intel_fbc_min_cdclk(const struct intel_crtc_state
> +*crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +
> +	/* WaFbcExceedCdClockThreshold:hsw,bdw */
> +	if (display->platform.haswell || display->platform.broadwell)
> +		return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95);
> +
> +	/* no FBC specific limits to worry about */
> +	return 0;
> +}
> +
>  static int intel_fbc_check_plane(struct intel_atomic_state *state,
>  				 struct intel_plane *plane)
>  {
> @@ -1556,18 +1567,9 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
>  		return 0;
>  	}
> 
> -	/* WaFbcExceedCdClockThreshold:hsw,bdw */
> -	if (display->platform.haswell || display->platform.broadwell) {
> -		const struct intel_cdclk_state *cdclk_state;
> -
> -		cdclk_state = intel_atomic_get_cdclk_state(state);
> -		if (IS_ERR(cdclk_state))
> -			return PTR_ERR(cdclk_state);
> -
> -		if (crtc_state->pixel_rate >= intel_cdclk_logical(cdclk_state) * 95 / 100) {
> -			plane_state->no_fbc_reason = "pixel rate too high";
> -			return 0;
> -		}
> +	if (_intel_fbc_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) {
> +		plane_state->no_fbc_reason = "pixel rate too high";
> +		return 0;
>  	}
> 
>  	plane_state->no_fbc_reason = NULL;
> @@ -1575,6 +1577,27 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
>  	return 0;
>  }
> 
> +int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state) {
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
> +	int min_cdclk;
> +
> +	if (!plane->fbc)
> +		return 0;
> +
> +	min_cdclk = _intel_fbc_min_cdclk(crtc_state);
> +
> +	/*
> +	 * Do not ask for more than the max CDCLK frequency,
> +	 * if that is not enough FBC will simply not be used.
> +	 */
> +	if (min_cdclk > display->cdclk.max_cdclk_freq)
> +		return 0;
> +
> +	return min_cdclk;
> +}
> 
>  static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state,
>  				    struct intel_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 0e715cb6b4e6..c86562404a00 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -28,6 +28,7 @@ enum intel_fbc_id {
>  };
> 
>  int intel_fbc_atomic_check(struct intel_atomic_state *state);
> +int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state);
>  bool intel_fbc_pre_update(struct intel_atomic_state *state,
>  			  struct intel_crtc *crtc);
>  void intel_fbc_post_update(struct intel_atomic_state *state,
> --
> 2.49.1

RE: [PATCH 6/9] drm/i915: s/min_cdck[]/plane_min_cdclk[]/

[Kahola, Mika]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Monday, 13 October 2025 23.13
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 6/9] drm/i915: s/min_cdck[]/plane_min_cdclk[]/
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Rename crtc_state->min_cdclk[] into crtc_state->plane_min_cdclk[] to better reflect what it represents.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c         | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-  drivers/gpu/drm/i915/display/intel_modeset_setup.c | 6 +++---
>  drivers/gpu/drm/i915/display/intel_plane.c         | 4 ++--
>  4 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d55b3dc23356..ed64fac7897d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2824,7 +2824,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	int min_cdclk = 0;
> 
>  	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
> -		min_cdclk = max(min_cdclk, crtc_state->min_cdclk[plane->id]);
> +		min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]);
> 
>  	return min_cdclk;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 87b7cec35320..f77d120733fd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1192,7 +1192,7 @@ struct intel_crtc_state {
> 
>  	struct intel_crtc_wm_state wm;
> 
> -	int min_cdclk[I915_MAX_PLANES];
> +	int plane_min_cdclk[I915_MAX_PLANES];
> 
>  	/* for packed/planar CbCr */
>  	u32 data_rate[I915_MAX_PLANES];
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index deb877b2aebd..d5c432b613ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -853,16 +853,16 @@ static void intel_modeset_readout_hw_state(struct intel_display *display)
>  			 */
>  			if (plane_state->uapi.visible && plane->min_cdclk) {
>  				if (crtc_state->double_wide || DISPLAY_VER(display) >= 10)
> -					crtc_state->min_cdclk[plane->id] =
> +					crtc_state->plane_min_cdclk[plane->id] =
>  						DIV_ROUND_UP(crtc_state->pixel_rate, 2);
>  				else
> -					crtc_state->min_cdclk[plane->id] =
> +					crtc_state->plane_min_cdclk[plane->id] =
>  						crtc_state->pixel_rate;
>  			}
>  			drm_dbg_kms(display->drm,
>  				    "[PLANE:%d:%s] min_cdclk %d kHz\n",
>  				    plane->base.base.id, plane->base.name,
> -				    crtc_state->min_cdclk[plane->id]);
> +				    crtc_state->plane_min_cdclk[plane->id]);
>  		}
> 
>  		intel_pmdemand_update_port_clock(display, pmdemand_state, pipe, diff --git
> a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
> index 074de9275951..78329deb395a 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> @@ -304,7 +304,7 @@ static void intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
> 
>  	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> 
> -	new_crtc_state->min_cdclk[plane->id] =
> +	new_crtc_state->plane_min_cdclk[plane->id] =
>  		plane->min_cdclk(new_crtc_state, plane_state);  }
> 
> @@ -391,7 +391,7 @@ void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
>  	crtc_state->data_rate_y[plane->id] = 0;
>  	crtc_state->rel_data_rate[plane->id] = 0;
>  	crtc_state->rel_data_rate_y[plane->id] = 0;
> -	crtc_state->min_cdclk[plane->id] = 0;
> +	crtc_state->plane_min_cdclk[plane->id] = 0;
> 
>  	plane_state->uapi.visible = false;
>  }
> --
> 2.49.1

RE: [PATCH 7/9] drm/i915: Compute per-crtc min_cdclk earlier

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Monday, 13 October 2025 23.13
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 7/9] drm/i915: Compute per-crtc min_cdclk earlier
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we compute the min_cdclk for each pipe during intel_cdclk_atomic_check(). But that is too late for the pipe prefill vs.
> vblank length checks (done during intel_compute_global_watermarks).
> 
> We can't just reorder these things due to other dependencies, so instead pull only the per-crtc minimum cdclk calculation ahead.
> We should have enough information for that as soon as we've computed the min cdclk for the planes.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c         | 8 ++++----
>  drivers/gpu/drm/i915/display/intel_cdclk.h         | 2 ++
>  drivers/gpu/drm/i915/display/intel_display.c       | 3 +++
>  drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++  drivers/gpu/drm/i915/display/intel_modeset_setup.c | 5 +++++
>  5 files changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index ed64fac7897d..af918e0e72ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2829,7 +2829,7 @@ static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
>  	return min_cdclk;
>  }
> 
> -static int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> +int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
>  {
>  	int min_cdclk;
> 
> @@ -3302,8 +3302,8 @@ static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state,
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i) {
>  		ret = intel_cdclk_update_crtc_min_cdclk(state, crtc,
> -							intel_crtc_compute_min_cdclk(old_crtc_state),
> -							intel_crtc_compute_min_cdclk(new_crtc_state),
> +							old_crtc_state->min_cdclk,
> +							new_crtc_state->min_cdclk,
>  							need_cdclk_calc);
>  		if (ret)
>  			return ret;
> @@ -3523,7 +3523,7 @@ void intel_cdclk_update_hw_state(struct intel_display *display)
>  		if (crtc_state->hw.active)
>  			cdclk_state->active_pipes |= BIT(pipe);
> 
> -		cdclk_state->min_cdclk[pipe] = intel_crtc_compute_min_cdclk(crtc_state);
> +		cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk;
>  		cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
>  	}
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index d9d7a8b3a48a..bad2da8d45d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -69,4 +69,6 @@ bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);  void
> intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);  void intel_cdclk_read_hw(struct
> intel_display *display);
> 
> +int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state);
> +
>  #endif /* __INTEL_CDCLK_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index d5b2612d4ec2..539017018884 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6443,6 +6443,9 @@ int intel_atomic_check(struct drm_device *dev,
>  	if (ret)
>  		goto fail;
> 
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
> +		new_crtc_state->min_cdclk = intel_crtc_min_cdclk(new_crtc_state);
> +
>  	ret = intel_compute_global_watermarks(state);
>  	if (ret)
>  		goto fail;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f77d120733fd..203dd38a9ec4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1192,6 +1192,8 @@ struct intel_crtc_state {
> 
>  	struct intel_crtc_wm_state wm;
> 
> +	int min_cdclk;
> +
>  	int plane_min_cdclk[I915_MAX_PLANES];
> 
>  	/* for packed/planar CbCr */
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index d5c432b613ce..0dcb0597879a 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -865,6 +865,11 @@ static void intel_modeset_readout_hw_state(struct intel_display *display)
>  				    crtc_state->plane_min_cdclk[plane->id]);
>  		}
> 
> +		crtc_state->min_cdclk = intel_crtc_min_cdclk(crtc_state);
> +
> +		drm_dbg_kms(display->drm, "[CRTC:%d:%s] min_cdclk %d kHz\n",
> +			    crtc->base.base.id, crtc->base.name, crtc_state->min_cdclk);
> +
>  		intel_pmdemand_update_port_clock(display, pmdemand_state, pipe,
>  						 crtc_state->port_clock);
>  	}
> --
> 2.49.1

RE: [PATCH 8/9] drm/i915: Include the per-crtc minimum cdclk in the crtc state dump

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Monday, 13 October 2025 23.13
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 8/9] drm/i915: Include the per-crtc minimum cdclk in the crtc state dump
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Include the crtc minimum cdclk in the crtc state dump. Might help figuring out who needed how much cdclk.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> index a14bcda4446c..23e25e97d060 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
> @@ -314,9 +314,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config,
>  	drm_printf(&p, "pipe mode: " DRM_MODE_FMT "\n",
>  		   DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
>  	intel_dump_crtc_timings(&p, &pipe_config->hw.pipe_mode);
> -	drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
> +	drm_printf(&p, "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate
> +%d, min cdclk %d\n",
>  		   pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
> -		   pipe_config->pixel_rate);
> +		   pipe_config->pixel_rate, pipe_config->min_cdclk);
> 
>  	drm_printf(&p, "linetime: %d, ips linetime: %d\n",
>  		   pipe_config->linetime, pipe_config->ips_linetime);
> --
> 2.49.1

RE: [PATCH 9/9] drm/i915: Neuter cdclk_prefill_adjustment()

[Kahola, Mika]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville Syrjala
> Sent: Monday, 13 October 2025 23.13
> To: intel-gfx@lists.freedesktop.org
> Cc: intel-xe@lists.freedesktop.org
> Subject: [PATCH 9/9] drm/i915: Neuter cdclk_prefill_adjustment()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> cdclk_prefill_adjustment() currently uses a stale cdclk value. And even if it was using the correct value it'd still just 'return 1'
> because the ratio that it's calculating is always <= 1.0, and it just rounds the ratio into an integer (and clamps the result to a
> maximum of 1).
> So for the moment, let's just 'return 1' since that's what the code ends up doing anyway.
> 
> This is actually safe because 1.0 is the worst case (ie. slowest
> prefill) and thus the actual prefill is always guaranteed to be at least as fast as what we assumed during the check.
> 
> We'll replace this soon with something that gives more accurate estimates.
> 

I'll buy the explanation

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 14 +-------------
>  1 file changed, 1 insertion(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 9df9ee137bf9..1b062c6c0e03 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2148,19 +2148,7 @@ static int icl_build_plane_wm(struct intel_crtc_state *crtc_state,  static int
> cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)  {
> -	struct intel_display *display = to_intel_display(crtc_state);
> -	struct intel_atomic_state *state =
> -		to_intel_atomic_state(crtc_state->uapi.state);
> -	const struct intel_cdclk_state *cdclk_state;
> -
> -	cdclk_state = intel_atomic_get_cdclk_state(state);
> -	if (IS_ERR(cdclk_state)) {
> -		drm_WARN_ON(display->drm, PTR_ERR(cdclk_state));
> -		return 1;
> -	}
> -
> -	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
> -				   2 * intel_cdclk_logical(cdclk_state)));
> +	return 1;
>  }
> 
>  static int
> --
> 2.49.1